Texas Instruments | ADS8864 16-bit, 400-kSPS, serial interface, micropower, miniature, single-ended input, SAR analog-to-digital converter (Rev. B) | Datasheet | Texas Instruments ADS8864 16-bit, 400-kSPS, serial interface, micropower, miniature, single-ended input, SAR analog-to-digital converter (Rev. B) Datasheet

Texas Instruments ADS8864 16-bit, 400-kSPS, serial interface, micropower, miniature, single-ended input, SAR analog-to-digital converter (Rev. B) Datasheet
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ADS8864
SBAS572B – MAY 2013 – REVISED MARCH 2019
ADS8864 16-bit, 400-kSPS, serial interface, micropower, miniature,
single-ended input, SAR analog-to-digital converter
1 Features
2 Applications
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
Sample rate: 400 kHz
No latency output
Unipolar, single-ended input range:
0 to +VREF
SPI™-compatible serial interface with
daisy-chain option
Excellent AC and DC performance:
– SNR: 93 dB, THD: –108 dB
– INL: ±1.0 LSB (typ), ±2.0 LSB (max)
– DNL: ±1.0 LSB (max), 16-bit NMC
Wide operating range:
– AVDD: 2.7 V to 3.6 V
– DVDD: 1.65 V to 3.6 V
(independent of AVDD)
– REF: 2.5 V to 5 V (independent of AVDD)
– Operating temperature: –40°C to +85°C
Low-power dissipation:
– 2.6 mW at 400 kSPS
– 0.65 mW at 100 kSPS
– 65 µW at 10 kSPS
Power-down current (AVDD): 50 nA
Full-scale step settling to 16 Bits: 1200 ns
Packages: VSSOP-10 and VSON-10
Automatic test equipment (ATE)
Instrumentation and process controls
Precision medical equipment
Low-power, battery-operated instruments
3 Description
The ADS8864 is a 16-bit, 400-kSPS, single-ended
input, analog-to-digital converter (ADC). The device
operates with a 2.5-V to 5-V external reference,
offering a wide selection of signal ranges without
additional input signal scaling. The reference voltage
setting is independent of, and can exceed, the analog
supply voltage (AVDD).
The device
that also
cascading
indicator bit
easy.
offers an SPI-compatible serial interface
supports daisy-chain operation for
multiple devices. An optional busymakes synchronizing with the digital host
The device supports unipolar single-ended analog
inputs in the range of –0.1 V to VREF + 0.1 V.
Device operation is optimized for very low-power
operation. Power consumption directly scales with
speed. This feature makes the ADS8864 excellent for
lower-speed applications.
Device Information(1)
PART NUMBER
ADS8864
PACKAGE
BODY SIZE (NOM)
VSSOP (10)
3.00 mm × 3.00 mm
VSON (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
No Separate LDO Required for the ADC Supply
2.7 V to 3.6 V
2.5 V to 5 V
REF
AVDD
DVDD
0 V - VREF
DIN
AINP
ADS8864
AINN
SCLK
DOUT
Digital Host
CONVST
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS8864
SBAS572B – MAY 2013 – REVISED MARCH 2019
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
1
1
1
2
4
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements: 3-Wire Operation .................. 8
Timing Requirements: 4-Wire Operation .................. 8
Timing Requirements: Daisy-Chain .......................... 9
Typical Characteristics ............................................ 11
8
Parameter Measurement Information ................ 18
9
Detailed Description ............................................ 19
8.1 Equivalent Circuits .................................................. 18
9.1 Overview ................................................................. 19
9.2 Functional Block Diagram ....................................... 19
9.3 Feature Description................................................. 19
9.4 Device Functional Modes........................................ 21
10 Application and Implementation........................ 30
10.1 Application Information.......................................... 30
10.2 Typical Applications .............................................. 32
11 Power Supply Recommendations ..................... 35
11.1 Power-Supply Decoupling..................................... 35
11.2 Power Saving ........................................................ 35
12 Layout................................................................... 37
12.1 Layout Guidelines ................................................. 37
12.2 Layout Example .................................................... 37
13 Device and Documentation Support ................. 38
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
38
38
38
38
38
39
14 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2013) to Revision B
Page
•
Added Device Information table, ESD Ratings table, Recommended Operating Conditions table, Parametric
Measurement Information section, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Changed analog input from pseudo-differential to single-ended throughout document......................................................... 1
•
Changed MSOP to VSSOP throughout document ................................................................................................................ 1
•
Changed title of Device Comparison Table from Family Information..................................................................................... 4
•
Changed footnotes of Family Information table...................................................................................................................... 4
•
Added Input current row to Absolute Maximum Ratings table .............................................................................................. 5
•
Changed LSB footnote in Electrical Characteristics table to include how to convert LSB to ppm ........................................ 6
•
Added more information about validity of data on SCLK edges in all interface modes ....................................................... 22
•
Changed diagrams and text for better explanation of the daisy-chain feature in the Daisy-Chain Mode section ............... 27
•
Changed Equation 1 and Equation 2 ................................................................................................................................... 30
•
Changed Charge-Kickback Filter section title and functionality description ........................................................................ 31
Changes from Original (May 2013) to Revision A
Page
•
Changed sub-bullets of AC and DC performance Features bullet ......................................................................................... 1
•
Changed Full-scale step settling Features bullet ................................................................................................................... 1
•
Deleted last two Applications bullets ...................................................................................................................................... 1
•
Changed Description section.................................................................................................................................................. 1
•
Changed front page graphic ................................................................................................................................................... 1
•
Added Family Information, Absolute Maximum Ratings, and Thermal Information tables..................................................... 4
•
Added Pin Configurations section .......................................................................................................................................... 4
2
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SBAS572B – MAY 2013 – REVISED MARCH 2019
•
Added Electrical Characteristics table .................................................................................................................................... 6
•
Added Timing Characteristics section .................................................................................................................................... 8
•
Added Typical Characteristics section.................................................................................................................................. 11
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5 Device Comparison Table
(1)
(2)
THROUGHPUT
18-BIT, TRUE-DIFFERENTIAL
16-BIT, SINGLE-ENDED
16-BIT, TRUE-DIFFERENTIAL
100 kSPS
ADS8887
ADS8866
ADS8867
250 kSPS
—
ADS8339 (1)
—
400 kSPS
ADS8885
ADS8864
ADS8865
500 kSPS
—
ADS8319 (1)
ADS8318 (1) (2)
680 kSPS
ADS8883
ADS8862
ADS8863
1 MSPS
ADS8881
ADS8860
ADS8861
Pin-to-pin compatible device with AVDD = 5 V.
Supports standard for fully-differential input.
6 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
REF
1
10
AVDD
2
9
DRC Package
10-Pin VSON
Top View
DVDD
AINP
3
8
SCLK
AINN
4
7
DOUT
GND
5
6
REF
1
10
AVDD
2
9
DVDD
DIN
DIN
Thermal pad
AINP
3
8
SCLK
AINN
4
7
DOUT
GND
5
6
CONVST
CONVST
Not to scale
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
AINN
4
Analog input
Inverting analog signal input
AINP
3
Analog input
Noninverting analog signal input
AVDD
2
Analog
CONVST
6
Digital input
Convert input. This pin also functions as the CS input in 3-wire interface mode; see the
Description and Timing Requirements sections for more details.
DIN
9
Digital input
Serial data input. The DIN level at the start of a conversion selects the mode of operation
(such as CS or daisy-chain mode). This pin also serves as the CS input in 4-wire interface
mode; see the Description and Timing Requirements sections for more details.
Analog power supply. This pin must be decoupled to GND with a 1-µF capacitor.
DOUT
7
Digital output
Serial data output
DVDD
10
Power supply
Digital interface power supply. This pin must be decoupled to GND with a 1-µF capacitor.
GND
5
Analog, digital
Device ground. Note that this pin is a common ground pin for both the analog power supply
(AVDD) and digital I/O supply (DVDD). The reference return line is also internally connected to
this pin.
REF
1
Analog
SCLK
8
Digital input
Thermal pad
4
—
Positive reference input. This pin must be decoupled with a 10-µF or larger capacitor.
Clock input for serial interface. Data output (on DOUT) are synchronized with this clock.
Exposed thermal pad (only for the DRC package option). Texas Instruments recommends
connecting the thermal pad to the printed circuit board (PCB) ground.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
AINP to GND or AINN to GND
–0.3
REF + 0.3
V
AVDD to GND or DVDD to GND
–0.3
4
V
REF to GND
–0.3
5.7
V
Digital input voltage to GND
–0.3
DVDD + 0.3
V
Digital output to GND
–0.3
DVDD + 0.3
V
Input current to any pin except supply pins
–10
10
mA
Operating temperature, TA
–40
85
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
AVDD
Analog power supply
3
V
DVDD
Digital power supply
3
V
VREF
Reference voltage
5
V
7.4 Thermal Information
ADS8864
THERMAL METRIC (1)
DGS (VSSOP)
DRC (VSON)
10 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
151.9
111.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
45.4
46.4
°C/W
RθJB
Junction-to-board thermal resistance
72.2
45.9
°C/W
ψJT
Junction-to-top characterization parameter
3.3
3.5
°C/W
ψJB
Junction-to-board characterization parameter
70.9
45.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
all minimum and maximum specifications are at AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 400 kSPS over the
operating free-air temperature range (unless otherwise noted); typical specifications are at TA = 25°C, AVDD = 3 V, and
DVDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
VREF
V
AINP
–0.1
VREF + 0.1
AINN
–0.1
+ 0.1
ANALOG INPUT
Full-scale input span (1)
Operating input range (1)
CI
AINP – AINN
Input capacitance
AINP and AINN terminal to GND
Input leakage current
During acquisition for dc input
V
59
pF
5
nA
EXTERNAL REFERENCE INPUT
VREF
Input range
2.5
Reference input current
During conversion, 400-kHz sample rate,
mid-code
Reference leakage current
CREF
Decoupling capacitor at the
REF input
10
5
V
100
μA
250
nA
22
µF
16
Bits
SYSTEM PERFORMANCE
Resolution
NMC
No missing codes
DNL
Differential linearity
INL
Integral linearity
EO
Offset error (4)
16
(3)
–0.99
±0.6
1
LSB (2)
–2
±0.8
2
LSB (2)
–4
±1
4
mV
Offset error drift with
temperature
EG
Bits
±1.5
Gain error
–0.01
Gain error drift with
temperature
±0.005
µV/°C
0.01
±0.15
CMRR
Common-mode rejection
ratio
With common-mode input signal = 5 VPP at
dc
PSRR
Power-supply rejection ratio
At mid-code
90
Transition noise
%FSR
ppm/°C
100
dB
80
dB
0.5
LSB
SAMPLING DYNAMICS
tconv
Conversion time
500
tACQ
Acquisition time
1200
1300
ns
Maximum throughput rate
with or without latency
(1)
(2)
(3)
(4)
6
ns
400
kHz
Aperture delay
4
ns
Aperture jitter, RMS
5
ps
Step response
Settling to 16-bit accuracy
1200
ns
Overvoltage recovery
Settling to 16-bit accuracy
1200
ns
Ideal input span, does not include gain or offset error.
LSB = least significant bit. 1 LSB at 16-bits is approximately 15.26 ppm.
This parameter is the endpoint INL, not best-fit.
Measured relative to actual measured reference.
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Electrical Characteristics (continued)
all minimum and maximum specifications are at AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 400 kSPS over the
operating free-air temperature range (unless otherwise noted); typical specifications are at TA = 25°C, AVDD = 3 V, and
DVDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
90.5
92.9
MAX
UNIT
DYNAMIC CHARACTERISTICS
At 1 kHz, VREF = 5 V
SINAD
Signal-to-noise + distortion
(5)
At 10 kHz, VREF = 5 V
92.9
At 100 kHz, VREF = 5 V
88.2
At 1 kHz, VREF = 5 V
SNR
THD
Signal-to-noise ratio
(5)
Total harmonic distortion
92
At 10 kHz, VREF = 5 V
(5) (6)
SFDR
Spurious-free dynamic
range (5)
BW–3dB
–3-dB small-signal bandwidth
dB
93
93
At 100 kHz, VREF = 5 V
88.5
At 1 kHz, VREF = 5 V
–108
At 10 kHz, VREF = 5 V
–108
At , VREF = 5 V
–101
At 1 kHz, VREF = 5 V
108
At 10 kHz, VREF = 5 V
108
At 100 kHz, VREF = 5 V
101
dB
dB
dB
30
MHz
POWER-SUPPLY REQUIREMENTS
Power-supply
voltage
AVDD
Analog supply
DVDD
Digital supply range
Supply current
AVDD
400-kHz sample rate, AVDD = 3 V
PVA
Power dissipation
IAPD
Device power-down
current (7)
2.7
3
3.6
1.65
1.8
3.6
0.85
1.2
400-kHz sample rate, AVDD = 3 V
2.6
3.6
100-kHz sample rate, AVDD = 3 V
0.65
10-kHz sample rate, AVDD = 3 V
V
mA
mW
65
μW
50
nA
DIGITAL INPUTS: LOGIC FAMILY (CMOS)
VIH
High-level input voltage
VIL
Low-level input voltage
ILK
Digital input leakage current
1.65 V < DVDD < 2.3 V
0.8 × DVDD
DVDD + 0.3
2.3 V < DVDD < 3.6 V
0.7 × DVDD
DVDD + 0.3
1.65 V < DVDD < 2.3 V
–0.3
0.2 × DVDD
2.3 V < DVDD < 3.6 V
–0.3
0.3 × DVDD
±10
V
V
±100
nA
0.8 × DVDD
DVDD
V
0
0.2 × DVDD
V
–40
85
°C
DIGITAL OUTPUTS: LOGIC FAMILY (CMOS)
VOH
High-level output voltage
IO = 500-μA source, CLOAD = 20 pF
VOL
Low-level output voltage
IO = 500-μA sink, CLOAD = 20 pF
TEMPERATURE RANGE
TA
(5)
(6)
(7)
Operating free-air
temperature
All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale,
unless otherwise specified.
Calculated on the first nine harmonics of the input frequency.
The device automatically enters a power-down state at the end of every conversion, and remains in power-down during the acquisition
phase.
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7.6 Timing Requirements: 3-Wire Operation
all specifications are at AVDD = 3 V, DVDD = 3 V, and over the operating free-air temperature range (unless otherwise noted)
MIN
TYP MAX UNIT
tACQ
Acquisition time
1200
tconv
Conversion time
500
ns
1/fsample
Time between conversions
twh-CNV
Pulse duration: CONVST high
fSCLK
SCLK frequency
tSCLK
SCLK period
tclkl
SCLK low time
0.45
0.55 tSCLK
tclkh
SCLK high time
0.45
0.55 tSCLK
th-CK-DO
SCLK falling edge to current data invalid
td-CK-DO
SCLK falling edge to next data valid delay
13.4
ns
td-CNV-DO
Enable time: CONVST low to MSB valid
12.3
ns
td-CNV-DOhz
Disable time: CONVST high or last SCLK falling edge to DOUT 3-state (CS mode)
13.2
ns
tquiet
Quiet time
1300
ns
2500
ns
10
ns
16
15
66.6 MHz
62.5
ns
3
ns
20
ns
7.7 Timing Requirements: 4-Wire Operation
all specifications are at AVDD = 3 V, DVDD = 3 V, and over the operating free-air temperature range (unless otherwise noted)
MIN
TYP MAX UNIT
tACQ
Acquisition time
1200
tconv
Conversion time
500
1/fsample
Time between conversions
2500
ns
twh-DI
Pulse duration: DIN high
10
ns
twl-CNV
Pulse width: CONVST low
20
td-DI-DO
Delay time: DIN low to MSB valid
td-DI-DOhz
Delay time: DIN high or last SCLK falling edge to DOUT 3-state
tsu-DI-CNV
Setup time: DIN high to CONVST rising edge
th-DI-CNV
Hold time: DIN high from CONVST rising edge (see Figure 61)
8
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ns
1300
ns
ns
12.3
ns
13.2
ns
7.5
ns
0
ns
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7.8 Timing Requirements: Daisy-Chain
all specifications are at AVDD = 3 V, DVDD = 3 V, and over the operating free-air temperature range (unless otherwise noted)
MIN
tACQ
Acquisition time
1200
tconv
Conversion time
500
1/fsample
Time between conversions
tsu-CK-CNV
Setup time: SCLK valid to CONVST rising edge
th-CK-CNV
Hold time: SCLK valid from CONVST rising edge
tsu-DI-CNV
Setup time: DIN low to CONVST rising edge (see Figure 2)
th-DI-CNV
Hold time: DIN low from CONVST rising edge (see Figure 61)
tsu-DI-CK
Setup time: DIN valid to SCLK falling edge
TYP MAX UNIT
ns
1300
ns
2500
ns
5
ns
5
ns
7.5
ns
0
ns
1.5
ns
1/fsample
DIN = HIGH
tconv-max
tACQ
tclkh
th-CK-DO
CONVST
tclkl
tquiet
œœ
SCLK
1
2
3
td-CNV-DO
D15
DOUT
14
15
16
D1
D0
tSCLK
œœ
D14
D13
D2
œœ
twh-CNV-min
td-CK-DOhz
td-CK-DO
Figure 1. 3-Wire Operation: CONVST Functions as Chip Select
NOTE: Figure 1 shows the timing diagram for the 3-Wire CS Mode Without a Busy Indicator interface option.
However, the timing parameters specified in Timing Requirements: 3-Wire Operation table are also applicable for
the 3-Wire CS Mode With a Busy Indicator interface option, unless otherwise specified; see the Device
Functional Modes section for specific details for each interface option.
1/fsample
tACQ
tconv-max
CONVST
tsu-DI-CNV
twl-CNV
DIN
œœ
SCLK
1
DOUT
D15
2
3
D14
D13
14
15
16
D1
D0
œœ
twh-DI-min
td-DI-DO
D2
œœ
td-DI-DOhz
Figure 2. 4-Wire Operation: DIN Functions as Chip Select
NOTE: Figure 2 shows the timing diagram for the 4-Wire CS Mode Without a Busy Indicator interface option.
However, the timing parameters specified in Timing Requirements: 4-Wire Operation table are also applicable for
the 4-Wire CS Mode With a Busy Indicator interface option, unless otherwise specified; see the Device
Functional Modes section for specific details for each interface option.
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1/fsample
tconv-
tACQ
max
CONVST
th-CK-CNV
SCLK
DIN 1 = LOW
1
2
15
16
17
18
31
32
D15
D14
D1
D0
tsu-DI-CK
tsu-CK-CNV
DOUT 1,
DIN 2
D15
D14
D1
D0
DOUT 2
D15
D15
D1
D0
Device 2 Data
Device 1 Data
Figure 3. Daisy-Chain Operation: Two Devices
NOTE: Figure 3 shows the timing diagram for the Daisy-Chain Mode Without a Busy Indicator interface option.
However, the timing parameters specified in Timing Requirements: Daisy-Chain table are also applicable for the
Daisy-Chain Mode With a Busy Indicator interface option, unless otherwise specified; see the Device Functional
Modes section for specific details for each interface option.
10
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7.9 Typical Characteristics
at TA = 25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 400 kSPS (unless otherwise noted)
1
Typical Differential Nonlinearity (LSB)
Typical Integral Nonlinearity (LSB)
2
AVDD = 3 V
REF = 2.5 V
TA = 25ƒC
1.5
1
0.5
0
-0.5
-1
-1.5
AVDD = 3 V
REF = 2.5 V
TA = 25ƒC
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-2
-1
0
13107
26214
39321
52428
ADC Output Code
65535
0
13107
C001
Figure 4. Typical INL (VREF = 2.5 V)
65535
C002
Figure 5. Typical DNL (VREF = 2.5 V)
Typical Differential Nonlinearity (LSB)
Typical Integral Nonlinearity (LSB)
52428
1
2
AVDD = 3 V
REF = 5 V
TA = 25ƒC
1.5
1
0.5
0
-0.5
-1
-1.5
AVDD = 3 V
REF = 5 V
TA = 25ƒC
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-2
0
13107
26214
39321
ADC Output Code
52428
0
65535
13107
26214
39321
52428
ADC Output Code
C003
Figure 6. Typical INL (VREF = 5 V)
65535
C004
Figure 7. Typical DNL (VREF = 5 V)
2
1
Differential Nonlinearity (LSB)
AVDD = 3 V
REF = 5 V
1.5
Integral Nonlinearity (LSB)
26214
39321
ADC Output Code
1
0.5
0
-0.5
-1
-1.5
-2
AVDD = 3 V
REF = 5 V
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-40
-15
10
35
60
Free-Air Temperature( oC)
85
-40
C00
Figure 8. INL vs Temperature
-15
10
35
Free-Air Temperature (oC)
60
85
C00
Figure 9. DNL vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 400 kSPS (unless otherwise noted)
2
1
Integral Nonlinearity (LSB)
1.5
Differential Nonlinearity (LSB)
AVDD = 3 V
TA = 25oC
1
0.5
0
-0.5
-1
-1.5
-2
AVDD = 3 V
TA = 25oC
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
2.5
3
3.5
4
Reference Voltage (V)
4.5
5
2.5
3
C00
Figure 10. INL vs Reference Voltage
C00
AVDD = 3 V
REF = 5 V
TA = 25oC
80
Hits per Code (%)
Hits per Code (%)
5
100
AVDD = 3 V
REF = 2.5 V
TA = 25oC
50
40
30
20
60
40
20
10
0
32735
32736
32737
32738
32739
32740
0
32741
ADC Output Code
32750
32751
C00
Figure 12. DC Input Histogram (VREF = 2.5 V)
32752
32753
ADC Output Code
32754
C01
Figure 13. DC Input Histogram (VREF = 5 V)
0
0
AVDD = 3 V
REF = 2.5 V
TA = 25ƒC
fIN = 1 kHz
SNR = 88.7 dB
THD = ±111 dB
±80
AVDD = 3 V
REF = 5 V
TA = 25ƒC
fIN = 1 kHz
SNR = 93 dB
THD = ±108 dB
±40
Power (dB)
±40
Power (dB)
4.5
Figure 11. DNL vs Reference Voltage
60
±120
±160
±80
±120
±160
±200
±200
0
40
80
120
160
Input Frequency (kHz)
200
0
C011
Figure 14. Typical FFT (VREF = 2.5 V)
12
3.5
4
Reference Voltage (V)
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40
80
120
Input Frequency (kHz)
160
200
C012
Figure 15. Typical FFT (VREF = 5 V)
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 400 kSPS (unless otherwise noted)
95
Signal-to-Noise and Distortion (dBFS)
Signal-to-Noise Ratio (dBFS)
95
94
93
92
91
90
89
88
fIN = 1 kHz
94
93
92
91
90
89
88
fIN = 1 kHz
87
87
2.5
3
3.5
4
Reference Voltage (V)
4.5
2.5
5
Figure 16. SNR vs Reference Voltage
4.5
5
C01
-105
Total Harmonic Distortion (dBFS)
fIN = 1 kHz
Effective Number of Bits
3.5
4
Reference Voltage (V)
Figure 17. SINAD vs Reference Voltage
16
15.5
15
14.5
fIN = 1 kHz
-107
-109
-111
-113
-115
14
2.5
3
3.5
4
Reference Voltage (V)
4.5
2.5
5
3
C01
Figure 18. ENOB vs Reference Voltage
3.5
4
Reference Voltage (V)
4.5
5
C01
Figure 19. THD vs Reference Voltage
115
96
fIN = 1 kHz
fIN = 1 kHz
Signal-to-Noise Ratio (dBFS)
Spurious-Free Dynamic Range (dBFS)
3
C01
113
111
109
107
105
95
94
93
92
91
90
2.5
3
3.5
4
Reference Voltage (V)
4.5
5
-40
C01
Figure 20. SFDR vs Reference Voltage
-15
10
35
60
Free-Air Temperature (oC)
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Figure 21. SNR vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 400 kSPS (unless otherwise noted)
16
fIN = 1 kHz
95
Effective Number of Bits
Signal-to-Noise and Distortion (dBFS)
96
94
93
92
15
14
13
91
fIN = 1 kHz
90
12
-40
-15
10
35
Free-Air Temperature (oC)
60
85
-40
Figure 22. SINAD vs Temperature
Spurious-Free Dynamic Reange (dBFS)
Total Harmonic Distortion (dBFS)
fIN = 1 kHz
-103
-106
-109
-112
-115
-15
10
35
Free-Air Temperature (oC)
60
85
C02
fIN = 1 kHz
112
109
106
103
100
-40
-15
C02
Figure 24. THD vs Temperature
10
35
60
Free-Air Temperfature (oC)
85
C02
Figure 25. SFDR vs Temperature
97
Signal-to-Noise and Distortion (dB FS)
Signal-to-Noise Ratio (dBFS)
60
115
85
97
95
93
91
89
87
85
95
93
91
89
87
85
0
20
40
60
Input Frequency (kHz)
80
100
0
C02
Figure 26. SNR vs Input Frequency
14
10
35
Free-Air Temperature (oC)
Figure 23. ENOB vs Temperature
-100
-40
-15
C01
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20
40
60
Input Frequency (kHz)
80
100
C02
Figure 27. SINAD vs Input Frequency
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 400 kSPS (unless otherwise noted)
-90
Total Harmonic Distortion (dBFS)
Effective Number of Bits
16
15
14
13
12
-95
-100
-105
-110
-115
0
20
40
60
Input Frequency (kHz)
80
100
0
20
C02
80
100
C02
Figure 29. THD vs Input Frequency
115
2
Analog Supply Current (mA)
Spurious-Free Dynamic Range (dBFS)
Figure 28. ENOB vs Input Frequency
40
60
Input Frequency (kHz)
110
105
100
95
1.6
1.2
0.8
0.4
90
0
0
20
40
60
Input Frequency (kHz)
80
100
-40
-15
C02
Figure 30. SFDR vs Input Frequency
10
35
60
Free-Air Temperature (oC)
85
C02
Figure 31. Supply Current vs Temperature
4
1
Analog Supply Current (mA)
Power Consumption (mW))
3.5
3
2.5
2
1.5
1
0.5
0
-40
-15
10
35
60
Free-Air Temperature (oC)
85
0.8
0.6
0.4
0.2
0
40
C02
Figure 32. Power Consumption vs Temperature
100
160
220
280
Throughput (kSPS)
340
400
Figure 33. Supply Current vs Throughput
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 400 kSPS (unless otherwise noted)
200
175
2.5
Power-Down Current (mA)
Power Consumption (mW)
3
2
1.5
1
0.5
150
125
100
75
50
25
0
0
40
100
160
220
280
Throughput (kSPS)
340
400
-40
Figure 34. Power Consumption vs Throughput
AVDD = 3 V
REF = 5 V
0.0050
Gain-Error (%FS)
1
0
-1
-2
0.0025
0.0000
-0.0025
-0.0050
-0.0075
-3
-0.0100
-4
-40
-15
10
35
60
Free-Air Temperature (oC)
-40
85
-15
10
35
60
Free-Air Temperature (oC)
C03
Figure 36. Offset vs Temperature
85
C03
Figure 37. Gain Error vs Temperature
2000
5000
AVDD = 3 V
REF = 2.5 V
TA = 25oC
6000 Devices
AVDD = 3 V
REF = 2.5 V
TA = 25oC
6000 Devices
1600
Frequency
Frequency
85
C03
0.0075
2
3000
2000
1200
800
400
1000
0
0
-0.01
-0.005
0
0.005
Gain Error (% FS)
-4
0.01
-3
-2
-1
0
1
2
3
Offset (mV)
C00
Figure 38. Typical Distribution of Gain Error
16
60
Figure 35. Power-Down Current vs Temperature
AVDD = 3 V
REF = 5 V
3
4000
10
35
Free-Air Temperature (oC)
0.0100
4
Offset (mV)
-15
C02
C03
4
C00
Figure 39. Typical Distribution of Offset Error
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 400 kSPS (unless otherwise noted)
6000
4000
AVDD = 3 V
REF = 2.5 V
TA = 25oC
6000 Devices
5000
AVDD = 3 V
REF = 2.5 V
TA = 25oC
6000 Devices
3000
Frequency
Frequency
4000
3000
2000
2000
1000
1000
0
0
-1
-0.5
0
0.5
Differential Nonlinearity Min and Max (LSB)
1
-2
C009
Figure 40. Typical Distribution of Differential Nonlinearity
(Minimum and Maximum)
-1
0
1
Integral Nonlinearity Min and Max (LSB)
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Figure 41. Typical Distribution of Integral
Nonlinearity (Minimum and Maximum)
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8 Parameter Measurement Information
8.1 Equivalent Circuits
500 µA
IOL
1.4 V
DOUT
20 pF
500 µA
IOH
Figure 42. Load Circuit for Digital Interface Timing
DIN
CONVST
SCLK
VIH
VIL
VOH
VOH
VOL
VOL
SDO
Figure 43. Voltage Levels for Timing
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9 Detailed Description
9.1 Overview
The ADS8864 is a high-speed, successive approximation register (SAR), analog-to-digital converter (ADC) from
a 16- and 18-bit device family. This compact device features high performance. Power consumption is inherently
low and scales linearly with sampling speed. The architecture is based on charge redistribution that inherently
includes a sample-and-hold (S/H) function.
The ADS8864 supports a single-ended analog input across two pins (INP and INN). When a conversion is
initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in
progress, both the INP and INN inputs are disconnected from the internal circuit.
The ADS8864 uses an internal clock to perform conversions. The device reconnects the sampling capacitors to
the INP and INN pins after conversion and then enters an acquisition phase. During the acquisition phase, the
device is powered down and the conversion result can be read.
The device digital output is available in SPI-compatible format, thus making interfacing with microprocessors,
digital signal processors (DSPs), or field-programmable gate arrays (FPGAs) easy.
9.2 Functional Block Diagram
Figure 44 shows the detailed functional block diagram for the device.
AVDD
REF
DVDD
REF
CONVST
AINP
Sample
and
Hold
AINN
SCLK
SAR
ADC
ADC
SPI
DOUT
DIN
AGND
REFM
DGND
GND
GND
Figure 44. Detailed Block Diagram
9.3 Feature Description
9.3.1 Analog Input
As shown in Figure 44, the device features a single-ended analog input. AINP can swing from GND – 0.1 V to
VREF + 0.1 V and AINN can swing from GND – 0.1 V to GND + 0.1 V. Both positive and negative inputs are
individually sampled on 55-pF sampling capacitors and the device converts for the voltage difference between
the two sampled values: VINP – VINN. The single-ended signal range is 0 V to VREF.
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Feature Description (continued)
Figure 45 shows an equivalent circuit of the input sampling stage. The sampling switch is represented by a 96-Ω
resistance in series with the ideal switch; see the ADC Input Driver section for more details on the recommended
driving circuits.
96
Device in Hold Mode
AINP
4 pF
55 pF
REF
4 pF
55 pF
96
GND
GND
AINN
Figure 45. Input Sampling Stage Equivalent Circuit
Figure 44 and Figure 45 illustrate electrostatic discharge (ESD) protection diodes to REF and GND from both
analog inputs. Make sure that these diodes do not turn on by keeping the analog inputs within the specified
range.
9.3.2 Reference
The device operates with an external reference voltage and switches binary-weighted capacitors onto the
reference terminal (REF pin) during the conversion process. The switching frequency is proportional to the
internal conversion clock frequency but the dynamic charge requirements are a function of the absolute value of
the input voltage and reference voltage. This dynamic load must be supported by a reference driver circuit
without degrading the noise and linearity performance of the device. During the acquisition process, the device
automatically powers down and does not take any dynamic current from the external reference source. The basic
circuit diagram for such a reference driver circuit for precision ADCs is shown in Figure 46; see the ADC
Reference Driver section for more details on the application circuits.
RREF_FLT
Buffer
CREF_FLT
RBUF_FLT
Voltage
Reference
REF
CBUF_FLT
ADC
Figure 46. Reference Driver Schematic
9.3.3 Clock
The device uses an internal clock for conversion. Conversion duration may vary but is bounded by the minimum
and maximum value of tconv, as specified in the Timing Requirements section. An external SCLK is only used for
a serial data read operation. Data are read after a conversion completes and when the device is in acquisition
phase for the next sample.
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Feature Description (continued)
9.3.4 ADC Transfer Function
The ADS8864 is a unipolar, single-ended input device. The device output is in straight binary format.
Figure 47 shows ideal characteristics for the device. The full-scale range for the ADC input (AINP – AINN) is
equal to the reference input voltage to the ADC (VREF). One LSB is equal to [(VREF / 216)].
ADC Code (Hex)
FFFF
8000
7FFF
0001
0000
VIN
1 LSB
VREF/2
VREF
Single-Ended Analog Input
(AINP ± AINN)
Figure 47. Single-Ended Transfer Characteristics
9.4 Device Functional Modes
The ADS8864 is a low pin-count device. However, the device offers six different options for interfacing with the
digital host.
These options can be broadly classified as being either CS mode (in either a 3- or 4-wire interface) or daisychain mode. The device operates in CS mode if DIN is high at the CONVST rising edge. If DIN is low at the
CONVST rising edge, or if DIN and CONVST are connected together, the device operates in daisy-chain mode.
In both modes, the device can either operate with or without a busy indicator, where the busy indicator is a bit
preceding the output data bits that can be used to interrupt the digital host and trigger the data transfer.
The 3-wire interface in CS mode is useful for applications that need galvanic isolation on-board. The 4-wire
interface in CS mode allows the user to sample the analog input independent of the serial interface timing and,
therefore, allows easier control of an individual device while having multiple, similar devices on-board. The daisychain mode is provided to hook multiple devices in a chain similar to a shift register and is useful in reducing
component count and the number of signal traces on the board.
9.4.1 CS Mode
CS mode is selected if DIN is high at the CONVST rising edge. There are six different interface options available
in this mode: 3-wire CS mode without a busy indicator, 3-wire CS mode with a busy indicator, 4-wire CS mode
without a busy indicator, and 4-wire CS mode with a busy indicator. The following sections discuss these
interface options in detail.
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Device Functional Modes (continued)
9.4.1.1 3-Wire CS Mode Without a Busy Indicator
This interface option is most useful when a single ADC is connected to an SPI-compatible digital host. In this
interface option, DIN can be connected to DVDD and CONVST functions as CS (as shown in Figure 48). As
shown in Figure 49, a CONVST rising edge forces DOUT to 3-state, samples the input signal, and causes the
device to enter a conversion phase. Conversion is done with the internal clock and continues regardless of the
state of CONVST. As a result, CONVST (functioning as CS) can be pulled low after the start of the conversion to
select other devices on the board. However, CONVST must return high before the minimum conversion time
(tconv-min) elapses and is held high until the maximum possible conversion time (tconv-max) elapses. A high level on
CONVST at the end of the conversion ensures the device does not generate a busy indicator.
DVDD
DIN
CONVST
CNV
SCLK
CLK
DOUT
SDI
ADC
Digital Host
Figure 48. Connection Diagram: 3-Wire CS Mode Without a Busy Indicator (DIN = 1)
1/fsample
DIN = HIGH
CONVST = 1
CONVST
œœ
SCLK
1
DOUT
D15
2
3
D14
D13
14
15
16
D1
D0
œœ
D2
œœ
tACQ
tconv-max
tconv-min
ADC
STATE
Acquiring
Sample N
Conversion Result of Sample N Clocked-out
while Acquiring Sample N+1
Converting
Sample N
End-of-Conversion
Figure 49. Interface Timing Diagram: 3-Wire CS Mode Without a Busy Indicator (DIN = 1)
When conversion is complete, the device enters an acquisition phase and powers down. CONVST (functioning
as CS) can be brought low after the maximum conversion time (tconv-max) elapses. On the CONVST falling edge,
DOUT comes out of 3-state and the device outputs the MSB of the data. The lower data bits are output on
subsequent SCLK falling edges. Data can be read at either SCLK falling or rising edges. Note that with any
SCLK frequency, reading data at SCLK falling edge requires the digital host to clock in the data during the
th_CK_DO-min time frame. DOUT goes to 3-state after the 16th SCLK falling edge or when CONVST goes high,
whichever occurs first.
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Device Functional Modes (continued)
9.4.1.2 3-Wire CS Mode With a Busy Indicator
This interface option is most useful when a single ADC is connected to an SPI-compatible digital host and an
interrupt-driven data transfer is desired. In this interface option, DIN can be connected to DVDD and CONVST
functions as CS (as shown in Figure 50). The pull-up resistor on the DOUT pin ensures that the IRQ pin of the
digital host is held high when DOUT goes to 3-state. As shown in Figure 51, a CONVST rising edge forces
DOUT to 3-state, samples the input signal, and causes the device to enter a conversion phase. Conversion is
done with the internal clock and continues regardless of the state of CONVST. As a result, CONVST (functioning
as CS) can be pulled low after the start of the conversion to select other devices on the board. However,
CONVST must be pulled low before the minimum conversion time (tconv-min) elapses and must remain low until
the maximum possible conversion time (tconv-max) elapses. A low level on the CONVST input at the end of a
conversion ensures the device generates a busy indicator.
DVDD
CNV
CONVST
CLK
SCLK
DIN
DVDD
DOUT
SDI
ADC
IRQ
Digital Host
Figure 50. Connection Diagram: 3-Wire CS Mode With a Busy Indicator
1/fsample
DIN = DVDD
CONVST
CONVST = 0
œœ
SCLK
1
2
3
D15
D14
15
16
17
D1
D0
œœ
SDO Pulled-up
DOUT
BUSY
D2
œœ
tACQ
tconv-max
tconv-min
ADC
STATE
Acquiring
Sample N
Conversion Result of Sample N Clocked-out
while Acquiring Sample N+1
Converting
Sample N
End-of-Conversion
Figure 51. Interface Timing Diagram: 3-Wire CS Mode With a Busy Indicator (DIN = 1)
When conversion is complete, the device enters an acquisition phase and powers down, DOUT comes out of 3state, and the device outputs a busy indicator bit (low level) on the DOUT pin. This configuration provides a highto-low transition on the IRQ pin of the digital host. The data bits are clocked out, MSB first, on the subsequent
SCLK falling edges. Data can be read at either SCLK falling or rising edges. Note that with any SCLK frequency,
reading data at SCLK falling edge requires the digital host to clock in the data during the th_CK_DO-min time frame.
DOUT goes to 3-state after the 17th SCLK falling edge or when CONVST goes high, whichever occurs first.
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Device Functional Modes (continued)
9.4.1.3 4-Wire CS Mode Without a Busy Indicator
This interface option is useful when one or more ADCs are connected to an SPI-compatible digital host.
Figure 52 shows the connection diagram for single ADC; see Figure 54 for the connection diagram for two ADCs.
CS
CNV
DIN
CONVST
DOUT
SDI
SCLK
CLK
ADC
Digital Host
Figure 52. Connection Diagram: Single ADC With 4-Wire CS Mode Without a Busy Indicator
In this interface option, DIN is controlled by the digital host and functions as CS. As shown in Figure 53, with DIN
high, a CONVST rising edge selects CS mode, forces DOUT to 3-state, samples the input signal, and causes the
device to enter a conversion phase. In this interface option, CONVST must be held at a high level from the start
of the conversion until all data bits are read. Conversion is done with the internal clock and continues regardless
of the state of DIN. As a result, DIN (functioning as CS) can be pulled low to select other devices on the board.
However, DIN must be pulled high before the minimum conversion time (tconv-min) elapses and remains high until
the maximum possible conversion time (tconv-max) elapses. A high level on DIN at the end of the conversion
ensures the device does not generate a busy indicator.
1/fsample
tconv-max
tACQ
tconv-min
CONVST
DIN = 1
DIN
œœ
SCLK
1
2
DOUT
D15
D14
15
16
œœ
ADC
STATE
End-ofConversion
Acquiring
Sample N
D1
D0
œœ
Read Sample N
Converting
Sample N
Acquiring Sample N+1
Figure 53. Interface Timing Diagram: Single ADC With 4-Wire CS Mode Without a Busy Indicator
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Device Functional Modes (continued)
When conversion is complete, the device enters acquisition phase and powers down. DIN (functioning as CS)
can be brought low after the maximum conversion time (tconv-max) elapses. On the DIN falling edge, DOUT comes
out of 3-state and the device outputs the MSB of the data. The lower data bits are output on subsequent SCLK
falling edges. Data can be read at either SCLK falling or rising edges. Note that with any SCLK frequency,
reading data at SCLK falling edge requires the digital host to clock in the data during the th_CK_DO-min time frame.
DOUT goes to 3-state after the 16th SCLK falling edge or when DIN goes high, whichever occurs first.
As shown in Figure 54, multiple devices can be hooked together on the same data bus. In this case, as shown in
Figure 55, the DIN of the second device (functioning as CS for the second device) can go low after the first
device data are read and the DOUT of the first device is in 3-state.
Care must be taken so that CONVST and DIN are not both low together at any time during the cycle.
CS1
CS2
CNV
CONVST
DIN
CONVST
DIN
DOUT
DOUT
SCLK
SDI
SCLK
CLK
ADC #1
ADC #2
Digital Host
Figure 54. Connection Diagram: Two ADCs With 4-Wire CS Mode Without a Busy Indicator
1/fsample
tconv-max
tACQ
tconv-min
CONVST
DIN = 1
DIN
(ADC 1)
DIN = 1
DIN
(ADC 2)
œœ
SCLK
1
2
DOUT
D15
D14
œœ
15
16
17
18
D0
D15
D14
ADC
STATE
Acquiring
Sample N
Converting
Sample N
32
œœ
œœ
End-ofConversion
31
D1
D1
D0
œœ
œœ
Read Sample N
ADC 1
Read Sample N
ADC 2
Acquiring Sample N+1
Figure 55. Interface Timing Diagram: Two ADCs With 4-Wire CS Mode Without a Busy Indicator
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Device Functional Modes (continued)
9.4.1.4 4-Wire CS Mode With a Busy Indicator
This interface option is most useful when a single ADC is connected to an SPI-compatible digital host and an
interrupt-driven data transfer is desired. In this interface option, the analog sample is least affected by clock jitter
because the CONVST signal (used to sample the input) is independent of the data read operation. In this
interface option, DIN is controlled by the digital host and functions as CS (as shown in Figure 56). The pull-up
resistor on the DOUT pin ensures that the IRQ pin of the digital host is held high when DOUT goes to 3-state. As
shown in Figure 57, when DIN is high, a CONVST rising edge selects CS mode, forces DOUT to 3-state,
samples the input signal, and causes the device to enter a conversion phase. In this interface option, CONVST
must be held high from the start of the conversion until all data bits are read. Conversion is done with the internal
clock and continues regardless of the state of DIN. As a result, DIN (acting as CS) can be pulled low to select
other devices on the board. However, DIN must be pulled low before the minimum conversion time (tconv-min)
elapses and remains low until the maximum possible conversion time (tconv-max) elapses. A low level on the DIN
input at the end of a conversion ensures the device generates a busy indicator.
CS
DIN
CNV
CONVST
CLK
SCLK
DVDD
DOUT
SDI
IRQ
ADC
Digital Host
Figure 56. Connection Diagram: 4-Wire CS Mode With a Busy Indicator
1/fsample
tACQ
tconv-max
tconv-min
CONVST
DIN =0
DIN
œœ
SCLK
1
2
3
D15
D14
15
16
17
D1
D0
œœ
DOUT
ADC
STATE
SDO Pulled-up
Acquiring
Sample N
Converting
Sample N
BUSY
D2
œœ
Conversion Result of Sample N Clocked-out
while Acquiring Sample N+1
Figure 57. Interface Timing Diagram: 4-Wire CS Mode With a Busy Indicator
When conversion is complete, the device enters an acquisition phase and powers down, DOUT comes out of 3state, and the device outputs a busy indicator bit (low level) on the DOUT pin. This configuration provides a highto-low transition on the IRQ pin of the digital host. The data bits are clocked out, MSB first, on the subsequent
SCLK falling edges. Data can be read at either SCLK falling or rising edges. Note that with any SCLK frequency,
reading data at SCLK falling edge requires the digital host to clock in the data during the th_CK_DO-min time frame.
DOUT goes to 3-state after the 17th SCLK falling edge or when DIN goes high, whichever occurs first. Care must
be taken so that CONVST and DIN are not both low together at any time during the cycle.
26
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Device Functional Modes (continued)
9.4.2 Daisy-Chain Mode
Daisy-chain mode is selected if DIN is low at the time of a CONVST rising edge or if DIN and CONVST are
connected together. Similar to CS mode, this mode features operation with or without a busy indicator. The
following sections discuss these interface modes in detail.
9.4.2.1 Daisy-Chain Mode Without a Busy Indicator
This interface option is most useful in applications where multiple ADC devices are used but the digital host has
limited interfacing capability. Figure 58 shows a connection diagram with N ADCs connected in the daisy-chain.
The CONVST pins of all ADCs in the chain are connected together and are controlled by a single pin of the
digital host. Similarly, the SCLK pins of all ADCs in the chain are connected together and are controlled by a
single pin of the digital host. The DIN pin for ADC 1 (DIN-1) is connected to GND. The DOUT pin of ADC 1
(DOUT-1) is connected to the DIN pin of ADC 2 (DIN-2), and so on. The DOUT pin of the last ADC in the chain
(DOUT-N) is connected to the SDI pin of the digital host.
CNV
CONVST
DIN1
DOUT1
SCLK
CONVST
DIN2
CONVST
DOUT2
}
DINN-2
SCLK
CONVST
DOUTN-1
DINN-1
SCLK
DOUTN
SDI
SCLK
CLK
ADC 1
ADC 2
}
ADC N
ADC N 1
Digital Host
Figure 58. Connection Diagram: Daisy-Chain Mode Without a Busy Indicator (DIN = 0)
As shown in Figure 59, the device DOUT pin is driven low when DIN and CONVST are low together. With DIN
low, a CONVST rising edge selects daisy-chain mode, samples the analog input, and causes the device to enter
a conversion phase. In this interface option, CONVST must remain high from the start of the conversion until all
data bits are read. When started, the conversion continues regardless of the state of SCLK, however SCLK must
be low at the CONVST rising edge so that the device does not generate a busy indicator at the end of the
conversion.
tconv-min
1/fsample
tconv-max
tACQ
CONVST
œœ
SCLK
1
2
œœ
15
16
17
18
31
32
DIN-1 = LOW
DOUT-1
& DIN-2
D15
D15
DOUT-2
End-ofConversion
ADC
STATE
Acquiring
6DPSOH µQ¶
Converting
6DPSOH µQ¶
ADC 1 data
œœ
D14
D1
œœ
D14
œœ
D0
D1
D0
ADC 1 data
œœ
D14
D1
œœ
D15
œœ
ADC 2 data
ADC 2 GDWD IRU VDPSOH µQ¶
D0
ADC 1 GDWD IRU VDPSOH µQ¶
$FTXLULQJ 6DPSOH µQ+1¶
Figure 59. Interface Timing Diagram: For Two Devices in Daisy-Chain Mode Without a Busy Indicator
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Device Functional Modes (continued)
At the end of conversion, every ADC in the chain loads its own conversion result into the internal, 16-bit, shift
register and also outputs the MSB bit of this conversion result on its own DOUT pin. All ADCs enter an
acquisition phase and power-down. On every subsequent SCLK falling edge, the internal shift register of each
ADC latches the data available on its DIN pin and shifts out the next bit of data on its DOUT pin. Therefore, the
digital host receives the data of ADC N, followed by the data of ADC N–1, and so on (in MSB-first fashion). A
total of 16 x N SCLK falling edges are required to capture the outputs of all N devices in the chain. Data can be
read at either SCLK falling or rising edges. Note that with any SCLK frequency, reading data at SCLK falling
edge requires the digital host to clock in the data during the th_CK_DO-min time frame.
9.4.2.2 Daisy-Chain Mode With a Busy Indicator
This interface option is most useful in applications where multiple ADC devices are used but the digital host has
limited interfacing capability and an interrupt-driven data transfer is desired. Figure 60 shows a connection
diagram with N ADCs connected in the daisy-chain. The CONVST pins of all ADCs in the chain are connected
together and are controlled by a single pin of the digital host. Similarly, the SCLK pins of all ADCs in the chain
are connected together and are controlled by a single pin of the digital host. The DIN pin for ADC 1 (DIN-1) is
connected to its CONVST. The DOUT pin of ADC 1 (DOUT-1) is connected to the DIN pin of ADC 2 (DIN-2), and
so on. The DOUT pin of the last ADC in the chain (DOUT-N) is connected to the SDI and IRQ pins of the digital
host.
CNV
CONVST
DIN1
DOUT1
SCLK
CONVST
DIN2
DOUT2
CONVST
}
SCLK
DINN-1
DOUTN-1
SCLK
CONVST
DINN
DOUTN
IRQ
SDI
SCLK
CLK
ADC 1
ADC 2
}
ADC N 1
ADC N
Digital Host
Figure 60. Connection Diagram: Daisy-Chain Mode With a Busy Indicator (DIN = 0)
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Device Functional Modes (continued)
As shown in Figure 61, the device DOUT pin is driven low when DIN and CONVST are low together. A CONVST
rising edge selects daisy-chain mode, samples the analog input, and causes the device to enter a conversion
phase. In this interface option, CONVST must remain high from the start of the conversion until all data bits are
read. When started, the conversion continues regardless of the state of SCLK, however SCLK must be high at
the CONVST rising edge so that the device generates a busy indicator at the end of the conversion.
tconv-min
1/fsample
tconv-max
tACQ
CONVST
œœ
SCLK
1
th-DI-CNV
DIN-1 =
CONVST
DOUT-1
& DIN-2
BUSY
BUSY
DOUT-2
End-ofConversion
ADC
STATE
Acquiring
6DPSOH µQ¶
Converting
6DPSOH µQ¶
2
œœ
16
17
18
ADC 1 data
œœ
D15
D1
D0
œœ
D15
œœ
19
32
33
ADC 1 data
œœ
D1
D0
D15
œœ
ADC 2 data
ADC 2 GDWD IRU VDPSOH µQ¶
D14
D1
D0
œœ
ADC 1 GDWD IRU VDPSOH µQ¶
$FTXLULQJ 6DPSOH µQ+1¶
Figure 61. Interface Timing Diagram: For Two Devices in Daisy-Chain Mode With a Busy Indicator
At the end of conversion, every ADC in the chain loads its own conversion result into the internal, 16-bit, shift
register and also forces its DOUT pin high, thereby providing a low-to-high transition on the IRQ pin of the digital
host. All ADCs enter an acquisition phase and power-down. On every subsequent SCLK falling edge, the internal
shift register of each ADC latches the data available on its DIN pin and shifts out the next bit of data on its DOUT
pin. Therefore, the digital host receives the interrupt signal followed by the data of ADC N followed by the data of
ADC N–1, and so on (in MSB-first fashion). A total of (16 × N) + 1 SCLK falling edges are required to capture the
outputs of all N devices in the chain. Data can be read at either SCLK falling or rising edges. With any SCLK
frequency, reading data at the SCLK falling edge requires the digital host to clock in the data during the th_CK_DOmin time frame. The busy indicator bits of ADC 1 to ADC N–1 do not propagate to the next device in the chain.
NOTE
SPI mode-3 (CPOL = 1, CPHA = 1) allows reading the conversion results of N ADCs in 18
× N SCLK cycles because the busy indicator bit is not clocked in by the host.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section details some general principles for designing these circuits, followed by some application circuits
designed using the ADS8864.
10.1.1 ADC Reference Driver
The external reference source to the ADS8864 must provide low-drift and very accurate voltage for the ADC
reference input and support the dynamic charge requirements without affecting the noise and linearity
performance of the device. The output broadband noise of most references can be in the order of a few hundred
μVRMS. Therefore, to prevent any degradation in the noise performance of the ADC, the output of the voltage
reference must be appropriately filtered by using a low-pass filter with a cutoff frequency of a few hundred hertz.
After band-limiting the noise of the reference circuit, the next important step is to design a reference buffer that
can drive the dynamic load posed by the reference input of the ADC. The reference buffer must regulate the
voltage at the reference pin such that the value of VREF stays within the 1-LSB error at the start of each
conversion. This condition necessitates the use of a large capacitor, CBUF_FLT (see Figure 46) for regulating the
voltage at the reference input of the ADC. The amplifier selected to drive the reference pin must have an
extremely low offset and temperature drift with a low output impedance to drive the capacitor at the ADC
reference pin without any stability issues.
10.1.2 ADC Input Driver
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a fly-wheel
RC filter. The amplifier is used for signal conditioning of the input voltage and its low output impedance provides
a buffer between the signal source and the switched capacitor inputs of the ADC. The RC filter helps attenuate
the sampling charge injection from the switched-capacitor input stage of the ADC and functions as an antialiasing
filter to band-limit the wideband noise contributed by the front-end circuit. Careful design of the front-end circuit is
critical to meet the linearity and noise performance of a high-precision, 16-bit ADC such as the ADS8864.
10.1.2.1 Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type as well as the performance
goals of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate
amplifier to drive the inputs of the ADC are:
• Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible
after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance
of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter (see the
Antialiasing Filter section) at the inputs of the ADC. Higher bandwidth also minimizes the harmonic distortion
at higher input frequencies. In order to maintain the overall stability of the input driver circuit, select the
amplifier bandwidth as described in Equation 1:
§
1
Unity Gain Bandwidth t 4 u ¨¨
© 2S u ( RFLT RFLT ) u C FLT
•
30
·
¸¸
¹
(1)
Noise. Noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in
SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data
acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit
must be kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is bandlimited by designing a low cutoff frequency RC filter, as explained in Equation 2.
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Application Information (continued)
§ V 1 _ AM P_ PP ·
¨
¸
NG u 2 u ¨ f
¸¸
6
.
6
¨
©
¹
2
en2 _ RM S u
S
uf
2
3 dB
d
1 VREF
u
u 10
5
2
§ SNR dB ·
¨
¸
20
©
¹
where:
•
•
•
•
•
V1 / f_AMP_PP is the peak-to-peak flicker noise in µV,
en_RMS is the amplifier broadband noise density in nV/√Hz,
f–3dB is the 3-dB bandwidth of the RC filter, and
NG is the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration.
THD AMP d THD ADC
•
(2)
Distortion. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. As a rule of
thumb, to ensure that the distortion performance of the data acquisition system is not limited by the front-end
circuit, the distortion of the input driver must be at least 10 dB lower than the distortion of the ADC, as shown
in Equation 3.
10 dB
(3)
Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal
must settle within an 16-bit accuracy at the device inputs during the acquisition time window. This condition is
critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data sheets specify
the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the desired
accuracy. Therefore, always verify the settling behavior of the input driver by TINA™-SPICE simulations
before selecting the amplifier.
10.1.2.2 Charge-Kickback Filter
The charge-kickback filter is an RC filter at the input pins of the ADC that filters the broadband noise from the
front-end drive circuitry and attenuates the sampling charge injection from the switched-capacitor input stage of
the ADC. As shown in Figure 62, a filter capacitor (CFLT) is connected from each input pin of the ADC to ground.
This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the
internal sample-and-hold capacitors during the acquisition process. Generally, the value of this capacitor must be
at least 20 times the specified value of the ADC sampling capacitance. For the ADS8864, the input sampling
capacitance is equal to 59 pF; therefore, for optimal performance, keep CFLT greater than 590 pF. This capacitor
must be a COG- or NPO-type. The type of dielectric used in COG or NPO ceramic capacitors provides the most
stable electrical properties over voltage, frequency, and temperature changes.
Driving capacitive loads can degrade the phase margin of the input amplifier, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT helps with amplifier stability, but adds distortion as a result of interactions
with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal
frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability of the
driver amplifier and distortion performance of the design. Always verify the stability and settling behavior of the
driving amplifier and charge-kickback filter by a TINA-TI™ SPICE simulation. Keep the tolerance of the selected
resistors less than 1% to keep the inputs balanced.
RFLT ” 22
f
3 dB
2S u R FLT
1
R FLT u CFLT
AINP
CFLT • 590 pF
Device
AINN
GND
RFLT ” 22
Figure 62. Charge-Kickback Filter
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Application Information (continued)
This section describes some common application circuits using the ADS8864. These data acquisition (DAQ)
blocks are optimized for specific input types and performance requirements of the system. For simplicity, powersupply decoupling capacitors are not shown in these circuit diagrams; see the Power-Supply Decoupling section
for suggested guidelines.
10.2 Typical Applications
10.2.1 DAQ Circuit for a 2.5-µs, Full-Scale Step Response
AVDD
AVDD
300
VIN
EN
OUT_F
OUT_S
REF60xx
5m
82
AVDD
GND
AINP
V+
-
47 µF
470 pF
OPA364
+
REF
GND_F
FILT
GND_S
SS
1 µF
ADS8866
+
AINN
GND
VIN
5m
AVDD
GND
GND
GND
16-Bit SAR ADC
INPUT DRIVER
GND
GND
REFERENCE DRIVE CIRCUIT
Figure 63. DAQ Circuit for a 2.5-µs, Full-Scale Step Response
10.2.1.1 Design Requirements
Step input signals are common in multiplexed applications when switching between different channels. In the
worst-case scenario, one channel is at the negative full-scale (NFS) and the other channel is at the positive fullscale (PFS) voltage, in which case the step size is the full-scale range (FSR) of the ADC when the MUX channel
is switched.
Design an application circuit optimized for using the ADS8864 to achieve
• Full-scale step input settling to 16-bit accuracy and
• INL of < ±2 LSB and
• Maximum specified throughput of 400 kSPS
10.2.1.2 Detailed Design Procedure
The application circuit is shown in Figure 63.
In such applications, the primary design requirement is to ensure that the full-scale step input signal settles to 16bit accuracy at the ADC inputs. This condition is critical to achieve the excellent linearity specifications of the
ADC. Therefore, the bandwidth of the charge-kickback RC filter must be large enough to allow optimal settling of
the input signal during the ADC acquisition time. The filter capacitor helps reduce the sampling charge injection
at the ADC inputs, but degrades the phase margin of the driving amplifier, thereby leading to stability issues.
Amplifier stability is maintained by the series isolation resistor.
During the conversion process, binary-weighted capacitors are switched onto the REF pin. In order to support
this dynamic load the output of the voltage reference must be buffered with a low-output impedance (highbandwidth) buffer.
The REF60xx family of voltage references are able to maintain an output voltage within 1 LSB (16-bit) with
minimal droop, even during the first conversion while driving the REF pin of the ADS8864. This feature is useful
in burst-mode, event-triggered, equivalent-time sampling, and variable-sampling-rate data-acquisition systems.
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Typical Applications (continued)
For the input driving amplifiers, key specifications include rail-to-rail input and output swing, high bandwidth, high
slew rate, and fast settling time. The CMOS amplifier meets all these specification requirements for this circuit
with a single-supply and low quiescent current. The component values of the antialiasing filter are selected to
meet the settling requirements of the system as well as to maintain the stability of the input driving amplifiers.
10.2.2 DAQ Circuit for Lowest Distortion and Noise Performance at 400 kSPS
AVDD
AVDD
1k
1k
VIN
EN
OUT_F
VIN
OUT_S
GND
5m
REF60xx
4.7
AVDD
OPA836
GND
+
REF
AINP
V+
+
47 µF
10 nF
GND_F
FILT
GND_S
SS
1 µF
ADS886x
4.7
AINN
AVDD
GND
VCM
5m
GND
GND
GND
INPUT DRIVER
16-Bit SAR ADC
GND
GND
REFERENCE DRIVE CIRCUIT
Figure 64. DAQ Circuit for Lowest Distortion and Noise at 400 kSPS
10.2.2.1 Design Requirements
Design an application circuit optimized for using the ADS8864 to achieve
• > 94.5-dB SNR, < –110-dB THD and
• ± 1-LSB linearity and
• maximum specified throughput of 400 kSPS
10.2.2.2 Detailed Design Procedure
This section describes an application circuit (as shown in Figure 64) optimized for using the ADS8864 with lowest
distortion and noise performance at a throughput of 400 kSPS. The input signal is processed through a highbandwidth, low-distortion amplifier in an inverting gain configuration and a low-pass RC filter before being fed into
the ADC.
As a rule of thumb, the distortion from the input driver must be at least 10 dB less than the ADC distortion. The
distortion resulting from variation in the common-mode signal is eliminated by using the amplifier in an inverting
gain configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates
the requirement of a rail-to-rail swing at the input of the amplifier. Therefore, the circuit uses the low-power
OPA836 as an input driver, which provides exceptional ac performance because of its extremely low-distortion,
high-bandwidth specifications.
In addition, the components of the charge-kickback filter are such that the noise from the front-end circuit is kept
low without adding distortion to the input signal.
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Typical Applications (continued)
10.2.3 Ultralow-Power DAQ Circuit at 10 kSPS
REFERENCE DRIVE CIRCUIT
1k
GND
-
AVDD
1k
REF3330
10 k
IN
+
OUT
GND
47 …F
+
OPA333
1 …F
10
AVDD
GND
GND
GND
INPUT DRIVER
GND
16-Bit SAR ADC
20 k
2.4 nF
AVDD
GND
REF
-
AVDD
20 k
AINP
+
+
VIN
OPA333
ADS886x
2.4 nF
AINN
AVDD
GND
GND
GND
Figure 65. Ultralow-Power DAQ Circuit at 10 kSPS
10.2.3.1 Design Requirements
Portable and battery-powered applications require ultralow-power consumption and do not need very high
throughput from the ADC.
Design a single-supply, data acquisition circuit optimized for using the ADS8864 to achieve
• ENOB > 14.5 bits and
• Ultralow-power consumption of < 1 mW at throughput of 10 kSPS
10.2.3.2 Detailed Design Procedure
The data acquisition circuit shown in Figure 65 is optimized for using the ADS8864 at a reduced throughput of
10 kSPS
In order to save power, this circuit is operated on a single 3.3-V supply. The circuit uses the OPA333 with a
maximum quiescent current of 28 µA in order to drive the ADC input. The input amplifier is configured in a
modified unity-gain buffer configuration. The filter capacitor at the ADC inputs attenuates the sampling charge
injection noise from the ADC but effects the stability of the input amplifiers by degrading the phase margin. This
attenuation requires a series isolation resistor to maintain amplifier stability. The value of the series resistor is
directly proportional to the open-loop output impedance of the driving amplifier to maintain stability, which is high
(in the order of kΩ) in the case of low-power amplifiers such as the OPA333. Therefore, a high value of 1 kΩ is
selected for the series resistor at the ADC inputs. However, this series resistor creates an additional voltage drop
in the signal path, thereby leading to linearity and distortion issues. The dual-feedback configuration used in
Figure 65 corrects for this additional voltage drop and maintains system performance at ultralow-power
consumption.
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11 Power Supply Recommendations
The device has two separate power supplies: AVDD and DVDD. The internal circuits of the device operate on
AVDD; DVDD is used for the digital interface. AVDD and DVDD can be independently set to any value within the
permissible range. During normal operation, if the voltage on the AVDD supply drops below the AVDD minimum
specification, then TI recommends ramping the AVDD supply down to ≤ 0.7 V before power up. Also, during
power-up, AVDD must monotonously rise to the desired operating voltage above the minimum AVDD
specification.
11.1 Power-Supply Decoupling
Decouple the AVDD and DVDD pins with GND, using individual 1-µF decoupling capacitors placed in close
proximity to the pin, as shown in Figure 66.
Digital
Supply
REF
Analog
Supply
DVDD
AVDD
1 µF
1 µF
DIN
AINP
SCLK
AINN
DOUT
GND
CONVST
Figure 66. Supply Decoupling
11.2 Power Saving
The device has an auto power-down feature that powers down the internal circuitry at the end of every
conversion. Referring to Figure 67, the input signal is acquired on the sampling capacitors when the device is in
a power-down state (tacq); at the same time, the result for the previous conversion is available for reading. The
device powers up on the start of the next conversion. During conversion phase (tconv), the device also consumes
current from the reference source (connected to the REF pin).
tTHROUGHPUT
Device Phase
tCONV
tACQ
œœ
IREF
tACQ
~50000X
~50000X
œœ
IAVDD
tCONV
2 x tTHROUGHPUT
~1200X
~1200X
~2X
IAVG(AVDD+REF)
Figure 67. Power Scaling With Throughput
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Power Saving (continued)
The conversion time, tconv, is independent of the SCLK frequency. When operating the device at speeds lower
than the maximum rated throughput, the conversion time, tconv, does not change; the device spends more time in
power-down state. Therefore, as shown in Figure 68, the device power consumption from the AVDD supply and
the external reference source is directly proportional to the speed of operation. Extremely low AVDD power-down
current (50 nA, typical) and extremely low external reference leakage current (250 nA, typical), make this device
ideal for very low throughput applications (such as pulsed measurements).
Analog Supply Current (mA)
1
0.8
0.6
0.4
0.2
0
40
100
160
220
280
Throughput (kSPS)
340
400
C03
Figure 68. Power Scaling With Throughput
36
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12 Layout
12.1 Layout Guidelines
Figure 69 shows a board layout example for the device. Appropriate layout that interconnects accompanying
capacitors and converters with low inductance is critical for achieving optimum performance. Thus, a PCB board
with at least four layers is recommended to keep all critical components on the top layer and interconnected to a
solid (low inductance) analog ground plane at the subsequent inner layer using 15-mil vias. Avoid crossing digital
lines with the analog signal path and keep the analog input signals and the reference input signals away from
noise sources. As shown in Figure 69, the analog input and reference signals are routed on the left side of the
board and the digital connections are routed on the right side of the device.
As a result of dynamic currents during conversion and data transfer, each supply pin (AVDD and DVDD) must
have a decoupling capacitor to keep the supply voltage stable. To maximize decoupling capabilities, inductance
between each supply capacitor and the supply pin of the converter is kept less than 5 nH by placing the
capacitor within 0.2-inches from the pin and connecting it with 20-mil traces and a 15-mil grounding via, as
shown in Figure 69. TI recommends using one 1-μF ceramic capacitor at each supply pin. Avoid placing vias
between the supply pin and its decoupling capacitor.
Dynamic currents are also present at the REF pin during the conversion phase and very good decoupling is
critical to achieve optimum performance. The inductance between the reference capacitor and the REF pin is
kept less than 2 nH by placing the capacitor within 0.1-inches from the pin and connecting it with 20-mil traces
and multiple 15-mil grounding vias, as shown in Figure 69. A single, 10-μF, X7R-grade, 0805-size, ceramic
capacitor with at least a 10-V rating is recommended for good performance over the rated temperature range.
Avoid using additional lower value capacitors because the interactions between multiple capacitors may affect
the ADC performance at higher sampling rates. A small, 0.1-Ω to 0.47-Ω, 0603-size resistor placed in series with
the reference capacitor (as shown in Figure 69) keeps the overall impedance low and constant, especially at very
high frequencies.
The fly-wheel RC filters are placed immediately next to the input pins. Among ceramic surface-mount capacitors,
COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG
(NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature
changes.
R
AVDD
12.2 Layout Example
EF
GND
DVDD
REF
1: REF
Analog Input
GND
DVDD
GND
1PF
1PF
0.1O t 0.47O
AVDD
10PF
GND
47O
10: DVDD
2: AVDD
9: SDI
47O
3: AINP
8: SCLK
4: AINN
7: SDO
5: GND
6: CONVST
GND
SDO
47O
Figure 69. Recommended Layout
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPAx333 1.8-V, micropower, CMOS operational amplifiers, zero-drift series data sheet
• Texas Instruments, THS452x Very Low power, negative rail input, rail-to-rail output, fully differential amplifier
data sheet
• Texas Instruments, THS4281 very low-power, high-speed, rail-to-rail input and output voltage-feedback
operational amplifier data sheet
• Texas Instruments, 1-MHz, micro-power, low-noise, RRIO,1.8-V CMOS operational amplifier precision value
line series data sheet
• Texas Instruments, OPAx350 High-speed, single-supply, rail-to-rail operational amplifiers microamplifier
series data sheet
• Texas Instruments, 1.8V, 7MHz, 90dB CMRR, single-supply, rail-to-rail I/O operational amplifier data sheet
• Texas Instruments, 18-bit data acquisition (DAQ) block optimized for 1-μs full-scale step response reference
guide
• Texas Instruments, 18-Bit, 1-MSPS data acquisition (DAQ) block optimized for lowest power reference guide
• Texas Instruments, 18 bit, 10kSPS data acquisition (DAQ) block optimized for ultra low power < 1 mW
reference guide
• Texas Instruments, 18-Bit, 1MSPS data acquisition block (DAQ) optimized for lowest distortion and noise
reference guide
• Texas Instruments, Ultra Low Power, 18 bit precision ECG data acquisition system reference guide
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
TINA, TINA-TI, E2E are trademarks of Texas Instruments.
SPI is a trademark of Motorola Inc.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
38
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13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS8864IDGS
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
8864
ADS8864IDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
8864
ADS8864IDRCR
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
8864
ADS8864IDRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
8864
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS8864IDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS8864IDRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS8864IDRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS8864IDGSR
VSSOP
DGS
10
2500
367.0
367.0
35.0
ADS8864IDRCR
VSON
DRC
10
3000
367.0
367.0
35.0
ADS8864IDRCT
VSON
DRC
10
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
SCALE 3.200
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
10
1
3.1
2.9
NOTE 3
8X 0.5
2X
2
5
6
B
10X
3.1
2.9
NOTE 4
SEE DETAIL A
0.27
0.17
0.1
C A
1.1 MAX
B
0.23
TYP
0.13
0.25
GAGE PLANE
0 -8
0.15
0.05
0.7
0.4
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
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EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (0.3)
10X (1.45)
(R0.05)
TYP
SYMM
1
10
SYMM
8X (0.5)
6
5
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
10X (0.3)
SYMM
1
(R0.05) TYP
10
SYMM
8X (0.5)
6
5
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DRC 10
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204102-3/M
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