Texas Instruments | DAC8560 16-Bit, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter With 2.5-V, 2-ppm/°C Internal Reference (Rev. C) | Datasheet | Texas Instruments DAC8560 16-Bit, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter With 2.5-V, 2-ppm/°C Internal Reference (Rev. C) Datasheet

Texas Instruments DAC8560 16-Bit, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter With 2.5-V, 2-ppm/°C Internal Reference (Rev. C) Datasheet
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DAC8560
SLAS464C – DECEMBER 2006 – REVISED JANUARY 2018
DAC8560 16-Bit, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter
With 2.5-V, 2-ppm/°C Internal Reference
1 Features
3 Description
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•
•
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The DAC8560 is a low-power, voltage output, 16-bit
digital-to-analog converter (DAC). The DAC8560
includes a 2.5-V, 2-ppm/°C internal reference
(enabled by default), giving a full-scale output voltage
range of 0 V to 2.5 V. The internal reference has an
initial accuracy of 0.02% and can source up to 20 mA
at the VREF pin. The device is monotonic, provides
very good linearity, and minimizes undesired code-tocode transient voltages (glitch). The DAC8560 uses a
versatile 3-wire serial interface that operates at clock
rates up to 30 MHz. It is compatible with standard
SPI, QSPI, Microwire, and digital-signal-processor
(DSP) interfaces.
1
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•
•
•
•
•
•
•
•
•
Relative Accuracy: 4 LSB
Glitch Energy: 0.15 nV-s
MicroPower Operation: 510 μA at 2.7 V
Internal Reference:
– 2.5-V Reference Voltage (Enabled by Default)
– 0.02% Initial Accuracy
– 2-ppm/°C Temperature Drift (Typical)
– 5-ppm/°C Temperature Drift (Maximum)
– 20-mA Sink/Source Capability
Power-On Reset to Zero
Power Supply: 2.7 V to 5.5 V
16-Bit Monotonic Over Temperature Range
Settling Time: 10 μs to ±0.003% FSR
Low-Power Serial Interface With SchmittTriggered Inputs
On-Chip Output Buffer Amplifier With Rail-to-Rail
Operation
Power-Down Capability
Drop-In Compatible With DAC8531/01 and
DAC8550 /51
Temperature Range: –40°C to +105°C
Available in a Tiny 8-Pin VSSOP Package
The DAC8560 incorporates a power-on-reset (POR)
circuit that ensures the DAC output powers up at zero
scale and remains there until a valid code is written to
the device. The DAC8560 contains a power-down
feature, accessed over the serial interface, that
reduces the current consumption of the device to
1.2 μA at 5 V.
The low-power consumption, internal reference, and
small footprint make this device ideal for portable,
battery-operated equipment. The power consumption
is 2.6 mW at 5 V, reducing to 6 μW in power-down
mode.
The DAC8560 is available in an 8-pin VSSOP
package.
2 Applications
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•
•
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Device Information(1)
Process Control
Data Acquisition Systems
Closed-Loop Servo-Control
PC Peripherals
Portable Instrumentation
PART NUMBER
DAC8560
PACKAGE
VSSOP (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
VDD
VFB
VREF
VOUT
Ref (+)
16-Bit DAC
2.5V
Reference
16
DAC Register
16
SYNC
SCLK
Shift Register
PWD
Control
Resistor
Network
DIN
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC8560
SLAS464C – DECEMBER 2006 – REVISED JANUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
1
1
1
2
3
4
Absolute Maximum Ratings ..................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics........................................... 5
Timing Requirements ................................................ 7
Typical Characteristics: Internal Reference .............. 8
Typical Characteristics: DAC at VDD = 5 V ............. 10
Typical Characteristics: DAC at VDD = 3.6 V .......... 15
Typical Characteristics: DAC at VDD = 2.7 V ........ 15
Detailed Description ............................................ 19
7.1 Overview ................................................................. 19
7.2 Functional Block Diagram ....................................... 19
7.3
7.4
7.5
7.6
8
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
19
24
25
26
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Applications ................................................ 27
9 Power Supply Recommendations...................... 32
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 32
11 Device and Documentation Support ................. 33
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
33
12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (November 2011) to Revision C
•
Page
Added topnav link for TI Designs, Device Information, ESD Ratings, Recommended Operating Conditions, and
Thermal Information tables, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision A (November 2011) to Revision B
Page
•
Changed Revision date from A, May 2011 to B, November 2011 ......................................................................................... 1
•
Changed "Zero-code error drift" in the ELEC CHARA table, TYP from ±20 to ±4 ................................................................. 5
Changes from Original (December 2006) to Revision A
Page
•
Changed Output Voltage parameter min/max values from 2.4995 and 2.5005 to 2.4975 and 2.5025, respectively............. 6
•
Changed Initial Accuracy parameter min/max values from –0.02 and 0.02 to –0.1 and 0.1, respectively ............................ 6
Changes from Revision A (May 2011) to Revision B
Page
•
Changed Revision date from A, May 2011 to B, November 2011 ......................................................................................... 1
•
Changed "Zero-code error drift" in the ELEC CHARA table, TYP from ±20 to ±4 ................................................................. 5
2
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SLAS464C – DECEMBER 2006 – REVISED JANUARY 2018
5 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
VDD
1
VREF
2
8
GND
7
DIN
DAC8560
VFB
3
6
SCLK
VOUT
4
5
SYNC
Pin Functions
PIN
NO.
NAME
I/O
1
VDD
PWR
2
VREF
I/O
DESCRIPTION
Power supply input, 2.7 V to 5.5 V
Reference voltage input/output
3
VFB
I
Feedback connection for the output amplifier. For voltage output operation, tie to VOUT externally.
4
VOUT
O
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
5
SYNC
I
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data.
When SYNC goes LOW, it enables the input shift register, and data is sampled on subsequent falling
clock edges. The DAC output updates following the 24th clock. If SYNC is taken HIGH before the
24th clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by
the DAC8560. Schmitt-Trigger logic input.
6
SCLK
I
Serial clock input, Schmitt-Trigger logic input.
7
DIN
I
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial
clock input. Schmitt-Trigger logic input.
8
GND
GND
Ground reference point for all circuitry on the device.
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SLAS464C – DECEMBER 2006 – REVISED JANUARY 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VDD to GND
–0.3
6
V
Digital input voltage to GND
–0.3
VDD + 0.3
V
VOUT to GND
–0.3
VDD + 0.3
V
Power dissipation (DGK)
(TJ(MAX) – TA) / RθJA
Operating temperature
–40
Junction temperature, TJ(MAX)
Storage temperature, Tstg
(1)
–65
105
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
Supply voltage (VDD to GND)
Digital input voltage (DIN, SCLK, and SYNC)
VFB
Output amplifier feedback input
TA
Operating ambient temperature
NOM
MAX
UNIT
2.7
5.5
V
0
VDD
V
125
°C
VOUT
V
–40
6.4 Thermal Information
DAC8560
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
206
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
44
°C/W
RθJB
Junction-to-board thermal resistance
94.2
°C/W
ψJT
Junction-to-top characterization parameter
10.2
°C/W
ψJB
Junction-to-board characterization parameter
92.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLAS464C – DECEMBER 2006 – REVISED JANUARY 2018
6.5 Electrical Characteristics
VDD = 2.7 V to 5.5 V, –40°C to +105°C range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±4
±12
LSB
STATIC PERFORMANCE (1)
Resolution
16
Relative accuracy
Measured by line passing through
codes 485 and 64714
Differential nonlinearity
16-bit Monotonic
DAC8560A, DAC8560C
DAC8560B, DAC8560D
Zero-code error
Full-scale error
Measured by line passing through codes 485 and 64714.
Gain error
Zero-code error drift
Gain temperature coefficient
PSRR
Bits
±4
±8
LSB
±0.5
±1
LSB
±5
±12
mV
±0.2
±0.5
% of FSR
±0.05
±0.2
% of FSR
±4
μV/°C
VDD = 5 V
±1
VDD = 2.7 V
±3
ppm of
FSR/°C
1
mV/V
Power supply rejection ratio
Output unloaded
OUTPUT CHARACTERISTICS (2)
Output voltage range
Output voltage settling time
0
To ±0.003% FSR, 0200h to FD00h, RL = 2 kΩ,
0 pF < CL < 200 pF
RL = 2 kΩ, CL = 500 pF
8
10
V
μs
12
Slew rate
Capacitive load stability
VREF
1.8
RL = ∞
470
V/μs
pF
RL = 2 kΩ
1000
Code change glitch impulse
1 LSB change around major carry
0.15
nV-s
Digital feedthrough
SCLK toggling, SYNC high
0.15
nV-s
DC output impedance
At mid-code input
Short-circuit current
Power-up time
1
VDD = 5 V
50
VDD = 3 V
20
Coming out of power-down mode VDD = 5 V
2.5
Coming out of power-down mode VDD = 3 V
5
Ω
mA
μs
AC PERFORMANCE (2)
SNR
88
dB
THD
TA = 25°C, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz,
1st 19 harmonics removed for SNR calculation
–77
dB
79
dB
77
dB
DAC output noise density
TA = 25°C, at mid-code input, fOUT = 1 kHz
170
nV/√Hz
DAC output noise
TA = 25°C, at mid-code input, 0.1 Hz to 10 Hz
50
μVPP
SFDR
SINAD
(1)
(2)
Linearity calculated using a reduced code range of 485 to 64714; output unloaded.
Ensured by design and characterization, not production tested.
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Electrical Characteristics (continued)
VDD = 2.7 V to 5.5 V, –40°C to +105°C range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE OUTPUT
Output voltage
TA = 25°C
2.4975
2.5
2.5025
Initial accuracy
TA = 25°C
–0.1%
±0.004%
0.1%
Output voltage temperature
drift
DAC8560A, DAC8560B (3)
5
25
DAC8560C, DAC8560D (4)
2
5
Output voltage noise
f = 0.1 Hz to 10 Hz
Output voltage noise density
(high-frequency noise)
16
TA = 25°C, f = 1 MHz, CL = 0 μF
125
TA = 25°C, f = 1 MHz, CL = 1 μF
20
TA = 25°C, f = 1 MHz, CL = 4 μF
V
ppm/°C
μVPP
nV/√Hz
2
Load regulation, sourcing (5)
TA = 25°C
30
μV/mA
Load regulation, sinking (5)
TA = 25°C
15
μV/mA
±20
mA
Output current load
capability (2)
Line regulation
TA = 25°C
10
μV/V
Long-term stability/drift
(aging) (5)
TA = 25°C, time = 0 to 1900 hours
50
ppm
Thermal hysteresis (5)
First cycle
100
Additional cycles
ppm
25
REFERENCE
Internal reference current
consumption
VDD = 5.5 V
360
VDD = 3.6 V
348
External reference current
External VREF = 2.5 V, if internal reference is disabled
Reference input range
20
0
Reference input impedance
LOGIC INPUTS
μA
μA
VDD
125
V
kΩ
(2)
Input current
±1
VINL
Logic input LOW
voltage
VDD = 5 V
VINH
Logic input HIGH
voltage
VDD = 5 V
2.4
VDD = 3 V
2.1
μA
0.8
VDD = 3 V
0.6
V
V
Pin capacitance
3
pF
5.5
V
POWER REQUIREMENTS
VDD
2.7
Normal mode
IDD
(6)
All power-down
modes
Normal mode
Power
dissipatio
n (6)
All power-down
modes
VDD = 3.6 V to 5.5 V, VIH = VDD and VIL = GND
0.53
0.85
VDD = 2.7 V to 3.6 V, VIH = VDD and VIL = GND
0.51
0.84
VDD = 3.6 V to 5.5 V, VIH = VDD and VIL = GND
1.2
2.5
VDD = 2.7 V to 3.6 V, VIH = VDD and VIL = GND
0.7
2.2
VDD = 3.6 V to 5.5 V
2.6
4.7
VDD = 2.7 V to 3.6 V
1.5
3
VDD = 3.6 V to 5.5 V
6
14
VDD = 2.7 V to 3.6 V
2
8
mA
μA
mW
μW
TEMPERATURE RANGE
Specified performance
(3)
(4)
(5)
(6)
6
–40
105
°C
Reference is trimmed and tested at room temperature, and is characterized from –40°C to +120°C.
Reference is trimmed and tested at two temperatures (25°C and 105°C), and is characterized from –40°C to +120°C.
Explained in more detail in Application and Implementation.
Input code = 32768, reference current included, no load.
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6.6 Timing Requirements
VDD = 2.7 V to 5.5 V, all specifications –40°C to +105°C (unless otherwise noted) (1)
(2)
PARAMETER
t1
(3)
SCLK cycle time
t2
SCLK HIGH time
t3
SCLK LOW time
t4
SYNC to SCLK rising edge setup time
t5
Data setup time
t6
Data hold time
t7
SCLK falling edge to SYNC rising edge
t8
Minimum SYNC HIGH time
t9
24th SCLK falling edge to SYNC falling edge
t10
SYNC rising edge to 24th SCLK falling edge
(for successful SYNC interrupt)
(1)
(2)
(3)
MIN
VDD = 2.7 V to 3.6 V
50
VDD = 3.6 V to 5.5 V
33
VDD = 2.7 V to 3.6 V
13
VDD = 3.6 V to 5.5 V
13
VDD = 2.7 V to 3.6 V
22.5
VDD = 3.6 V to 5.5 V
13
VDD = 2.7 V to 3.6 V
0
VDD = 3.6 V to 5.5 V
0
VDD = 2.7 V to 3.6 V
5
VDD = 3.6 V to 5.5 V
5
VDD = 2.7 V to 3.6 V
4.5
VDD = 3.6 V to 5.5 V
4.5
VDD = 2.7 V to 3.6 V
0
VDD = 3.6 V to 5.5 V
0
VDD = 2.7 V to 3.6 V
50
VDD = 3.6 V to 5.5 V
33
VDD = 2.7 V to 3.6 V
100
VDD = 3.6 V to 5.5 V
100
VDD = 2.7 V to 3.6 V
15
VDD = 3.6 V to 5.5 V
15
NOM
MAX UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
All input signals are specified with tR = tF = 3 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH) / 2.
See Figure 1.
Maximum SCLK frequency is 3 0MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.
t9
t1
SCLK
1
24
t8
t3
t4
t2
t7
SYNC
t10
t6
t5
DIN
DB23
DB0
DB23
Figure 1. Serial Write Operation
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6.7 Typical Characteristics: Internal Reference
2.503
2.503
2.502
2.502
2.501
2.501
VREF (V)
VREF (V)
At TA = 25°C, unless otherwise noted.
2.500
2.499
2.500
2.499
2.498
2.498
10 Units Shown
2.497
-40
-20
0
20
40
60
100
13 Units Shown
2.497
-40
120
-20
0
20
Temperature (°C)
40
60
80
100
120
Temperature (°C)
Figure 2. Internal Reference Voltage vs Temperature
(Grades C and D)
Figure 3. Internal Reference Voltage vs Temperature
(Grades A and B)
40
30
Typ: 5ppm/°C
Max: 25ppm/°C
Typ: 2ppm/°C
Max: 5ppm/°C
Population (%)
Population (%)
30
20
20
10
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1
5.0
3
Temperature Drift (ppm/°C)
7
9
11
13
15
17
19
Temperature Drift (ppm/°C)
Figure 4. Reference Output Temperature Drift (–40°C to
120°C, Grades C and D)
Figure 5. Reference Output Temperature Drift (–40°C to
120°, Grades A and B)
200
40
Typ: 1.2ppm/°C
Max: 3ppm/°C
See the Applications Information
section for more information
150
100
Drift (ppm)
30
Population (%)
5
20
10
50
0
-50
Average
-100
-150
-200
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
300
600
900
1200
1800
1500
Time (Hours)
Temperature Drift (ppm/°C)
1900
20 Units Shown
0
Explained in more detail in Application and Implementation .
Figure 6. Reference Output Temperature Drift (0°C to 120°C,
Grades C and D)
Figure 7. Long-Term Stability/Drift
(1)
(1)
8
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Typical Characteristics: Internal Reference (continued)
At TA = 25°C, unless otherwise noted.
400
See the Applications Information
section for more information
See the Applications Information
section for more information
16mVPP
VNOISE (4mV/div)
Vn (nV/ÖHz)
300
VDD = 5V
Reference Unbuffered
CREF = 0mF
200
100
CREF = 4mF
0
10
100
1k
10k
100k
Time (2s/div)
1M
Frequency (Hz)
Explained in more detail in Application and Implementation.
Explained in more detail in Application and Implementation.
Figure 9. Internal Reference Noise 0.1 Hz to 10 Hz
Figure 8. Internal Reference Noise Density vs Frequency
2.504
2.504
2.503
2.503
-40°C
2.502
2.502
15mV/mA (sinking)
-40°C
2.501
+25°C
2.500
2.499
VREF (V)
VREF (V)
15mV/mA (sinking)
+25°C
2.500
2.499
30mV/mA (sourcing)
+120°C
2.498
2.501
2.498
30mV/mA (sourcing)
2.497
2.497
2.496
-25
2.496
-25
-20
-15
-10
-5
0
5
10
15
20
25
+120°C
-20
-15
-10
-5
ILOAD (mA)
Figure 10. Internal Reference Voltage vs Load Current
(Grades C and D)
5
10
15
20
25
Figure 11. Internal Reference Voltage vs Load Current
(Grades A and B)
2.504
2.504
2.503
2.503
2.502
-40°C
2.502
-40°C
< 10mV/V
2.501
+25°C
2.500
2.499
VREF (V)
VREF (V)
0
ILOAD (mA)
2.501
< 10mV/V
+25°C
2.500
2.499
+120°C
2.498
2.498
2.497
+120°C
2.497
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
VDD (V)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
Figure 12. Internal Reference Voltage vs Supply Voltage
(Grades C and D)
Figure 13. Internal Reference Voltage vs Supply Voltage
(Grades A and B)
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6.8 Typical Characteristics: DAC at VDD = 5 V
At TA = 25°C, external reference used, and DAC output not loaded, unless otherwise noted.
6
4
2
0
-2
-4
-6
LE (LSB)
VDD = 5V, External VREF = 4.99V
1.0
1.0
0.5
0.5
DLE (LSB)
DLE (LSB)
LE (LSB)
6
4
2
0
-2
-4
-6
0
-0.5
VDD = 5V, External VREF = 4.99V
0
-0.5
-1.0
-1.0
0
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
–40°C
25°C
Figure 14. Linearity Error and Differential Linearity Error vs
Digital Input Code
10
VDD = 5V, External VREF = 4.99V
VDD = 5.0V
Internal VREF = 2.5V
5
1.0
DLE (LSB)
Figure 15. Linearity Error and Differential Linearity Error vs
Digital Input Code
Error (mV)
LE (LSB)
6
4
2
0
-2
-4
-6
57344 65536
Digital Input Code
0
0.5
0
-0.5
-5
-40
-1.0
0
8192
16384 24576 32768 40960 49152
57344 65536
0
40
80
Digital Input Code
Temperature (°C)
Figure 16. Linearity Error and Differential Linearity Error vs
Digital Input Code
Figure 17. Zero-Scale Error vs Temperature
120
105°C
10
3.0
VDD = 5.0V
Internal VREF = 2.5V
2.5
5
VDD = 5V
Internal Reference Enabled
DAC Loaded with FFFFh
VOUT (V)
Error (mV)
2.0
0
1.5
1.0
0.5
DAC Loaded with 0000h
-5
-40
0
0
40
80
120
0
5
Temperature (°C)
Figure 18. Full-Scale Error vs Temperature
10
10
15
20
ISOURCE/SINK (mA)
Figure 19. Source and Sink Current Capability
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Typical Characteristics: DAC at VDD = 5 V (continued)
At TA = 25°C, external reference used, and DAC output not loaded, unless otherwise noted.
650
6
VDD = 5.5V
Internal VREF = 2.5V
5
VDD = 5V
Internal Reference Disabled
External VREF = 4.99V
DAC Loaded with FFFFh
3
600
IDD (mA)
VOUT (V)
4
550
2
500
1
DAC Loaded with 0000h
450
0
0
5
10
15
0
20
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
ISOURCE/SINK (mA)
Figure 20. Source and Sink Current Capability
700
650
Figure 21. Power-Supply Current vs Digital Input Code
510
VDD = 5.5V
Internal VREF = 2.5V
VDD = 2.7V to 5.5V
Internal VREF Included
505
IDD (mA)
IDD (mA)
600
550
500
495
500
490
450
400
-40
485
0
40
80
120
2.7
3.1
3.5
3.9
Temperature (°C)
Figure 22. Power-Supply Current vs Temperature
4.7
5.1
5.5
Figure 23. Power-Supply Current vs Power-Supply Voltage
2500
1.4
VDD = 5.5V, Internal VREF Included,
Sweep from 0V to 5V
SCLK Input
(all other digital inputs = GND)
Sweep from 5V to 0V
VDD = 2.7V to 5.5V
1.2
2000
1.0
IDD (mA)
Power-Down Current (mA)
4.3
VDD (V)
0.8
0.6
1500
1000
0.4
500
0.2
0
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
0
VDD (V)
1
2
3
4
5
VLOGIC (V)
Figure 24. Power-Down Current vs Power-Supply Voltage
Figure 25. Power-Supply Current vs Logic Input Voltage
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Typical Characteristics: DAC at VDD = 5 V (continued)
At TA = 25°C, external reference used, and DAC output not loaded, unless otherwise noted.
80
70
-40
VDD = 5.5V
Internal VREF = 2.5V
VDD = 5V, External VREF = 4.9V
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
-50
-60
50
THD (dB)
Occurrences
60
40
30
THD
-70
2nd Harmonic
-80
20
10
-90
0
-100
3rd Harmonic
450
475
500
525
550
575
600
0
1
IDD (mA)
3
4
5
fOUT (kHz)
Figure 26. Power-Supply Current Histogram
Figure 27. Total Harmonic Distortion vs Output Frequency
Trigger Pulse 5V/div
VDD = 5V
Ext VREF = 4.096V
From Code: 0000h
To Code: FFFFh
Rising Edge
1V/div
2
Zoomed Rising Edge
1mV/div
Trigger Pulse 5V/div
VDD = 5V
Ext VREF = 4.096V
From Code: FFFFh
To Code: 0000h
Falling
Edge
1V/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
5-V Rising Edge
5-V Falling Edge
Figure 28. Full-Scale Settling Time
Figure 29. Full-Scale Settling Time
Trigger Pulse 5V/div
Trigger Pulse 5V/div
VDD = 5V
Ext VREF = 4.096V
From Code: CFFFh
To Code: 4000h
VDD = 5V
Ext VREF = 4.096V
From Code: 4000h
To Code: CFFFh
Rising
Edge
1V/div
Zoomed Rising Edge
1mV/div
Falling
Edge
1V/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
5-V Rising Edge
5-V Falling Edge
Figure 30. Half-Scale Settling Time
12
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Figure 31. Half-Scale Settling Time
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Typical Characteristics: DAC at VDD = 5 V (continued)
VDD = 5V
Ext VREF = 4.096V
From Code: 7FFFh
To Code: 8000h
Glitch: 0.08nV-s
VOUT (500mV/div)
VOUT (500mV/div)
At TA = 25°C, external reference used, and DAC output not loaded, unless otherwise noted.
Time (400ns/div)
Rising Edge
Time (400ns/div)
5V
1-LSB Step
Falling Edge
Time (400ns/div)
Falling Edge
VOUT (5mV/div)
VOUT (5mV/div)
5V
16-LSB Step
Figure 35. Glitch Energy
VDD = 5V
Ext VREF = 4.096V
From Code: 8000h
To Code: 80FFh
Glitch: Not Detected
Theoretical Worst Case
VDD = 5V
Ext VREF = 4.096V
From Code: 80FFh
To Code: 8000h
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
5V
VDD = 5V
Ext VREF = 4.096V
From Code: 8010h
To Code: 8000h
Glitch: 0.08nV-s
Time (400ns/div)
16-LSB Step
Figure 34. Glitch Energy
Rising Edge
1-LSB Step
Figure 33. Glitch Energy
VDD = 5V
Ext VREF = 4.096V
From Code: 8000h
To Code: 8010h
Glitch: 0.04nV-s
5V
5V
VOUT (500mV/div)
VOUT (500mV/div)
Figure 32. Glitch Energy
Rising Edge
VDD = 5V
Ext VREF = 4.096V
From Code: 8000h
To Code: 7FFFh
Glitch: 0.16nV-s
Measured Worst Case
2566-LSB Step
Falling Edge
Figure 36. Glitch Energy
5V
256-LSB Step
Figure 37. Glitch Energy
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Typical Characteristics: DAC at VDD = 5 V (continued)
At TA = 25°C, external reference used, and DAC output not loaded, unless otherwise noted.
98
VDD = 5V, External VREF = 4.9V
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
96
Gain (dB)
SNR (dB)
94
92
90
88
86
84
0
1
2
3
4
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
VDD = 5V, External VREF = 4.9V
fOUT = 1kHz, fS = 225kSPS
Measurement Bandwidth = 20kHz
0
5
5
Figure 38. Signal-to-Noise Ratio vs Output Frequency
1800
1200
Full-Scale
1000
Midscale
800
Zero-Scale
600
20
Internal Reference Enabled
4mF vs No Load at VREF Pin
See the Applications Information
section for more information
800
Vn (nV/ÖHz)
Vn (nV/ÖHz)
1400
15
Figure 39. Power Spectral Density
1000
Internal Reference Enabled
No Load at VREF Pin
See the Applications Information
section for more information
1600
10
Frequency (kHz)
fOUT (kHz)
400
600
400
CREF = 0mF
200
CREF = 4mF
200
0
0
10
100
1k
10k
100k
1M
10
100
Frequency (Hz)
1k
10k
100k
1M
Frequency (Hz)
Explained in more detail in Application and Implementation.
Explained in more detail in the Application and Implementation
Figure 40. DAC Output Noise Density vs Frequency
Figure 41. DAC Output Noise Density vs Frequency
VNOISE (10mV/div)
DAC = Midscale
Internal Reference Enabled
50mVPP
Time (2s/div)
0.1 Hz to 10 Hz
Figure 42. DAC Output Noise
14
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6.9 Typical Characteristics: DAC at VDD = 3.6 V
At TA = 25°C, internal reference used, and DAC output not loaded, unless otherwise noted
700
90
VDD = 3.6V
Internal VREF = 2.5V
650
VDD = 3.6V
Internal VREF = 2.5V
80
70
Occurrences
IDD (mA)
600
550
500
60
50
40
30
20
450
10
400
-40
0
0
40
80
120
450
475
500
Temperature (°C)
525
550
575
600
IDD (mA)
Figure 43. Power-Supply Current vs Temperature
Figure 44. Power-Supply Current Histogram
6.10 Typical Characteristics: DAC at VDD = 2.7 V
6
4
2
0
-2
-4
-6
VDD = 2.7V, Internal VREF = 2.5V
LE (LSB)
LE (LSB)
At TA = 25°C, internal reference used, and DAC output not loaded, unless otherwise noted
VDD = 2.7V, Internal VREF = 2.5V
1.0
DLE (LSB)
DLE (LSB)
1.0
6
4
2
0
-2
-4
-6
0.5
0
-0.5
-1.0
0.5
0
-0.5
-1.0
0
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
Digital Input Code
16384 24576 32768 40960 49152
57344 65536
Digital Input Code
–40°C
25°C
Figure 45. Linearity Error and Differential Linearity Error vs
Digital Input Code
Figure 46. Linearity Error and Differential Linearity Error vs
Digital Input Code
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Typical Characteristics: DAC at VDD = 2.7 V (continued)
At TA = 25°C, internal reference used, and DAC output not loaded, unless otherwise noted
10
VDD = 2.7V, Internal VREF = 2.5V
VDD = 2.7V
Internal VREF = 2.5V
5
Error (mV)
LE (LSB)
6
4
2
0
-2
-4
-6
DLE (LSB)
1.0
0
0.5
0
-0.5
-5
-40
-1.0
0
8192
16384 24576 32768 40960 49152
57344 65536
0
40
80
120
Digital Input Code
Temperature (°C)
Figure 47. Linearity Error and Differential Linearity Error vs
Digital Input Code
Figure 48. Zero-Scale Error vs Temperature
105°C
10
3.0
VDD = 2.7V
Internal VREF = 2.5V
2.5
5
VDD = 2.7V
Internal Reference Enabled
DAC Loaded with FFFFh
VOUT (V)
Error (mV)
2.0
0
1.5
1.0
0.5
DAC Loaded with 0000h
-5
-40
0
0
40
80
120
0
5
10
15
20
Temperature (°C)
ISOURCE/SINK (mA)
Figure 49. Full-Scale Error vs Temperature
Figure 50. Source and Sink Current Capability
650
1000
VDD = 2.7V
Internal VREF = 2.5V
VDD = 2.7V, Internal VREF Included,
SCLK Input
(all other digital inputs = GND)
Sweep from 0V to 2.7V
900
600
IDD (mA)
IDD (mA)
800
550
700
Sweep from 2.7V to 0V
600
500
500
450
400
0
8192 16384 24576 32768 40960 49152 57344 65536
0
Digital Input Code
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
VLOGIC (V)
Figure 51. Supply Current vs Digital Input Code
16
0.3
Figure 52. Power-Supply Current vs Logic Input Voltage
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Typical Characteristics: DAC at VDD = 2.7 V (continued)
At TA = 25°C, internal reference used, and DAC output not loaded, unless otherwise noted
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
VDD = 2.7V
Int VREF = 2.5V
From Code: FFFFh
To Code: 0000h
Rising
Edge
0.5V/div
VDD = 2.7V
Int VREF = 2.5V
From Code: 0000h
To Code: FFFFh
Zoomed Falling Edge
1mV/div
Falling
Edge
0.5V/div
Zoomed Rising Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
2.7-V Rising Edge
2.7-V Falling Edge
Figure 53. Full-Scale Settling Time
Figure 54. Full-Scale Settling Time: 2.7-V Falling Edge
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
VDD = 2.7V
Int VREF = 2.5V
From Code: CFFFh
To Code: 4000h
VDD = 2.7V
Int VREF = 2.5V
From Code: 4000h
To Code: CFFFh
Rising
Edge
0.5V/div
Falling
Edge
0.5V/div
Zoomed Rising Edge
1mV/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
2.7-V Rising Edge
2.7-V Falling Edge
Figure 56. Half-Scale Settling Time
VDD = 2.7V
Int VREF = 2.5V
From Code: 7FFFh
To Code: 8000h
Glitch: 0.08nV-s
VOUT (200mV/div)
VOUT (200mV/div)
Figure 55. Half-Scale Settling Time
Time (400ns/div)
Rising Edge
2.7 V
VDD = 2.7V
Int VREF = 2.5V
From Code: 8000h
To Code: 7FFFh
Glitch: 0.16nV-s
Measured Worst Case
Time (400ns/div)
1-LSB Step
Falling Edge
Figure 57. Glitch Energy
2.7 V
1-LSB Step
Figure 58. Glitch Energy
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Typical Characteristics: DAC at VDD = 2.7 V (continued)
VDD = 2.7V
Int VREF = 2.5V
From Code: 8000h
To Code: 8010h
Glitch: 0.04nV-s
VDD = 2.7V
Int VREF = 2.5V
From Code: 8010h
To Code: 8000h
Glitch: 0.12nV-s
VOUT (200mV/div)
VOUT (200mV/div)
At TA = 25°C, internal reference used, and DAC output not loaded, unless otherwise noted
Time (400ns/div)
Rising Edge
2.7 V
Time (400ns/div)
16-LSB Step
Falling Edge
VDD = 2.7V
Int VREF = 2.5V
From Code: 8000h
To Code: 80FFh
Glitch: Not Detected
Theoretical Worst Case
VDD = 2.7V
Int VREF = 2.5V
From Code: 80FFh
To Code: 8000h
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Rising Edge
2.7 V
Time (400ns/div)
256-LSB Step
Falling Edge
Figure 61. Glitch Energy
18
16-LSB Step
Figure 60. Glitch Energy
VOUT (5mV/div)
VOUT (5mV/div)
Figure 59. Glitch Energy
2.7 V
2.7 V
256-LSB Step
Figure 62. Glitch Energy
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7 Detailed Description
7.1 Overview
The DAC8560 is a low-power, voltage output, 16-bit digital-to-analog converter (DAC). The DAC8560 includes a
2.5-V, 2-ppm/°C internal reference (enabled by default), giving a full-scale output voltage range of 2.5 V. The
internal reference has an initial accuracy of 0.02% and can source up to 20 mA at the VREF pin. The device is
monotonic, provides very good linearity, and minimizes undesired code-to-code transient voltages (glitch). The
DAC8560 uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz. It is compatible with
standard SPI, QSPI, Microwire, and digital-signal-processor (DSP) interfaces.
7.2 Functional Block Diagram
VDD
VFB
VREF
VOUT
Ref (+)
16-Bit DAC
2.5V
Reference
16
DAC Register
16
SYNC
Shift Register
SCLK
PWD
Control
Resistor
Network
DIN
GND
7.3 Feature Description
7.3.1 Digital-to-Analog Converter (DAC)
The DAC8560 architecture consists of a string DAC followed by an output buffer amplifier. Figure 63 shows a
block diagram of the DAC architecture.
VREF
50kW
50kW
VFB
62kW
DAC
Register
REF (+)
Register String
REF (-)
VOUT
GND
Figure 63. DAC8560 Architecture
The input coding to the DAC8560 is straight binary, so the ideal output voltage is given by:
DIN
V OUT +
V REF
65536
where DIN = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to
65535.
(1)
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Feature Description (continued)
7.3.2 Resistor String
The resistor string section is shown in Figure 64. It is simply a string of resistors, each of value R. The code
loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the
output amplifier by closing one of the switches connecting the string to the amplifier. It is monotonic because it is
a string of resistors.
VREF
RDIVIDER
VREF
2
R
R
To Output Amplifier
(2x Gain)
R
R
Figure 64. Resistor String
7.3.3 Output Amplifier
The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0
V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities
of the output amplifier can be seen in the Typical Characteristics: DAC at VDD = 5 V. The slew rate is 1.8 V/μs
with a full-scale settling time of 8 μs with the output unloaded.
The inverting input of the output amplifier is available at the VFB pin. This feature allows better accuracy in critical
applications by tying the VFB point and the amplifier output together directly at the load. Other signal conditioning
circuitry may also be connected between these points for specific applications.
20
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Feature Description (continued)
7.3.4 DAC Noise Performance
Typical noise performance for the DAC8560 with the internal reference enabled is shown in Figure 40 to
Figure 42. Output noise spectral density at pin VOUT versus frequency is depicted in Figure 40 for full-scale,
midscale, and zero-scale input codes. The typical noise density for midscale code is 170 nV/√Hz at 1 kHz and
100nV/√Hz at 1MHz. High-frequency noise can be improved by filtering the reference noise as shown in
Figure 41, where a 4-μF load capacitor is connected to the VREF pin and compared to the no-load condition.
Integrated output noise between 0.1 Hz and 10 Hz is close to 50 μVPP (midscale), as shown in Figure 42.
7.3.5 Internal Reference
The DAC8560 includes a 2.5-V internal reference that is enabled by default. The internal reference is externally
available at the VREF pin. TI recommends a minimum 100-nF capacitor between the reference output and GND
for noise filtering.
The internal reference of the DAC8560 is a bipolar transistor-based, precision bandgap voltage reference. The
basic bandgap topology is shown in Figure 65. Transistors Q1 and Q2 are biased such that the current density of
Q1 is greater than that of Q2. The difference of the two base-emitter voltages (VBE1 – VBE2) has a positive
temperature coefficient and is forced across resistor R1. This voltage is gained up and added to the base-emitter
voltage of Q2, which has a negative temperature coefficient. The resulting output voltage is virtually independent
of temperature. The short-circuit current is limited by design to approximately 100 mA.
VREF
Reference
Disable
Q1
1
N
Q2
R1
R2
Figure 65. Simplified Schematic of the Bandgap Reference
7.3.5.1 Enable/Disable Internal Reference
The DAC8560 internal reference is enabled by default; however, the reference can be disabled for debugging or
evaluation purposes. A serial command requiring at least two additional SCLK cycles at the end of the 24-bit
write sequence (see Serial Interface) must be used to disable the internal reference. For proper operation, a total
of at least 26 SCLK cycles are required for each enable/disable internal reference update sequence, during
which SYNC must be held low. To disable the internal reference, execute the write sequence illustrated in
Table 2 followed by at least two additional SCLK falling edges while SYNC is low.
To then enable the reference, either perform a power-cycle to reset the device, or sequentially execute the two
write sequences in Table 3 and Table 4. Each of these write sequences must be followed by at least two
additional SCLK falling edges while SYNC remains low.
During the time that the internal reference is disabled, the DAC will function normally using an external reference.
At this point, the internal reference is disconnected from the VREF pin (tri-state). Do not attempt to drive the VREF
pin externally and internally at the same time indefinitely.
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Feature Description (continued)
7.3.5.2 Internal Reference Load
The DAC8560 internal reference does not require an external load capacitor for stability because it is stable with
any capacitive load. However, for improved noise performance, TI recommends an external load capacitor of 150
nF or larger connected to the VREF output. Figure 66 shows the typical connections required for operation of the
DAC8560 internal reference. A supply bypass capacitor at the VDD input is also recommended.
DAC8560
VDD
GND
8
DIN
7
VFB
SCLK
6
VOUT
SYNC
5
1
VDD
2
VREF
3
4
1mF
VREF
150nF
Figure 66. Typical Connections for Operating the DAC8560 Internal Reference
7.3.5.2.1 Supply Voltage
The DAC8560 internal reference features an extremely low dropout voltage. It can be operated with a supply of
only 5mV above the reference output voltage in an unloaded condition. For loaded conditions, refer to the Load
Regulation section. The stability of the DAC8560 internal reference with variations in supply voltage (line
regulation, DC PSRR) is also exceptional. Within the specified supply voltage range of 2.7 V to 5.5 V, the
variation at VREF is smaller than 10 μV/V; see the Typical Characteristics: Internal Reference.
7.3.5.2.2 Temperature Drift
The DAC8560 internal reference is designed to exhibit minimal drift error, defined as the change in reference
output voltage over varying temperature. The drift is calculated using the box method, which is described by
Equation 2:
Drift Error +
ǒ
Ǔ
V REF_MAX * V REF_MIN
V REF T RANGE
10 6 (ppmń°C)
where
•
•
•
VREF_MAX = maximum reference voltage observed within temperature range TRANGE
VREF_MIN = minimum reference voltage observed within temperature range TRANGE
VREF = 2.5 V, target value for reference output voltage
(2)
The DAC8560 internal reference (grades C and D) features an exceptional typical drift coefficient of 2 ppm/°C
from –40°C to +120°C. Characterizing a large number of units, a maximum drift coefficient of 5 ppm/°C (grades
C and D) is observed. Temperature drift results are summarized in the Typical Characteristics: Internal
Reference.
7.3.5.2.3 Noise Performance
Typical 0.1-Hz to 10-Hz voltage noise can be seen in Figure 9. Additional filtering can be used to improve output
noise levels, although care should be taken to ensure the output impedance does not degrade the AC
performance. The output noise spectrum at VREF without any external components is depicted in Figure 8,
Internal Reference Noise Density vs Frequency. Another noise density spectrum is also shown in Figure 8, which
was obtained using a 4μF load capacitor at VREF for noise filtering. Internal reference noise impacts the DAC
output noise; see the DAC Noise Performance section for more details.
22
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Feature Description (continued)
7.3.5.2.4 Load Regulation
Load regulation is defined as the change in reference output voltage as a result of changes in load current. The
load regulation of the DAC8560 internal reference is measured using force and sense contacts as pictured in
Figure 67. The force and sense lines reduce the impact of contact and trace resistance, resulting in accurate
measurement of the load regulation contributed solely by the DAC8560 internal reference. Measurement results
are summarized in the Typical Characteristics: Internal Reference. Force and sense lines should be used for
applications requiring improved load regulation.
Output Pin
Contact and
Trace Resistance
VOUT
Force Line
IL
Sense Line
Meter
Load
Figure 67. Accurate Load Regulation of the DAC8560 Internal Reference
7.3.5.2.5 Long-Term Stability
Long-term stability/aging refers to the change of the output voltage of a reference over a period of months or
years. This effect lessens as time progresses, as shown in Figure 7, the typical long-term stability curve. The
typical drift value for the DAC8560 internal reference is 50 ppm from 0 hours to 1900 hours. This parameter is
characterized by powering up and measuring 20 units at regular intervals for a period of 1900 hours.
7.3.5.2.6 Thermal Hysteresis
Thermal hysteresis for a reference is defined as the change in output voltage after operating the device at 25°C,
cycling the device through the specified temperature range, and returning to 25°C. It is expressed in Equation 3:
Ť VREF_PRE * V REF_POST Ť
10 6 (ppm)
V HYST +
VREF_NOM
ǒ
Ǔ
where
•
•
•
VHYST = thermal hysteresis
VREF_PRE = output voltage measured at 25°C pre-temperature cycling
VREF_POST = output voltage measured after the device has been cycled through the temperature range of –40°C
to +120°C, and returned to 25°C
(3)
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7.4 Device Functional Modes
7.4.1 Power-Down Modes
The DAC8560 supports four separate modes of operation. These modes are programmable by setting two bits
(PD1 and PD0) in the control register. Table 1 shows how to control the operating mode with data bits PD1
(DB17) and PD0 (DB16).
Table 1. Operating Modes
PD1 (DB17)
PD0 (DB16)
0
0
Normal operation
OPERATING MODE
0
1
Power-down 1 kΩ to GND
1
0
Power-down 100 kΩ to GND
1
1
Power-down High-Z
When both bits are set to 0, the device works normally with its typical current consumption of 530 μA at 5.5 V.
However, for the three power-down modes, the supply current falls to 1.2 μA at 5.5 V (0.7 μA at 3.6 V). Not only
does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a
resistor network of known values.
The advantage of this switching is that the output impedance of the device is known while it is in power-down
mode. As shown in Table 1, there are three different power-down options. VOUT can be connected internally to
GND through a 1-kΩ resistor, a 100-kΩ resistor, or open-circuited (High-Z). The output stage is shown in
Figure 68.
VFB
Resistor
String
DAC
Amplifier
Power-Down
Circuitry
VOUT
Resistor
Network
Figure 68. Output Stage During Power Down
All analog circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power down. The time to exit power down is typically 2.5 μs for VDD = 5 V, and 5
μs for VDD = 3 V. See the Typical Characteristics: DAC at VDD = 5 V for more information.
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7.5 Programming
7.5.1 Serial Interface
The DAC8560 has a 3-wire serial interface ( SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and
Microwire interface standards, as well as most DSPs. See Figure 1 for an example of a typical write sequence.
The write sequence begins by bringing the SYNC line LOW. Data from the DIN line is clocked into the 24-bit shift
register on each falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the
DAC8560 compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is
clocked in and the programmed function is executed.
At this point, the SYNC line may be kept LOW or brought HIGH. In either case, it must be brought HIGH for a
minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write
sequence. As previously mentioned, it must be brought HIGH again before the next write sequence.
7.5.2 Input Shift Register
The input shift register is 24 bits wide, as shown in Table 5. The first six bits must be 000000. The next two bits
(PD1 and PD0) are control bits that set the desired mode of operation (normal mode or any one of three powerdown modes) as indicated in Table 1.
A more complete description of the various modes is located in Power-Down Modes. The next 16 bits are the
data bits, which are transferred to the DAC register on the 24th falling edge of SCLK under normal operation
(see Table 1).
7.5.3
SYNC Interrupt
In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the DAC is
updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, it acts as an
interrupt to the write sequence. The shift register is reset, and the write sequence is seen as invalid. Neither an
update of the DAC register contents, nor a change in the operating mode occurs, as shown in Figure 69.
7.5.4 Power-On Reset
The DAC8560 contains a power-on-reset circuit that controls the output voltage during power up. On power up,
all registers are filled with zeros and the output voltage is zero-scale; it remains there until a valid write sequence
is made to the DAC. This feature is useful in applications where it is important to know the state of the output of
the DAC while it is in the process of powering up.
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7.6 Register Maps
7.6.1 Write Sequence for Disabling the DAC8560 Internal Reference
Table 2. Write Sequence for Disabling the DAC8560 Internal Reference
DB23
0
DB0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
7.6.2 Enabling the DAC8560 Internal Reference (Write Sequence 1 of 2)
Table 3. Enabling the DAC8560 Internal Reference (Write Sequence 1 of 2)
DB23
0
DB0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
7.6.3 Enabling the DAC8560 Internal Reference (Write Sequence 2 of 2)
Table 4. Enabling the DAC8560 Internal Reference (Write Sequence 2 of 2)
DB23
0
DB0
1
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
7.6.4 DAC8560 Data Input Register Format
Table 5. DAC8560 Data Input Register Format
DB23
0
DB0
0
0
0
0
0
PD1
PD0
D15
D14
D13
D12
D11
D10
D9
D8
24th Falling Edge
D7
D6
D5
D4
D3
D2
D1
D0
24th Falling Edge
CLK
SYNC
DIN
DB23
DB0
DB23
Invalid/Interrupted Write Sequence:
Output/Mode Does Not Update on the 24th Falling Edge
DB0
Valid Write Sequence:
Output/Mode Updates on the 24th Falling Edge
Figure 69. SYNC Interrupt Facility
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The low-power consumption of the DAC8560, coupled with the ultra-low current power-down modes, makes the
device a great choice for battery-operated and portable applications such as oscilloscopes and similar test and
measurement equipment. In addition to the low-power requirement, these applications often require a bipolar
output range for offset and gain calibration as described in the following sections.
8.2 Typical Applications
The output voltage with Figure 70 and Figure 71 for any input code can be calculated using Equation 4:
ƪ
V O + VREF
D Ǔ
ǒ65536
ǒR R) R Ǔ * V
1
ǒRR Ǔƫ
2
2
REF
1
1
where D represents the input code in decimal (0–65535).
(4)
With VREF = 5 V, R1 = R2 = 10 kΩ.
ǒ
Ǔ
V O + 10 D * 5V
65536
(5)
This result has an output voltage range of ±5 V with 0000h corresponding to a –5-V output and FFFFh
corresponding to a 5-V output, as shown in Figure 70. Similarly, using the internal reference, a ±2.5-V output
voltage range can be achieved, as shown in Figure 71.
V
V
REF
R2
10kW
DD
+6V
R1
10kW
OPA703
VDD
VREF
10mF
0.1mF
±5V
VFB
DAC8560
VOUT
-6V
GND
Three-Wire
Serial Interface
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Figure 70. Bipolar Output Range Using External Reference at 5 V
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Typical Applications (continued)
V
R2
10kW
DD
+6V
R1
10kW
±2.5V
OPA703
VDD
VREF
VFB
DAC8560
150nF
VOUT
GND
-6V
Three-Wire
Serial Interface
Copyright © 2018, Texas Instruments Incorporated
Figure 71. Bipolar Output Range Using Internal Reference
RG1
RFB
CCOMP
VREF
RG2
VOUT
+
DAC8560
RISO
CLOAD
OPA188
Copyright © 2018, Texas Instruments Incorporated
Figure 72. Bipolar Output Range > ±VREF
8.2.1 Design Requirements
The design requirements and performance goals are summarized as follows:
• DAC Supply Voltage: +5-V DC
• Amplifier Supply Voltage: ±15-V DC
• Input: 3-wire, 24-bit SPI
• Output: ±10-V DC
• Capacitance Load: 20 nF
Table 6. Comparison of Design Goal, Simulation, and Measured Performance
Total unadjusted error (%FSR)
28
GOAL
SIMULATED
MEASURED
0.25
0.23
0.0939
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8.2.2 Detailed Design Procedure or Bipolar Operation > ±VREF
8.2.2.1 Bipolar Operation Greater Than ±VREF
The DAC8560 has been designed for single-supply operation; a bipolar output range is also possible using the
circuit in Figure 71. This unipolar-to-bipolar signal conditioning circuit uses an operational amplifier (op amp) with
negative feedback and three resistors in a modified summing amplifier configuration to generate high-voltage
bipolar outputs. The DC transfer function is based on the ratio of the feedback resistor RFB and gain setting
resistors RG1 and RG2. This design takes consideration for generating voltage outputs and for driving reactive
loads such as long cables common in industrial process control applications. The circuit shown in Figure 72 gives
an output voltage range greater than ±VREF.
The DC transfer function for this design is defined as:
§ RFB RFB ·
RFB
VOUT ¨ 1
VREF
¸ VDAC
RG2
© RG2 RG1 ¹
(6)
8.2.2.1.1 Passive Component Selection
The amplifier in this circuit uses negative feedback to ensure that the voltages at the inverting and non-inverting
terminals are equal. When the DAC output is at zero scale (0 V) the inverting terminal is a virtual ground so no
current flows across RG1; this causes the circuit to function as an inverting amplifier with gain equal to RFB / RG2.
When the DAC output is full-scale (VREF) the inverting terminal potential is equal to VREF so no current flows
across RG2; this causes the circuit to function as a non-inverting amplifier with gain equal to (1 + RFB / RG1). A
simple three-step process can be used to select the resistor values used to realize any bipolar output range
using DAC8560. The internal VREF value is 2.5 V. The desired output range for this design is ±10 V. First, using
the transfer function shown in Equation 6, consider the negative full-scale output case when VDAC is equal to 0 V,
VREF is equal to 2.5 V, and VOUT is equal to –10 V. This case is used to calculate the ratio of RFB to RG2 and is
shown explicitly in Equation 7.
§ RFB RFB ·
RFB
10 V ¨ 1
2.5 V
¸ 0
RG2
© RG2 RG1 ¹
RFB
2.5 V
RG2
10 V
RFB
4 u RG2
(7)
Second, consider the positive full-scale output case when VDAC is equal to 2.5 V, VREF is equal to 2.5 V, and
VOUT is equal to 10 V. This case is used to calculate the ratio of RFB to RG1 and is shown explicitly in Equation 8.
10 V
§ RFB
¨1
© RG2
10 V
RFB ·
¸ 2.5
RG1 ¹
RFB
2.5 V
RG2
§ RFB ·
¸ 2.5 V
¨1
© RG1 ¹
RG1
RFB
3
(8)
Finally, seed the ideal value of RG2 to calculate the ideal values of RFB and RG2. The key considerations for
seeding the value of RG2 should be the drive strength of the reference source as well as choosing small resistor
values to minimize noise contributed by the resistor network. For this design RG2 of 8.25 kΩ was chosen, which
limits the peak current drawn from the reference source to approximately 333 µA under nominal conditions, well
within the 20-mA limit of the DAC8560. In this case the nearest, 0.1% tolerance, 0603 package values for each
resistor are ideal.
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Standard values for 0.1% resistors can be an obstacle for this design and it may take multiple iterations of
seeding the values to find real components or they may not exist. Workarounds can include utilizing multiple
resistors in series and/or parallel, using potentiometers for analog trim calibration, or providing extra gain in the
output circuit and applying digital calibration. In systems where the output voltage must reach the design-goal
end-points (±10 V) it may be desirable to apply additional gain to the circuit. This approach may contribute
additional overall system error since the end-point errors vary from system to system. For this design, use the
exact values calculated in the design process to keep error analysis easy to follow.
To deliver a near-universal cable drive solution, choose CLOAD to be relatively large compared to typical cable
capacitance such that its capacitance dominates the reactive load seen by the output amplifier. To drive larger
capacitive loads RISO, CCOMP, and CLOAD may need to be adjusted. An RISO of 70 Ω and CCOMP of 150 pF are
used for this design.
Resistor matching for the op amp resistor network is critical for the success of this design; choose components
with tight tolerances. For this design 0.1% resistor values are implemented but this constraint may be adjusted
based on application specific design goals. Resistor matching contributes to both offset error and gain error in
this design. The tolerance of stability components RISO and CCOMP is not critical and 1% components are
acceptable.
Table 7. Values of Resistor Network
RESISTOR
VALUE
RG1
11 kΩ
RG2
8.25 kΩ
RFB
33 kΩ
8.2.2.1.2 Amplifier Selection
Amplifier input offset voltage (VOS) is a key consideration for this design. VOS of an op amp is a typical data-sheet
specification but in-circuit performance is also impacted by drift over temperature, the common-mode rejection
ratio (CMRR), and power supply rejection ratio (PSRR). Thus, consider these parameters as well. For AC
operation also consider slew rate and settling time. Input-bias current (IB) can also be a factor, but typically the
resistor network is implemented with sufficiently small resistor values that the effects of input-bias current are
negligible.
8.2.2.2 Microprocessor Interfacing
8.2.2.2.1 DAC8560 to 8051 Interface
See Figure 73 for a serial interface between the DAC8560 and a typical 8051-type microcontroller. The setup for
the interface is as follows: TXD of the 8051 drives SCLK of the DAC8560, while RXD drives the serial data line of
the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case, port
line P3.3 is used. When data is to be transmitted to the DAC8560, P3.3 is taken LOW. The 8051 transmits data
in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left
LOW after the first eight bits are transmitted, then a second write cycle is initiated to transmit the second byte of
data. P3.3 is taken HIGH following the completion of the third write cycle. The 8051 outputs the serial data in a
format which has the LSB first. The DAC8560 requires its data with the MSB as the first bit received. The 8051
transmit routine must therefore take this into account, and mirror the data as needed.
DAC8560 (1)
80C51/80L51(1)
P3.3
SYNC
TXD
SCLK
RXD
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 73. DAC8560 to 80C51/80L51 Interface
8.2.2.2.2 DAC8560 to Microwire Interface
Figure 74 shows an interface between the DAC8560 and any Microwire compatible device. Serial data is shifted
out on the falling edge of the serial clock and is clocked into the DAC8560 on the rising edge of the SK signal.
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MicrowireTM
DAC8560 (1)
CS
SYNC
SK
SCLK
SO
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 74. DAC8560 to Microwire Interface
8.2.2.2.3 DAC8560 to 68HC11 Interface
Figure 75 shows a serial interface between the DAC8560 and the 68HC11 microcontroller. SCK of the 68HC11
drives the SCLK of the DAC8560, while the MOSI output drives the serial data line of the DAC. The SYNC signal
is derived from a port line (PC7), similar to the 8051 diagram.
DAC8560 (1)
68HC11(1)
PC7
SYNC
SCK
SCLK
MOSI
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 75. DAC8560 to 68HC11 Interface
Configure the 68HC11 so that its CPOL bit is 0, and its CPHA bit is 1. This configuration causes data appearing
on the MOSI output to be valid on the falling edge of SCK. When data is being transmitted to the DAC, the SYNC
line is held LOW (PC7). Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data is transmitted MSB first.) In order to load data to the DAC8560, PC7
is left LOW after the first eight bits are transferred, then a second and third serial write operation is performed to
the DAC. PC7 is taken HIGH at the end of this procedure.
8.2.3 Application Curves
0.04
Output Error (%FSR)
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
0
10000
20000 30000 40000
Input Code (Decimal)
50000
60000
D001
Figure 76. Output Voltage Error vs Input Code
Figure 77. Full-Scale Step Response
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9 Power Supply Recommendations
The DAC8560 can operate within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to VDD
must be well-regulated and low-noise. Switching power supplies and DC-DC converters often have highfrequency glitches or spikes riding on the output voltage. In addition, digital components can create similar highfrequency spikes. This noise can easily couple into the DAC output voltage through various paths between the
power connections and analog output. In order to further minimize noise from the power supply, TI strongly
recommends a 1-μF to 10-μF capacitor and 0.1-μF bypass capacitor. The current consumption on the VDD pin,
the short-circuit current limit, and the load current for the device is listed in Electrical Characteristics. The power
supply must meet the aforementioned current requirements.
10 Layout
10.1 Layout Guidelines
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies.
The DAC8560 offers single-supply operation, and it often is used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and
the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output.
As a result of the single ground pin of the DAC8560, all return currents, including digital and analog return
currents for the DAC, must flow through a single point. Ideally, connect GND directly to an analog ground plane.
This plane would be separate from the ground connection for the digital components until they were connected at
the power-entry point of the system.
The power applied to VDD must be well regulated and low noise. Switching power supplies and DC-DC
converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes as their internal logic switches states. This noise can easily
couple into the DAC output voltage through various paths between the power connections and analog output.
As with the GND connection, connect VDD to a power-supply plane or trace that is separate from the connection
for digital logic until they are connected at the power-entry point. In addition, a 1-μF to 10-μF capacitor and 0.1μF bypass capacitor are strongly recommended. In some situations, additional bypassing may be required, such
as a 100-μF electrolytic capacitor or even a Pi filter made up of inductors and capacitors – all designed to
essentially low-pass filter the supply, removing the high-frequency noise.
10.2 Layout Example
Figure 78. DAC8560 Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
CMOS, Rail-to-Rail, I/O OPERATIONAL AMPLIFIERS
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC8560IADGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IADGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IADGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IBDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IBDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IBDGKTG4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560ICDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560ICDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560ICDGKTG4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IDDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IDDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IDDGKTG4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
DAC8560IADGKR
VSSOP
DGK
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8560IADGKT
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8560IBDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8560IBDGKT
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8560ICDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8560ICDGKT
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8560IDDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8560IDDGKT
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC8560IADGKR
VSSOP
DGK
8
2500
350.0
350.0
43.0
DAC8560IADGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
DAC8560IBDGKR
VSSOP
DGK
8
2500
350.0
350.0
43.0
DAC8560IBDGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
DAC8560ICDGKR
VSSOP
DGK
8
2500
350.0
350.0
43.0
DAC8560ICDGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
DAC8560IDDGKR
VSSOP
DGK
8
2500
350.0
350.0
43.0
DAC8560IDDGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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