Texas Instruments | ADC08DJ3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 8-Bit, RF-Sampling Analog-to-Digital Converter (ADC) | Datasheet | Texas Instruments ADC08DJ3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 8-Bit, RF-Sampling Analog-to-Digital Converter (ADC) Datasheet

Texas Instruments ADC08DJ3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 8-Bit, RF-Sampling Analog-to-Digital Converter (ADC) Datasheet
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ADC08DJ3200
SLVSDR1 – FEBRUARY 2018
ADC08DJ3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel,
8-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
1 Features
2 Applications
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
ADC Core:
– 8-Bit Resolution
– Up to 6.4 GSPS in Single-Channel Mode
– Up to 3.2 GSPS in Dual-Channel Mode
Performance Specifications (fIN = 997 MHz):
– ENOB: 7.8 Bits
– SFDR:
– Dual-Channel Mode: 67 dBFS
– Single-Channel Mode: 62 dBFS
Buffered Analog Inputs With VCMI of 0 V:
– Analog Input Bandwidth (–3 dB): 8.0 GHz
– Usable Input Frequency Range: >10 GHz
– Full-Scale Input Voltage (VFS, Default): 0.8 VPP
– Analog Input Common-Mode (VICM): 0 V
Noiseless Aperture Delay (TAD) Adjustment:
– Precise Sampling Control: 19-fs Step
– Simplifies Synchronization and Interleaving
– Temperature and Voltage Invariant Delays
Easy-to-Use Synchronization Features:
– Automatic SYSREF Timing Calibration
– Timestamp for Sample Marking
JESD204B Serial Data Interface:
– Supports Subclass 0 and 1
– Maximum Lane Rate: 12.8 Gbps
– Up to 16 Lanes Allows Reduced Lane Rate
Power Consumption: 2.8 W
Power Supplies: 1.1 V, 1.9 V
ADC08DJ3200 Measured Input Bandwidth
Normalized Gain Response (dB)
3
0
Satellite Communications (SATCOM)
Synthetic Aperture Radar (SAR)
Time-of-Flight and LIDAR Distance Measurement
Oscilloscopes and Wideband Digitizers
Microwave Backhaul
RF Sampling Software-Defined Radio (SDR)
Spectrometry
3 Description
The ADC08DJ3200 device is an RF-sampling, gigasample, analog-to-digital converter (ADC) that can
directly sample input frequencies from DC to above
10 GHz. In dual-channel mode, the ADC08DJ3200
can sample up to 3200 MSPS and up to 6400 MSPS
in single-channel mode. Programmable tradeoffs in
channel count (dual-channel mode) and Nyquist
bandwidth (single-channel mode) allow development
of flexible hardware that meets the needs of both high
channel count or wide instantaneous signal
bandwidth applications. Full-power input bandwidth
(–3 dB) of 8.0 GHz, with usable frequencies
exceeding the –3-dB point in both dual- and singlechannel modes, allows direct RF sampling of L-band,
S-band, C-band, and X-band for frequency agile
systems.
The ADC08DJ3200 uses a high-speed JESD204B
output interface with up to 16 serialized lanes and
subclass-1 compliance for deterministic latency and
multi-device synchronization. The serial output lanes
support up to 12.8 Gbps and can be configured to
trade-off bit rate and number of lanes. At 5 GSPS,
only four total lanes are required running at 12.5
Gbps or 16 lanes can be used to reduce the lane rate
to 3.125 Gbps. Innovative synchronization features,
including noiseless aperture delay (TAD) adjustment
and SYSREF windowing, simplify system design for
phased array radar and MIMO communications.
-3
Device Information(1)
-6
PART NUMBER
-9
ADC08DJ3200
Single Channel Mode
Dual Channel Mode
-12
2
4
6
8
Input Frequency (GHz)
BODY SIZE (NOM)
FCBGA (144) 10.00 mm × 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
-15
0
PACKAGE
10
12
D_BW
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADC08DJ3200
SLVSDR1 – FEBRUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7.4 Device Functional Modes........................................ 49
7.5 Programming........................................................... 61
7.6 Register Maps ......................................................... 62
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions ......................... 3
Specifications....................................................... 10
8
8.1 Application Information.......................................... 106
8.2 Typical Applications ............................................. 106
8.3 Initialization Set Up .............................................. 112
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings .................................... 10
ESD Ratings............................................................ 10
Recommended Operating Conditions..................... 11
Thermal Information ................................................ 11
Electrical Characteristics: DC Specifications .......... 12
Electrical Characteristics: Power Consumption ...... 14
Electrical Characteristics: AC Specifications (DualChannel Mode) ........................................................ 15
6.8 Electrical Characteristics: AC Specifications (SingleChannel Mode) ........................................................ 18
6.9 Timing Requirements .............................................. 21
6.10 Switching Characteristics ...................................... 22
6.11 Typical Characteristics .......................................... 25
7
Application and Implementation ...................... 106
9
Power Supply Recommendations.................... 112
9.1 Power Sequencing ................................................ 114
10 Layout................................................................. 114
10.1 Layout Guidelines ............................................... 114
10.2 Layout Example .................................................. 115
11 Device and Documentation Support ............... 118
11.1 Device Support ..................................................
11.2 Documentation Support ......................................
11.3 Receiving Notification of Documentation
Updates..................................................................
11.4 Community Resources........................................
11.5 Trademarks .........................................................
11.6 Electrostatic Discharge Caution ..........................
11.7 Glossary ..............................................................
Detailed Description ............................................ 35
7.1 Overview ................................................................. 35
7.2 Functional Block Diagram ....................................... 36
7.3 Feature Description................................................. 36
118
118
118
119
119
119
119
12 Mechanical, Packaging, and Orderable
Information ......................................................... 119
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
February 2018
*
Initial release.
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SLVSDR1 – FEBRUARY 2018
5 Pin Configuration and Functions
AAV Package
144-Ball Flip Chip BGA
Top View
1
2
3
4
5
6
7
8
9
10
11
12
A
AGND
AGND
AGND
INA+
INA±
AGND
AGND
DA3+
DA3±
DA2+
DA2±
DGND
B
TMSTP+
AGND
AGND
AGND
AGND
AGND
AGND
DA7+
DA7±
DA6+
DA6±
DGND
C
TMSTP±
SYNCSE
BG
VA19
VA11
AGND
NCOA0
ORA0
VD11
VD11
DA5+
DA1+
D
AGND
VA11
VA11
VA19
VA11
AGND
NCOA1
ORA1
DGND
DGND
DA5±
DA1±
E
AGND
VA19
VA19
VA19
VA11
AGND
CALTRIG
SCS
VD11
VD11
DA4+
DA0+
F
CLK+
AGND
AGND
VA19
VA11
AGND
CALSTAT
SCLK
DGND
DGND
DA4±
DA0±
G
CLK±
AGND
AGND
VA19
VA11
AGND
VD11
SDI
DGND
DGND
DB4±
DB0±
H
AGND
VA19
VA19
VA19
VA11
AGND
VD11
SDO
VD11
VD11
DB4+
DB0+
J
AGND
VA11
VA11
VA19
VA11
AGND
NCOB1
ORB1
DGND
DGND
DB5±
DB1±
K
SYSREF+
TDIODE+
TDIODE±
VA19
VA11
PD
NCOB0
ORB0
VD11
VD11
DB5+
DB1+
L
SYSREF±
AGND
AGND
AGND
AGND
AGND
AGND
DB7+
DB7±
DB6+
DB6±
DGND
M
AGND
AGND
AGND
INB+
INB±
AGND
AGND
DB3+
DB3±
DB2+
DB2±
DGND
Not to scale
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Pin Functions
PIN
NO.
NAME
A1, A2, A3
AGND
I/O
—
DESCRIPTION
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
A4
INA+
I
Channel A analog input positive connection. The differential full-scale input voltage is determined
by the FS_RANGE_A register (see the Full-Scale Voltage (VFS) Adjustment section). This input
is terminated to ground through a 50-Ω termination resistor. The input common-mode voltage is
typically be set to 0 V (GND) and must follow the recommendations in the Recommended
Operating Conditions table. This pin can be left disconnected if not used. Using INA± is
recommended in single-channel mode for optimized performance.
A5
INA–
I
Channel A analog input negative connection. See INA+ (pin A4) for detailed description. This
input is terminated to ground through a 50-Ω termination resistor. This pin can be left
disconnected if not used.
AGND
—
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
A6, A7
A8
DA3+
O
High-speed serialized-data output for channel A, lane 3, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
A9
DA3–
O
High-speed serialized-data output for channel A, lane 3, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
A10
DA2+
O
High-speed serialized-data output for channel A, lane 2, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
A11
DA2–
O
High-speed serialized-data output for channel A, lane 2, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
A12
DGND
—
Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
B1
B2, B3, B4,
B5, B6, B7
(1)
4
TMSTP+
I
AGND
—
Timestamp input positive connection or differential JESD204B SYNC positive connection. This
input is a timestamp input, used to mark a specific sample, when TIMESTAMP_EN is set to 1.
This differential input is used as the JESD204B SYNC signal input when SYNC_SEL is set 1.
This input can be used as both a timestamp and differential SYNC input at the same time,
allowing feedback of the SYNC signal using the timestamp mechanism. TMSTP± uses active low
signaling when used as a JESD204B SYNC. For additional usage information, see the
Timestamp section.
TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to
TMSTP–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when
TMSTP_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin
(TMSTP+ and TMSTP–) and can be DC coupled when TMSTP_LVPECL_EN is set to 1. This pin
is not self-biased and therefore must be externally biased for both AC- and DC-coupled
configurations. The common-mode voltage must be within the range provided in the
Recommended Operating Conditions table when both AC and DC coupled. This pin can be left
disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for JESD204B SYNC
and timestamp is not required.
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
Powering down the high-speed data outputs (DA0± ... DA7±, DB0± ... DB7±) for extended times may reduce performance of the output
serializers, especially at high data rates. Powering down the serializers occurs when the PD pin is held high, the MODE register is
programmed to a value other than 0x00 or 0x01, the PD_ACH or PD_BCH registers settings are programmed to 1, or when the JMODE
register setting is programmed to a mode that uses less than the 16 total lanes that the device allows. For instance, JMODE 0 uses
eight total lanes and therefore the four highest-indexed lanes for each JESD204B link (DA4± ... DA7±, DB4± ... DB7±) are powered
down in this mode. When the PD pin is held high or the MODE register is programmed to a value other than 0x00 or 0x01, all output
serializers are powered down. When the PD_ACH or PD_BCH register settings are programmed to 1, the associated ADC channel and
lanes are powered down. To prevent unreliable operation, the PD pin and MODE register must only be used for brief periods of time to
measure temperature diode offsets and not used for long-term power savings. Furthermore, using a JMODE that uses fewer than 16
lanes results in unreliable operation of the unused lanes. If the system will never use the unused lanes during the lifetime of the device,
then the unused lanes do not cause issues and can be powered down. If the system may make use of the unused lanes at a later time,
the reliable operation of the serializer outputs can be maintained by enabling JEXTRA_A and JEXTRA_B, which results in the VD11
power consumption to increase and the output serializers to toggle.
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
NO.
NAME
B8
DA7+
O
High-speed serialized data output for channel A, lane 7, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
B9
DA7–
O
High-speed serialized data output for channel A, lane 7, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
B10
DA6+
O
High-speed serialized data output for channel A, lane 6, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
B11
DA6–
O
High-speed serialized data output for channel A, lane 6, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
B12
DGND
—
Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
C1
TMSTP–
I
Timestamp input positive connection or differential JESD204B SYNC negative connection. This
pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for
JESD204B SYNC and timestamp is not required.
C2
SYNCSE
I
Single-ended JESD204B SYNC signal. This input is an active low input that is used to initialize
the JESD204B serial link when SYNC_SEL is set to 0. When toggled low this input initiates code
group synchronization (see the Code Group Synchronization (CGS) section). After code group
synchronization, this input must be toggled high to start the initial lane alignment sequence (see
the Initial Lane Alignment Sequence (ILAS) section). A differential SYNC signal can be used
instead by setting SYNC_SEL to 1 and using TMSTP± as a differential SYNC input. Tie this pin to
GND if differential SYNC (TMSTP±) is used as the JESD204B SYNC signal.
C3
BG
O
Band-gap voltage output. This pin is capable of sourcing only small currents and driving limited
capacitive loads, as specified in the Recommended Operating Conditions table. This pin can be
left disconnected if not used.
C4
VA19
I
1.9-V analog supply
C5
VA11
I
1.1-V analog supply
C6
AGND
—
C7
NCOA0
I
Tie this pin to GND.
C8
ORA0
O
Fast overrange detection status for channel A for the OVR_T0 threshold. When the analog input
exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum
pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.
This pin can be left disconnected if not used.
C9, C10
VD11
I
1.1-V digital supply
O
High-speed serialized data output for channel A, lane 5, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
C11
DA5+
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
C12
DA1+
O
High-speed serialized data output for channel A, lane 1, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
D1
AGND
—
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
D2, D3
VA11
I
1.1-V analog supply
D4
VA19
I
1.9-V analog supply
D5
VA11
I
1.1-V analog supply
D6
AGND
—
D7
NCOA1
I
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
Tie this pin to GND.
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
ORA1
O
Fast overrange detection status for channel A for the OVR_T1 threshold. When the analog input
exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum
pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.
This pin can be left disconnected if not used.
D9, D10
DGND
—
Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
D11
DA5–
O
High-speed serialized data output for channel A, lane 5, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
D12
DA1–
O
High-speed serialized data output for channel A, lane 1, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
E1
AGND
—
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
E2, E3, E4
VA19
I
1.9-V analog supply
E5
VA11
I
1.1-V analog supply
E6
AGND
—
E7
CALTRIG
I
Foreground calibration trigger input. This pin is only used if hardware calibration triggering is
selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG.
Tie this pin to GND if not used.
E8
SCS
I
Serial interface chip select active low input. The Using the Serial Interface section describes the
serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. This pin has a 82-kΩ
pullup resistor to VD11.
E9, E10
VD11
I
1.1-V digital supply
E11
DA4+
O
High-speed serialized data output for channel A, lane 4, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
E12
DA0+
O
High-speed serialized data output for channel A, lane 0, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
Device (sampling) clock positive input. The clock signal is strongly recommended to be ACcoupled to this input for best performance. In single-channel mode, the analog input signal is
sampled on both the rising and falling edges. In dual-channel mode, the analog signal is sampled
on the rising edge. This differential input has an internal untrimmed 100-Ω differential termination
and is self-biased to the optimal input common-mode voltage as long as DEVCLK_LVPECL_EN
is set to 0.
NO.
NAME
D8
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
F1
CLK+
I
F2, F3
AGND
—
F4
VA19
I
1.9-V analog supply
F5
VA11
I
1.1-V analog supply
F6
AGND
—
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
F7
CALSTAT
O
Foreground calibration status output or device alarm output. Functionality is programmed through
CAL_STATUS_SEL. This pin can be left disconnected if not used.
F8
SCLK
I
Serial interface clock. This pin functions as the serial-interface clock input that clocks the serial
programming data in and out. The Using the Serial Interface section describes the serial interface
in more detail. Supports 1.1-V and 1.8-V CMOS levels.
F9, F10
DGND
—
Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
F11
DA4–
O
High-speed serialized data output for channel A, lane 4, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
6
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
DA0–
O
High-speed serialized data output for channel A, lane 0, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
G1
CLK–
I
Device (sampling) clock negative input. TI strongly recommends using AC-coupling for best
performance.
G2, G3
AGND
—
G4
VA19
I
1.9-V analog supply
G5
VA11
I
1.1-V analog supply
G6
AGND
—
G7
VD11
I
1.1-V digital supply
G8
SDI
I
Serial interface data input. The Using the Serial Interface section describes the serial interface in
more detail. Supports 1.1-V and 1.8-V CMOS levels.
G9, G10
DGND
—
Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
G11
DB4–
O
High-speed serialized data output for channel B, lane 4, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
G12
DB0–
O
High-speed serialized data output for channel B, lane 0, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
H1
AGND
—
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
H2, H3, H4
VA19
I
1.9-V analog supply
H5
VA11
I
1.1-V analog supply
H6
AGND
—
H7
VD11
I
1.1-V digital supply
H8
SDO
O
Serial interface data output. The Using the Serial Interface section describes the serial interface
in more detail. This pin is high impedance during normal device operation. This pin outputs 1.9-V
CMOS levels during serial interface read operations. This pin can be left disconnected if not used.
H9, H10
VD11
I
1.1-V digital supply
H11
DB4+
O
High-speed serialized data output for channel B, lane 4, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
H12
DB0+
O
High-speed serialized data output for channel B, lane 0, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
J1
AGND
—
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
J2, J3
VA11
I
1.1-V analog supply
J4
VA19
I
1.9-V analog supply
J5
VA11
I
1.1-V analog supply
J6
AGND
—
J7
NCOB1
I
Tie this pin to GND.
NO.
NAME
F12
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
J8
ORB1
O
Fast overrange detection status for channel B for the OVR_T1 threshold. When the analog input
exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum
pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.
This pin can be left disconnected if not used.
J9, J10
DGND
—
Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
DB5–
O
High-speed serialized data output for channel B, lane 5, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
DB1–
O
High-speed serialized data output for channel B, lane 1, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
NO.
NAME
J11
J12
K1
SYSREF+
I
The SYSREF positive input is used to achieve synchronization and deterministic latency across
the JESD204B interface. This differential input (SYSREF+ to SYSREF–) has an internal
untrimmed 100-Ω differential termination and can be AC-coupled when SYSREF_LVPECL_EN is
set to 0. This input is self-biased when SYSREF_LVPECL_EN is set to 0. The termination
changes to 50 Ω to ground on each input pin (SYSREF+ and SYSREF–) and can be DC-coupled
when SYSREF_LVPECL_EN is set to 1. This input is not self-biased when
SYSREF_LVPECL_EN is set to 1 and must be biased externally to the input common-mode
voltage range provided in the Recommended Operating Conditions table.
K2
TDIODE+
I
Temperature diode positive (anode) connection. An external temperature sensor can be
connected to TDIODE+ and TDIODE– to monitor the junction temperature of the device. This pin
can be left disconnected if not used.
K3
TDIODE–
I
Temperature diode negative (cathode) connection. This pin can be left disconnected if not used.
K4
VA19
I
1.9-V analog supply
K5
VA11
I
1.1-V analog supply
K6
PD
I
This pin disables all analog circuits and serializer outputs when set high for temperature diode
calibration only. Do not use this pin to power down the device for power savings. Tie this pin to
GND during normal operation. For information regarding reliable serializer operation, see footnote
(1)
in the Pin Functions table.
K7
NCOB0
I
Tie this pin to GND.
K8
ORB0
O
Fast overrange detection status for channel B for the OVR_T0 threshold. When the analog input
exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum
pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information.
This pin can be left disconnected if not used.
K9, K10
VD11
I
1.1-V digital supply
K11
DB5+
O
High-speed serialized data output for channel B, lane 5, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
K12
DB1+
O
High-speed serialized data output for channel B, lane 1, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
SYSREF negative input
L1
SYSREF–
I
L2, L3, L4, L5,
L6, L7
AGND
—
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
L8
DB7+
O
High-speed serialized data output for channel B, lane 7, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
L9
DB7–
O
High-speed serialized data output for channel B, lane 7, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
L10
DB6+
O
High-speed serialized data output for channel B, lane 6, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
L11
DB6–
O
High-speed serialized data output for channel B, lane 6, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
L12
DGND
—
Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
8
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Pin Functions (continued)
PIN
NO.
NAME
M1, M2, M3
AGND
I/O
—
DESCRIPTION
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
M4
INB+
I
Channel B analog input positive connection. The differential full-scale input voltage is determined
by the FS_RANGE_B register (see the Full-Scale Voltage (VFS) Adjustment section). This input
is terminated to ground through a 50-Ω termination resistor. The input common-mode voltage
must typically be set to 0 V (GND) and must follow the recommendations in the Recommended
Operating Conditions table. This pin can be left disconnected if not used. Using INA± is
recommended in single-channel mode for optimized performance.
M5
INB–
I
Channel B analog input negative connection. See INB+ for detailed description. This input is
terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not
used.
AGND
—
Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
M6, M7
M8
DB3+
O
High-speed serialized data output for channel B, lane 3, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
M9
DB3–
O
High-speed serialized data output for channel B, lane 3, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
M10
DB2+
O
High-speed serialized data output for channel B, lane 2, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential termination
at the receiver. This pin can be left disconnected if not used. For information regarding reliable
serializer operation, see footnote (1) in the Pin Functions table.
M11
DB2–
O
High-speed serialized data output for channel B, lane 2, negative connection. This pin can be left
disconnected if not used. For information regarding reliable serializer operation, see footnote (1) in
the Pin Functions table.
M12
DGND
—
Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit
board.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range
MIN
MAX
VA19 (2)
–0.3
2.35
VA11 (2)
–0.3
1.32
VD11 (3)
–0.3
1.32
Voltage between VD11 and VA11
–1.32
1.32
Voltage between AGND and DGND
UNIT
V
–0.1
0.1
DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–,
TMSTP+, TMSTP– (3)
–0.5
min(1.32,
VD11+0.5)
CLK+, CLK–, SYSREF+, SYSREF– (2)
–0.5
min(1.32,
VA11+0.5)
BG, TDIODE+, TDIODE– (2)
–0.5
min(2.35,
VA19+0.5)
–1
1
–0.5
VA19+0.5
Peak input current (any input except INA+, INA–, INB+, INB–)
–25
25
mA
Peak input current (INA+, INA–, INB+, INB–)
–50
50
mA
16.4
dBm
100
mA
Pin voltage range
INA+, INA–, INB+, INB–
(2)
CALSTAT, CALTRIG, NCOA0, NCOA1,
NCOB0, NCOB1, ORA0, ORA1, ORB0,
ORB1, PD, SCLK, SCS, SDI, SDO,
SYNCSE (2)
Peak RF input power (INA+, INA–, INB+, INB–)
Single-ended with ZS-SE = 50 Ω or differential
with ZS-DIFF = 100 Ω
Peak total input current (sum of absolute value of all currents forced in or out, not including
power-supply current)
Operating free-air temperature, TA
–40
Operating junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
–65
V
V
85
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Measured to AGND.
Measured to DGND.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
10
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±2500
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
(1)
1.8
1.9
2.0
VA11, analog 1.1-V supply (1)
1.05
1.1
1.15
VD11, digital 1.1-V supply (2)
1.05
1.1
1.15
INA+, INA–, INB+, INB– (1)
–50
0
100
0
0.3
0.55
0
0.3
0.55
0.4
1.0
2.0
VA19, analog 1.9-V supply
VDD
Supply voltage range
VCMI
CLK+, CLK–, SYSREF+,
SYSREF– (1) (3)
Input common-mode voltage
TMSTP+, TMSTP–
CLK+ to CLK–, SYSREF+ to
SYSREF–, TMSTP+ to TMSTP–
Input voltage, peak-to-peak
differential
VID
(1) (4)
INA+ to INA–, INB+ to INB–
(5)
VIH
High-level input voltage
CALTRIG, NCOA0, NCOA1,
NCOB0, NCOB1, PD, SCLK, SCS,
SDI, SYNCSE (1)
VIL
Low-level input voltage
CALTRIG, NCOA0, NCOA1,
NCOB0, NCOB1, PD, SCLK, SCS,
SDI, SYNCSE (1)
IC_TD
Temperature diode input current
TDIODE+ to TDIODE–
CL
BG max load capacitance
IO
BG max output current
DC
Input clock duty cycle
TA
Operating free-air temperature
TJ
(1)
(2)
(3)
(4)
(5)
(6)
(7)
UNIT
V
mV
V
VPP-DIFF
1.0
0.7
V
0.45
V
100
30%
Operating junction temperature
MAX
50%
–40
(6) (7)
µA
50
pF
100
µA
70%
85
°C
105
°C
Measured to AGND.
Measured to DGND.
TI strongly recommends that CLK± be AC-coupled with DEVCLK_LVPECL_EN set to 0 to allow CLK± to self-bias to the optimal input
common-mode voltage for best performance. TI recommends AC-coupling for SYSREF± unless DC-coupling is required, in which case
the LVPECL input mode must be used (SYSREF_LVPECL_EN = 1).
TMSTP± does not have internal biasing that requires TMSTP± to be biased externally whether AC-coupled with TMSTP_LVPECL_EN =
0 or DC-coupled with TMSTP_LVPECL_EN = 1.
The ADC output code saturates when VID for INA± or INB± exceeds the programmed full-scale voltage (VFS) set by FS_RANGE_A for
INA± or FS_RANGE_B for INB±.
Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.
Tested up to 1000 hours continuous operation at TJ = 125°C. See the Absolute Maximum Ratings table for the absolute maximum
operational temperature.
6.4 Thermal Information
ADC08DJ3200
THERMAL METRIC
(1)
AAV (FCBGA)
UNIT
144 PINS
RθJA
Junction-to-ambient thermal resistance
25.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
1.1
°C/W
RθJB
Junction-to-board thermal resistance
8.2
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
8.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: DC Specifications
typical values are at TA = 25°C, VA19 = 1.9 V , VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA± in single-channel modes, fIN = 248 MHz, AIN = –1 dBFS, fCLK =
maximum-rated clock frequency, filtered 1-VPP sine-wave clock, JMODE = 17, and background calibration (unless otherwise
noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range
provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC ACCURACY
Resolution
DNL
Differential nonlinearity
INL
Integral nonlinearity
Resolution with no missing codes
8
Bits
±0.15
LSB
±0.3
LSB
ANALOG INPUTS (INA+, INA–, INB+, INB–)
VOFF
Offset error
Default full-scale voltage, OS_CAL disabled
±0.6
mV
VOFF_ADJ
Input offset voltage
adjustment range
Available offset correction range (see
OS_CAL or OADJ_x_INx)
±55
mV
VOFF_DRIFT
Offset drift
Foreground calibration at nominal
temperature only
23
Foreground calibration at each temperature
Analog differential input fullscale range
VIN_FSR
VIN_FSR_DRIFT
Analog differential input fullscale range drift
Default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000)
750
800
Maximum full-scale voltage (FS_RANGE_A
= FS_RANGE_B = 0xFFFF)
1000
1040
Minimum full-scale voltage (FS_RANGE_A
= FS_RANGE_B = 0x2000)
480
Default FS_RANGE_A and FS_RANGE_B
setting, foreground calibration at nominal
temperature only, inputs driven by 50-Ω
source, includes effect of RIN drift
–0.01
Default FS_RANGE_A and FS_RANGE_B
setting, foreground calibration at each
temperature, inputs driven by 50-Ω source,
includes effect of RIN drift
0.03
VIN_FSR_MATCH
Analog differential input fullscale range matching
Matching between INA+, INA– and INB+,
INB–, default setting, dual-channel mode
RIN
Single-ended input resistance
to AGND
Each input pin is terminated to AGND,
measured at TA = 25°C
RIN_TEMPCO
Input termination linear temperature coefficient
CIN
Single-ended input
capacitance
µV/°C
0
850
mVPP
500
%/°C
0.625%
48
50
17.6
Single-channel mode at DC
0.4
Dual-channel mode at DC
0.4
52
Ω
mΩ/°C
pF
TEMPERATURE DIODE CHARACTERISTICS (TDIODE+, TDIODE–)
Temperature diode voltage
slope
ΔVBE
Forced forward current of 100 µA. Offset
voltage (approximately 0.792 V at 0°C)
varies with process and must be measured
for each part. Offset measurement must be
done with the device unpowered or with the
PD pin asserted to minimize device selfheating. Assert the PD pin only long enough
to take the offset measurement.
–1.6
mV/°C
BAND-GAP VOLTAGE OUTPUT (BG)
VBG
Reference output voltage
IL ≤ 100 µA
1.1
V
VBG_DRIFT
Reference output temperature
IL ≤ 100 µA
drift
–64
µV/°C
12
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Electrical Characteristics: DC Specifications (continued)
typical values are at TA = 25°C, VA19 = 1.9 V , VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA± in single-channel modes, fIN = 248 MHz, AIN = –1 dBFS, fCLK =
maximum-rated clock frequency, filtered 1-VPP sine-wave clock, JMODE = 17, and background calibration (unless otherwise
noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range
provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CLOCK INPUTS (CLK+, CLK–, SYSREF+, SYSREF–, TMSTP+, TMSTP–)
ZT
VCM
Internal termination
Input common-mode voltage,
self-biased
Differential termination with
DEVCLK_LVPECL_EN = 0,
SYSREF_LVPECL_EN = 0, and
TMSTP_LVPECL_EN = 0
110
Ω
Single-ended termination to GND (per pin)
with DEVCLK_LVPECL_EN = 0,
SYSREF_LVPECL_EN = 0, and
TMSTP_LVPECL_EN = 0
55
Self-biasing common-mode voltage for
CLK± when AC-coupled
(DEVCLK_LVPECL_EN must be set to 0)
0.26
Self-biasing common-mode voltage for
SYSREF± when AC-coupled
(SYSREF_LVPECL_EN must be set to 0)
and with receiver enabled
(SYSREF_RECV_EN = 1)
0.29
Self-biasing common mode voltage for
SYSREF± when AC-coupled
(SYSREF_LVPECL_EN must be set to 0)
and with receiver disabled
(SYSREF_RECV_EN = 0)
VA11
V
CL_DIFF
Differential input capacitance
Between positive and negative differential
input pins
0.1
pF
CL_SE
Single-ended input
capacitance
Each input to ground
0.5
pF
SERDES OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)
VOD
Differential output voltage,
peak-to-peak
VCM
Output common mode voltage AC coupled
ZDIFF
Differential output impedance
100-Ω load
550
600
650
mVPPDIFF
VD11 / 2
V
100
Ω
CMOS INTERFACE (SCLK, SDI, SDO, SCS, PD, NCOA0, NCOA1, NCOB0, NCOB1, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1,
SYNCSE)
IIH
High-level input current
–40
40
µA
IIL
Low-level input current
–40
40
µA
CI
Input capacitance
VOH
High-level output voltage
ILOAD = –400 µA
VOL
Low-level output voltage
ILOAD = 400 µA
2
pF
1.65
V
150
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6.6 Electrical Characteristics: Power Consumption
typical values are at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA± in single-channel modes, fIN = 248 MHz, AIN = –1 dBFS, fCLK =
maximum-rated clock frequency, filtered 1-VPP sine-wave clock, JMODE = 17, and background calibration (unless otherwise
noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range
provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
899
950
mA
501
620
mA
451
650
mA
2.8
3.2
W
IVA19
1.9-V analog supply current
IVA11
1.1-V analog supply current
IVD11
1.1-V digital supply current
PDIS
Power dissipation
IVA19
1.9-V analog supply current
IVA11
1.1-V analog supply current
IVD11
1.1-V digital supply current
PDIS
Power dissipation
IVA19
1.9-V analog supply current
IVA11
1.1-V analog supply current
IVD11
1.1-V digital supply current
PDIS
Power dissipation
3.4
W
IVA19
1.9-V analog supply current
981
mA
IVA11
1.1-V analog supply current
501
mA
IVD11
1.1-V digital supply current
447
mA
PDIS
Power dissipation
2.9
W
IVA19
1.9-V analog supply current
899
mA
IVA11
1.1-V analog supply current
519
mA
IVD11
1.1-V digital supply current
363
mA
PDIS
Power dissipation
2.6
W
14
Power mode 1: single-channel
mode, JMODE 5 (8 lanes),
foreground calibration
Power mode 2: dual-channel mode,
JMODE 7 (8 lanes), foreground
calibration
Power mode 3: single-channel
mode, JMODE 5 (8 lanes),
background calibration
Power mode 4: dual-channel mode,
JMODE 18 (16 lanes), foreground
calibration
Power mode 5: single-channel
mode, JMODE 4 (4 lanes),
foreground calibration, fCLK =
2.5 GHz
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981
mA
501
mA
463
mA
2.9
W
1179
mA
602
mA
467
mA
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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode)
typical values are at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock frequency, filtered 1-VPP sine-wave
clock, JMODE = 18, and background calibration (unless otherwise noted); minimum and maximum values are at nominal
supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
FPBW
XTALK
Full-power input bandwidth
(–3 dB) (1)
Channel-to-channel crosstalk
TEST CONDITIONS
MIN
TYP
Foreground calibration
8.1
Background calibration
8.1
Dual-channel mode, aggressor =
400 MHz, –1 dBFS
–92
Dual-channel mode, aggressor =
3 GHz, –1 dBFS
–67
Dual-channel mode, aggressor =
6 GHz, –1 dBFS
–61
MAX
UNIT
GHz
dB
CER
Code error rate
Maximum CER, does not include
SerDes bit-error rate (BER)
10–18
Errors/
sample
NOISEDC
DC input noise standard deviation
No input, foreground calibration,
excludes DC offset, includes fixed
interleaving spur (fs / 2 spur)
0.45
LSB
fIN = 347 MHz, AIN = –1 dBFS
49.1
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A and
FS_RANGE_B setting, foreground
calibration
49.3
fIN = 997 MHz, AIN = –1 dBFS
SNR
SNR
SINAD
Signal-to-noise ratio, large signal,
excluding DC, HD2 to HD9 and
interleaving spurs
Signal-to-noise ratio, small signal,
excluding DC, HD2 to HD9 and
interleaving spurs
Signal-to-noise and distortion ratio,
large signal, excluding DC and fS / 2
fixed spurs
fIN = 2397 MHz, AIN = –1 dBFS
49.0
47.0
49.0
fIN = 4997 MHz, AIN = –1 dBFS
48.3
fIN = 6397 MHz, AIN = –1 dBFS
47.8
fIN = 8197 MHz, AIN = –1 dBFS
47.2
fIN = 347 MHz, AIN = –16 dBFS
49.1
fIN = 997 MHz, AIN = –16 dBFS
49.1
fIN = 2397 MHz, AIN = –16 dBFS
49.1
fIN = 4997 MHz, AIN = –16 dBFS
49.4
fIN = 6397 MHz, AIN = –16 dBFS
49.2
fIN = 8197 MHz, AIN = –16 dBFS
49.4
fIN = 347 MHz, AIN = –1 dBFS
48.8
fIN = 997 MHz, AIN = –1 dBFS
48.7
fIN = 2397 MHz, AIN = –1 dBFS
46.3
ENOB
(1)
48.5
fIN = 4997 MHz, AIN = –1 dBFS
47.0
fIN = 6397 MHz, AIN = –1 dBFS
46.2
fIN = 8197 MHz, AIN = –1 dBFS
44.8
fIN = 347 MHz, AIN = –1 dBFS
7.8
fIN = 997 MHz, AIN = –1 dBFS
Effective number of bits, large
signal, excluding DC and fS / 2 fixed
spurs
48.8
fIN = 2397 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A and
FS_RANGE_B setting, foreground
calibration
fIN = 2397 MHz, AIN = –1 dBFS
dBFS
dBFS
dBFS
7.8
7.4
7.8
fIN = 4997 MHz, AIN = –1 dBFS
7.5
fIN = 6397 MHz, AIN = –1 dBFS
7.4
fIN = 8197 MHz, AIN = –1 dBFS
7.1
Bits
Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC drops 3 dB below the
power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB full-power input bandwidth.
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Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)
typical values are at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock frequency, filtered 1-VPP sine-wave
clock, JMODE = 18, and background calibration (unless otherwise noted); minimum and maximum values are at nominal
supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
SFDR
SFDR
fS / 2
HD2
HD3
16
Spurious-free dynamic range, large
signal, excluding DC and fS / 2 fixed
spurs
Spurious-free dynamic range, small
signal, excluding DC and fS / 2 fixed
spurs
fS / 2 fixed interleaving spur,
independent of input signal
Second-order harmonic distortion
Third-order harmonic distortion
TEST CONDITIONS
MIN
TYP
fIN = 347 MHz, AIN = –1 dBFS
69
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A and
FS_RANGE_B setting, foreground
calibration
68
fIN = 997 MHz, AIN = –1 dBFS
67
fIN = 2397 MHz, AIN = –1 dBFS
55
66
fIN = 2397 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A and
FS_RANGE_B setting, foreground
calibration
62
fIN = 4997 MHz, AIN = –1 dBFS
57
fIN = 6397 MHz, AIN = –1 dBFS
55
fIN = 8197 MHz, AIN = –1 dBFS
52
fIN = 347 MHz, AIN = –16 dBFS
67
fIN = 997 MHz, AIN = –16 dBFS
67
fIN = 2397 MHz, AIN = –16 dBFS
67
fIN = 4997 MHz, AIN = –16 dBFS
67
fIN = 6397 MHz, AIN = –16 dBFS
67
fIN = 8197 MHz, AIN = –16 dBFS
67
No input
–70
fIN = 347 MHz, AIN = –1 dBFS
–75
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A and
FS_RANGE_B setting, foreground
calibration
–73
fIN = 997 MHz, AIN = –1 dBFS
–75
fIN = 2397 MHz, AIN = –1 dBFS
–73
fIN = 2397 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A and
FS_RANGE_B setting, foreground
calibration
–72
fIN = 4997 MHz, AIN = –1 dBFS
–68
fIN = 6397 MHz, AIN = –1 dBFS
–67
fIN = 8197 MHz, AIN = –1 dBFS
–61
fIN = 347 MHz, AIN = –1 dBFS
–71
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A and
FS_RANGE_B setting, foreground
calibration
–69
fIN = 997 MHz, AIN = –1 dBFS
–69
fIN = 2397 MHz, AIN = –1 dBFS
–67
fIN = 2397 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A and
FS_RANGE_B setting, foreground
calibration
–62
fIN = 4997 MHz, AIN = –1 dBFS
–57
fIN = 6397 MHz, AIN = –1 dBFS
–55
fIN = 8197 MHz, AIN = –1 dBFS
–52
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MAX
UNIT
dBFS
dBFS
–55
–60
–60
dBFS
dBFS
dBFS
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Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)
typical values are at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock frequency, filtered 1-VPP sine-wave
clock, JMODE = 18, and background calibration (unless otherwise noted); minimum and maximum values are at nominal
supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER
fS / 2 – fIN
SPUR
IMD3
fS / 2 – fIN interleaving spur, signal
dependent
Worst harmonic, fourth-order
distortion or higher
Third-order intermodulation
distortion
TEST CONDITIONS
MIN
TYP
fIN = 347 MHz, AIN = –1 dBFS
–72
fIN = 997 MHz, AIN = –1 dBFS
–70
fIN = 2397 MHz, AIN = –1 dBFS
–69
fIN = 4997 MHz, AIN = –1 dBFS
–66
fIN = 6397 MHz, AIN = –1 dBFS
–64
fIN = 8197 MHz, AIN = –1 dBFS
–63
fIN = 347 MHz, AIN = –1 dBFS
–74
fIN = 997 MHz, AIN = –1 dBFS
–71
fIN = 2397 MHz, AIN = –1 dBFS
–73
fIN = 4997 MHz, AIN = –1 dBFS
–78
fIN = 6397 MHz, AIN = –1 dBFS
–78
fIN = 8197 MHz, AIN = –1 dBFS
–78
fIN = 347 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone
–92
fIN = 997 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone
–80
fIN = 2485 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone
–71
fIN = 4997 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone
–63
fIN = 5997 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone
–60
fIN = 7997 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone
–49
MAX
–55
–60
UNIT
dBFS
dBFS
dBFS
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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode)
typical values are at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A =
0xA000), input signal applied to INA±, fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock frequency, filtered 1-VPP
sine-wave clock, JMODE = 17, and background calibration (unless otherwise noted); minimum and maximum values are at
nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating
Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
Foreground calibration
7.9
Background calibration
7.9
MAX
UNIT
FPBW
Full-power input bandwidth
(–3 dB) (1)
CER
Code error rate
Maximum CER, does not include
SerDes bit-error rate (BER)
10–18
Errors/
sample
NOISEDC
DC input noise standard deviation
No input, foreground calibration,
excludes DC offset, includes fixed
interleaving spurs (fS / 2 and fS / 4
spurs)
0.35
LSB
fIN = 347 MHz, AIN = –1 dBFS
49.0
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
49.2
fIN = 997 MHz, AIN = –1 dBFS
SNR
SNR
SINAD
Signal-to-noise ratio, large signal,
excluding DC, HD2 to HD9 and
interleaving spurs
Signal-to-noise ratio, small signal,
excluding DC, HD2 to HD9 and
interleaving spurs
fIN = 2397 MHz, AIN = –1 dBFS
49.0
47.0
49.0
fIN = 4997 MHz, AIN = –1 dBFS
48.2
fIN = 6397 MHz, AIN = –1 dBFS
47.9
fIN = 8197 MHz, AIN = –1 dBFS
47.1
fIN = 347 MHz, AIN = –16 dBFS
49.2
fIN = 997 MHz, AIN = –16 dBFS
49.2
fIN = 2397 MHz, AIN = –16 dBFS
49.2
fIN = 4997 MHz, AIN = –16 dBFS
49.2
fIN = 6397 MHz, AIN = –16 dBFS
49.2
fIN = 8197 MHz, AIN = –16 dBFS
49.2
fIN = 347 MHz, AIN = –1 dBFS
48.7
fIN = 997 MHz, AIN = –1 dBFS
48.4
45.1
44.8
fIN = 347 MHz, AIN = –1 dBFS
7.8
Effective number of bits, large
fIN = 2397 MHz, AIN = –1 dBFS
signal, excluding DC and fS / 2 fixed
fIN = 4997 MHz, AIN = –1 dBFS
spurs
fIN = 6397 MHz, AIN = –1 dBFS
18
dBFS
dBFS
dBFS
46.6
fIN = 8197 MHz, AIN = –1 dBFS
fIN = 8197 MHz, AIN = –1 dBFS
(1)
48.0
47.2
fIN = 997 MHz, AIN = –1 dBFS
ENOB
48.8
fIN = 2397 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
Signal-to-noise and distortion ratio,
fIN = 2397 MHz, AIN = –1 dBFS
large signal, excluding DC and fS / 2
fIN = 4997 MHz, AIN = –1 dBFS
fixed spurs
fIN = 6397 MHz, AIN = –1 dBFS
GHz
7.8
7.2
7.7
7.6
dBFS
7.5
7.1
Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC drops 3 dB below the
power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB full-power input bandwidth.
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SLVSDR1 – FEBRUARY 2018
Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)
typical values are at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A =
0xA000), input signal applied to INA±, fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock frequency, filtered 1-VPP
sine-wave clock, JMODE = 17, and background calibration (unless otherwise noted); minimum and maximum values are at
nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating
Conditions table
PARAMETER
TEST CONDITIONS
MIN
fIN = 347 MHz, AIN = –1 dBFS
66
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
64
fIN = 997 MHz, AIN = –1 dBFS
SFDR
SFDR
Spurious free dynamic range, large
signal, excluding DC, fS / 4 and
fS / 2 fixed spurs
Spurious free dynamic range, small
signal, excluding DC, fS / 4 and
fS / 2 fixed spurs
TYP
fIN = 2397 MHz, AIN = –1 dBFS
58
fIN = 2397 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
54
fIN = 4997 MHz, AIN = –1 dBFS
59
fIN = 6397 MHz, AIN = –1 dBFS
57
fIN = 8197 MHz, AIN = –1 dBFS
52
fIN = 347 MHz, AIN = –16 dBFS
68
fIN = 997 MHz, AIN = –16 dBFS
68
fIN = 2397 MHz, AIN = –16 dBFS
68
fIN = 4997 MHz, AIN = –16 dBFS
68
fIN = 6397 MHz, AIN = –16 dBFS
68
fIN = 8197 MHz, AIN = –16 dBFS
67
–65
fS / 2
fS / 2 fixed interleaving spur,
independent of input signal
fS / 4
fS / 4 fixed interleaving spur,
independent of input signal
No input
–64
fIN = 347 MHz, AIN = –1 dBFS
–74
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
–71
fIN = 997 MHz, AIN = –1 dBFS
–72
fIN = 2397 MHz, AIN = –1 dBFS
–75
fIN = 2397 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
–72
fIN = 4997 MHz, AIN = –1 dBFS
–72
fIN = 6397 MHz, AIN = –1 dBFS
–68
fIN = 8197 MHz, AIN = –1 dBFS
–68
fIN = 347 MHz, AIN = –1 dBFS
–71
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
–69
fIN = 997 MHz, AIN = –1 dBFS
–68
fIN = 2397 MHz, AIN = –1 dBFS
–68
fIN = 2397 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
–63
fIN = 4997 MHz, AIN = –1 dBFS
–59
fIN = 6397 MHz, AIN = –1 dBFS
–58
fIN = 8197 MHz, AIN = –1 dBFS
–55
HD3
Second-order harmonic distortion
Third-order harmonic distortion
UNIT
62
45
No input, foreground calibration,
OS_CAL disabled, spur can be
improved by running OS_CAL
HD2
MAX
dBFS
dBFS
dBFS
–55
–60
–60
dBFS
dBFS
dBFS
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Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)
typical values are at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A =
0xA000), input signal applied to INA±, fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock frequency, filtered 1-VPP
sine-wave clock, JMODE = 17, and background calibration (unless otherwise noted); minimum and maximum values are at
nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating
Conditions table
PARAMETER
fS / 2 – fIN
fS / 4 ± fIN
SPUR
IMD3
20
fS / 2 – fIN interleaving spur, signal
dependent
fS / 4 ± fIN interleaving spurs, signal
dependent
Worst harmonic, fourth-order
distortion or higher
Third-order intermodulation
distortion
TEST CONDITIONS
MIN
TYP
fIN = 347 MHz, AIN = –1 dBFS
–68
fIN = 997 MHz, AIN = –1 dBFS
–62
fIN = 2397 MHz, AIN = –1 dBFS
–58
fIN = 4997 MHz, AIN = –1 dBFS
–62
fIN = 6397 MHz, AIN = –1 dBFS
–63
fIN = 8197 MHz, AIN = –1 dBFS
–53
fIN = 347 MHz, AIN = –1 dBFS
–72
fIN = 997 MHz, AIN = –1 dBFS
–72
fIN = 2397 MHz, AIN = –1 dBFS
–72
fIN = 4997 MHz, AIN = –1 dBFS
–68
fIN = 6397 MHz, AIN = –1 dBFS
–65
fIN = 8197 MHz, AIN = –1 dBFS
–63
fIN = 347 MHz, AIN = –1 dBFS
–73
fIN = 997 MHz, AIN = –1 dBFS
–72
fIN = 2397 MHz, AIN = –1 dBFS
–73
fIN = 4997 MHz, AIN = –1 dBFS
–80
fIN = 6397 MHz, AIN = –1 dBFS
–82
fIN = 8197 MHz, AIN = –1 dBFS
–79
fIN = 347 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone
–83
fIN = 997 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone
–79
fIN = 2485 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone
–70
fIN = 4997 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone
–64
fIN = 5997 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone
–62
fIN = 7997 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone
–52
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MAX
–45
–60
–60
UNIT
dBFS
dBFS
dBFS
dBFS
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6.9 Timing Requirements
MIN
NOM
MAX
UNIT
3200
MHz
DEVICE (Sampling) CLOCK (CLK+, CLK–)
Input clock frequency (CLK+, CLK–), both single-channel and dual-channel
modes (1)
fCLK
800
SYSREF (SYSREF+, SYSREF–)
tINV(SYSREF)
Width of invalid SYSREF capture region of CLK± period, indicating setup or
hold time violation, as measured by the SYSREF_POS status register (2)
tINV(TEMP)
Drift of invalid SYSREF capture region over temperature, positive number
indicates a shift toward the MSB of the SYSREF_POS register
tINV(VA11)
Drift of invalid SYSREF capture region over the VA11 supply voltage, positive
number indicates a shift toward the MSB of the SYSREF_POS register
tSTEP(SP)
Delay of the SYSREF_POS LSB
t(PH_SYS)
Minimum SYSREF± assertion duration after a SYSREF± rising edge event
4
ns
t(PL_SYS)
Minimum SYSREF± de-assertion duration after a SYSREF± falling edge event
1
ns
48
ps
0
ps/°C
0.36
ps/mV
SYSREF_ZOOM = 0
77
SYSREF_ZOOM = 1
24
ps
JESD204B SYNC TIMING (SYNCSE or TMSTP±)
tH(SYNCSE)
tSU(SYNCSE)
t(SYNCSE)
Minimum hold time from a multiframe boundary
(SYSREF rising edge captured high) to deassertion of the JESD204B SYNC signal
(SYNCSE if SYNC_SEL = 0 or TMSTP± if
SYNC_SEL = 1) for NCO synchronization
(NCO_SYNC_ILA = 1)
JMODE = 4 or 6
21
JMODE = 5 or 7
17
JMODE = 17 or 18
9
Minimum setup time from de-assertion of the
JMODE = 4 or 6
JESD204B SYNC signal (SYNCSE if SYNC_SEL
JMODE = 5 or 7
= 0 or TMSTP± if SYNC_SEL = 1) to multiframe
boundary (SYSREF rising edge captured high)
JMODE = 17 or 18
for NCO synchronization (NCO_SYNC_ILA = 1)
–2
SYNCSE minimum assertion time to trigger link resynchronization
tCLK
cycles
2
tCLK
cycles
10
4
Frames
SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)
fCLK(SCLK)
Maximum serial clock frequency
t(PH)
Minimum serial clock high value pulse duration
32
ns
t(PL)
Minimum serial clock low value pulse duration
32
ns
tSU(SCS)
Minimum setup time from SCS to rising edge of SCLK
30
ns
tH(SCS)
Minimum hold time from rising edge of SCLK to SCS
3
ns
tSU(SDI)
Minimum setup time from SDI to rising edge of SCLK
30
ns
tH(SDI)
Minimum hold time from rising edge of SCLK to SDI
3
ns
(1)
(2)
15.625
MHz
Unless functionally limited to a smaller range in Table 10 based on the programmed JMODE.
Use SYSREF_POS to select an optimal SYSREF_SEL value for SYSREF capture, see the SYSREF Position Detector and Sampling
Position Selection (SYSREF Windowing) section for more information on SYSREF windowing. The invalid region, specified by
tINV(SYSREF), indicates the portion of the CLK± period (tCLK), as measured by SYSREF_SEL, that may result in a setup and hold violation.
Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that used to
find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in SYSREF_POS,
otherwise a temperature-dependent SYSREF_SEL selection may be needed to track the skew between CLK± and SYSREF±.
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6.10 Switching Characteristics
typical values are at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA± in single-channel modes, fIN = 248 MHz, AIN = –1 dBFS, fCLK =
maximum-rated clock frequency, filtered 1-VPP sine-wave clock, JMODE = 17, and background calibration (unless otherwise
noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range
provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEVICE (Sampling) CLOCK (CLK+, CLK–)
tAD
Sampling (aperture) delay from
CLK± rising edge (dual-channel
mode) or rising and falling edge
(single-channel mode) to sampling
instant
tTAD(MAX)
tTAD(STEP)
tAJ
TAD_COARSE = 0x00, TAD_FINE =
0x00, and TAD_INV = 0
360
Maximum tAD adjust programmable
delay, not including clock inversion
(TAD_INV = 0)
Coarse adjustment (TAD_COARSE
= 0xFF)
289
Fine adjustment (TAD_FINE = 0xFF)
4.9
tAD adjust programmable delay step
size
Coarse adjustment (TAD_COARSE)
Aperture jitter, rms
ps
ps
1.13
ps
Fine adjustment (TAD_FINE)
19
fs
Minimum tAD adjust coarse setting
(TAD_COARSE = 0x00, TAD_INV =
0)
50
Maximum tAD adjust coarse setting
(TAD_COARSE = 0xFF) excluding
TAD_INV (TAD_INV = 0)
(1)
fs
70
SERIAL DATA OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)
fSERDES
Serialized output bit rate
UI
Serialized output unit interval
tTLH
Low-to-high transition time
(differential)
20% to 80%, PRBS-7 test pattern,
12.8 Gbps, SER_PE = 0x04
37
ps
tTHL
High-to-low transition time
(differential)
20% to 80%, PRBS-7 test pattern,
12.8 Gbps, SER_PE = 0x04
37
ps
DDJ
Data dependent jitter, peak-to-peak
PRBS-7 test pattern, 12.8 Gbps,
SER_PE = 0x04, JMODE = 2
7.8
ps
RJ
Random jitter, RMS
PRBS-7 test pattern, 12.8 Gbps,
SER_PE = 0x04, JMODE = 2
1.1
ps
TJ
Total jitter, peak-to-peak, with
PRBS-7 test pattern, 8 Gbps,
Gaussian portion defined with
SER_PE = 0x04, JMODE = 4, 5, 6,
respect to a BER = 1e-15 (Q = 7.94) 7
28
ps
(1)
22
1
12.8
Gbps
78.125
1000
ps
tAJ increases because of additional attenuation on the internal clock path.
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Switching Characteristics (continued)
typical values are at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA± in single-channel modes, fIN = 248 MHz, AIN = –1 dBFS, fCLK =
maximum-rated clock frequency, filtered 1-VPP sine-wave clock, JMODE = 17, and background calibration (unless otherwise
noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range
provided in the Recommended Operating Conditions table
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC CORE LATENCY
Deterministic delay from the CLK±
edge that samples the reference
sample to the CLK± edge that
samples SYSREF going high (2)
tADC
JMODE = 4
–4.5
JMODE = 5
–24.5
JMODE = 6
–5
JMODE = 7
–25
JMODE = 17
–48.5
JMODE = 18
–49
tCLK cycles
JESD204B AND SERIALIZER LATENCY
Delay from the CLK± rising edge
that samples SYSREF high to the
first bit of the multiframe on the
JESD204B serial output lane
corresponding to the reference
sample of tADC (3)
tTX
JMODE = 4
67
80
JMODE = 5
106
119
JMODE = 6
67
80
JMODE = 7
106
119
JMODE = 17
195
208
JMODE = 18
195
208
tCLK cycles
SERIAL PROGRAMMING INTERFACE (SDO)
t(OZD)
Maximum delay from the falling
edge of the 16th SCLK cycle during
read operation for SDO transition
from tri-state to valid data
7
ns
t(ODZ)
Maximum delay from the SCS rising
edge for SDO transition from valid
data to tri-state
7
ns
t(OD)
Maximum delay from the falling
edge of the 16th SCLK cycle during
read operation to SDO valid
12
ns
(2)
(3)
tADC is an exact, unrounded, deterministic delay. The delay can be negative if the reference sample is sampled after the SYSREF high
capture point, in which case the total latency is smaller than the delay given by tTX.
The values given for tTX include deterministic and non-deterministic delays. The delay varies over process, temperature, and voltage.
JESD204B accounts for these variations when operating in subclass-1 mode in order to achieve deterministic latency. Proper receiver
RBD values must be chosen such that the elastic buffer release point does not occur within the invalid region of the local multiframe
clock (LMFC) cycle.
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S1
S2
S0
tAD
tADC
tCLK
CLK+
CLK±
SYSREF+
SYSREF±
tSU(SYSREF)
tH(SYSREF)
tTX
Start of Multi-Frame
DA0+/±(1)
(1)
S0
S1
S2
Only the SerDes lane DA0± is shown, but DA0± is representative of all lanes. The number of output lanes used and
bit-packing format is dependent on the programmed JMODE value.
Figure 1. ADC Timing Diagram
CLK+
CLK±
SYSREF+
SYSREF±
LMFC(1)
(Internal)
One multi-frame
One multi-frame
tSU(SYNCSE)
tH(SYNCSE)
SYNCSE
(SYNC_SEL = 0)
TMSTP+/±
(SYNC_SEL = 1)
tTX
Start of ILAS
DA0+/±(2)
/R
(2)
The internal LMFC is assumed to be aligned with the CLK± rising edge that captures the SYSREF± high value.
(3)
Only SerDes lane DA0± is shown, but DA0± is representative of all lanes. All lanes output /R at approximately the
same point in time. The number of lanes is dependent on the programmed JMODE value.
Figure 2. SYNCSE and TMSTP± Timing Diagram for NCO Synchronization
1st clock
16th clock
24th clock
SCLK
tSU(SCS)
tH(SCS)
t(PH)
t(PL)
tH(SCS)
tSU(SCS)
t(PH) + t(PL) = t(P) = 1 / ¦CLK(SCLK)
SCS
tSU(SDI)
tSU(SDI) tH(SDI)
SDI
D7
D0
Write Command
COMMAND FIELD
SDO
D1
tH(SDI)
t(OD)
Hi-Z
D7
t(OZD)
D1
D0
Read Command
Hi-Z
t(ODZ)
Figure 3. Serial Interface Timing
24
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6.11 Typical Characteristics
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B
= 0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock
frequency, filtered, 1-VPP sine-wave clock, JMODE = 17, and background calibration (unless otherwise noted); SNR results
exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and fixed-frequency
interleaving spurs
8
8
BG Calibration
FG Calibration
Effective Number of Bits (Bits)
Effective Number of Bits (Bits)
BG Calibration
FG Calibration
7.5
7
7.5
7
6.5
6.5
0
2000
4000
6000
fIN (MHz)
8000
0
10000
2000
D010
Figure 4. ENOB vs Input Frequency
10000
D002
Figure 5. ENOB vs Input Frequency
75
75
SNR
SINAD
SFDR
70
SNR
SINAD
SFDR
70
65
Magnitude (dBFS)
Magnitude (dBFS)
8000
JMODE5, fS = 6400 MSPS, FG and BG calibration
JMODE7, fS = 3200 MSPS, foreground (FG) and background (BG)
calibration
60
55
50
45
65
60
55
50
45
40
40
0
2000
4000
6000
fIN (MHz)
8000
10000
0
2000
D131
JMODE7, fS = 3200 MSPS, FG calibration
4000
6000
fIN (MHz)
8000
10000
D129
JMODE5, fS = 6400 MSPS, FG calibration
Figure 6. SNR, SINAD, SFDR vs Input Frequency
Figure 7. SNR, SINAD, SFDR vs Input Frequency
-45
-45
-50
-50
-55
Magnitude (dBFS)
-55
Magnitude (dBFS)
4000
6000
fIN (MHz)
-60
-65
-70
-75
-65
-70
-75
-80
HD2
HD3
THD
-80
-60
HD2
HD3
THD
-85
-85
-90
0
2000
4000
6000
fIN (MHz)
8000
10000
0
2000
D132
4000
6000
fIN (MHz)
8000
10000
JMODE7, fS = 3200 MSPS, FG calibration
JMODE5, fS = 6400 MSPS, FG calibration
Figure 8. HD2, HD3, THD vs Input Frequency
Figure 9. HD2, HD3, THD vs Input Frequency
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Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B
= 0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock
frequency, filtered, 1-VPP sine-wave clock, JMODE = 17, and background calibration (unless otherwise noted); SNR results
exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and fixed-frequency
interleaving spurs
75
75
SNR
SINAD
SFDR
SNR
SINAD
SFDR
70
65
Magnitude (dBFS)
Magnitude (dBFS)
70
60
55
50
65
60
55
50
45
45
40
40
0
2000
4000
6000
fIN (MHz)
8000
0
10000
2000
D009
JMODE7, fS = 3200 MSPS, BG calibration
-45
-50
-50
-55
-55
Magnitude (dBFS)
Magnitude (dBFS)
-45
-60
-65
-70
HD2
HD3
THD
D001
-60
-65
-70
HD2
HD3
THD
-75
-80
0
2000
4000
6000
fIN (MHz)
8000
10000
0
2000
D011
JMODE7, fS = 3200 MSPS, BG calibration
8000
10000
D003
Figure 13. HD2, HD3, THD vs Input Frequency
8.25
Effective Number of Bits (Bits)
8.25
8
7.75
7.5
7.25
800
4000
6000
fIN (MHz)
JMODE5, fS = 6400 MSPS, BG calibration
Figure 12. HD2, HD3, THD vs Input Frequency
Effective Number of Bits (Bits)
10000
Figure 11. SNR, SINAD, SFDR vs Input Frequency
-80
1200
1600
2000
fS (MSPS)
2400
2800
3200
8
7.75
7.5
7.25
1600
2400
D013
JMODE7, fIN = 347 MHz, BG calibration
3200
4000
fS (MSPS)
4800
5600
6400
D005
JMODE5, fIN = 347 MHz, BG calibration
Figure 14. ENOB vs Sampling Rate
26
8000
JMODE5, fS = 6400 MSPS, BG calibration
Figure 10. SNR, SINAD, SFDR vs Input Frequency
-75
4000
6000
fIN (MHz)
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Figure 15. ENOB vs Sampling Rate
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Typical Characteristics (continued)
75
75
70
70
65
65
Magnitude (dBFS)
Magnitude (dBFS)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B
= 0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock
frequency, filtered, 1-VPP sine-wave clock, JMODE = 17, and background calibration (unless otherwise noted); SNR results
exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and fixed-frequency
interleaving spurs
60
55
50
45
60
55
50
45
SNR
SINAD
SFDR
40
35
800
1200
1600
2000
fS (MSPS)
2400
2800
SNR
SINAD
SFDR
40
35
1600
3200
JMODE7, fIN = 347 MHz, BG calibration
4000
fS (MSPS)
4800
5600
6400
D004
Figure 17. SNR, SINAD, SFDR vs Sampling Rate
-55
-55
HD2
HD3
THD
-60
HD2
HD3
THD
-60
-65
Magnitude (dBFS)
Magnitude (dBFS)
3200
JMODE5, fIN = 347 MHz, BG calibration
Figure 16. SNR, SINAD, SFDR vs Sampling Rate
-70
-75
-80
-85
-65
-70
-75
-80
-85
-90
800
1200
1600
2000
fS (MSPS)
2400
2800
-90
1600
3200
2400
3200
D014
JMODE7, fIN = 347 MHz, BG calibration
4000
fS (MSPS)
4800
5600
6400
D006
JMODE5, fIN = 347 MHz, BG calibration
Figure 18. HD2, HD3, THD vs Sampling Rate
Figure 19. HD2, HD3, THD vs Sampling Rate
0
0
-30
-30
Magnitude (dBFS)
Magnitude (dBFS)
2400
D012
-60
-90
-120
-60
-90
-120
-150
-150
0
400
800
Frequency (MHz)
1200
1600
0
800
D139
JMODE7, fIN = 350 MHz, FG calibration, SNR = 49.1 dBFS,
SFDR = 70.1 dBFS, ENOB = 7.80 bits
Figure 20. Single-Tone FFT at AIN = –1 dBFS
1600
Frequency (MHz)
2400
3200
D134
JMODE5, fIN = 350 MHz, FG calibration, SNR = 49.0 dBFS,
SFDR = 64.0 dBFS, ENOB = 7.80 bits
Figure 21. Single-Tone FFT at AIN = –1 dBFS
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Typical Characteristics (continued)
0
0
-30
-30
Magnitude (dBFS)
Magnitude (dBFS)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B
= 0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock
frequency, filtered, 1-VPP sine-wave clock, JMODE = 17, and background calibration (unless otherwise noted); SNR results
exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and fixed-frequency
interleaving spurs
-60
-90
-120
-60
-90
-120
-150
-150
0
320
640
960
Frequency (MHz)
1280
1600
0
JMODE7, fIN = 2400 MHz, FG calibration, SNR = 48.8 dBFS,
SFDR = 63.7 dBFS, ENOB = 7.74 bits
-30
-30
Magnitude (dBFS)
Magnitude (dBFS)
0
-60
-90
2560
3200
D135
Figure 23. Single-Tone FFT at AIN = –1 dBFS
0
-60
-90
-120
-120
-150
-150
0
400
800
Frequency (MHz)
1200
0
1600
800
D141
JMODE7, fIN = 5000 MHz, FG calibration, SNR = 48.4 dBFS,
SFDR = 57.1 dBFS, ENOB = 7.52 bits
-30
-30
Magnitude (dBFS)
0
-90
-120
2400
3200
D136
Figure 25. Single-Tone FFT at AIN = –1 dBFS
0
-60
1600
Frequency (MHz)
JMODE5, fIN = 5000 MHz, FG calibration, SNR = 48.3 dBFS,
SFDR = 57.2 dBFS, ENOB = 7.48 bits
Figure 24. Single-Tone FFT at AIN = –1 dBFS
Magnitude (dBFS)
1280
1920
Frequency (MHz)
JMODE5, fIN = 2400 MHz, FG calibration, SNR = 48.8 dBFS,
SFDR = 52.4 dBFS, ENOB = 7.53 bits
Figure 22. Single-Tone FFT at AIN = –1 dBFS
-60
-90
-120
-150
-150
0
400
800
Frequency (MHz)
1200
1600
0
800
D145
JMODE7, fIN = 8200 MHz, FG calibration, SNR = 47.4 dBFS,
SFDR = 52.4 dBFS, ENOB = 7.19 bits
Figure 26. Single-Tone FFT at AIN = –1 dBFS
28
640
D140
1600
Frequency (MHz)
2400
3200
D144
JMODE5, fIN = 8200 MHz, FG calibration, SNR = 47.4 dBFS,
SFDR = 51.4 dBFS, ENOB = 7.10 bits
Figure 27. Single-Tone FFT at AIN = –1 dBFS
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Typical Characteristics (continued)
0
0
-30
-30
Magnitude (dBFS)
Magnitude (dBFS)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B
= 0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock
frequency, filtered, 1-VPP sine-wave clock, JMODE = 17, and background calibration (unless otherwise noted); SNR results
exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and fixed-frequency
interleaving spurs
-60
-90
-60
-90
-120
-120
-150
-150
0
400
800
Frequency (MHz)
1200
0
1600
JMODE7, fIN = 8200 MHz, FG calibration, SNR = 49.2 dBFS,
SFDR = 65.9 dBFS, ENOB = 7.80 bits
Figure 28. Single-Tone FFT at AIN = –16 dBFS
2400
3200
D137
Figure 29. Single-Tone FFT at AIN = –16 dBFS
0.5
Integral Non-Linearity (LSB)
0.2
0.1
0
-0.1
-0.2
0.25
0
-0.25
-0.5
-0.3
0
0
255
Code
255
Code
D048
JMODE5, fS = 6400 MSPS, FG calibration
Figure 30. DNL vs Code
Figure 31. INL vs Code
-55
SNR
SINAD
SFDR
-60
Magnitude (dBFS)
70
65
60
55
50
45
-75
D049
JMODE5, fS = 6400 MSPS, FG calibration
75
Magnitude (dBFS)
1600
Frequency (MHz)
JMODE5, fIN = 8200 MHz, FG calibration, SNR = 49.0 dBFS,
SFDR = 67.5 dBFS, ENOB = 7.79 bits
0.3
Differential Non-Linearity (LSB)
800
D142
-65
-70
-75
-80
HD2
HD3
THD
-85
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
-90
-75
-50
D039
JMODE5, fS = 6400 MSPS, fIN = 2400 MHz, BG calibration
Figure 32. SNR, SINAD, SFDR vs Temperature
-25
0
25
50
75
Ambient Temperature (°C)
100
125
D041
JMODE5, fS = 6400 MSPS, fIN = 2400 MHz, BG calibration
Figure 33. HD2, HD3, THD vs Temperature
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Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B
= 0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock
frequency, filtered, 1-VPP sine-wave clock, JMODE = 17, and background calibration (unless otherwise noted); SNR results
exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and fixed-frequency
interleaving spurs
8.5
8
FG Calibration at Each Temperature
FG Calibration at 25°C
Effective Number of Bits (Bits)
Effective Number of Bits (Bits)
BG Calibration
FG Calibration at Each Temperature
7.75
7.5
7.25
7
-75
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
8
7.5
7
6.5
-75
125
JMODE5, fIN = 2400 MHz, fS = 6400 MSPS
100
125
D121
Figure 35. ENOB vs Temperature and Calibration Type
FG Calibration at Each Temperature
FG Calibration at 25°C
51
Spurious-Free Dynamic Range (dBFS)
Signal-to-Noise Ratio (dBFS)
0
25
50
75
Ambient Temperature (°C)
70
52
50
49
48
47
46
-75
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
FG Calibration at Each Temperature
FG Calibration at 25°C
65
60
55
50
-75
125
-25
0
25
50
75
Ambient Temperature (°C)
100
125
D064
JMODE5, fIN = 600 MHz, fS = 6400 MSPS
Figure 36. SNR vs Temperature and Calibration Type
Figure 37. SFDR vs Temperature and Calibration Type
-45
-55
Third-Order Harmonic Distortion (dBFS)
FG Calibration at Each Temperature
FG Calibration at 25°C
-60
-65
-70
-75
-80
-85
-90
-75
-50
D063
JMODE5, fIN = 600 MHz, fS = 6400 MSPS
Second-Order Harmonic Distortion (dBFS)
-25
JMODE5, fIN = 600 MHz, fS = 6400 MSPS
Figure 34. ENOB vs Temperature and Calibration Type
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FG Calibration at Each Temperature
FG Calibration at 25°C
-50
-55
-60
-65
-70
-75
-80
-75
-50
D119
JMODE5, fIN = 600 MHz, fS = 6400 MSPS
Figure 38. HD2 vs Temperature and Calibration Type
30
-50
D040
-25
0
25
50
75
Ambient Temperature (°C)
100
125
D120
JMODE5, fIN = 600 MHz, fS = 6400 MSPS
Figure 39. HD3 vs Temperature and Calibration Type
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Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B
= 0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock
frequency, filtered, 1-VPP sine-wave clock, JMODE = 17, and background calibration (unless otherwise noted); SNR results
exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and fixed-frequency
interleaving spurs
8
56
Effective Number of Bits (Bits)
54
Magnitude (dBFS)
52
50
48
46
44
SNR
SINAD
SFDR
42
40
-5
-2.5
0
Supply Voltage (%)
2.5
7.75
7.5
7.25
7
-5
5
-2.5
D036
JMODE5, fS = 6400 MSPS, fIN = 2400 MHz, FG calibration
0
Supply Voltage (%)
2.5
5
D037
JMODE5, fS = 6400 MSPS, fIN = 2400 MHz, FG calibration
Figure 40. SNR, SINAD, SFDR vs Supply Voltage
Figure 41. ENOB vs Supply Voltage
1.2
-50
HD2
HD3
THD
-55
1
Supply Current (A)
Magnitude (dBFS)
-60
-65
-70
-75
0.8
0.6
0.4
-80
0
1600
-90
-5
-2.5
0
Supply Voltage (%)
2.5
5
2400
3200
D038
JMODE5, fS = 6400 MSPS, fIN = 2400 MHz, FG calibration
4000
fS (MSPS)
4800
5600
D007
Figure 43. Supply Current vs Sampling Rate
1.2
3
1
Supply Current (A)
3.2
2.8
2.6
2.4
2.2
0.8
0.6
0.4
IA19
IA11
ID11
0.2
2
1600
2400
3200
4000
fS (MSPS)
4800
5600
6400
JMODE5, fIN = 347 MHz, FG calibration
Figure 42. HD2, HD3, THD vs Supply Voltage
Power Consumption (W)
IA19
IA11
ID11
0.2
-85
6400
0
800
1200
D008
JMODE5, fIN = 347 MHz, FG calibration
Figure 44. Power Consumption vs Sampling Rate
1600
2000
fS (MSPS)
2400
2800
3200
D015
JMODE7, fIN = 347 MHz, FG calibration
Figure 45. Supply Current vs Sampling Rate
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Typical Characteristics (continued)
3.2
1.4
3
1.2
Supply Current (A)
Power Consumption (W)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B
= 0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock
frequency, filtered, 1-VPP sine-wave clock, JMODE = 17, and background calibration (unless otherwise noted); SNR results
exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and fixed-frequency
interleaving spurs
2.8
2.6
2.4
2.2
1
0.8
0.6
0.4
IA19
IA11
ID11
0.2
2
800
1200
1600
2000
fS (MSPS)
2400
2800
0
-75
3200
JMODE7, fIN = 347 MHz, FG calibration
4
3.75
0.9
3.5
0.8
Supply Current (A)
Power Consumption (W)
0
25
50
75
Ambient Temperature (°C)
100
125
D047
Figure 47. Supply Current vs Temperature
1
3.25
3
2.75
0.7
0.6
0.5
0.4
2.5
2.25
IA19
IA11
ID11
0.3
BG Calibration
FG Calibration
2
-75
0.2
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
-5
125
-2.5
D046
JMODE5, fS = 6400 MSPS, fIN = 2400 MHz, BG calibration
0
Supply Voltage (%)
2.5
5
D045
JMODE5, fS = 6400 MSPS, FG calibration
Figure 48. Power Consumption vs Temperature
Figure 49. Supply Current vs Supply Voltage
1.2
3.2
1.1
Supply Current (A)
3
2.8
1
0.9
2.6
0.8
2.4
-5
-2.5
0
Supply Voltage (%)
2.5
5
FG Calibration
BG Calibration
LPBG Calibration
0.7
800
1200
D044
JMODE5, fS = 6400 MSPS, FG calibration
Figure 50. Power Consumption vs Supply Voltage
32
-25
JMODE5, fS = 6400 MSPS, fIN = 2400 MHz, BG calibration
Figure 46. Power Consumption vs Sampling Rate
Power Consumption (W)
-50
D016
1600
2000
fCLK (MHz)
2400
2800
3200
D123
JMODE5, fIN = 607 MHz
Figure 51. IA19 Supply Current vs Clock Frequency
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Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B
= 0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock
frequency, filtered, 1-VPP sine-wave clock, JMODE = 17, and background calibration (unless otherwise noted); SNR results
exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and fixed-frequency
interleaving spurs
0.8
0.8
FG Calibration
BG Calibration
LPBG Calibration
0.6
Supply Current (A)
Supply Current (A)
0.6
0.4
0.2
0.4
0.2
FG Calibration
BG Calibration
LPBG Calibration
0
800
1200
1600
2000
fCLK (MHz)
2400
2800
0
800
3200
1200
JMODE5, fIN = 607 MHz
2000
fCLK (MHz)
2400
2800
3200
D117
JMODE5, fIN = 607 MHz
Figure 52. IA11 Supply Current vs Clock Frequency
Figure 53. ID11 Supply Current vs Clock Frequency
4
1.5
FG Calibration
BG Calibration
LPBG Calibration
IA19
IA11
ID11
1.25
3.5
Supply Current (A)
Power Consumption (W)
1600
D124
3
1
0.75
0.5
2.5
0.25
2
800
0
1200
1600
2000
fCLK (MHz)
2400
2800
3200
4
6
JMODE5, fIN = 607 MHz
Figure 54. Power Consumption vs Clock Frequency
14
16
18
D034
Figure 55. Supply Current vs JMODE
4
1.25
3.75
Power Consumption (W)
Supply Current (A)
10
12
JMODE
fIN = 2400 MHz, fCLK = 3200 MHz, FG calibration
1.5
1
0.75
0.5
IA19
IA11
ID11
0.25
8
D118
FG Calibration
BG Calibration
LPBG Calibration
3.5
3.25
3
2.75
2.5
0
4
6
8
10
12
JMODE
14
16
18
4
6
D122
fIN = 2400 MHz, fCLK = 3200 MHz, BG calibration
Figure 56. Supply Current vs JMODE
8
10
12
JMODE
14
16
18
D033
fIN = 2400 MHz, fCLK = 3200 MHz
Figure 57. Power Consumption vs JMODE
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Typical Characteristics (continued)
typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B
= 0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock
frequency, filtered, 1-VPP sine-wave clock, JMODE = 17, and background calibration (unless otherwise noted); SNR results
exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and fixed-frequency
interleaving spurs
256
140
130
Zoomed Area
in Following Plot
Sample Value
Sample Value
192
128
120
110
64
100
0
0
5000
10000
15000 20000 25000
Sample Number
30000
90
14800
35000
15600
Sample Number
16000
16400
D126
JMODE4, fCLK = 3200 MHz, fIN = 3199.9 MHz
Figure 58. Background Calibration Core Transition
(AC Signal)
Figure 59. Background Calibration Core Transition
(AC Signal Zoomed)
260
240
220
200
180
160
140
120
100
80
60
40
20
0
32
-0.35 V Differential
+0.35 V Differential
-0.35 V Differential
0 V Differential
24
Sample Value
Sample Value
JMODE4, fCLK = 3200 MHz, fIN = 3199.9 MHz
1000
2000
3000 4000 5000
Sample Number
16
8
Zoomed Area
in Following Plot
0
6000
7000
8000
0
1600
1700
D127
JMODE4, fCLK = 3200 MHz, DC input
Figure 60. Background Calibration Core Transition
(DC Signal)
34
15200
D125
1800
1900 2000 2100
Sample Number
2200
2300
2400
D128
JMODE4, fCLK = 3200 MHz, DC input
Figure 61. Background Calibration Core Transition
(DC Signal Zoomed)
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7 Detailed Description
7.1 Overview
The ADC08DJ3200 is an RF-sampling, giga-sample analog-to-digital converter (ADC) that can directly sample
input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC08DJ3200 can sample up to
3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dualchannel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets
the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input
bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and singlechannel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
Time interleaving is achieved internally through four active cores. In dual-channel mode, two cores are
interleaved per channel to increase the sample rate to twice the core sample rate. In single-channel mode, all
four cores are time interleaved to increase the sample rate to 4x the core sample rate. Either input can be used
in single-channel mode, however performance is optimized for INA±. The user provides a clock at twice the ADC
core sample rate and clock generation for the interleaved cores is done internally for both single-channel mode
and dual-channel mode. The ADC08DJ3200 also provides foreground and background calibration options to
match the gain and offset between cores to minimize spurious artifacts from interleaving.
The ADC08DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1
compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to
12.8 Gbps and can be configured to trade-off bit rate and number of lanes. At 5 Gsps, only four total lanes are
required running at 12.5 Gbps or 16 lanes can be used to reduce the lane rate to 3.125 Gbps. Innovative
synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify
system design for phased array radar and multiple-input-multiple-output (MIMO) communications.
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7.2 Functional Block Diagram
CALTRG
SCLK
SDI
SDO
SCS\
PD
SPI Registers and
Device Control
TMSTP+
DA0+
DA0-
TMSTPInput
MUX
INA+
JESD204B
Link A
ADC A
DA7+
DA7-
INA-
Overrange
SYNCSE\
DB0+
DB0-
INB+
INB-
Input
MUX
JESD204B
Link B
ADC B
DB7+
DB7-
Aperture
Delay Adjust
CLK+
Clock Distribution
and Synchronization
CLK-
SYSREF+
Status
Indicators
SYSREF
Windowing
SYSREF-
TDIODE+
ORA0
ORA1
ORB0
ORB1
CALSTAT
TDIODECopyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Device Comparison
The devices listed in Table 1 are part of a pin-to-pin compatible, high-speed, wide-bandwidth ADC family. The
family is offered to provide a scalable family of devices for varying levels of performance, speed, and signal
bandwidth.
Table 1. Device Family Comparison
PART NUMBER
SPEED GRADE
RESOLUTION
ADC12DJ3200
Single 6.4 GSPS or dual 3.2 GSPS
12-bit
ADC12DJ2700
Single 5.4 GSPS or dual 2.7 GSPS
12-bit
ADC08DJ3200
Single 6.4 GSPS or dual 3.2 GSPS
8-bit
7.3.2 Analog Inputs
The analog inputs of the ADC08DJ3200 have internal buffers to enable high input bandwidth and to isolate
sampling capacitor glitch noise from the input circuit. Analog inputs must be driven differentially because
operation with a single-ended signal results in degraded performance. Both AC-coupling and DC-coupling of the
analog inputs is supported. The analog inputs are designed for an input common-mode voltage (VCMI) of 0 V,
which is terminated internally through single-ended, 50-Ω resistors to ground (GND) on each input pin. DC36
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coupled input signals must have a common-mode voltage that meets the device input common-mode
requirements specified as VCMI in the Recommended Operating Conditions table. The 0-V input common-mode
voltage simplifies the interface to split-supply, fully-differential amplifiers and to a variety of transformers and
baluns. The ADC08DJ3200 includes internal analog input protection to protect the ADC inputs during overranged
input conditions; see the Analog Input Protection section. Figure 62 provides a simplified analog input model.
AGND
Analog input
protection
diodes.
50
INA+, INB+
ADC
INA-, INBInput Buffer
50
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Figure 62. ADC08DJ3200 Analog Input Internal Termination and Protection Diagram
There is minimal degradation in analog input bandwidth when using single-channel mode versus dual-channel
mode. In single-channel mode, INA± is strongly recommended to be used as the input to the ADC because ADC
performance is optimized for INA±. However, either analog input (INA+ and INA– or INB+ and INB–) can be
used. Using INB± results in degraded performance unless custom trim routines are used to optimize performance
for INB± in each device. The desired input can be chosen using SINGLE_INPUT in the input mux control
register.
NOTE
INA± is strongly recommended to be used as the input to the ADC in single-channel mode
for optimized performance.
7.3.2.1 Analog Input Protection
The analog inputs are protected against overdrive conditions by internal clamping diodes that are capable of
sourcing or sinking input currents during overrange conditions, see the voltage and current limits in the Absolute
Maximum Ratings table. The overrange protection is also defined for a peak RF input power in the Absolute
Maximum Ratings table, which is frequency independent. Operation above the maximum conditions listed in the
Recommended Operating Conditions table results in an increase in failure-in-time (FIT) rate, so the system must
correct the overdrive condition as quickly as possible. Figure 62 shows the analog input protection diodes.
7.3.2.2 Full-Scale Voltage (VFS) Adjustment
Input full-scale voltage (VFS) adjustment is available, in fine increments, for each analog input through the
FS_RANGE_A register setting (see the INA full-scale range adjust register) and FS_RANGE_B register setting
(see the INB full-scale range adjust register) for INA± and INB±, respectively. The available adjustment range is
specified in the Electrical Characteristics: DC Specifications table. Larger full-scale voltages improve SNR and
noise floor (in dBFS/Hz) performance, but can degrade harmonic distortion. The full-scale voltage adjustment is
useful for matching the full-scale range of multiple ADCs when developing a multi-converter system or for
external interleaving of multiple ADC08DJ3200s to achieve higher sampling rates.
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7.3.2.3 Analog Input Offset Adjust
The input offset voltage for each input can be adjusted through the OADJ_x_INy registers (registers 0x08A and
0x095), where x represents the ADC core (A, B, or C) and y represents the analog input (INA± or INB±). The
adjustment range is approximately 28 mV to –28 mV differential. See the Calibration Modes and Trimming
section for more information.
7.3.3 ADC Core
The ADC08DJ3200 consists of a total of six ADC cores. The cores are interleaved for higher sampling rates and
swapped on-the-fly for calibration as required by the operating mode. This section highlights the theory and key
features of the ADC cores.
7.3.3.1 ADC Theory of Operation
The differential voltages at the analog inputs are captured by the rising edge of CLK± in dual-channel mode or by
the rising and falling edges of CLK± in single-channel mode. After capturing the input signal, the ADC converts
the analog voltage to a digital value by comparing the voltage to the internal reference voltage. If the voltage on
INA– or INB– is higher than the voltage on INA+ or INB+, respectively, then the digital output is a negative 2's
complement value. If the voltage on INA+ or INB+ is higher than the voltage on INA– or INB–, respectively, then
the digital output is a positive 2's complement value. Equation 1 can calculate the differential voltage at the input
pins from the digital output.
Code
VIN
V FS
2N
where
•
•
•
Code is the signed decimation output code (for example, –2048 to +2047)
N is the ADC resolution
and VFS is the full-scale input voltage of the ADC as specified in the Recommended Operating Conditions
table, including any adjustment performed by programming FS_RANGE_A or FS_RANGE_B
(1)
7.3.3.2 ADC Core Calibration
ADC core calibration is required to optimize the analog performance of the ADC cores. Calibration must be
repeated when operating conditions change significantly, namely temperature, in order to maintain optimal
performance. The ADC08DJ3200 has a built-in calibration routine that can be run as a foreground operation or a
background operation. Foreground operation requires ADC downtime, where the ADC is no longer sampling the
input signal, to complete the process. Background calibration can be used to overcome this limitation and allow
constant operation of the ADC. See the Calibration Modes and Trimming section for detailed information on each
mode.
7.3.3.3 ADC Overrange Detection
To ensure that system gain management has the quickest possible response time, a low-latency configurable
overrange function is included. The overrange function works by monitoring the converted 8-bit samples at the
ADC to quickly detect if the ADC is near saturation or already in an overrange condition. The absolute value of
the 8 bits of the ADC data are checked against two programmable thresholds, OVR_T0 and OVR_T1. These
thresholds apply to both channel A and channel B in dual-channel mode. Table 2 lists how an ADC sample is
converted to an absolute value for a comparison of the thresholds.
Table 2. Conversion of ADC Sample for Overrange Comparison
ADC SAMPLE
(Offset Binary)
ADC SAMPLE
(2's Complement)
ABSOLUTE VALUE
8 BITS USED FOR COMPARISON
1111 1111 (255)
0111 1111 (+127)
111 1111 (127)
1111 1111 (255)
1000 0000 (128)
0000 0000 (0)
000 0000 (0)
0000 0000 (0)
0000 0001 (1)
1000 0001 (–127)
111 1111 (127)
1111 1110 (254)
0000 0000 (0)
1000 0000 (–128)
111 1111 (127)
1111 1111 (255)
38
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If the 8 bits of the absolute value equal or exceed the OVR_T0 or OVR_T1 thresholds during the monitoring
period, then the overrange bit associated with the threshold is set to 1, otherwise the overrange bit is 0. In dualchannel mode, the overrange status can be monitored on the ORA0 and ORA1 pins for channel A and the ORB0
and ORB1 pins for channel B, where ORx0 corresponds to the OVR_T0 threshold and ORx1 corresponds to the
OVR_T1 threshold. In single-channel mode, the overrange status for the OVR_T0 threshold is determined by
monitoring both the ORA0 and ORB0 outputs and the OVR_T1 threshold is determined by monitoring both ORA1
and ORB1 outputs. In single-channel mode, the two outputs for each threshold must be OR'd together to
determine whether an overrange condition occurred. OVR_N can be used to set the output pulse duration from
the last overrange event. Table 3 lists the overrange pulse lengths for the various OVR_N settings (see the
overrange configuration register).
Table 3. Overrange Monitoring Period for the ORA0, ORA1, ORB0, and ORB1 Outputs
OVR_N
OVERRANGE PULSE LENGTH SINCE LAST OVERRANGE
EVENT (DEVCLK Cycles)
0
8
1
16
2
32
3
64
4
128
5
256
6
512
7
1024
Typically, the OVR_T0 threshold can be set near the full-scale value (228 for example). When the threshold is
triggered, a typical system can turn down the system gain to avoid clipping. The OVR_T1 threshold can be set
much lower. For example, the OVR_T1 threshold can be set to 64 (peak input voltage of −12 dBFS). If the input
signal is strong, the OVR_T1 threshold is tripped occasionally. If the input is quite weak, the threshold is never
tripped. The downstream logic device monitors the OVR_T1 bit. If OVR_T1 stays low for an extended period of
time, then the system gain can be increased until the threshold is occasionally tripped (meaning the peak level of
the signal is above −12 dBFS).
7.3.3.4 Code Error Rate (CER)
ADC cores can generate bit errors within a sample, often called code errors (CER) or referred to as sparkle
codes, resulting from metastability caused by non-ideal comparator limitations. The ADC08DJ3200 uses a
unique ADC architecture that inherently allows significant code error rate improvements from traditional pipelined
flash or successive approximation register (SAR) ADCs. The code error rate of the ADC08DJ3200 is multiple
orders of magnitude better than what can be achieved in alternative architectures at equivalent sampling rates
providing significant signal reliability improvements.
7.3.4 Timestamp
The TMSTP+ and TMSTP– differential input can be used as a time-stamp input to mark a specific sample based
on the timing of an external trigger event relative to the sampled signal. TIMESTAMP_EN (see the LSB control
bit output register) must be set in order to use the timestamp feature and output the timestamp data. When
enabled, the LSB of the 8-bit ADC digital output reports the status of the TMSTP± input. In effect, the 8-bit output
sample consists of the upper 7-bits of the 8-bit converter and the LSB of the 8-bit output sample is the output of a
parallel 1-bit converter (TMSTP±) with the same latency as the ADC core. The trigger must be applied to the
differential TMSTP+ and TMSTP– inputs. The trigger can be asynchronous to the ADC sampling clock and is
sampled at approximately the same time as the analog input. Timestamp cannot be used when a JMODE with
decimation is selected and instead SYSREF must be used to achieve synchronization through the JESD204B
subclass-1 method for achieving deterministic latency.
7.3.5 Clocking
The clocking subsystem of the ADC08DJ3200 has two input signals, device clock (CLK+, CLK–) and SYSREF
(SYSREF+, SYSREF–). Within the clocking subsystem there is a noiseless aperture delay adjustment (tAD
adjust), a clock duty cycle corrector, and a SYSREF capture block. Figure 63 describes the clocking subsystem.
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Duty Cycle
Correction
tAD Adjust
Clock Distribution
and Synchronization
(ADC cores, digital,
JESD204B, etc.)
CLK+
E
TA
D
_F
IN
O
AR
_C
TA
D
TA
D
_I
N
V
SE
CLK-
SYSREF Capture
SYSREF+
SYSREF Windowing
SYSREF-
SYSREF_POS
SYSREF_SEL
Automatic
SYSREF
Calibration
SRC_EN
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Figure 63. ADC08DJ3200 Clocking Subsystem
The device clock is used as the sampling clock for the ADC core as well as the clocking for the digital processing
and serializer outputs. Use a low-noise (low jitter) device clock to maintain high signal-to-noise ratio (SNR) within
the ADC. In dual-channel mode, the analog input signal for each input is sampled on the rising edge of the
device clock. In single-channel mode, both the rising and falling edges of the device clock are used to capture
the analog signal to reduce the maximum clock rate required by the ADC. A noiseless aperture delay adjustment
(tAD adjust) allows the user to shift the sampling instance of the ADC in fine steps in order to synchronize multiple
ADC08DJ3200s or to fine-tune system latency. Duty cycle correction is implemented in the ADC08DJ3200 to
ease the requirements on the external device clock while maintaining high performance. Table 4 summarizes the
device clock interface in dual-channel mode and single-channel mode.
Table 4. Device Clock vs Mode of Operation
MODE OF OPERATION
SAMPLING RATE VS fCLK
Dual-channel mode
1 × fCLK
SAMPLING INSTANT
Rising edge
Single-channel mode
2 × fCLK
Rising and falling edge
SYSREF is a system timing reference used for JESD204B subclass-1 implementations of deterministic latency.
SYSREF is used to achieve deterministic latency and for multi-device synchronization. SYSREF must be
captured by the correct device clock edge in order to achieve repeatable latency and synchronization. The
ADC08DJ3200 includes SYSREF windowing and automatic SYSREF calibration to ease the requirements on the
external clocking circuits and to simplify the synchronization process. SYSREF can be implemented as a single
pulse or as a periodic clock. In periodic implementations, SYSREF must be equal to, or an integer division of, the
local multiframe clock frequency. Equation 2 is used to calculate valid SYSREF frequencies.
f SYSREF
R u f CLK
10 u F u K u n
where
•
•
•
•
40
R and F are set by the JMODE setting (see Table 10)
fCLK is the device clock frequency (CLK±)
K is the programmed multiframe length (see Table 10 for valid K settings)
and n is any positive integer
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7.3.5.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
The ADC08DJ3200 contains a delay adjustment on the device clock (sampling clock) input path, called tAD
adjust, that can be used to shift the sampling instance within the device in order to align sampling instances
among multiple devices or for external interleaving of multiple ADC08DJ3200s. Further, tAD adjust can be used
for automatic SYSREF calibration to simplify synchronization; see the Automatic SYSREF Calibration section.
Aperture delay adjustment is implemented in a way that adds no additional noise to the clock path, however a
slight degradation in aperture jitter (tAJ) is possible at large values of TAD_COARSE because of internal clock
path attenuation. The degradation in aperture jitter can result in minor SNR degradations at high input
frequencies (see tAJ in the Switching Characteristics table). This feature is programmed using TAD_INV,
TAD_COARSE, and TAD_FINE in the DEVCLK timing adjust ramp control register. Setting TAD_INV inverts the
input clock resulting in a delay equal to half the clock period. Table 5 summarizes the step sizes and ranges of
the TAD_COARSE and TAD_FINE variable analog delays. All three delay options are independent and can be
used in conjunction. All clocks within the device are shifted by the programmed tAD adjust amount, which results
in a shift of the timing of the JESD204B serialized outputs and affects the capture of SYSREF.
Table 5. tAD Adjust Adjustment Ranges
ADJUSTMENT PARAMETER
ADJUSTMENT STEP
DELAY SETTINGS
TAD_INV
1 / (fCLK × 2)
1
MAXIMUM DELAY
1 / (fCLK × 2)
TAD_COARSE
See tTAD(STEP) in the Switching
Characteristics table
256
See tTAD(MAX) in the Switching
Characteristics table
TAD_FINE
See tTAD(STEP) in the Switching
Characteristics table
256
See tTAD(MAX) in the Switching
Characteristics table
In order to maintain timing alignment between converters, stable and matched power-supply voltages and device
temperatures must be provided.
Aperture delay adjustment can be changed on-the-fly during normal operation but may result in brief upsets to
the JESD204B data link. Use TAD_RAMP to reduce the probability of the JESD204B link losing synchronization;
see the Aperture Delay Ramp Control (TAD_RAMP) section.
7.3.5.2 Aperture Delay Ramp Control (TAD_RAMP)
The ADC08DJ3200 contains a function to gradually adjust the tAD adjust setting towards the newly written
TAD_COARSE value. This functionality allows the tAD adjust setting to be adjusted with minimal internal clock
circuitry glitches. The TAD_RAMP_RATE parameter allows either a slower (one TAD_COARSE LSB per 256
tCLK cycles) or faster ramp (four TAD_COARSE LSBs per 256 tCLK cycles) to be selected. The TAD_RAMP_EN
parameter enables the ramp feature and any subsequent writes to TAD_COARSE initiate a new cramp.
7.3.5.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
The clocking subsystem is largely responsible for achieving multi-device synchronization and deterministic
latency. The ADC08DJ3200 uses the JESD204B subclass-1 method to achieve deterministic latency and
synchronization. Subclass 1 requires that the SYSREF signal be captured by a deterministic device clock (CLK±)
edge at each system power-on and at each device in the system. This requirement imposes setup and hold
constraints on SYSREF relative to CLK±, which can be difficult to meet at giga-sample clock rates over all
system operating conditions. The ADC08DJ3200 includes a number of features to simplify this synchronization
process and to relax system timing constraints:
• The ADC08DJ3200 uses dual-edge sampling (DES) in single-channel mode to reduce the CLK± input
frequency by half and double the timing window for SYSREF (see Table 4)
• A SYSREF position detector (relative to CLK±) and selectable SYSREF sampling position aid the user in
meeting setup and hold times over all conditions; see the SYSREF Position Detector and Sampling Position
Selection (SYSREF Windowing) section
• Easy-to-use automatic SYSREF calibration uses the aperture timing adjust block (tAD adjust) to shift the ADC
sampling instance based on the phase of SYSREF (rather than adjusting SYSREF based on the phase of the
ADC sampling instance); see the Automatic SYSREF Calibration section
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7.3.5.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
The SYSREF windowing block is used to first detect the position of SYSREF relative to the CLK± rising edge and
then to select a desired SYSREF sampling instance, which is a delay version of CLK±, to maximize setup and
hold timing margins. In many cases a single SYSREF sampling position (SYSREF_SEL) is sufficient to meet
timing for all systems (device-to-device variation) and conditions (temperature and voltage variations). However,
this feature can also be used by the system to expand the timing window by tracking the movement of SYSREF
as operating conditions change or to remove system-to-system variation at production test by finding a unique
optimal value at nominal conditions for each system.
This section describes proper usage of the SYSREF windowing block. First, apply the device clock and SYSREF
to the device. The location of SYSREF relative to the device clock cycle is determined and stored in the
SYSREF_POS bits of the SYSREF capture position register. Each bit of SYSREF_POS represents a potential
SYSREF sampling position. If a bit in SYSREF_POS is set to 1, then the corresponding SYSREF sampling
position has a potential setup or hold violation. Upon determining the valid SYSREF sampling positions (the
positions of SYSREF_POS that are set to 0) the desired sampling position can be chosen by setting
SYSREF_SEL in the clock control register 0 to the value corresponding to that SYSREF_POS position. In
general, the middle sampling position between two setup and hold instances is chosen. Ideally, SYSREF_POS
and SYSREF_SEL are performed at the nominal operating conditions of the system (temperature and supply
voltage) to provide maximum margin for operating condition variations. This process can be performed at final
test and the optimal SYSREF_SEL setting can be stored for use at every system power up. Further,
SYSREF_POS can be used to characterize the skew between CLK± and SYSREF± over operating conditions for
a system by sweeping the system temperature and supply voltages. For systems that have large variations in
CLK± to SYSREF± skew, this characterization can be used to track the optimal SYSREF sampling position as
system operating conditions change. In general, a single value can be found that meets timing over all conditions
for well-matched systems, such as those where CLK± and SYSREF± come from a single clocking device.
NOTE
SYSREF_SEL must be set to 0 when using automatic SYSREF calibration; see the
Automatic SYSREF Calibration section.
The step size between each SYSREF_POS sampling position can be adjusted using SYSREF_ZOOM. When
SYSREF_ZOOM is set to 0, the delay steps are coarser. When SYSREF_ZOOM is set to 1, the delay steps are
finer. See the Switching Characteristics table for delay step sizes when SYSREF_ZOOM is enabled and
disabled. In general, SYSREF_ZOOM is recommended to always be used (SYSREF_ZOOM = 1) unless a
transition region (defined by 1's in SYSREF_POS) is not observed, which can be the case for low clock rates.
Bits 0 and 23 of SYSREF_POS are always be set to 1 because there is insufficient information to determine if
these settings are close to a timing violation, although the actual valid window can extend beyond these sampling
positions. The value programmed into SYSREF_SEL is the decimal number representing the desired bit location
in SYSREF_POS. Table 6 lists some example SYSREF_POS readings and the optimal SYSREF_SEL settings.
Although 24 sampling positions are provided by the SYSREF_POS status register, SYSREF_SEL only allows
selection of the first 16 sampling positions, corresponding to SYSREF_POS bits 0 to 15. The additional
SYSREF_POS status bits are intended only to provide additional knowledge of the SYSREF valid window. In
general, lower values of SYSREF_SEL are selected because of delay variation over supply voltage, however in
the fourth example a value of 15 provides additional margin and can be selected instead.
Table 6. Examples of SYSREF_POS Readings and SYSREF_SEL Selections
SYSREF_POS[23:0]
(1)
42
OPTIMAL SYSREF_SEL
SETTING
0x02E[7:0]
(Largest Delay)
0x02D[7:0] (1)
0x02C[7:0] (1)
(Smallest Delay)
b10000000
b01100000
b00011001
b10011000
b00000000
b00110001
12
b10000000
b01100000
b00000001
6 or 7
b10000000
b00000011
b00000001
4 or 15
b10001100
b01100011
b00011001
6
8 or 9
Red coloration indicates the bits that are selected, as given in the last column of this table.
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7.3.5.3.2 Automatic SYSREF Calibration
The ADC08DJ3200 has an automatic SYSREF calibration feature to alleviate the often challenging setup and
hold times associated with capturing SYSREF for giga-sample data converters. Automatic SYSREF calibration
uses the tAD adjust feature to shift the device clock to maximize the SYSREF setup and hold times or to align the
sampling instance based on the SYSREF rising edge.
The ADC08DJ3200 must have a proper device clock applied and be programmed for normal operation before
starting the automatic SYSREF calibration. When ready to initiate automatic SYSREF calibration, a continuous
SYSREF signal must be applied. SYSREF must be a continuous (periodic) signal when using the automatic
SYSREF calibration. Start the calibration process by setting SRC_EN high in the SYSREF calibration enable
register after configuring the automatic SYSREF calibration using the SRC_CFG register. Upon setting SRC_EN
high, the ADC08DJ3200 searches for the optimal tAD adjust setting until the device clock falling edge is internally
aligned to the SYSREF rising edge. TAD_DONE in the SYSREF calibration status register can be monitored to
ensure that the SYSREF calibration has finished. By aligning the device clock falling edge with the SYSREF
rising edge, automatic SYSREF calibration maximizes the internal SYSREF setup and hold times relative to the
device clock and also sets the sampling instant based on the SYSREF rising edge. After the automatic SYSREF
calibration finishes, the rest of the startup procedure can be performed to finish bringing up the system.
For multi-device synchronization, the SYSREF rising edge timing must be matched at all devices and therefore
trace lengths must be matched from a common SYSREF source to each ADC08DJ3200. Any skew between the
SYSREF rising edge at each device results in additional error in the sampling instance between devices,
however repeatable deterministic latency from system startup to startup through each device must still be
achieved. No other design requirements are needed in order to achieve multi-device synchronization as long as
a proper elastic buffer release point is chosen in the JESD2048 receiver.
Figure 64 provides a timing diagram of the SYSREF calibration procedure. The optimized setup and hold times
are shown as tSU(OPT) and tH(OPT), respectively. Device clock and SYSREF are referred to as internal in this
diagram because the phase of the internal signals are aligned within the device and not to the external (applied)
phase of the device clock or SYSREF.
Sampled Input Signal
Internal Unadjusted
Device Clock
Internal Calibrated
Device Clock
tTAD(SRC)
Internal SYSREF
tCAL(SRC)
SRC_EN
(SPI register bit)
tH(OPT)
tSU(OPT)
Before calibration, device clock falling edge does
not align with SYSREF rising edge
Calibration
enabled
TAD_DONE
(SPI register bit)
After calibration, device clock falling edge
aligns with SYSREF rising edge
Calibration
finished
Figure 64. SYSREF Calibration Timing Diagram
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When finished, the tAD adjust setting found by the automatic SYSREF calibration can be read from SRC_TAD in
the SYSREF calibration status register. After calibration, the system continues to use the calibrated tAD adjust
setting for operation until the system is powered down. However, if desired, the user can then disable the
SYSREF calibration and fine-tune the tAD adjust setting according to the systems needs. Alternatively, the use of
the automatic SYSREF calibration can be done at product test (or periodic recalibration) of the optimal tAD adjust
setting for each system. This value can be stored and written to the TAD register (TAD_INV, TAD_COARSE, and
TAD_FINE) upon system startup.
Do not run the SYSREF calibration when the ADC calibration (foreground or background) is running. If
background calibration is the desired use case, disable the background calibration when the SYSREF calibration
is used, then reenable the background calibration after TAD_DONE goes high. SYSREF_SEL in the clock control
register 0 must be set to 0 when using SYSREF calibration.
SYSREF calibration searches the TAD_COARSE delays using both noninverted (TAD_INV = 0) and inverted
clock polarity (TAD_INV = 1) to minimize the required TAD_COARSE setting in order to minimize loss on the
clock path to reduce aperture jitter (tAJ).
7.3.6 JESD204B Interface
The ADC08DJ3200 uses the JESD204B high-speed serial interface for data converters to transfer data from the
ADC to the receiving logic device. The ADC08DJ3200 serialized lanes are capable of operating up to 12.8 Gbps,
slightly above the JESD204B maximum lane rate. A maximum of 16 lanes can be used to allow lower lane rates
for interfacing with speed-limited logic devices. Figure 65 shows a simplified block diagram of the JESD204B
interface protocol.
ADC
JESD204B Block
ADC
JESD204B
TRANSPORT
LAYER
SCRAMBLER
(Optional)
JESD204B
LINK LAYER
8b/10b
ENCODER
JESD204B
TX
ANALOG
CHANNEL
Logic Device
JESD204B Block
APPLICATION
LAYER
JESD204B
TRANSPORT
LAYER
DESCRAMBLE
(Optional)
JESD204B
LINK LAYER
8b/10b
DECODER
JESD204B
RX
Copyright © 2017, Texas Instruments Incorporated
Figure 65. Simplified JESD204B Interface Diagram
The various signals used in the JESD204B interface and the associated ADC08DJ3200 pin names are
summarized briefly in Table 7 for reference.
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Table 7. Summary of JESD204B Signals
SIGNAL NAME
Data
SYNC
Device clock
SYSREF
ADC08DJ3200 PIN NAMES
DESCRIPTION
DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)
High-speed serialized data after 8b,
10b encoding
SYNCSE, TMSTP+, TMSTP–
Link initialization signal (handshake),
toggles low to start code group
synchronization (CGS) process
CLK+, CLK–
ADC sampling clock, also used for
clocking digital logic and output
serializers
SYSREF+, SYSREF–
System timing reference used to
deterministically reset the internal local
multiframe counters in each
JESD204B device
7.3.6.1 Transport Layer
The transport layer takes samples from the ADC output and maps the samples into octets, frames, multiframes,
and lanes. Sample mapping is defined by the JESD204B mode that is used, defined by parameters such as L,
M, F, S, N, N', CF, and so forth. There are a number of predefined transport layer modes in the ADC08DJ3200
that are defined in Table 10. The high level configuration parameters for the transport layer in the ADC08DJ3200
are described in Table 8. For simplicity, the transport layer mode is chosen by simply setting the JMODE
parameter and the desired K value. For reference, the various configuration parameters for JESD204B are
defined in Table 9.
7.3.6.2 Scrambler
An optional data scrambler can be used to scramble the octets before transmission across the channel.
Scrambling is recommended in order to remove the possibility of spectral peaks in the transmitted data. The
JESD204B receiver automatically synchronizes its descrambler to the incoming scrambled data stream. The
initial lane alignment sequence (ILA) is never scrambled. Scrambling can be enabled by setting SCR (in the
JESD204B control register).
7.3.6.3 Link Layer
The link layer serves multiple purposes in JESD204B, including establishing the code boundaries (see the Code
Group Synchronization (CGS) section), initializing the link (see the Initial Lane Alignment Sequence (ILAS)
section), encoding the data (see the 8b, 10b Encoding section), and monitoring the health of the link (see the
Frame and Multiframe Monitoring section).
7.3.6.3.1 Code Group Synchronization (CGS)
The first step in initializing the JESD204B link, after SYSREF is processed, is to achieve code group
synchronization. The receiver first asserts the SYNC signal when ready to initialize the link. The transmitter
responds to the request by sending a stream of K28.5 characters. The receiver then aligns its character clock to
the K28.5 character sequence. Code group synchronization is achieved after receiving four K28.5 characters
successfully. The receiver deasserts SYNC on the next local multiframe clock (LMFC) edge after CGS is
achieved and waits for the transmitter to start the initial lane alignment sequence.
7.3.6.3.2 Initial Lane Alignment Sequence (ILAS)
After the transmitter detects the SYNC signal deassert, the transmitter waits until its next LMFC edge to start
sending the initial lane alignment sequence. The ILAS consists of four multiframes each containing a
predetermined sequence. The receiver searches for the start of the ILAS to determine the frame and multiframe
boundaries. As the ILAS reaches the receiver for each lane, the lane starts to buffer its data until all receivers
have received the ILAS and subsequently release the ILAS from all lanes at the same time in order to align the
lanes. The second multiframe of the ILAS contains configuration parameters for the JESD204B that can be used
by the receiver to verify that the transmitter and receiver configurations match.
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7.3.6.3.3 8b, 10b Encoding
The data link layer converts the 8-bit octets from the transport layer into 10-bit characters for transmission across
the link using 8b, 10b encoding. 8b, 10b encoding provides DC balance for AC-coupling of the SerDes links and
a sufficient number of edge transitions for the receiver to reliably recover the data clock. 8b, 10b also provides
some amount of error detection where a single bit error in a character likely results in either not being able to find
the 10-bit character in the 8b, 10b decoder lookup table or incorrect character disparity.
7.3.6.3.4 Frame and Multiframe Monitoring
The ADC08DJ3200 supports frame and multiframe monitoring for verifying the health of the JESD204B link. If
the last octet of a frame matches the last octet of the previous frame, then the last octet in the second frame is
replaced with an /F/ (/K28.7/) character. If the second frame is the last frame of a multiframe, then an /A/
(/K28.3/) character is used instead. When scrambling is enabled, if the last octet of a frame is 0xFC then the
transmitter replaces the octet with an /F/ (/K28.7/) character. With scrambling, if the last octet of a multiframe is
0x7C then the transmitter replaces the octet with an /A/ (/K28.3/) character. When the receiver detects an /F/ or
/A/ character, the receiver checks if the character occurs at the end of a frame or multiframe, and replaces that
octet with the appropriate data character. The receiver can report an error if the alignment characters occur in
the incorrect place and trigger a link realignment.
7.3.6.4 Physical Layer
The JESD204B physical layer consists of a current mode logic (CML) output driver and receiver. The receiver
consists of a clock detection and recovery (CDR) unit to extract the data clock from the serialized data stream
and can contain an equalizer to correct for the low-pass response of the physical transmission channel. Likewise,
the transmitter can contain pre-equalization to account for frequency dependent losses across the channel. The
total reach of the SerDes links depends on the data rate, board material, connectors, equalization, noise and
jitter, and required bit-error performance. The SerDes lanes do not have to be matched in length because the
receiver aligns the lanes during the initial lane alignment sequence.
7.3.6.4.1 SerDes Pre-Emphasis
The ADC08DJ3200 high-speed output drivers can pre-equalize the transmitted data stream by using preemphasis in order to compensate for the low-pass response of the transmission channel. Configurable preemphasis settings allow the output drive waveform to be optimized for different PCB materials and signal
transmission distances. The pre-emphasis setting is adjusted through the serializer pre-emphasis setting
SER_PE (in the serializer pre-emphasis control register). Higher values increase the pre-emphasis to
compensate for more lossy PCB materials. This adjustment is best used in conjunction with an eye-diagram
analysis capability in the receiver. Adjust the pre-emphasis setting to optimize the eye-opening for the specific
hardware configuration and line rates needed.
7.3.6.5 JESD204B Enable
The JESD204B interface must be disabled through JESD_EN (in the JESD204B enable register) while any of the
other JESD204B parameters are being changed. When JESD_EN is set to 0 the block is held in reset and the
serializers are powered down. The clocks for this section are also gated off to further save power. When the
parameters are set as desired, the JESD204B block can be enabled (JESD_EN is set to 1).
7.3.6.6 Multi-Device Synchronization and Deterministic Latency
JESD204B subclass 1 outlines a method to achieve deterministic latency across the serial link. If two devices
achieve the same deterministic latency then they can be considered synchronized. This latency must be
achieved from system startup to startup to be deterministic. There are two key requirements to achieve
deterministic latency. The first is proper capture of SYSREF for which the ADC08DJ3200 provides a number of
features to simplify this requirement at giga-sample clock rates (see the SYSREF Capture for Multi-Device
Synchronization and Deterministic Latency section for more information).
The second requirement is to choose a proper elastic buffer release point in the receiver. Because the
ADC08DJ3200 is an ADC, the ADC08DJ3200 is the transmitter (TX) in the JESD204B link and the logic device
is the receiver (RX). The elastic buffer is the key block for achieving deterministic latency, and does so by
absorbing variations in the propagation delays of the serialized data as the data travels from the transmitter to
the receiver. A proper release point is one that provides sufficient margin against delay variations. An incorrect
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release point results in a latency variation of one LMFC period. Choosing a proper release point requires
knowing the average arrival time of data at the elastic buffer, referenced to an LMFC edge, and the total
expected delay variation for all devices. With this information the region of invalid release points within the LMFC
period can be defined, which stretches from the minimum to maximum delay for all lanes. Essentially, the
designer must ensure that the data for all lanes arrives at all devices before the release point occurs.
Figure 66 provides a timing diagram that demonstrates this requirement. In this figure, the data for two ADCs is
shown. The second ADC has a longer routing distance (tPCB) and results in a longer link delay. First, the invalid
region of the LMFC period is marked off as determined by the data arrival times for all devices. Then, the release
point is set by using the release buffer delay (RBD) parameter to shift the release point an appropriate number of
frame clocks from the LMFC edge so that the release point occurs within the valid region of the LMFC cycle. In
the case of Figure 66, the LMFC edge (RBD = 0) is a good choice for the release point because there is
sufficient margin on each side of the valid region.
Nominal Link Delay
(Arrival at Elastic Buffer)
ADC 1 Data
Propagation
tTX
ADC 2 Data
Propagation
tTX
tPCB
Link Delay
Variation
tRX-DESER
tPCB
tRX-DESER
Release point
margin
Choose LMFC
edge as release
point (RBD = 0)
TX LMFC
RX LMFC
Time
Invalid Region
of LMFC
Valid Region
of LMFC
Figure 66. LMFC Valid Region Definition for Elastic Buffer Release Point Selection
The TX and RX LMFCs do not necessarily need to be phase aligned, but knowledge of their phase is important
for proper elastic buffer release point selection. Also, the elastic buffer release point occurs within every LMFC
cycle, but the buffers only release when all lanes have arrived. Therefore, the total link delay can exceed a single
LMFC period; see JESD204B multi-device synchronization: Breaking down the requirements for more
information.
7.3.6.7 Operation in Subclass 0 Systems
The ADC08DJ3200 can operate with subclass 0 compatibility provided that multi-ADC synchronization and
deterministic latency are not required. With these limitations, the device can operate without the application of
SYSREF. The internal local multiframe clock is automatically self-generated with unknown timing. SYNC is used
as normal to initiate the CGS and ILA.
7.3.7 Alarm Monitoring
A number of built-in alarms are available to monitor internal events. Several types of alarms and upsets are
detected by this feature:
1. Serializer PLL is not locked
2. JESD204B link is not transmitting data (not in the data transmission state)
3. SYSREF causes internal clocks to be realigned
4. An upset that impacts the internal clocks
When an alarm occurs, a bit for each specific alarm is set in ALM_STATUS. Each alarm bit remains set until the
host system writes a 1 to clear the alarm. If the alarm type is not masked (see the alarm mask register), then the
alarm is also indicated by the ALARM register. The CALSTAT output pin can be configured as an alarm output
that goes high when an alarm occurs; see the CAL_STATUS_SEL bit in the calibration pin configuration register.
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7.3.7.1 Clock Upset Detection
The CLK_ALM register bit indicates if the internal clocks have been upset. The clocks in channel A are
continuously compared to channel B. If the clocks differ for even one DEVCLK / 2 cycle, the CLK_ALM register
bit is set and remains set until cleared by the host system by writing a 1. For the CLK_ALM register bit to function
properly, follow these steps:
1.
2.
3.
4.
5.
6.
Program JESD_EN = 0
Ensure the part is configured to use both channels (PD_ACH = 0, PD_BCH = 0)
Program JESD_EN = 1
Write CLK_ALM = 1 to clear CLK_ALM
Monitor the CLK_ALM status bit or the CALSTAT output pin if CAL_STATUS_SEL is properly configured
When exiting global power-down (via MODE or the PD pin), the CLK_ALM status bit may be set and must be
cleared by writing a 1 to CLK_ALM
7.3.8 Temperature Monitoring Diode
A built-in thermal monitoring diode is made available on the TDIODE+ and TDIODE– pins. This diode facilitates
temperature monitoring and characterization of the device in higher ambient temperature environments. Although
the on-chip diode is not highly characterized, the diode can be used effectively by performing a baseline
measurement (offset) at a known ambient or board temperature and creating a linear equation with the diode
voltage slope provided in the Electrical Characteristics: DC Specifications table. Perform offset measurement
with the device unpowered or with the PD pin asserted to minimize device self-heating. Only assert the PD pin
long enough to take the offset measurement. Recommended monitoring devices include the LM95233 device
and similar remote-diode temperature monitoring products from Texas Instruments.
7.3.9 Analog Reference Voltage
The reference voltage for the ADC08DJ3200 is derived from an internal band-gap reference. A buffered version
of the reference voltage is available at the BG pin for user convenience. This output has an output-current
capability of ±100 µA. The BG output must be buffered if more current is required. No provision exists for the use
of an external reference voltage, but the full-scale input voltage can be adjusted through the full-scale-range
register settings. In unique cases, the VA11 supply voltage can act as the reference voltage by setting
BG_BYPASS (see the internal reference bypass register).
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7.4 Device Functional Modes
The ADC08DJ3200 can be configured to operate in a number of functional modes. These modes are described
in this section.
7.4.1 Dual-Channel Mode
The ADC08DJ3200 can be used as a dual-channel ADC where the sampling rate is equal to the clock frequency
(fS = fCLK) provided at the CLK+ and CLK– pins. The two inputs, AIN± and BIN±, serve as the respective inputs
for each channel in this mode. This mode is chosen simply by setting JMODE to the appropriate setting for the
desired configuration as described in Table 10. The analog inputs can be swapped by setting DUAL_INPUT (see
the input mux control register)
7.4.2 Single-Channel Mode (DES Mode)
The ADC08DJ3200 can also be used as a single-channel ADC where the sampling rate is equal to two times the
clock frequency (fS = 2 × fCLK) provided at the CLK+ and CLK– pins. This mode effectively interleaves the two
ADC channels together to form a single-channel ADC at twice the sampling rate. This mode is chosen simply by
setting JMODE to the appropriate setting for the desired configuration as described in Table 10. Either analog
input, INA± or INB±, can serve as the input to the ADC, however INA± is recommended for best performance.
The analog input can be selected using SINGLE_INPUT (see the input mux control register). The digital downconverters cannot be used in single-channel mode.
NOTE
INA± is strongly recommended to be used as the input to the ADC for optimized
performance in single-channel mode.
7.4.3 JESD204B Modes
The ADC08DJ3200 can be programmed as a single-channel or dual-channel ADC and a number JESD204B
output formats. Table 8 summarizes the basic operating mode configuration parameters and whether they are
user configured or derived.
NOTE
Powering down high-speed data outputs (DA0± ... DA7±, DB0± ... DB7±) for extended
times can reduce performance of the output serializers, especially at high data rates. For
information regarding reliable serializer operation, see footnote 1 in the Pin Functions
table.
Table 8. ADC08DJ3200 Operating Mode Configuration Parameters
PARAMETER
DESCRIPTION
USER CONFIGURED
OR DERIVED
VALUE
JMODE
JESD204B operating mode, automatically
derives the rest of the JESD204B
parameters, single-channel or dual-channel
mode
User configured
Set by JMODE (see the JESD204B mode
register)
D
Decimation factor
Derived
See Table 10
DES
1 = single-channel mode, 0 = dual-channel
mode
Derived
See Table 10
R
Number of bits transmitted per lane per
DEVCLK cycle. The JESD204B line rate is
the DEVCLK frequency times R. This
parameter sets the SerDes PLL
multiplication factor or controls bypassing of
the SerDes PLL.
Derived
See Table 10
Links
Number of JESD204B links used
Derived
See Table 10
K
Number of frames per multiframe
User configured
Set by KM1 (see the JESD204B K
parameter register), see the allowed values
in Table 10
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There are a number of parameters required to define the JESD204B format, all of which are sent across the link
during the initial lane alignment sequence. In the ADC08DJ3200, most parameters are automatically derived
based on the selected JMODE; however, a few are configured by the user. Table 9 describes these parameters.
Table 9. JESD204B Initial Lane Alignment Sequence Parameters
PARAMETER
DESCRIPTION
USER CONFIGURED
OR DERIVED
VALUE
ADJCNT
LMFC adjustment amount (not applicable)
Derived
Always 0
ADJDIR
LMFC adjustment direction (not applicable)
Derived
Always 0
BID
Bank ID
Derived
Always 0
CF
Number of control words per frame
Derived
Always 0
CS
Control bits per sample
Derived
Always set to 0 in ILAS, see Table 10 for
actual usage
DID
Device identifier, used to identify the link
User configured
Set by DID (see the JESD204B DID
parameter register), see Table 11
F
Number of octets (bytes) per frame (per
lane)
Derived
See Table 10
HD
High-density format (samples split between
lanes)
Derived
Always 0
JESDV
JESD204 standard revision
Derived
Always 1
K
Number of frames per multiframe
User configured
Set by the KM1 register, see the JESD204B
K parameter register
L
Number of serial output lanes per link
Derived
See Table 10
LID
Lane identifier for each lane
Derived
See Table 11
M
Number of converters used to determine
lane bit packing; may not match number of
ADC channels in the device
Derived
See Table 10
N
Sample resolution (before adding control
and tail bits)
Derived
See Table 10
N'
Bits per sample after adding control and tail
bits
Derived
See Table 10
S
Number of samples per converter (M) per
frame
Derived
See Table 10
SCR
Scrambler enabled
User configured
Set by the JESD204B control register
SUBCLASSV
Device subclass version
Derived
Always 1
RES1
Reserved field 1
Derived
Always 0
RES2
Reserved field 2
Derived
Always 0
CHKSUM
Checksum for ILAS checking (sum of all
above parameters modulo 256)
Derived
Computed based on parameters in this table
Configuring the ADC08DJ3200 is made easy by using a single configuration parameter called JMODE (see the
JESD204B mode register). Using Table 10, the correct JMODE value can be found for the desired operating
mode. The modes listed in Table 10 are the only available operating modes. This table also gives a range and
allowable step size for the K parameter (set by KM1, see the JESD204B K parameter register), which sets the
multiframe length in number of frames.
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Table 10. ADC08DJ3200 Operating Modes
USER-SPECIFIED
PARAMETER
ADC08DJ3200 OPERATING MODE
JMODE
Reserved
DERIVED PARAMETERS
K
[Min:Step:Max]
D
DES
LINKS
N
CS
N’
L
(Per
Link)
M
(Per
Link)
F
S
R
(Fbit / Fclk)
INPUT CLOCK
RANGE (MHz)
0-3
—
—
—
—
—
—
—
—
—
—
—
—
—
8-bit, single-channel, 4 lanes
4
18:2:32
1
1
2
8
0
8
2
1
1
2
5
800-2560
8-bit, single-channel, 8 lanes
5
18:2:32
1
1
2
8
0
8
4
1
1
4
2.5
800-3200
8-bit, dual-channel, 4 lanes
6
18:2:32
1
0
2
8
0
8
2
1
1
2
5
800-2560
800-3200
8-bit, dual-channel, 8 lanes
7
18:2:32
1
0
2
8
0
8
4
1
1
4
2.5
8-16
—
—
—
—
—
—
—
—
—
—
—
—
—
8-bit, single-channel, 16 lanes
17
18:2:32
1
1
2
8
0
8
8
1
1
8
1.25
800-3200
8-bit, dual-channel, 16 lanes
18
18:2:32
1
0
2
8
0
8
8
1
1
8
1.25
800-3200
Reserved
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The ADC08DJ3200 has a total of 16 high-speed output drivers that are grouped into two 8-lane JESD204B links.
Most operating modes use two links with up to eight lanes per link. The lanes and their derived configuration
parameters are described in Table 11. For a specified JMODE, the lowest indexed lanes for each link are used
and the higher indexed lanes for each link are automatically powered down. Always route the lowest indexed
lanes to the logic device.
Table 11. ADC08DJ3200 Lane Assignment and Parameters
DEVICE PIN
DESIGNATION
LINK
DID (User Configured)
LID (Derived)
DA0±
0
DA1±
1
DA2±
2
DA3±
Set by DID (see the JESD204B DID parameter
register), the effective DID is equal to the DID register
setting (DID)
A
DA4±
3
4
DA5±
5
DA6±
6
DA7±
7
DB0±
0
DB1±
1
DB2±
2
DB3±
Set by DID (see the JESD204B DID parameter
register), the effective DID is equal to the DID register
setting plus 1 (DID+1)
B
DB4±
3
4
DB5±
5
DB6±
6
DB7±
7
7.4.3.1 JESD204B Output Data Formats
Output data are formatted in a specific optimized fashion for each JMODE setting. The following tables show the
specific mapping formats for a single frame. In all mappings the tail bits (T) are 0 (zero). In Table 12 to Table 17,
the single-channel format samples are defined as Sn, where n is the sample number within the frame. In the
dual-channel output formats, the samples are defined as An and Bn, where An are samples from channel A and
Bn are samples from channel B. All samples are formatted as MSB first, LSB last.
Table 12. JMODE 4 (8-Bit, Decimate-by-1, Single-Channel, 4 Lanes)
OCTET
NIBBLE
52
0
0
1
DA0
S0
DA1
S2
DB0
S1
DB1
S3
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Table 13. JMODE 5 (8-Bit, Decimate-by-1, Single-Channel, 8 Lanes)
OCTET
NIBBLE
0
0
1
DA0
S0
DA1
S2
DA2
S4
DA3
S6
DB0
S1
DB1
S3
DB2
S5
DB3
S7
Table 14. JMODE 6 (8-Bit, Decimate-by-1, Dual-Channel, 4 Lanes)
OCTET
NIBBLE
0
0
1
DA0
A0
DA1
A1
DB0
B0
DB1
B1
Table 15. JMODE 7 (8-Bit, Decimate-by-1, Dual-Channel, 8 Lanes)
OCTET
NIBBLE
0
0
1
DA0
A0
DA1
A1
DA2
A2
DA3
A3
DB0
B0
DB1
B1
DB2
B2
DB3
B3
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Table 16. JMODE 17 (8-bit, Decimate-by-1, Single-Channel, 16 lanes)
OCTET
NIBBLE
0
0
1
DA0
S0
DA1
S2
DA2
S4
DA3
S6
DA4
S8
DA5
S10
DA6
S12
DA7
S14
DB0
S1
DB1
S3
DB2
S5
DB3
S7
DB4
S9
DB5
S11
DB6
S13
DB7
S15
Table 17. JMODE 18 (8-Bit, Decimate-by-1, Dual-Channel, 16 Lanes)
OCTET
NIBBLE
0
0
1
DA0
A0
DA1
A1
DA2
A2
DA3
A3
DA4
A4
DA5
A5
DA6
A6
DA7
A7
DB0
B0
DB1
B1
DB2
B2
DB3
B3
DB4
B4
DB5
B5
DB6
B6
DB7
B7
7.4.4 Power-Down Modes
The PD input pin allows the ADC08DJ3200 devices to be entirely powered down. Power-down can also be
controlled by MODE (see the device configuration register). The serial data output drivers are disabled when PD
is high. When the device returns to normal operation, the JESD204 link must be re-established, and the ADC
pipeline contain meaningless information so the system must wait a sufficient time for the data to be flushed. If
power-down for power savings is desired, the system must power down the supply voltages regulators for VA19,
VA11, and VD11 rather than make use of the PD input or MODE settings.
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NOTE
Powering down high speed data outputs (DA[7:0]±, DB[7:0]±) for extended times may
reduce performance of the output serializers, especially at high data rates. For information
regarding reliable serializer operation, see footnote 1 in the Pin Functions table.
7.4.5 Test Modes
A number of device test modes are available. These modes insert known patterns of information into the device
data path for assistance with system debug, development, or characterization.
7.4.5.1 Serializer Test-Mode Details
Test modes are enabled by setting JTEST (see the JESD204B test pattern control register) to the desired test
mode. Each test mode is described in detail in the following sections. Regardless of the test mode, the serializer
outputs are powered up based on JMODE. Only enable the test modes when the JESD204B link is disabled.
Figure 67 provides a diagram showing the various test mode insertion points.
ADC
JESD204B Block
JESD204B
TRANSPORT
LAYER
ADC
SCRAMBLER
(Optional)
Long/Short Transport
Octet Ramp
Test Mode Enable
JESD204B
LINK
LAYER
8b/10b
ENCODER
Repeated ILA
Modified RPAT
Test Mode Enable
JESD204B
TX
Active Lanes and
Serial Rates
Set by JMODE
PRBS
D21.5
K28.5
Serial Outputs High/Low
Test Mode Enable
Figure 67. Test Mode Insertion Points
7.4.5.2 PRBS Test Modes
The PRBS test modes bypass the 8b, 10b encoder. These test modes produce pseudo-random bit streams that
comply with the ITU-T O.150 specification. These bit streams are used with lab test equipment that can selfsynchronize to the bit pattern and, therefore, the initial phase of the pattern is not defined.
The sequences are defined by a recursive equation. For example, Equation 3 defines the PRBS7 sequence.
y[n] = y[n – 6]⊕y[n – 7]
where
•
bit n is the XOR of bit [n – 6] and bit [n – 7], which are previously transmitted bits
(3)
Table 18 lists equations and sequence lengths for the available PRBS test modes. The initial phase of the
pattern is unique for each lane.
Table 18. PBRS Mode Equations
PRBS TEST MODE
SEQUENCE
SEQUENCE LENGTH (bits)
PRBS7
y[n] = y[n – 6]⊕y[n – 7]
127
PRBS15
y[n] = y[n – 14]⊕y[n – 15]
32767
PRBS23
y[n] = y[n – 18]⊕y[n – 23]
8388607
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7.4.5.3 Ramp Test Mode
In the ramp test mode, the JESD204B link layer operates normally, but the transport layer is disabled and the
input from the formatter is ignored. After the ILA sequence, each lane transmits an identical octet stream that
increments from 0x00 to 0xFF and repeats.
7.4.5.4 Short and Long Transport Test Mode
JESD204B defines both short and long transport test modes to verify that the transport layers in the transmitter
and receiver are operating correctly. The ADC08DJ3200 only supports the short transport test pattern.
7.4.5.4.1 Short Transport Test Pattern
Short transport test patterns send a predefined octet format that repeats every frame. In the ADC08DJ3200, all
JMODE configurations that have an N' value of 8 use the short transport test pattern. Table 19 define the short
transport test patterns for N' values of 8. All applicable lanes are shown, however only the enabled lanes (lowest
indexed) for the configured JMODE are used.
Table 19. Short Transport Test Pattern for N' = 8 Modes (Length = 2 Frames)
FRAME
0
1
DA0
0x00
0xFF
DA1
0x01
0xFE
DA2
0x02
0xFD
DA3
0x03
0xFC
DB0
0x00
0xFF
DB1
0x01
0xFE
DB2
0x02
0xFD
DB3
0x03
0xFC
7.4.5.5 D21.5 Test Mode
In this test mode, the controller transmits a continuous stream of D21.5 characters (alternating 0s and 1s).
7.4.5.6 K28.5 Test Mode
In this test mode, the controller transmits a continuous stream of K28.5 characters.
7.4.5.7 Repeated ILA Test Mode
In this test mode, the JESD204B link layer operates normally, except that the ILA sequence (ILAS) repeats
indefinitely instead of starting the data phase. Whenever the receiver issues a synchronization request, the
transmitter initiates code group synchronization. Upon completion of code group synchronization, the transmitter
repeatedly transmits the ILA sequence.
7.4.5.8 Modified RPAT Test Mode
A 12-octet repeating pattern is defined in INCITS TR-35-2004. The purpose of this pattern is to generate white
spectral content for JESD204B compliance and jitter testing. Table 20 lists the pattern before and after 8b, 10b
encoding.
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Table 20. Modified RPAT Pattern Values
OCTET NUMBER
Dx.y NOTATION
8-BIT INPUT TO 8b, 10b ENCODER
0
D30.5
0xBE
1
D23.6
0xD7
2
D3.1
0x23
3
D7.2
0x47
4
D11.3
0x6B
5
D15.4
0x8F
6
D19.5
0xB3
7
D20.0
0x14
8
D30.2
0x5E
9
D27.7
0xFB
10
D21.1
0x35
11
D25.2
0x59
20b OUTPUT OF 8b, 10b ENCODER
(Two Characters)
0x86BA6
0xC6475
0xD0E8D
0xCA8B4
0x7949E
0xAA665
7.4.6 Calibration Modes and Trimming
The ADC08DJ3200 has two calibration modes available: foreground calibration and background calibration.
When foreground calibration is initiated the ADCs are automatically taken offline and the output data becomes
mid-code (0x000 in 2's complement) while a calibration is occurring. Background calibration allows the ADC to
continue normal operation while the ADC cores are calibrated in the background by swapping in a different ADC
core to take its place. Additional offset calibration features are available in both foreground and background
calibration modes. Further, a number of ADC parameters can be trimmed to optimize performance in a user
system.
The ADC08DJ3200 consists of a total of six sub-ADCs, each referred to as a bank, with two banks forming an
ADC core. The banks sample out-of-phase so that each ADC core is two-way interleaved. The six banks form
three ADC cores, referred to as ADC A, ADC B, and ADC C. In foreground calibration mode, ADC A samples
INA± and ADC B samples INB± in dual-channel mode and both ADC A and ADC B sample INA± (or INB±) in
single-channel mode. In the background calibration modes, the third ADC core, ADC C, is swapped in
periodically for ADC A and ADC B so that they can be calibrated without disrupting operation. Figure 68 provides
a diagram of the calibration system including labeling of the banks that make up each ADC core. When
calibration is performed the linearity, gain, and offset voltage for each bank are calibrated to an internally
generated calibration signal. The analog inputs can be driven during calibration, both foreground and
background, except that when offset calibration (OS_CAL or BGOS_CAL) is used there must be no signals (or
aliased signals) near DC for proper estimation of the offset (see the Offset Calibration section).
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ADC A
Interleave
Bank 0
MUX
INA
+
Calibration
Signal
INA-
Bank 1
Calibration
Engine
MUX
ADC C
Interleave
Bank 2
MUX
Calibration
Signal
Calibration
Engine
Bank 3
Calibration
Engine
INB
+
ADC A
Output
ADC B
MUX
ADC B
Output
Interleave
Bank 4
INBMUX
Calibration
Signal
Calibration
Engine
Bank 5
Calibration
Engine
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Figure 68. ADC08DJ3200 Calibration System Block Diagram
In addition to calibration, a number of ADC parameters are user controllable to provide trimming for optimal
performance. These parameters include input offset voltage, ADC gain, interleaving timing, and input termination
resistance. The default trim values are programmed at the factory to unique values for each device that are
determined to be optimal at the test system operating conditions. The user can read the factory-programmed
values from the trim registers and adjust as desired. The register fields that control the trimming are labeled
according to the input that is being sampled (INA± or INB±), the bank that is being trimmed, or the ADC core that
is being trimmed. The user is not expected to change the trim values as operating conditions change, however
optimal performance can be obtained by doing so. Any custom trimming must be done on a per device basis
because of process variations, meaning that there is no global optimal setting for all parts. See the Trimming
section for information about the available trim parameters and associated registers.
7.4.6.1 Foreground Calibration Mode
Foreground calibration requires the ADC to stop converting the analog input signals during the procedure.
Foreground calibration always runs on power-up and the user must wait a sufficient time before programming the
device to ensure that the calibration is finished. Foreground calibration can be initiated by triggering the
calibration engine. The trigger source can be either the CAL_TRIG pin or CAL_SOFT_TRIG (see the calibration
software trigger register) and is chosen by setting CAL_TRIG_EN (see the calibration pin configuration register).
7.4.6.2 Background Calibration Mode
Background calibration mode allows the ADC to continuously operate, with no interruption of data. This
continuous operation is accomplished by activating an extra ADC core that is calibrated and then takes over
operation for one of the other previously active ADC cores. When that ADC core is taken off-line, that ADC is
calibrated and can in turn take over to allow the next ADC to be calibrated. This process operates continuously,
ensuring the ADC cores always provide the optimum performance regardless of system operating condition
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changes. Because of the additional active ADC core, background calibration mode has increased power
consumption in comparison to foreground calibration mode. The low-power background calibration (LPBG) mode
discussed in the Low-Power Background Calibration (LPBG) Mode section provides reduced average power
consumption in comparison with the standard background calibration mode. Background calibration can be
enabled by setting CAL_BG (see the calibration configuration 0 register). CAL_TRIG_EN must be set to 0 and
CAL_SOFT_TRIG must be set to 1.
Great care has been taken to minimize effects on converted data as the core switching process occurs, however,
small brief glitches may still occur on the converter data as the cores are swapped. See the Typical
Characteristics section for examples of possible glitches in sine-wave and DC signals.
7.4.6.3 Low-Power Background Calibration (LPBG) Mode
Low-power background calibration (LPBG) mode reduces the power-overhead of enabling additional ADC cores.
Off-line cores are powered down until ready to be calibrated and put on-line. Set LP_EN = 1 to enable the lowpower background calibration feature. LP_SLEEP_DLY is used to adjust the amount of time an ADC sleeps
before waking up for calibration (if LP_EN = 1 and LP_TRIG = 0). LP_WAKE_DLY sets how long the core is
allowed to stabilize before calibration and being put on-line. LP_TRIG is used to select between an automatic
switching process or one that is controlled by the user via CAL_SOFT_TRIG or CAL_TRIG. In this mode there is
an increase in power consumption during the ADC core calibration. The power consumption roughly alternates
between the power consumption in foreground calibration when the spare ADC core is sleeping to the power
consumption in background calibration when the spare ADC is being calibrated. Design the power-supply
network to handle the transient power requirements for this mode.
7.4.7 Offset Calibration
Foreground calibration and background calibration modes inherently calibrate the offsets of the ADC cores;
however, the input buffers sit outside of the calibration loop and therefore their offsets are not calibrated by the
standard calibration process. In both dual-channel mode and single-channel mode, uncalibrated input buffer
offsets result in a shift in the mid-code output (DC offset) with no input. Further, in single-channel mode
uncalibrated input buffer offsets can result in a fixed spur at fS / 2. A separate calibration is provided to correct
the input buffer offsets.
There must be no signals at or near DC or aliased signals that fall at or near DC in order to properly calibration
the offsets, requiring the system to ensure this condition during normal operation or have the ability to mute the
input signal during calibration. Foreground offset calibration is enabled via CAL_OS and only performs the
calibration one time as part of the foreground calibration procedure. Background offset calibration is enabled via
CAL_BGOS and continues to correct the offset as part of the background calibration routine to account for
operating condition changes. When CAL_BGOS is set, the system must ensure that there are no DC or near DC
signals or aliased signals that fall at or near DC during normal operation. Offset calibration can be performed as
a foreground operation when using background calibration by setting CAL_OS to 1 before setting CAL_EN, but
does not correct for variations as operating conditions change.
The offset calibration correction uses the input offset voltage trim registers (see Table 21) to correct the offset
and therefore must not be written by the user when offset calibration is used. The user can read the calibrated
values by reading the OADJ_x_VINy registers, where x is the ADC core and y is the input (INA± or INB±), after
calibration is completed. Only read the values when FG_DONE is read as 1 when using foreground offset
calibration (CAL_OS = 1) and do not read the values when using background offset calibration (CAL_BGOS = 1).
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7.4.8 Trimming
Table 21 lists the parameters that can be trimmed and the associated registers.
Table 21. Trim Register Descriptions
TRIM PARAMETER
Band-gap reference
TRIM REGISTER
BG_TRIM
NOTES
Measurement on BG output pin.
RTRIM_x,
where x = A for INA± or B for INB±)
The device must be powered on with a clock
applied.
Input offset voltage
OADJ_x_VINy,
where x = ADC core (A, B or C)
and y = A for INA± or B for INB±)
A different trim value is allowed for each
ADC core (A, B, or C) to allow more
consistent offset performance in background
calibration mode.
INA± and INB± gain
GAIN_TRIM_x,
where x = A for INA± or B for INB±)
Set FS_RANGE_A and FS_RANGE_B to
default values before trimming the input. Use
FS_RANGE_A and FS_RANGE_B to adjust
the full-scale input voltage.
FS_RANGE_x,
where x = A for INA± or B for INB±)
Full-scale input voltage adjustment for each
input. The default value is effected by
GAIN_TRIM_x (x = A or B). Trim
GAIN_TRIM_x with FS_RANGE_x set to the
default value. FS_RANGE_x can then be
used to trim the full-scale input voltage.
Bx_TIME_y,
where x = bank number (0–5)
and y = 0° or –90° clock phase
Trims the timing between the two banks of
an ADC core (ADC A, B, or C) for two clock
phases, either 0° or –90°. The –90° clock
phase is used in single-channel mode only.
Input termination resistance
INA± and INB± full-scale input voltage
Intra-ADC core timing (bank timing)
Inter-ADC core timing (dual-channel mode)
Inter-ADC core timing (single-channel mode)
TADJ_A, TADJ_B, TADJ_CA, TADJ_CB
The suffix letter (A, B, CA, or CB) indicates
the ADC core that is being trimmed. CA
indicates the timing trim in background
calibration mode for ADC C when standing in
for ADC A, whereas CB is the timing trim for
ADC C when standing in for ADC B.
TADJ_A_FG90, TADJ_B_FG0,
TADJ_A_BG90, TADJ_C_BG0,
TADJ_C_BG90, TADJ_B_BG0
The middle letter (A, B, or C) indicates the
ADC core that is being trimmed. FG indicates
a trim for foreground calibration while BG
indicates background calibration. The suffix
of 0 or 90 indicates the clock phase applied
to the ADC core. 0 indicates a 0° clock and is
sampling in-phase with the clock input. 90
indicates a 90° clock and therefore is
sampling out-of-phase with the clock input.
These timings must be trimmed for optimal
performance if the user prefers to use INB±
in single-channel mode. These timings are
trimmed for INA± at the factory.
7.4.9 Offset Filtering
The ADC08DJ3200 has an additional feature that can be enabled to reduce offset-related interleaving spurs at fS
/ 2 and fS / 4 (single input mode only). Offset filtering is enabled via CAL_OSFILT. The OSFILT_BW and
OSFILT_SOAK parameters can be adjusted to tradeoff offset spur reduction with potential impact on information
in the mission mode signal being processed. Set these two parameters to the same value under most situations.
The DC_RESTORE setting is used to either retain or filter out all DC-related content in the signal.
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7.5 Programming
7.5.1 Using the Serial Interface
The serial interface is accessed using the following four pins: serial clock (SCLK), serial data in (SDI), serial data
out (SDO), and serial interface chip-select (SCS). Register access is enabled through the SCS pin.
7.5.1.1 SCS
This signal must be asserted low to access a register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
7.5.1.2 SCLK
Serial data input is accepted at the rising edge of this signal. SCLK has no minimum frequency requirement.
7.5.1.3 SDI
Each register access requires a specific 24-bit pattern at this input. This pattern consists of a read-and-write
(R/W) bit, register address, and register value. The data are shifted in MSB first and multi-byte registers are
always in little-endian format (least significant byte stored at the lowest address). Setup and hold times with
respect to the SCLK must be observed (see the Timing Requirements table).
7.5.1.4 SDO
The SDO signal provides the output data requested by a read command. This output is high impedance during
write bus cycles and during the read bit and register address portion of read bus cycles.
As shown in Figure 69, each register access consists of 24 bits. The first bit is high for a read and low for a write.
The next 15 bits are the address of the register that is to be written to. During write operations, the last eight bits
are the data written to the addressed register. During read operations, the last eight bits on SDI are ignored and,
during this time, the SDO outputs the data from the addressed register. Figure 69 shows the serial protocol
details.
Single Register Access
SCS
1
8
16
17
24
SCLK
Command Field
SDI
R/W
A14
A13 A12
A11
A10
A9
A8
A7
A6
Data Field
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Data Field
SDO
(read mode)
High Z
D7
D6
D5
D4
D3
D2
D1
D0
High Z
Figure 69. Serial Interface Protocol: Single Read/Write
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Programming (continued)
7.5.1.5 Streaming Mode
The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction
specifics the access type, register address, and data value as normal. Additional clock cycles of write or read
data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The
register address auto increments (default) or decrements for each subsequent 8-bit transfer of the streaming
transaction. The ADDR_ASC bit (register 000h, bits 5 and 2) controls whether the address value ascends
(increments) or descends (decrements). Streaming mode can be disabled by setting the ADDR_HOLD bit (see
the user SPI configuration register). Figure 70 shows the streaming mode transaction details.
Multiple Register Access
SCS
8
1
16
17
24
25
32
SCLK
Command Field
SDI
R/W A14
A13
A12
A1
1
A10
A9
A8
A7
Data Field (write mode)
Data Field (write mode)
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D7
D6
D5
D4
D3
D2
D1
D0
Data Field
Data Field
High Z
SDO
(read mode)
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
High Z
Figure 70. Serial Interface Protocol: Streaming Read/Write
See the Register Maps section for detailed information regarding the registers.
NOTE
The serial interface must not be accessed during ADC calibration. Accessing the serial
interface during this time impairs the performance of the device until the device is
calibrated correctly. Writing or reading the serial registers also reduces dynamic ADC
performance for the duration of the register access time.
7.6 Register Maps
The Memory Map lists all the ADC08DJ3200 registers.
Memory Map
ADDRESS
RESET
ACRONYM
TYPE
REGISTER NAME
STANDARD SPI-3.0 (0x000 to 0x00F)
0x000
0x30
CONFIG_A
R/W
0x001
Undefined
RESERVED
R
Configuration A Register
0x002
0x00
DEVICE_CONFIG
R/W
0x003
0x03
CHIP_TYPE
R
Chip Type Register
0x004-0x005
0x0020
CHIP_ID
R
Chip ID Registers
0x006
0x0A
CHIP_VERSION
R
Chip Version Register
RESERVED
Device Configuration Register
0x007-0x00B
Undefined
RESERVED
R
RESERVED
0x00C-0x00D
0x0451
VENDOR_ID
R
Vendor Identification Register
0x00E-0x00F
Undefined
RESERVED
R
RESERVED
USER SPI CONFIGURATION (0x010 to 0x01F)
0x010
0x00
USR0
R/W
0x011-0x01F
Undefined
RESERVED
R
62
User SPI Configuration Register
RESERVED
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Register Maps (continued)
Memory Map (continued)
ADDRESS
RESET
ACRONYM
TYPE
REGISTER NAME
MISCELLANEOUS ANALOG REGISTERS (0x020 to 0x047)
0x020-0x028
Undefined
RESERVED
R
0x029
0x00
CLK_CTRL0
R/W
RESERVED
Clock Control Register 0
0x02A
0x20
CLK_CTRL1
R/W
Clock Control Register 1
0x02B
Undefined
RESERVED
R
RESERVED
0x02C-0x02E
Undefined
SYSREF_POS
R
SYSREF Capture Position Register
0x02F
Undefined
RESERVED
R
RESERVED
0x030-0x031
0xA000
FS_RANGE_A
R/W
INA Full-Scale Range Adjust Register
0x032-0x033
0xA000
FS_RANGE_B
R/W
INB Full-Scale Range Adjust Register
0x034-0x037
Undefined
RESERVED
R
0x038
0x00
BG_BYPASS
R/W
0x039-0x03A
Undefined
RESERVED
R
0x03B
0x00
TMSTP_CTRL
R/W
0x03C-0x047
Undefined
RESERVED
R
RESERVED
Internal Reference Bypass Register
RESERVED
TMSTP± Control Register
RESERVED
SERIALIZER REGISTERS (0x048 to 0x05F)
0x048
0x00
SER_PE
R/W
0x049-0x05F
Undefined
RESERVED
R
Serializer Pre-Emphasis Control Register
RESERVED
CALIBRATION REGISTERS (0x060 to 0x0FF)
0x060
0x01
INPUT_MUX
R/W
Input Mux Control Register
0x061
0x01
CAL_EN
R/W
Calibration Enable Register
0x062
0x01
CAL_CFG0
R/W
Calibration Configuration 0 Register
0x063-0x069
Undefined
RESERVED
R
RESERVED
0x06A
Undefined
CAL_STATUS
R
Calibration Status Register
0x06B
0x00
CAL_PIN_CFG
R/W
Calibration Pin Configuration Register
0x06C
0x01
CAL_SOFT_TRIG
R/W
Calibration Software Trigger Register
0x06D
Undefined
RESERVED
R
0x06E
0x88
CAL_LP
R/W
0x06F
Undefined
RESERVED
R
0x070
0x00
CAL_DATA_EN
R/W
Calibration Data Enable Register
0x071
Undefined
CAL_DATA
R/W
Calibration Data Register
0x072-0x079
Undefined
RESERVED
R
0x07A
Undefined
GAIN_TRIM_A
R/W
Channel A Gain Trim Register
0x07B
Undefined
GAIN_TRIM_B
R/W
Channel B Gain Trim Register
0x07C
Undefined
BG_TRIM
R/W
Band-Gap Reference Trim Register
0x07D
Undefined
RESERVED
R
0x07E
Undefined
RTRIM_A
R/W
VINA Input Resistor Trim Register
0x07F
Undefined
RTRIM_B
R/W
VINB Input Resistor Trim Register
0x080
Undefined
TADJ_A_FG90
R/W
Timing Adjustment for A-ADC, Single-Channel Mode,
Foreground Calibration Register
0x081
Undefined
TADJ_B_FG0
R/W
Timing Adjustment for B-ADC, Single-Channel Mode,
Foreground Calibration Register
0x082
Undefined
TADJ_A_BG90
R/W
Timing Adjustment for A-ADC, Single-Channel Mode,
Background Calibration Register
0x083
Undefined
TADJ_C_BG0
R/W
Timing Adjustment for C-ADC, Single-Channel Mode,
Background Calibration Register
0x084
Undefined
TADJ_C_BG90
R/W
Timing Adjustment for C-ADC, Single-Channel Mode,
Background Calibration Register
RESERVED
Low-Power Background Calibration Register
RESERVED
RESERVED
RESERVED
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Register Maps (continued)
Memory Map (continued)
ADDRESS
RESET
ACRONYM
TYPE
REGISTER NAME
0x085
Undefined
TADJ_B_BG0
R/W
Timing Adjustment for B-ADC, Single-Channel Mode,
Background Calibration Register
0x086
Undefined
TADJ_A
R/W
Timing Adjustment for A-ADC, Dual-Channel Mode Register
0x087
Undefined
TADJ_CA
R/W
Timing Adjustment for C-ADC Acting for A-ADC, DualChannel Mode Register
0x088
Undefined
TADJ_CB
R/W
Timing Adjustment for C-ADC Acting for B-ADC, DualChannel Mode Register
0x089
Undefined
TADJ_B
R/W
Timing Adjustment for B-ADC, Dual-Channel Mode Register
0x08A-0x08B
Undefined
OADJ_A_INA
R/W
Offset Adjustment for A-ADC and INA Register
0x08C-0x08D
Undefined
OADJ_A_INB
R/W
Offset Adjustment for A-ADC and INB Register
0x08E-0x08F
Undefined
OADJ_C_INA
R/W
Offset Adjustment for C-ADC and INA Register
0x090-0x091
Undefined
OADJ_C_INB
R/W
Offset Adjustment for C-ADC and INB Register
0x092-0x093
Undefined
OADJ_B_INA
R/W
Offset Adjustment for B-ADC and INA Register
0x094-0x095
Undefined
OADJ_B_INB
R/W
Offset Adjustment for B-ADC and INB Register
0x096
Undefined
RESERVED
R
0x097
0x00
OSFILT0
R/W
Offset Filtering Control 0
0x098
0x33
OSFILT1
R/W
Offset Filtering Control 1
0x099-0x0FF
Undefined
RESERVED
R
RESERVED
RESERVED
RESERVED
ADC BANK REGISTERS (0x100 to 0x15F)
0x100-0x101
Undefined
RESERVED
R
0x102
Undefined
B0_TIME_0
R/W
Timing Adjustment for Bank 0 (0° Clock) Register
0x103
Undefined
B0_TIME_90
R/W
Timing Adjustment for Bank 0 (–90° Clock) Register
0x104-0x111
Undefined
RESERVED
R
0x112
Undefined
B1_TIME_0
R/W
Timing Adjustment for Bank 1 (0° Clock) Register
0x113
Undefined
B1_TIME_90
R/W
Timing Adjustment for Bank 1 (–90° Clock) Register
0x114-0x121
Undefined
RESERVED
R
0x122
Undefined
B2_TIME_0
R/W
Timing Adjustment for Bank 2 (0° Clock) Register
0x123
Undefined
B2_TIME_90
R/W
Timing Adjustment for Bank 2 (–90° Clock) Register
0x124-0x131
Undefined
RESERVED
R
0x132
Undefined
B3_TIME_0
R/W
Timing Adjustment for Bank 3 (0° Clock) Register
0x133
Undefined
B3_TIME_90
R/W
Timing Adjustment for Bank 3 (–90° Clock) Register
0x134-0x141
Undefined
RESERVED
R
0x142
Undefined
B4_TIME_0
R/W
Timing Adjustment for Bank 4 (0° Clock) Register
0x143
Undefined
B4_TIME_90
R/W
Timing Adjustment for Bank 4 (–90° Clock) Register
0x144-0x151
Undefined
RESERVED
R
0x152
Undefined
B5_TIME_0
R/W
Timing Adjustment for Bank 5 (0° Clock) Register
0x153
Undefined
B5_TIME_90
R/W
Timing Adjustment for Bank 5 (–90° Clock) Register
0x154-0x15F
Undefined
RESERVED
R
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
LSB CONTROL REGISTERS (0x160 to 0x1FF)
0x160
0x00
ENC_LSB
R/W
0x161-0x1FF
Undefined
RESERVED
R
LSB Control Bit Output Register
RESERVED
JESD204B REGISTERS (0x200 to 0x20F)
64
0x200
0x01
JESD_EN
R/W
JESD204B Enable Register
0x201
0x02
JMODE
R/W
JESD204B Mode (JMODE) Register
0x202
0x1F
KM1
R/W
JESD204B K Parameter Register
0x203
0x01
JSYNC_N
R/W
JESD204B Manual SYNC Request Register
0x204
0x02
JCTRL
R/W
JESD204B Control Register
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Register Maps (continued)
Memory Map (continued)
ADDRESS
RESET
ACRONYM
TYPE
0x205
0x00
JTEST
R/W
JESD204B Test Pattern Control Register
REGISTER NAME
0x206
0x00
DID
R/W
JESD204B DID Parameter Register
0x207
0x00
FCHAR
R/W
JESD204B Frame Character Register
0x208
Undefined
JESD_STATUS
R/W
JESD204B, System Status Register
0x209
0x00
PD_CH
R/W
JESD204B Channel Power-Down
0x20A
0x00
JEXTRA_A
R/W
JESD204B Extra Lane Enable (Link A)
0x20B
0x00
JEXTRA_B
R/W
JESD204B Extra Lane Enable (Link B)
0x20C-0x210
Undefined
RESERVED
R
RESERVED
DIGITAL DOWN CONVERTER REGISTERS (0x210-0x2AF)
0x211
0xF2
OVR_T0
R/W
Overrange Threshold 0 Register
0x212
0xAB
OVR_T1
R/W
Overrange Threshold 1 Register
Overrange Configuration Register
0x213
0x07
OVR_CFG
R/W
0x214-0x296
Undefined
RESERVED
R
RESERVED
0x297
Undefined
SPIN_ID
R
Spin Identification Value
0x298-0x2AF
Undefined
RESERVED
R
RESERVED
SYSREF CALIBRATION REGISTERS (0x2B0 to 0x2BF)
0x2B0
0x00
SRC_EN
R/W
SYSREF Calibration Enable Register
0x2B1
0x05
SRC_CFG
R/W
SYSREF Calibration Configuration Register
0x2B2-0x2B4
Undefined
SRC_STATUS
R
0x2B5-0x2B7
0x00
TAD
R/W
DEVCLK Aperture Delay Adjustment Register
0x2B8
0x00
TAD_RAMP
R/W
DEVCLK Timing Adjust Ramp Control Register
0x2B9-0x2BF
Undefined
RESERVED
R
RESERVED
Alarm Interrupt Status Register
SYSREF Calibration Status
ALARM REGISTERS (0x2C0 to 0x2C2)
0x2C0
Undefined
ALARM
R
0x2C1
0x1F
ALM_STATUS
R/W
Alarm Status Register
0x2C2
0x1F
ALM_MASK
R/W
Alarm Mask Register
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7.6.1 Register Descriptions
Table 22 lists the access codes for the ADC08DJ3200 registers.
Table 22. ADC08DJ3200 Access Type Codes
Access Type
Code
Description
R
R
Read
R-W
R/W
Read or write
W
W
Write
-n
Value after reset or the default
value
7.6.1.1 Standard SPI-3.0 (0x000 to 0x00F)
Table 23. Standard SPI-3.0 Registers
ADDRESS
RESET
ACRONYM
0x000
0x30
CONFIG_A
Configuration A Register
REGISTER NAME
0x001
Undefined
RESERVED
RESERVED
0x002
0x00
—
DEVICE_CONFIG Device Configuration Register
0x003
0x03
CHIP_TYPE
0x004-0x005
0x0020
CHIP_ID
SECTION
Configuration A Register (address = 0x000) [reset = 0x30]
Device Configuration Register (address = 0x002) [reset =
0x00]
Chip Type Register
Chip Type Register (address = 0x003) [reset = 0x03]
Chip ID Registers
Chip ID Register (address = 0x004 to 0x005) [reset =
0x0020]
0x006
0x0A
CHIP_VERSION
0x007-0x00B
Undefined
RESERVED
Chip Version Register
RESERVED
Chip Version Register (address = 0x006) [reset = 0x01]
0x00C-0x00D
0x0451
VENDOR_ID
Vendor Identification Register
0x00E-0x00F
Undefined
RESERVED
RESERVED
—
Vendor Identification Register (address = 0x00C to
0x00D) [reset = 0x0451]
—
7.6.1.1.1 Configuration A Register (address = 0x000) [reset = 0x30]
Figure 71. Configuration A Register (CONFIG_A)
7
SOFT_RESET
R/W-0
6
RESERVED
R-0
5
ADDR_ASC
R/W-1
4
SDO_ACTIVE
R-1
3
2
1
0
RESERVED
R-0000
Table 24. CONFIG_A Field Descriptions
Bit
Field
Type
Reset
Description
7
SOFT_RESET
R/W
0
Setting this bit results in a full reset of the device. This bit is selfclearing. After writing this bit, the device may take up to 750 ns
to reset. During this time, do not perform any SPI transactions.
6
RESERVED
R
0
RESERVED
5
ADDR_ASC
R/W
1
0: Descend – decrement address while streaming reads/writes
1: Ascend – increment address while streaming reads/writes
(default)
4
SDO_ACTIVE
R
1
Always returns 1, indicating that the device always uses 4-wire
SPI mode.
RESERVED
R
0000
RESERVED
3-0
66
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7.6.1.1.2 Device Configuration Register (address = 0x002) [reset = 0x00]
Figure 72. Device Configuration Register (DEVICE_CONFIG)
7
6
5
4
3
2
1
RESERVED
R-0000 00
0
MODE
R/W-00
Table 25. DEVICE_CONFIG Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
0000 00
RESERVED
1-0
MODE
R/W
00
The SPI 3.0 specification lists 1 as the low-power functional
mode, 2 as the low-power fast resume, and 3 as power-down.
This device does not support these modes.
0: Normal operation – full power and full performance (default)
1: Normal operation – full power and full performance
2: Power down - everything is powered down. Only use this
setting for brief periods of time to calibrate the on-chip
temperature diode measurement. See the Recommended
Operating Conditions table for more information.
3: Power down - everything is powered down. Only use this
setting for brief periods of time to calibrate the on-chip
temperature diode measurement. See the Recommended
Operating Conditions table for more information.
7.6.1.1.3 Chip Type Register (address = 0x003) [reset = 0x03]
Figure 73. Chip Type Register (CHIP_TYPE)
7
6
5
4
3
2
RESERVED
R-0000
1
0
CHIP_TYPE
R-0011
Table 26. CHIP_TYPE Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0000
RESERVED
3-0
CHIP_TYPE
R
0011
Always returns 0x3, indicating that the device is a high-speed
ADC.
7.6.1.1.4 Chip ID Register (address = 0x004 to 0x005) [reset = 0x0020]
Figure 74. Chip ID Register (CHIP_ID)
15
14
13
12
11
10
9
8
3
2
1
0
CHIP_ID[15:8]
R-0x00h
7
6
5
4
CHIP_ID[7:0]
R-0x20h
Table 27. CHIP_ID Field Descriptions
Bit
15-0
Field
Type
Reset
Description
CHIP_ID
R
0x0020h
Always returns 0x0020, indicating that this device is part of the
ADC08DJxx00 family.
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7.6.1.1.5 Chip Version Register (address = 0x006) [reset = 0x01]
Figure 75. Chip Version Register (CHIP_VERSION)
7
6
5
4
3
CHIP_VERSION
R-0000 1010
2
1
0
Table 28. CHIP_VERSION Field Descriptions
Bit
Field
Type
Reset
7-0
CHIP_VERSION
R
0000 1010 Chip version, returns 0x0A.
Description
7.6.1.1.6 Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451]
Figure 76. Vendor Identification Register (VENDOR_ID)
15
14
13
12
11
VENDOR_ID[15:8]
R-0x04h
10
9
8
7
6
5
4
3
VENDOR_ID[7:0]
R-0x51h
2
1
0
Table 29. VENDOR_ID Field Descriptions
Bit
15-0
Field
Type
Reset
Description
VENDOR_ID
R
0x0451h
Always returns 0x0451 (TI vendor ID).
7.6.1.2 User SPI Configuration (0x010 to 0x01F)
Table 30. User SPI Configuration Registers
ADDRESS
RESET
ACRONYM
0x010
0x00
USR0
0x011-0x01F
Undefined
RESERVED
REGISTER NAME
User SPI Configuration Register
SECTION
User SPI Configuration Register (address = 0x010) [reset
= 0x00]
RESERVED
—
7.6.1.2.1 User SPI Configuration Register (address = 0x010) [reset = 0x00]
Figure 77. User SPI Configuration Register (USR0)
7
6
5
4
RESERVED
R-0000 000
3
2
1
0
ADDR_HOLD
R/W-0
Table 31. USR0 Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
ADDR_HOLD
R/W
0
0: Use the ADDR_ASC bit to define what happens to the
address during streaming (default)
1: Address remains static throughout streaming operation; this
setting is useful for reading/writing calibration vector information
at the CAL_DATA register
0
68
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7.6.1.3 Miscellaneous Analog Registers (0x020 to 0x047)
Table 32. Miscellaneous Analog Registers
ADDRESS
RESET
ACRONYM
0x020-0x028
Undefined
RESERVED
RESERVED
REGISTER NAME
SECTION
—
0x029
0x00
CLK_CTRL0
Clock Control Register 0
Clock Control Register 0 (address = 0x029) [reset = 0x00]
0x02A
0x20
CLK_CTRL1
Clock Control Register 1
Clock Control Register 1 (address = 0x02A) [reset = 0x00]
RESERVED
0x02B
Undefined
RESERVED
0x02C-0x02E
Undefined
SYSREF_POS
—
SYSREF Capture Position Register
SYSREF Capture Position Register (address = 0x02C0x02E) [reset = Undefined]
0x02F
Undefined
RESERVED
0x030-0x031
0xA000
FS_RANGE_A
RESERVED
INA Full-Scale Range Adjust Register
INA Full-Scale Range Adjust Register (address = 0x0300x031) [reset = 0xA000]
—
0x032-0x033
0xA000
FS_RANGE_B
INB Full-Scale Range Adjust Register
INB Full-Scale Range Adjust Register (address = 0x0320x033) [reset = 0xA000]
0x034-0x037
Undefined
RESERVED
RESERVED
0x038
0x00
BG_BYPASS
Internal Reference Bypass Register
0x039-0x03A
Undefined
RESERVED
RESERVED
0x03B
0x00
SYNC_CTRL
TMSTP± Control Register
0x03C-0x047
Undefined
RESERVED
RESERVED
—
Internal Reference Bypass Register (address = 0x038)
[reset = 0x00]
—
TMSTP± Control Register (address = 0x03B) [reset =
0x00]
—
7.6.1.3.1 Clock Control Register 0 (address = 0x029) [reset = 0x00]
Figure 78. Clock Control Register 0 (CLK_CTRL0)
7
RESERVED
R/W-0
6
SYSREF_PROC_EN
R/W-0
5
SYSREF_RECV_EN
R/W-0
4
SYSREF_ZOOM
R/W-0
3
2
1
SYSREF_SEL
R/W-0000
0
Table 33. CLK_CTRL0 Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
RESERVED
6
SYSREF_PROC_EN
R/W
0
This bit enables the SYSREF processor. This bit must be set to
allow the device to process SYSREF events.
SYSREF_RECV_EN must be set before setting
SYSREF_PROC_EN.
5
SYSREF_RECV_EN
R/W
0
Set this bit to enable the SYSREF receiver circuit.
4
SYSREF_ZOOM
R/W
0
Set this bit to zoom in the SYSREF strobe status (affects
SYSREF_POS).
SYSREF_SEL
R/W
0000
Set this field to select which SYSREF delay to use. Set this field
based on the results returned by SYSREF_POS. Set this field to
0 to use SYSREF calibration.
3-0
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7.6.1.3.2 Clock Control Register 1 (address = 0x02A) [reset = 0x00]
Figure 79. Clock Control Register 1 (CLK_CTRL1)
7
6
5
RESERVED
R/W-0010 0
4
3
2
DEVCLK_LVPECL_EN
R/W-0
1
SYSREF_LVPECL_EN
R/W-0
0
SYSREF_INVERTED
R/W-0
Table 34. CLK_CTRL1 Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R/W
0010 0
RESERVED
2
DEVCLK_LVPECL_EN
R/W
0
Activate low-voltage PECL mode for DEVCLK.
1
SYSREF_LVPECL_EN
R/W
0
Activate low-voltage PECL mode for SYSREF.
0
SYSREF_INVERTED
R/W
0
Inverts the SYSREF signal used for alignment.
7.6.1.3.3 SYSREF Capture Position Register (address = 0x02C-0x02E) [reset = Undefined]
Figure 80. SYSREF Capture Position Register (SYSREF_POS)
23
22
21
15
14
13
7
6
5
20
19
SYSREF_POS[23:16]
R-Undefined
12
11
SYSREF_POS[15:8]
R-Undefined
4
3
SYSREF_POS[7:0]
R-Undefined
18
17
16
10
9
8
2
1
0
Table 35. SYSREF_POS Field Descriptions
Bit
23-0
Field
Type
Reset
Description
SYSREF_POS
R
Undefined
This field returns a 24-bit status value that indicates the position
of the SYSREF edge with respect to DEVCLK. Use this field to
program SYSREF_SEL.
7.6.1.3.4 INA Full-Scale Range Adjust Register (address = 0x030-0x031) [reset = 0xA000]
Figure 81. INA Full-Scale Range Adjust Register (FS_RANGE_A)
15
14
13
7
6
5
12
11
FS_RANGE_A[15:8]
R/W-0xA0h
4
3
FS_RANGE_A[7:0]
R/W-0x00h
10
9
8
2
1
0
Table 36. FS_RANGE_A Field Descriptions
Bit
15-0
70
Field
Type
Reset
Description
FS_RANGE_A
R/W
0xA000h
This field enables adjustment of the analog full-scale range for
INA.
0x0000: Settings below 0x2000 may result in degraded device
performance
0x2000: 500 mVPP - Recommended minimum setting
0xA000: 800 mVPP (default)
0xFFFF: 1000 mVPP
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7.6.1.3.5 INB Full-Scale Range Adjust Register (address = 0x032-0x033) [reset = 0xA000]
Figure 82. INB Full Scale Range Adjust Register (FS_RANGE_B)
15
14
13
7
6
5
12
11
FS_RANGE_B[15:8]
R/W-0xA0
4
3
FS_RANGE_B[7:0]
R/W-0x00
10
9
8
2
1
0
Table 37. FS_RANGE_B Field Descriptions
Bit
15-0
Field
Type
Reset
Description
FS_RANGE_B
R/W
0xA000h
This field enables adjustment of the analog full-scale range for
INB.
0x0000: Settings below 0x2000 may result in degraded device
performance
0x2000: 500 mVPP - Recommended minimum setting
0xA000: 800 mVPP (default)
0xFFFF: 1000 mVPP
7.6.1.3.6 Internal Reference Bypass Register (address = 0x038) [reset = 0x00]
Figure 83. Internal Reference Bypass Register (BG_BYPASS)
7
6
5
4
RESERVED
R/W-0000 000
3
2
1
0
BG_BYPASS
R/W-0
Table 38. BG_BYPASS Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
0
BG_BYPASS
R/W
0
When set, VA11 is used as the voltage reference instead of the
internal reference.
7.6.1.3.7 TMSTP± Control Register (address = 0x03B) [reset = 0x00]
Figure 84. TMSTP± Control Register (TMSTP_CTRL)
7
6
5
4
RESERVED
R/W-0000 00
3
2
1
TMSTP_LVPECL_EN
R/W-0
0
TMSTP_RECV_EN
R/W-0
Table 39. TMSTP_CTRL Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R/W
0000 00
RESERVED
1
TMSTP_LVPECL_EN
R/W
0
When set, this bit activates the low-voltage PECL mode for the
differential TMSTP± input.
0
TMSTP_RECV_EN
R/W
0
This bit enables the differential TMSTP± input.
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7.6.1.4 Serializer Registers (0x048 to 0x05F)
Table 40. Serializer Registers
ADDRESS
RESET
ACRONYM
0x048
0x00
SER_PE
0x049-0x05F
Undefined
RESERVED
REGISTER NAME
Serializer Pre-Emphasis Control
Register
SECTION
Serializer Pre-Emphasis Control Register (address =
0x048) [reset = 0x00]
RESERVED
—
7.6.1.4.1 Serializer Pre-Emphasis Control Register (address = 0x048) [reset = 0x00]
Figure 85. Serializer Pre-Emphasis Control Register (SER_PE)
7
6
5
4
3
RESERVED
R/W-0000
2
1
0
SER_PE
R/W-0000
Table 41. SER_PE Field Descriptions
72
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
RESERVED
3-0
SER_PE
R/W
0000
This field sets the pre-emphasis for the serial lanes to
compensate for the low-pass response of the PCB trace. This
setting is a global setting that affects all 16 lanes.
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7.6.1.5 Calibration Registers (0x060 to 0x0FF)
Table 42. Calibration Registers
ADDRESS
RESET
ACRONYM
0x060
0x01
INPUT_MUX
Input Mux Control Register
REGISTER NAME
Input Mux Control Register (address = 0x060) [reset =
0x01]
0x061
0x01
CAL_EN
Calibration Enable Register
Calibration Enable Register (address = 0x061) [reset =
0x01]
0x062
0x01
CAL_CFG0
Calibration Configuration 0 Register
Calibration Configuration 0 Register (address = 0x062)
[reset = 0x01]
0x063-0x069
Undefined
RESERVED
RESERVED
0x06A
Undefined
CAL_STATUS
Calibration Status Register
0x06B
0x00
CAL_PIN_CFG
Calibration Pin Configuration
Register
0x06C
0x01
0x06D
Undefined
RESERVED
0x06E
0x88
CAL_LP
0x06F
Undefined
RESERVED
0x070
0x00
CAL_DATA_EN
0x071
Undefined
CAL_DATA
Calibration Data Register
0x072-0x079
Undefined
RESERVED
RESERVED
0x07A
Undefined
GAIN_TRIM_A
Channel A Gain Trim Register
Channel A Gain Trim Register (address = 0x07A) [reset =
Undefined]
0x07B
Undefined
GAIN_TRIM_B
Channel B Gain Trim Register
Channel B Gain Trim Register (address = 0x07B) [reset =
Undefined]
0x07C
Undefined
BG_TRIM
0x07D
Undefined
RESERVED
0x07E
Undefined
RTRIM_A
VINA Input Resistor Trim Register
VINA Input Resistor Trim Register (address = 0x07E)
[reset = Undefined]
0x07F
Undefined
RTRIM_B
VINB Input Resistor Trim Register
VINB Input Resistor Trim Register (address = 0x07F)
[reset = Undefined]
0x080
Undefined
TADJ_A_FG90
Timing Adjustment for A-ADC,
Single-Channel Mode, Foreground
Calibration Register
Timing Adjust for A-ADC, Single-Channel Mode,
Foreground Calibration Register (address = 0x080) [reset
= Undefined]
0x081
Undefined
TADJ_B_FG0
Timing Adjustment for B-ADC,
Single-Channel Mode, Foreground
Calibration Register
Timing Adjust for B-ADC, Single-Channel Mode,
Foreground Calibration Register (address = 0x081) [reset
= Undefined]
0x082
Undefined
TADJ_A_BG90
Timing Adjustment for A-ADC,
Single-Channel Mode, Background
Calibration Register
Timing Adjust for A-ADC, Single-Channel Mode,
Background Calibration Register (address = 0x082) [reset
= Undefined]
0x083
Undefined
TADJ_C_BG0
Timing Adjustment for C-ADC,
Single-Channel Mode, Background
Calibration Register
Timing Adjust for C-ADC, Single-Channel Mode,
Background Calibration Register (address = 0x084) [reset
= Undefined]
0x084
Undefined
TADJ_C_BG90
Timing Adjustment for C-ADC,
Single-Channel Mode, Background
Calibration Register
Timing Adjust for C-ADC, Single-Channel Mode,
Background Calibration Register (address = 0x084) [reset
= Undefined]
0x085
Undefined
TADJ_B_BG0
Timing Adjustment for B-ADC,
Single-Channel Mode, Background
Calibration Register
Timing Adjust for B-ADC, Single-Channel Mode,
Background Calibration Register (address = 0x085) [reset
= Undefined]
0x086
Undefined
TADJ_A
Timing Adjustment for A-ADC, DualChannel Mode Register
Timing Adjust for A-ADC, Dual-Channel Mode Register
(address = 0x086) [reset = Undefined]
0x087
Undefined
TADJ_CA
Timing Adjustment for C-ADC Acting
for A-ADC, Dual-Channel Mode
Register
Timing Adjust for C-ADC Acting for A-ADC, Dual-Channel
Mode Register (address = 0x087) [reset = Undefined]
0x088
Undefined
TADJ_CB
Timing Adjustment for C-ADC Acting
for B-ADC, Dual-Channel Mode
Register
Timing Adjust for C-ADC Acting for B-ADC, Dual-Channel
Mode Register (address = 0x088) [reset = Undefined]
CAL_SOFT_TRIG Calibration Software Trigger Register
RESERVED
Low-Power Background Calibration
Register
RESERVED
Calibration Data Enable Register
Band-Gap Reference Trim Register
RESERVED
SECTION
—
Calibration Status Register (address = 0x06A) [reset =
Undefined]
Calibration Pin Configuration Register (address = 0x06B)
[reset = 0x00]
Calibration Software Trigger Register (address = 0x06C)
[reset = 0x01]
—
Low-Power Background Calibration Register (address =
0x06E) [reset = 0x88]
—
Calibration Data Enable Register (address = 0x070) [reset
= 0x00]
Calibration Data Register (address = 0x071) [reset =
Undefined]
—
Band-Gap Reference Trim Register (address = 0x07C)
[reset = Undefined]
—
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Table 42. Calibration Registers (continued)
ADDRESS
RESET
ACRONYM
0x089
Undefined
TADJ_B
REGISTER NAME
SECTION
0x08A-0x08B
Undefined
OADJ_A_INA
Offset Adjustment for A-ADC and INA Offset Adjustment for A-ADC and INA Register (address =
Register
0x08A-0x08B) [reset = Undefined]
0x08C-0x08D
Undefined
OADJ_A_INB
Offset Adjustment for A-ADC and INB Offset Adjustment for A-ADC and INB Register (address =
Register
0x08C-0x08D) [reset = Undefined]
0x08E-0x08F
Undefined
OADJ_C_INA
Offset Adjustment for C-ADC and
INA Register
Offset Adjustment for C-ADC and INA Register (address =
0x08E-0x08F) [reset = Undefined]
0x090-0x091
Undefined
OADJ_C_INB
Offset Adjustment for C-ADC and
INB Register
Offset Adjustment for C-ADC and INB Register (address =
0x090-0x091) [reset = Undefined]
0x092-0x093
Undefined
OADJ_B_INA
Offset Adjustment for B-ADC and INA Offset Adjustment for B-ADC and INA Register (address =
Register
0x092-0x093) [reset = Undefined]
0x094-0x095
Undefined
OADJ_B_INB
Offset Adjustment for B-ADC and INB Offset Adjustment for B-ADC and INB Register (address =
Register
0x094-0x095) [reset = Undefined]
0x096
Undefined
RESERVED
RESERVED
0x097
0x00
0SFILT0
Offset Filtering Control 0
Offset Filtering Control 0 Register (address = 0x097)
[reset = 0x00]
0x098
0x33
OSFILT1
Offset Filtering Control 1
Offset Filtering Control 1 Register (address = 0x098)
[reset = 0x33]
0x099-0x0FF
Undefined
RESERVED
Timing Adjustment for B-ADC, DualChannel Mode Register
Timing Adjust for B-ADC, Dual-Channel Mode Register
(address = 0x089) [reset = Undefined]
—
RESERVED
—
7.6.1.5.1 Input Mux Control Register (address = 0x060) [reset = 0x01]
Figure 86. Input Mux Control Register (INPUT_MUX)
7
6
RESERVED
R/W-000
5
4
DUAL_INPUT
R/W-0
3
2
RESERVED
R/W-00
1
0
SINGLE_INPUT
R/W-01
Table 43. INPUT_MUX Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
RESERVED
DUAL_INPUT
R/W
0
This bit selects inputs for dual-channel modes. If JMODE is
selecting a single-channel mode, this register has no effect.
0: A channel samples INA, B channel samples INB (no swap,
default)
1: A channel samples INB, B channel samples INA (swap)
3-2
RESERVED
R/W
00
RESERVED
1-0
SINGLE_INPUT
R/W
01
Thid field defines which input is sampled in single-channel
mode. If JMODE is not selecting a single-channel mode, this
register has no effect.
0: Reserved
1: INA is used (default)
2: INB is used
3: Reserved
4
74
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7.6.1.5.2 Calibration Enable Register (address = 0x061) [reset = 0x01]
Figure 87. Calibration Enable Register (CAL_EN)
7
6
5
4
RESERVED
R/W-0000 000
3
2
1
0
CAL_EN
R/W-1
Table 44. CAL_EN Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
CAL_EN
R/W
1
Calibration enable. Set this bit high to run calibration. Set this bit
low to hold the calibration in reset to program new calibration
settings. Clearing CAL_EN also resets the clock dividers that
clock the digital block and JESD204B interface.
Some calibration registers require clearing CAL_EN before
making any changes. All registers with this requirement contain
a note in their descriptions. After changing the registers, set
CAL_EN to re-run calibration with the new settings.
Always set CAL_EN before setting JESD_EN. Always clear
JESD_EN before clearing CAL_EN.
0
7.6.1.5.3 Calibration Configuration 0 Register (address = 0x062) [reset = 0x01]
Only change this register when CAL_EN is 0.
Figure 88. Calibration Configuration 0 Register (CAL_CFG0)
7
6
RESERVED
R/W-000
5
4
CAL_OSFILT
R/W-0
3
CAL_BGOS
R/W-0
2
CAL_OS
R/W-0
1
CAL_BG
R/W-0
0
CAL_FG
R/W-1
Table 45. CAL_CFG0 Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
0000
RESERVED
4
CAL_OSFILT
R/W
0
Enable offset filtering by setting this bit high.
3
CAL_BGOS
R/W
0
0 : Disables background offset calibration (default)
1: Enables background offset calibration (requires CAL_BG to
be set).
2
CAL_OS
R/W
0
0 : Disables foreground offset calibration (default)
1: Enables foreground offset calibration (requires CAL_FG to be
set)
1
CAL_BG
R/W
0
0 : Disables background calibration (default)
1: Enables background calibration
0
CAL_FG
R/W
1
0 : Resets calibration values, skips foreground calibration
1: Resets calibration values, then runs foreground calibration
(default)
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7.6.1.5.4 Calibration Status Register (address = 0x06A) [reset = Undefined]
Figure 89. Calibration Status Register (CAL_STATUS)
7
6
5
4
3
2
1
CAL_STOPPED
R
RESERVED
R
0
FG_DONE
R
Table 46. CAL_STATUS Field Descriptions
Bit
Field
Type
7-2
RESERVED
R
Reset
Description
RESERVED
1
CAL_STOPPED
R
This bit returns a 1 when the background calibration has
successfully stopped at the requested phase. This bit returns a 0
when calibration starts operating again. If background calibration
is disabled, this bit is set when foreground calibration is
completed or skipped.
0
FG_DONE
R
This bit is set high when the foreground calibration completes.
7.6.1.5.5 Calibration Pin Configuration Register (address = 0x06B) [reset = 0x00]
Figure 90. Calibration Pin Configuration Register (CAL_PIN_CFG)
7
6
5
RESERVED
R/W-0000 0
4
3
2
1
CAL_STATUS_SEL
R/W-00
0
CAL_TRIG_EN
R/W-0
Table 47. CAL_PIN_CFG Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R/W
0000 0
RESERVED
2-1
CAL_STATUS_SEL
R/W
00
0: CALSTAT output pin matches FG_DONE
1: RESERVED
2: CALSTAT output pin matches ALARM
3: CALSTAT output pin is always low
CAL_TRIG_EN
R/W
0
Choose the hardware or software trigger source with this bit.
0: Use the CAL_SOFT_TRIG register for the calibration trigger;
the CAL_TRIG input is disabled (ignored)
1: Use the CAL_TRIG input for the calibration trigger; the
CAL_SOFT_TRIG register is ignored
0
7.6.1.5.6 Calibration Software Trigger Register (address = 0x06C) [reset = 0x01]
Figure 91. Calibration Software Trigger Register (CAL_SOFT_TRIG)
7
6
5
4
RESERVED
R/W-0000 000
3
2
1
0
CAL_SOFT_TRIG
R/W-1
Table 48. CAL_SOFT_TRIG Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
CAL_SOFT_TRIG
R/W
1
CAL_SOFT_TRIG is a software bit to provide functionality of the
CAL_TRIG input. Program CAL_TRIG_EN = 0 to use
CAL_SOFT_TRIG for the calibration trigger. If no calibration
trigger is needed, leave CAL_TRIG_EN = 0 and
CAL_SOFT_TRIG = 1 (trigger is set high).
0
76
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7.6.1.5.7 Low-Power Background Calibration Register (address = 0x06E) [reset = 0x88]
Figure 92. Low-Power Background Calibration Register (CAL_LP)
7
6
LP_SLEEP_DLY
R/W-010
5
4
3
2
RESERVED
R/W-0
LP_WAKE_DLY
R/W-01
1
LP_TRIG
R/W-0
0
LP_EN
R/W-0
Table 49. CAL_LP Field Descriptions
Bit
Field
Type
Reset
Description
7-5
LP_SLEEP_DLY
R/W
010
Adjust how long an ADC sleeps before waking up for calibration
(only applies when LP_EN = 1 and LP_TRIG = 0). Values below
4 are not recommended because of limited overall power
reduction benefits.
0: Sleep delay = (23 + 1) × 256 × tDEVCLK
1: Sleep delay = (215 + 1) × 256 × tDEVCLK
2: Sleep delay = (218 + 1) × 256 × tDEVCLK
3: Sleep delay = (221 + 1) × 256 × tDEVCLK
4: Sleep delay = (224 + 1) × 256 × tDEVCLK : default is
approximately 1338 ms with a 3.2-GHz clock
5: Sleep delay = (227 + 1) × 256 × tDEVCLK
6: Sleep delay = (230 + 1) × 256 × tDEVCLK
7: Sleep delay = (233 + 1) × 256 × tDEVCLK
4-3
LP_WAKE_DLY
R/W
01
Adjust how much time is given up for settling before calibrating
an ADC after wake-up (only applies when LP_EN = 1). Values
lower than 1 are not recommended because there is insufficient
time for the core to stabilize before calibration begins.
0:Wake Delay = (23 + 1) × 256 × tDEVCLK
1: Wake Delay = (218 + 1) × 256 × tDEVCLK : default is
approximately 21 ms with a 3.2-GHz clock
2: Wake Delay = (221 + 1) × 256 × tDEVCLK
3: Wake Delay = (224 + 1) × 256 × tDEVCLK
2
RESERVED
R/W
0
RESERVED
1
LP_TRIG
R/W
0
0: ADC sleep duration is set by LP_SLEEP_DLY (autonomous
mode)
1: ADCs sleep until woken by a trigger; an ADC is awoken when
the calibration trigger (CAL_SOFT_TRIG bit or CAL_TRIG input)
is low
0
LP_EN
R/W
0
0: Disables low-power background calibration (default)
1: Enables low-power background calibration (only applies when
CAL_BG = 1)
7.6.1.5.8 Calibration Data Enable Register (address = 0x070) [reset = 0x00]
Figure 93. Calibration Data Enable Register (CAL_DATA_EN)
7
6
5
4
RESERVED
R/W-0000 000
3
2
1
0
CAL_DATA_EN
R/W-0
Table 50. CAL_DATA_EN Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
CAL_DATA_EN
R/W
0
Set this bit to enable the CAL_DATA register to enable reading
and writing of calibration data; see the calibration data register
for more information.
0
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7.6.1.5.9 Calibration Data Register (address = 0x071) [reset = Undefined]
Figure 94. Calibration Data Register (CAL_DATA)
7
6
5
4
3
2
1
0
CAL_DATA
R/W
Table 51. CAL_DATA Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CAL_DATA
R/W
Undefined
After setting CAL_DATA_EN, repeated reads of this register
return all calibration values for the ADCs. Repeated writes of this
register input all calibration values for the ADCs. To read the
calibration data, read the register 673 times. To write the vector,
write the register 673 times with previously stored calibration
data.
To speed up the read/write operation, set ADDR_HOLD = 1 and
use the streaming read or write process.
Accessing the CAL_DATA register when CAL_STOPPED = 0
corrupts the calibration. Also, stopping the process before
reading or writing 673 times leaved the calibration data in an
invalid state.
7.6.1.5.10 Channel A Gain Trim Register (address = 0x07A) [reset = Undefined]
Figure 95. Channel A Gain Trim Register (GAIN_TRIM_A)
7
6
5
4
3
2
1
0
GAIN_TRIM_A
R/W
Table 52. GAIN_TRIM_A Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GAIN_TRIM_A
R/W
Undefined
This register enables gain trim of channel A. After reset, the
factory-trimmed value can be read and adjusted as required.
7.6.1.5.11 Channel B Gain Trim Register (address = 0x07B) [reset = Undefined]
Figure 96. Channel B Gain Trim Register (GAIN_TRIM_B)
7
6
5
4
3
2
1
0
GAIN_TRIM_B
R/W
Table 53. GAIN_TRIM_B Field Descriptions
78
Bit
Field
Type
Reset
Description
7-0
GAIN_TRIM_B
R/W
Undefined
This register enables gain trim of channel B. After reset, the
factory-trimmed value can be read and adjusted as required.
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7.6.1.5.12 Band-Gap Reference Trim Register (address = 0x07C) [reset = Undefined]
Figure 97. Band-Gap Reference Trim Register (BG_TRIM)
7
6
5
4
3
2
1
RESERVED
R/W-0000
0
BG_TRIM
R/W
Table 54. BG_TRIM Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
RESERVED
3-0
BG_TRIM
R/W
Undefined
This register enables the internal band-gap reference to be
trimmed. After reset, the factory-trimmed value can be read and
adjusted as required.
7.6.1.5.13 VINA Input Resistor Trim Register (address = 0x07E) [reset = Undefined]
Figure 98. VINA Input Resistor Trim Register (RTRIM_A)
7
6
5
4
3
2
1
0
RTRIM
R/W
Table 55. RTRIM_A Field Descriptions
Bit
Field
Type
Reset
Description
7-0
RTRIM_A
R/W
Undefined
This register controls the VINA ADC input termination trim. After
reset, the factory-trimmed value can be read and adjusted as
required.
7.6.1.5.14 VINB Input Resistor Trim Register (address = 0x07F) [reset = Undefined]
Figure 99. VINB Input Resistor Trim Register (RTRIM_B)
7
6
5
4
3
2
1
0
RTRIM
R/W
Table 56. RTRIM_B Field Descriptions
Bit
Field
Type
Reset
Description
7-0
RTRIM_B
R/W
Undefined
This register controls the VINB ADC input termination trim. After
reset, the factory-trimmed value can be read and adjusted as
required.
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7.6.1.5.15 Timing Adjust for A-ADC, Single-Channel Mode, Foreground Calibration Register (address = 0x080) [reset
= Undefined]
Figure 100. Register (TADJ_A_FG90)
7
6
5
4
3
2
1
0
TADJ_A_FG90
R/W
Table 57. TADJ_A_FG90 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_A_FG90
R/W
Undefined
This register (and other subsequent TADJ* registers) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factorytrimmed value can be read and adjusted as required.
7.6.1.5.16 Timing Adjust for B-ADC, Single-Channel Mode, Foreground Calibration Register (address = 0x081) [reset
= Undefined]
Figure 101. Register (TADJ_B_FG0)
7
6
5
4
3
2
1
0
TADJ_B_FG0
R/W
Table 58. TADJ_B_FG0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_B_FG0
R/W
Undefined
This register (and other subsequent TADJ* registers) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factorytrimmed value can be read and adjusted as required.
7.6.1.5.17 Timing Adjust for A-ADC, Single-Channel Mode, Background Calibration Register (address = 0x082)
[reset = Undefined]
Figure 102. Register (TADJ_A_BG90)
7
6
5
4
3
2
1
0
TADJ_A_BG90
R/W
Table 59. TADJ_B_FG0 Field Descriptions
80
Bit
Field
Type
Reset
Description
7-0
TADJ_A_BG90
R/W
Undefined
This register (and other subsequent TADJ* registers) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factorytrimmed value can be read and adjusted as required.
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7.6.1.5.18 Timing Adjust for C-ADC, Single-Channel Mode, Background Calibration Register (address = 0x083)
[reset = Undefined]
Figure 103. Timing Adjust for C-ADC, Single-Channel Mode, Background Calibration Register
(TADJ_C_BG0)
7
6
5
4
3
2
1
0
TADJ_C_BG0
R/W
Table 60. TADJ_B_FG0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_C_BG0
R/W
Undefined
This register (and other subsequent TADJ* registers) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factorytrimmed value can be read and adjusted as required.
7.6.1.5.19 Timing Adjust for C-ADC, Single-Channel Mode, Background Calibration Register (address = 0x084)
[reset = Undefined]
Figure 104. Timing Adjust for C-ADC, Single-Channel Mode, Background Calibration Register
(TADJ_C_BG90)
7
6
5
4
3
2
1
0
TADJ_C_BG90
R/W
Table 61. TADJ_B_FG0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_C_BG90
R/W
Undefined
This register (and other subsequent TADJ* registers) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factorytrimmed value can be read and adjusted as required.
7.6.1.5.20 Timing Adjust for B-ADC, Single-Channel Mode, Background Calibration Register (address = 0x085)
[reset = Undefined]
Figure 105. Timing Adjust for B-ADC, Single-Channel Mode, Background Calibration Register
(TADJ_B_BG0)
7
6
5
4
3
2
1
0
TADJ_B_BG0
R/W
Table 62. TADJ_B_FG0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_B_BG0
R/W
Undefined
This register (and other subsequent TADJ* registers) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factorytrimmed value can be read and adjusted as required.
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7.6.1.5.21 Timing Adjust for A-ADC, Dual-Channel Mode Register (address = 0x086) [reset = Undefined]
Figure 106. Timing Adjust for A-ADC, Dual-Channel Mode Register (TADJ_A)
7
6
5
4
3
2
1
0
TADJ_A
R/W
Table 63. TADJ_A Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_A
R/W
Undefined
This register (and other subsequent TADJ* registers) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factorytrimmed value can be read and adjusted as required.
7.6.1.5.22 Timing Adjust for C-ADC Acting for A-ADC, Dual-Channel Mode Register (address = 0x087) [reset =
Undefined]
Figure 107. Timing Adjust for C-ADC Acting for A-ADC, Dual-Channel Mode Register (TADJ_CA)
7
6
5
4
3
2
1
0
TADJ_CA
R/W
Table 64. TADJ_CA Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_CA
R/W
Undefined
This register (and other subsequent TADJ* registers) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factorytrimmed value can be read and adjusted as required.
7.6.1.5.23 Timing Adjust for C-ADC Acting for B-ADC, Dual-Channel Mode Register (address = 0x088) [reset =
Undefined]
Figure 108. Timing Adjust for C-ADC Acting for B-ADC, Dual-Channel Mode Register (TADJ_CB)
7
6
5
4
3
2
1
0
TADJ_CB
R/W
Table 65. TADJ_CB Field Descriptions
82
Bit
Field
Type
Reset
Description
7-0
TADJ_CB
R/W
Undefined
This register (and other subsequent TADJ* registers) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factorytrimmed value can be read and adjusted as required.
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7.6.1.5.24 Timing Adjust for B-ADC, Dual-Channel Mode Register (address = 0x089) [reset = Undefined]
Figure 109. Timing Adjust for B-ADC, Dual-Channel Mode Register (TADJ_B)
7
6
5
4
3
2
1
0
TADJ_B
R/W
Table 66. TADJ_B Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_B
R/W
Undefined
This register (and other subsequent TADJ* registers) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factorytrimmed value can be read and adjusted as required.
7.6.1.5.25 Offset Adjustment for A-ADC and INA Register (address = 0x08A-0x08B) [reset = Undefined]
Figure 110. Offset Adjustment for A-ADC and INA Register (OADJ_A_INA)
15
14
13
12
11
5
4
3
OADJ_A_INA[7:0]
R/W
RESERVED
R/W-0000
7
6
10
9
OADJ_A_INA[11:8]
R/W
2
1
8
0
Table 67. OADJ_A_INA Field Descriptions
Field
Type
Reset
Description
15-12
Bit
RESERVED
R/W
0000
RESERVED
11-0
OADJ_A_INA
R/W
Undefined
Offset adjustment value for ADC0 (A-ADC) applied when ADC0
samples INA. The format is unsigned. After reset, the factorytrimmed value can be read and adjusted as required.
Important notes:
•
Never write OADJ* registers while foreground calibration is
underway
•
Never write OADJ* registers if CAL_BG and CAL_BGOS
are set
•
If CAL_OS = 1 and CAL_BGOS = 0, only read OADJ*
registers if FG_DONE = 1
•
If CAL_BG = 1 and CAL_BGOS = 1, only read OADJ*
register if CAL_STOPPED = 1
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7.6.1.5.26 Offset Adjustment for A-ADC and INB Register (address = 0x08C-0x08D) [reset = Undefined]
Figure 111. Offset Adjustment for A-ADC and INB Register (OADJ_A_INB)
15
14
13
12
11
5
4
3
OADJ_A_INB[7:0]
R/W
RESERVED
R/W-0000
7
6
10
9
OADJ_A_INB[11:8]
R/W
2
1
8
0
Table 68. OADJ_A_INB Field Descriptions
Field
Type
Reset
Description
15-12
Bit
RESERVED
R/W
0000
RESERVED
11-0
OADJ_A_INB
R/W
Undefined
Offset adjustment value for ADC0 (A-ADC) applied when ADC0
samples INB. The format is unsigned. After reset, the factorytrimmed value can be read and adjusted as required.
Important notes:
•
Never write OADJ* registers while foreground calibration is
underway
•
Never write OADJ* registers if CAL_BG and CAL_BGOS
are set
•
If CAL_OS = 1 and CAL_BGOS = 0, only read OADJ*
registers if FG_DONE = 1
•
If CAL_BG = 1 and CAL_BGOS = 1, only read OADJ*
register if CAL_STOPPED = 1
7.6.1.5.27 Offset Adjustment for C-ADC and INA Register (address = 0x08E-0x08F) [reset = Undefined]
Figure 112. Offset Adjustment for C-ADC and INA Register (OADJ_C_INA)
15
14
13
12
11
5
4
3
OADJ_C_INA[7:0]
R/W
RESERVED
R/W-0000
7
6
10
9
OADJ_C_INA[11:8]
R/W
2
1
8
0
Table 69. OADJ_C_INA Field Descriptions
Bit
84
Field
Type
Reset
Description
15-12
RESERVED
R/W
0000
RESERVED
11-0
OADJ_C_INA
R/W
Undefined
Offset adjustment value for ADC1 (A-ADC) applied when ADC1
samples INA. The format is unsigned. After reset, the factorytrimmed value can be read and adjusted as required.
Important notes:
•
Never write OADJ* registers while foreground calibration is
underway
•
Never write OADJ* registers if CAL_BG and CAL_BGOS
are set
•
If CAL_OS = 1 and CAL_BGOS = 0, only read OADJ*
registers if FG_DONE = 1
•
If CAL_BG = 1 and CAL_BGOS = 1, only read OADJ*
register if CAL_STOPPED = 1
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7.6.1.5.28 Offset Adjustment for C-ADC and INB Register (address = 0x090-0x091) [reset = Undefined]
Figure 113. Offset Adjustment for C-ADC and INB Register (OADJ_C_INB)
15
14
13
12
11
5
4
3
OADJ_C_INB[7:0]
R/W
RESERVED
R/W-0000
7
6
10
9
OADJ_C_INB[11:8]
R/W
2
1
8
0
Table 70. OADJ_C_INB Field Descriptions
Field
Type
Reset
Description
15-12
Bit
RESERVED
R/W
0000
RESERVED
11-0
OADJ_C_INB
R/W
Undefined
Offset adjustment value for ADC1 (A-ADC) applied when ADC1
samples INB. The format is unsigned. After reset, the factorytrimmed value can be read and adjusted as required.
Important notes:
•
Never write OADJ* registers while foreground calibration is
underway
•
Never write OADJ* registers if CAL_BG and CAL_BGOS
are set
•
If CAL_OS = 1 and CAL_BGOS = 0, only read OADJ*
registers if FG_DONE = 1
•
If CAL_BG = 1 and CAL_BGOS = 1, only read OADJ*
register if CAL_STOPPED = 1
7.6.1.5.29 Offset Adjustment for B-ADC and INA Register (address = 0x092-0x093) [reset = Undefined]
Figure 114. Offset Adjustment for B-ADC and INA Register (OADJ_B_INA)
15
14
13
12
11
5
4
3
OADJ_B_INA[7:0]
R/W
RESERVED
R/W-0000
7
6
10
9
OADJ_B_INA[11:8]
R/W
2
1
8
0
Table 71. OADJ_B_INA Field Descriptions
Bit
Field
Type
Reset
Description
15-12
RESERVED
R/W
0000
RESERVED
11-0
OADJ_B_INA
R/W
Undefined
Offset adjustment value for ADC2 (B-ADC) applied when ADC2
samples INA. The format is unsigned. After reset, the factorytrimmed value can be read and adjusted as required.
Important notes:
•
Never write OADJ* registers while foreground calibration is
underway
•
Never write OADJ* registers if CAL_BG and CAL_BGOS
are set
•
If CAL_OS = 1 and CAL_BGOS = 0, only read OADJ*
registers if FG_DONE = 1
•
If CAL_BG = 1 and CAL_BGOS = 1, only read OADJ*
register if CAL_STOPPED = 1
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7.6.1.5.30 Offset Adjustment for B-ADC and INB Register (address = 0x094-0x095) [reset = Undefined]
Figure 115. Offset Adjustment for B-ADC and INB Register (OADJ_B_INB)
15
14
13
12
11
5
4
3
OADJ_B_INB[7:0]
R/W
10
9
OADJ_B_INB[11:8]
R/W
2
1
RESERVED
R/W-0000
7
6
8
0
Table 72. OADJ_B_INB Field Descriptions
Field
Type
Reset
Description
15-12
Bit
RESERVED
R/W
0000
RESERVED
11-0
OADJ_B_INB
R/W
Undefined
Offset adjustment value for ADC2 (B-ADC) applied when ADC2
samples INB. The format is unsigned. After reset, the factorytrimmed value can be read and adjusted as required.
Important notes:
•
Never write OADJ* registers while foreground calibration is
underway
•
Never write OADJ* registers if CAL_BG and CAL_BGOS
are set
•
If CAL_OS = 1 and CAL_BGOS=0, only read OADJ*
registers if FG_DONE = 1
•
If CAL_BG = 1 and CAL_BGOS=1, only read OADJ*
register if CAL_STOPPED = 1
7.6.1.5.31 Offset Filtering Control 0 Register (address = 0x097) [reset = 0x00]
Figure 116. Offset Filtering Control 0 Register (OSFILT0)
7
6
5
4
RESERVED
R/W-0000 000
3
2
1
0
DC_RESTORE
R/W
Table 73. OSFILT0 Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
DC_RESTORE
R/W
0
When set, the offset filtering feature (enabled by CAL_OSFILT)
filters only the offset mismatch across ADC banks and does not
remove the frequency content near DC. When cleared, the
feature filters all offsets from all banks, thus filtering all DC
content in the signal; see the Offset Filtering section.
0
86
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7.6.1.5.32 Offset Filtering Control 1 Register (address = 0x098) [reset = 0x33]
Figure 117. Offset Filtering Control 1 Register (OSFILT1)
7
6
5
4
3
OSFILT_BW
R/W-0011
2
1
0
OSFILT_SOAK
R/W-0011
Table 74. OSFILT1 Field Descriptions
Bit
Field
Type
Reset
Description
7-4
OSFILT_BW
R/W
0011
This field adjusts the IIR filter bandwidth for the offset filtering
feature (enabled by CAL_OSFILT). More bandwidth suppresses
more flicker noise from the ADCs and reduces the offset spurs.
Less bandwidth minimizes the impact of the filters on the
mission mode signal.
OSFILT_BW: IIR coefficient: –3-dB bandwidth (single sided)
0: Reserved
1: 2-10 : 609e-9 × FDEVCLK
2: 2-11 : 305e-9 × FDEVCLK
3: 2-12 : 152e-9 × FDEVCLK
4: 2-13 : 76e-9 × FDEVCLK
5: 2-14 : 38e-9 × FDEVCLK
6-15: Reserved
3-0
OSFILT_SOAK
R/W
0011
This field adjusts the IIR soak time for the offset filtering feature.
This field applies when offset filtering and background calibration
are both enabled. This field determines how long the IIR filter is
allowed to settle when first connected to an ADC after the ADC
is calibrated. After the soak time completes, the ADC is placed
online using the IIR filter. Set OSFILT_SOAK = OSFILT_BW.
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7.6.1.6 ADC Bank Registers (0x100 to 0x15F)
Table 75. ADC Bank Registers
ADDRESS
RESET
ACRONYM
0x100-0x101
Undefined
RESERVED
RESERVED
REGISTER NAME
0x102
Undefined
B0_TIME_0
Timing Adjustment for Bank 0 (0°
Clock) Register
0x103
Undefined
B0_TIME_90
Timing Adjustment for Bank 0 (–90°
Clock) Register
0x104-0x111
Undefined
RESERVED
RESERVED
0x112
Undefined
B1_TIME_0
Timing Adjustment for Bank 1 (0°
Clock) Register
0x113
Undefined
B1_TIME_90
Timing Adjustment for Bank 1 (–90°
Clock) Register
0x114-0x121
Undefined
RESERVED
RESERVED
0x122
Undefined
B2_TIME_0
Timing Adjustment for Bank 2 (0°
Clock) Register
0x123
Undefined
B2_TIME_90
Timing Adjustment for Bank 2 (–90°
Clock) Register
0x124-0x131
Undefined
RESERVED
RESERVED
0x132
Undefined
B3_TIME_0
Timing Adjustment for Bank 3 (0°
Clock) Register
0x133
Undefined
B3_TIME_90
Timing Adjustment for Bank 3 (–90°
Clock) Register
0x134-0x141
Undefined
RESERVED
RESERVED
0x142
Undefined
B4_TIME_0
Timing Adjustment for Bank 4 (0°
Clock) Register
0x143
Undefined
B4_TIME_90
Timing Adjustment for Bank 4 (–90°
Clock) Register
0x144-0x151
Undefined
RESERVED
RESERVED
0x152
Undefined
B5_TIME_0
Timing Adjustment for Bank 5 (0°
Clock) Register
0x153
Undefined
B5_TIME_90
Timing Adjustment for Bank 5 (–90°
Clock) Register
0x154-0x15F
Undefined
RESERVED
RESERVED
SECTION
—
Timing Adjustment for Bank 0 (0° Clock) Register
(address = 0x102) [reset = Undefined]
Timing Adjustment for Bank 0 (–90° Clock) Register
(address = 0x103) [reset = Undefined]
—
Timing Adjustment for Bank 1 (0° Clock) Register
(address = 0x112) [reset = Undefined]
Timing Adjustment for Bank 1 (–90° Clock) Register
(address = 0x113) [reset = Undefined]
—
Timing Adjustment for Bank 2 (0° Clock) Register
(address = 0x122) [reset = Undefined]
Timing Adjustment for Bank 2 (–90° Clock) Register
(address = 0x123) [reset = Undefined]
—
Timing Adjustment for Bank 3 (0° Clock) Register
(address = 0x132) [reset = Undefined]
Timing Adjustment for Bank 3 (–90° Clock) Register
(address = 0x133) [reset = Undefined]
—
Timing Adjustment for Bank 4 (0° Clock) Register
(address = 0x142) [reset = Undefined]
Timing Adjustment for Bank 4 (–90° Clock) Register
(address = 0x143) [reset = Undefined]
—
Timing Adjustment for Bank 5 (0° Clock) Register
(address = 0x152) [reset = Undefined]
Timing Adjustment for Bank 5 (–90° Clock) Register
(address = 0x153) [reset = Undefined]
—
7.6.1.6.1 Timing Adjustment for Bank 0 (0° Clock) Register (address = 0x102) [reset = Undefined]
Figure 118. Timing Adjustment for Bank 0 (0° Clock) Register (B0_TIME_0)
7
6
5
4
3
2
1
0
B0_TIME_0
R/W
Table 76. B0_TIME_0 Field Descriptions
88
Bit
Field
Type
Reset
Description
7-0
B0_TIME_0
R/W
Undefined
Time adjustment for bank 0 (applied when the ADC is configured
for 0° clock phase). After reset, the factory-trimmed value can be
read and adjusted as required.
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7.6.1.6.2 Timing Adjustment for Bank 0 (–90° Clock) Register (address = 0x103) [reset = Undefined]
Figure 119. Timing Adjustment for Bank 0 (–90° Clock) Register (B0_TIME_90)
7
6
5
4
3
2
1
0
B0_TIME_90
R/W
Table 77. B0_TIME_90 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B0_TIME_90
R/W
Undefined
Time adjustment for bank 0 (applied when the ADC is configured
for –90° clock phase). After reset, the factory-trimmed value can
be read and adjusted as required.
7.6.1.6.3 Timing Adjustment for Bank 1 (0° Clock) Register (address = 0x112) [reset = Undefined]
Figure 120. Timing Adjustment for Bank 1 (0° Clock) Register (B1_TIME_0)
7
6
5
4
3
2
1
0
B1_TIME_0
R/W
Table 78. B1_TIME_0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B1_TIME_0
R/W
Undefined
Time adjustment for bank 1 (applied when the ADC is configured
for 0° clock phase). After reset, the factory-trimmed value can be
read and adjusted as required.
7.6.1.6.4 Timing Adjustment for Bank 1 (–90° Clock) Register (address = 0x113) [reset = Undefined]
Figure 121. Timing Adjustment for Bank 1 (–90° Clock) Register (B1_TIME_90)
7
6
5
4
3
2
1
0
B1_TIME_90
R/W
Table 79. B1_TIME_90 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B1_TIME_90
R/W
Undefined
Time adjustment for bank 1 (applied when the ADC is configured
for –90° clock phase). After reset, the factory-trimmed value can
be read and adjusted as required.
7.6.1.6.5 Timing Adjustment for Bank 2 (0° Clock) Register (address = 0x122) [reset = Undefined]
Figure 122. Timing Adjustment for Bank 2 (0° Clock) Register (B2_TIME_0)
7
6
5
4
3
2
1
0
B2_TIME_0
R/W
Table 80. B2_TIME_0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B2_TIME_0
R/W
Undefined
Time adjustment for bank 2 (applied when the ADC is configured
for 0° clock phase). After reset, the factory-trimmed value can be
read and adjusted as required.
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7.6.1.6.6 Timing Adjustment for Bank 2 (–90° Clock) Register (address = 0x123) [reset = Undefined]
Figure 123. Timing Adjustment for Bank 2 (–90° Clock) Register (B2_TIME_90)
7
6
5
4
3
2
1
0
B2_TIME_90
R/W
Table 81. B2_TIME_90 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B2_TIME_90
R/W
Undefined
Time adjustment for bank 2 (applied when the ADC is configured
for –90° clock phase). After reset, the factory-trimmed value can
be read and adjusted as required.
7.6.1.6.7 Timing Adjustment for Bank 3 (0° Clock) Register (address = 0x132) [reset = Undefined]
Figure 124. Timing Adjustment for Bank 3 (0° Clock) Register (B3_TIME_0)
7
6
5
4
3
2
1
0
B3_TIME_0
R/W
Table 82. B3_TIME_0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B3_TIME_0
R/W
Undefined
Time adjustment for bank 3 (applied when the ADC is configured
for 0° clock phase). After reset, the factory-trimmed value can be
read and adjusted as required.
7.6.1.6.8 Timing Adjustment for Bank 3 (–90° Clock) Register (address = 0x133) [reset = Undefined]
Figure 125. Timing Adjustment for Bank 3 (–90° Clock) Register (B3_TIME_90)
7
6
5
4
3
2
1
0
B3_TIME_90
R/W
Table 83. B3_TIME_90 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B3_TIME_90
R/W
Undefined
Time adjustment for bank 3 (applied when the ADC is configured
for –90° clock phase). After reset, the factory-trimmed value can
be read and adjusted as required.
7.6.1.6.9 Timing Adjustment for Bank 4 (0° Clock) Register (address = 0x142) [reset = Undefined]
Figure 126. Timing Adjustment for Bank 4 (0° Clock) Register (B4_TIME_0)
7
6
5
4
3
2
1
0
B4_TIME_0
R/W
Table 84. B4_TIME_0 Field Descriptions
90
Bit
Field
Type
Reset
Description
7-0
B4_TIME_0
R/W
Undefined
Time adjustment for bank 4 (applied when the ADC is configured
for 0° clock phase). After reset, the factory-trimmed value can be
read and adjusted as required.
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7.6.1.6.10 Timing Adjustment for Bank 4 (–90° Clock) Register (address = 0x143) [reset = Undefined]
Figure 127. Timing Adjustment for Bank 4 (–90° Clock) Register (B4_TIME_90)
7
6
5
4
3
2
1
0
B4_TIME_90
R/W
Table 85. B4_TIME_90 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B4_TIME_90
R/W
Undefined
Time adjustment for bank 4 (applied when the ADC is configured
for –90° clock phase). After reset, the factory-trimmed value can
be read and adjusted as required.
7.6.1.6.11 Timing Adjustment for Bank 5 (0° Clock) Register (address = 0x152) [reset = Undefined]
Figure 128. Timing Adjustment for Bank 5 (0° Clock) Register (B5_TIME_0)
7
6
5
4
3
2
1
0
B5_TIME_0
R/W
Table 86. B5_TIME_0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B5_TIME_0
R/W
Undefined
Time adjustment for bank 5 (applied when the ADC is configured
for 0° clock phase). After reset, the factory-trimmed value can be
read and adjusted as required.
7.6.1.6.12 Timing Adjustment for Bank 5 (–90° Clock) Register (address = 0x153) [reset = Undefined]
Figure 129. Timing Adjustment for Bank 5 (–90° Clock) Register (B5_TIME_90)
7
6
5
4
3
2
1
0
B5_TIME_90
R/W
Table 87. B5_TIME_90 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B5_TIME_90
R/W
Undefined
Time adjustment for bank 5 (applied when the ADC is configured
for –90° clock phase). After reset, the factory-trimmed value can
be read and adjusted as required.
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7.6.1.7 LSB Control Registers (0x160 to 0x1FF)
Table 88. LSB Control Registers
ADDRESS
RESET
ACRONYM
0x160
0x00
ENC_LSB
0x161-0x1FF
Undefined
RESERVED
REGISTER NAME
SECTION
LSB Control Bit Output Register
LSB Control Bit Output Register (address = 0x160) [reset
= 0x00]
RESERVED
—
7.6.1.7.1 LSB Control Bit Output Register (address = 0x160) [reset = 0x00]
Figure 130. LSB Control Bit Output Register (ENC_LSB)
7
6
5
4
RESERVED
R/W-0000 000
3
2
1
0
TIMESTAMP_EN
R/W-0
Table 89. ENC_LSB Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
TIMESTAMP_EN
R/W
0
When set, the transport layer transmits the timestamp signal on
the LSB of the output samples. TIMESTAMP_EN has priority
over CAL_STATE_EN. TMSTP_RECV_EN must also be set
high when using timestamp. The latency of the timestamp signal
(through the entire device) matches the latency of the analog
ADC inputs.
The control bit enabled by this register is never advertised in the
ILA (the CS field is 0 in the ILA).
0
92
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7.6.1.8 JESD204B Registers (0x200 to 0x20F)
Table 90. JESD204B Registers
ADDRESS
RESET
ACRONYM
0x200
0x01
JESD_EN
0x201
0x02
JMODE
0x202
0x1F
KM1
0x203
0x01
JSYNC_N
0x204
0x02
0x205
REGISTER NAME
JESD204B Enable Register
SECTION
JESD204B Enable Register (address = 0x200) [reset =
0x01]
JESD204B Mode Register
JESD204B Mode Register (address = 0x201) [reset =
0x02]
JESD204B K Parameter Register
JESD204B K Parameter Register (address = 0x202)
[reset = 0x1F]
JESD204B Manual SYNC Request
Register
JESD204B Manual SYNC Request Register (address =
0x203) [reset = 0x01]
JCTRL
JESD204B Control Register
JESD204B Control Register (address = 0x204) [reset =
0x02]
0x00
JTEST
JESD204B Test Pattern Control
Register
0x206
0x00
DID
0x207
0x00
FCHAR
0x208
Undefined
JESD_STATUS
0x209
0x00
PD_CH
0x20A
0x00
JEXTRA_A
JESD204B Extra Lane Enable (Link
A)
JESD204B Extra Lane Enable (Link A) Register (address
= 0x20A) [reset = 0x00]
0x20B
0x00
JEXTRA_B
JESD204B Extra Lane Enable (Link
B)
JESD204B Extra Lane Enable (Link B) Register (address
= 0x20B) [reset = 0x00]
0x20C-0x210
Undefined
RESERVED
RESERVED
JESD204B DID Parameter Register
JESD204B Frame Character
Register
JESD204B Test Pattern Control Register (address =
0x205) [reset = 0x00]
JESD204B DID Parameter Register (address = 0x206)
[reset = 0x00]
JESD204B Frame Character Register (address = 0x207)
[reset = 0x00]
JESD204B, System Status Register
JESD204B, System Status Register (address = 0x208)
[reset = Undefined]
JESD204B Channel Power-Down
JESD204B Channel Power-Down Register (address =
0x209) [reset = 0x00]
—
7.6.1.8.1 JESD204B Enable Register (address = 0x200) [reset = 0x01]
Figure 131. JESD204B Enable Register (JESD_EN)
7
6
5
4
RESERVED
R/W-0000 000
3
2
1
0
JESD_EN
R/W-1
Table 91. JESD_EN Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
JESD_EN
R/W
1
0 : Disables JESD204B interface
1 : Enables JESD204B interface
Before altering other JESD204B registers, JESD_EN must be
cleared. When JESD_EN is 0, the block is held in reset and the
serializers are powered down. The clocks are gated off to save
power. The LMFC counter is also held in reset, so SYSREF
does not align the LMFC.
Always set CAL_EN before setting JESD_EN.
Always clear JESD_EN before clearing CAL_EN.
0
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7.6.1.8.2 JESD204B Mode Register (address = 0x201) [reset = 0x02]
Figure 132. JESD204B Mode Register (JMODE)
7
6
RESERVED
R/W-000
5
4
3
2
JMODE
R/W-0001 0
1
0
Table 92. JMODE Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
RESERVED
4-0
JMODE
R/W
0001 0
Specify the JESD204B output mode.
Only change this register when JESD_EN = 0 and CAL_EN = 0.
7.6.1.8.3 JESD204B K Parameter Register (address = 0x202) [reset = 0x1F]
Figure 133. JESD204B K Parameter Register (KM1)
7
6
RESERVED
R/W-000
5
4
3
2
KM1
R/W-1111 1
1
0
Table 93. KM1 Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
RESERVED
4-0
KM1
R/W
1111 1
K is the number of frames per multiframe and this register must
be programmed as K-1. Depending on the JMODE setting, there
are constraints on the legal values of K. (default: KM1 = 31, K =
32).
Only change this register when JESD_EN is 0.
7.6.1.8.4 JESD204B Manual SYNC Request Register (address = 0x203) [reset = 0x01]
Figure 134. JESD204B Manual SYNC Request Register (JSYNC_N)
7
6
5
4
RESERVED
R/W-0000 000
3
2
1
0
JSYNC_N
R/W-1
Table 94. JSYNC_N Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
JSYNC_N
R/W
1
Set this bit to 0 to request JESD204B synchronization
(equivalent to the SYNCSE pin being asserted). For normal
operation, leave this bit set to 1.
The JSYNC_N register can always generate a synchronization
request, regardless of the SYNC_SEL register. However, if the
selected sync pin is stuck low, the synchronization request
cannot be de-asserted unless SYNC_SEL = 2 is programmed.
0
94
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7.6.1.8.5 JESD204B Control Register (address = 0x204) [reset = 0x02]
Figure 135. JESD204B Control Register (JCTRL)
7
6
5
4
3
RESERVED
R/W-0000
2
1
SFORMAT
R/W-1
SYNC_SEL
R/W-00
0
SCR
R/W-0
Table 95. JCTRL Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
RESERVED
3-2
SYNC_SEL
R/W
00
0: Use the SYNCSE input for the SYNC~ function (default)
1: Use the TMSTP± differential input for the SYNC~ function;
TMSTP_RECV_EN must also be set
2: Do not use any sync input signal (use software SYNC~
through JSYNC_N)
1
SFORMAT
R/W
1
Output sample format for JESD204B samples.
0: Offset binary
1: Signed 2’s complement (default)
0
SCR
R/W
0
0: Scrambler disabled (default)
1: Scrambler enabled
Only change this register when JESD_EN is 0.
7.6.1.8.6 JESD204B Test Pattern Control Register (address = 0x205) [reset = 0x00]
Figure 136. JESD204B Test Pattern Control Register (JTEST)
7
6
5
4
3
RESERVED
R/W-0000
2
1
0
JTEST
R/W-0000
Table 96. JTEST Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
RESERVED
3-0
JTEST
R/W
0000
0: Test mode disabled; normal operation (default)
1: PRBS7 test mode
2: PRBS15 test mode
3: PRBS23 test mode
4: Ramp test mode
5: Transport layer test mode
6: D21.5 test mode
7: K28.5 test mode
8: Repeated ILA test mode
9: Modified RPAT test mode
10: Serial outputs held low
11: Serial outputs held high
12–15: Reserved
Only change this register when JESD_EN is 0.
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7.6.1.8.7 JESD204B DID Parameter Register (address = 0x206) [reset = 0x00]
Figure 137. JESD204B DID Parameter Register (DID)
7
6
5
4
3
2
1
0
DID
R/W-0000 0000
Table 97. DID Field Descriptions
Bit
Field
Type
Reset
7-0
DID
R/W
0000 0000 Specifies the device ID (DID) value that is transmitted during the
second multiframe of the JESD204B ILA. Link A transmits DID,
and link B transmits DID+1. Bit 0 is ignored and always returns 0
(if an odd number is programmed, that number is decremented
to an even number).
Only change this register when JESD_EN is 0.
Description
7.6.1.8.8 JESD204B Frame Character Register (address = 0x207) [reset = 0x00]
Figure 138. JESD204B Frame Character Register (FCHAR)
7
6
5
4
3
RESERVED
R/W-0000 00
2
1
0
FCHAR
R/W-00
Table 98. FCHAR Field Descriptions
96
Bit
Field
Type
Reset
Description
7-2
RESERVED
R/W
0000 00
RESERVED
1-0
FCHAR
R/W
00
Specify which comma character is used to denote end-of-frame.
This character is transmitted opportunistically (see the Frame
and Multiframe Monitoring section).
0: Use K28.7 (default, JESD204B compliant)
1: Use K28.1 (not JESD204B compliant)
2: Use K28.5 (not JESD204B compliant)
3: Reserved
When using a JESD204B receiver, always use FCHAR = 0.
When using a general-purpose 8b, 10b receiver, the K28.7
character may cause issues. When K28.7 is combined with
certain data characters, a false, misaligned comma character
can result, and some receivers realign to the false comma. To
avoid this condition, program FCHAR to 1 or 2.
Only change this register when JESD_EN is 0.
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7.6.1.8.9 JESD204B, System Status Register (address = 0x208) [reset = Undefined]
Figure 139. JESD204B, System Status Register (JESD_STATUS)
7
RESERVED
R
6
LINK_UP
R
5
SYNC_STATUS
R
4
REALIGNED
R/W
3
ALIGNED
R/W
2
PLL_LOCKED
R
1
0
RESERVED
R
Table 99. JESD_STATUS Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R
Undefined
RESERVED
6
LINK_UP
R
Undefined
When set, this bit indicates that the JESD204B link is up.
5
SYNC_STATUS
R
Undefined
Returns the state of the JESD204B SYNC~ signal.
0: SYNC~ asserted
1: SYNC~ de-asserted
4
REALIGNED
R/W
Undefined
When high, this bit indicates that an internal digital clock, frame
clock, or multiframe (LMFC) clock phase was realigned by
SYSREF. Write a 1 to clear this bit.
3
ALIGNED
R/W
Undefined
When high, this bit indicates that the multiframe (LMFC) clock
phase has been established by SYSREF. The first SYSREF
event after enabling the JESD204B encoder will set this bit.
Write a 1 to clear this bit.
2
PLL_LOCKED
R
Undefined
When high, this bit indicates that the PLL is locked.
RESERVED
R
Undefined
RESERVED
1-0
7.6.1.8.10 JESD204B Channel Power-Down Register (address = 0x209) [reset = 0x00]
Figure 140. JESD204B Channel Power-Down Register (PD_CH)
7
6
5
4
3
RESERVED
R/W-0000 00
2
1
PD_BCH
R/W-0
0
PD_ACH
R/W-0
Table 100. PD_CH Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R/W
0000 00
RESERVED
1
PD_BCH
R/W
0
When set, the B ADC channel is powered down. The ADC
channel B SerDes lanes are also powered down when PD_BCH
is set.
Important notes:
Set JESD_EN = 0 before changing PD_CH.
To power-down both ADC channels, use MODE.
If both channels are powered down, then the entire JESD204B
subsystem (including the PLL and LMFC) are powered down
If the selected JESD204B mode transmits A and B data on link
A, and the B digital channel is disabled, link A remains
operational, but the B-channel samples are undefined.
0
PD_ACH
R/W
0
When set, the A ADC channel is powered down. The ADC
channel A SerDes lanes are also powered down when PD_ACH
is set.
Important notes:
Set JESD_EN = 0 before changing PD_CH.
To power-down both ADC channels, use MODE.
If both channels are powered down, then the entire JESD204B
subsystem (including the PLL and LMFC) are powered down
If the selected JESD204B mode transmits A and B data on link
A, and the B digital channel is disabled, link A remains
operational, but the B-channel samples are undefined.
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7.6.1.8.11 JESD204B Extra Lane Enable (Link A) Register (address = 0x20A) [reset = 0x00]
Figure 141. JESD204B Extra Lane Enable (Link A) Register (JEXTRA_A)
7
6
5
4
EXTRA_LANE_A
R/W-0000 000
3
2
1
0
EXTRA_SER_A
R/W-0
Table 101. JESD204B Extra Lane Enable (Link A) Field Descriptions
Bit
Field
Type
Reset
Description
7-1
EXTRA_LANE_A
R/W
0000 000
Program these register bits to enable extra lanes (even if the
selected JMODE does not require the lanes to be enabled).
EXTRA_LANE_A(n) enables An (n = 1 to 7). This register
enables the link layer clocks for the affected lanes. To also
enable the extra serializes set EXTRA_SER_A = 1.
0
EXTRA_SER_A
R/W
0
0: Only the link layer clocks for extra lanes are enabled.
1: Serializers for extra lanes are also enabled. Use this mode to
transmit data from the extra lanes.
Important notes:
Only change this register when JESD_EN = 0.
The bit-rate and mode of the extra lanes are set by the JMODE
and JTEST parameters.
This register does not override the PD_CH register, so ensure
that the link is enabled to use this feature.
To enable serializer n, the lower number lanes 0 to n-1 must
also be enabled, otherwise serializer n does not receive a clock.
7.6.1.8.12 JESD204B Extra Lane Enable (Link B) Register (address = 0x20B) [reset = 0x00]
Figure 142. JESD204B Extra Lane Enable (Link B) Register (JEXTRA_B)
7
6
5
4
EXTRA_LANE_B
R/W-0000 000
3
2
1
0
EXTRA_SER_B
R/W-0
Table 102. JESD204B Extra Lane Enable (Link B) Field Descriptions
98
Bit
Field
Type
Reset
Description
7-1
EXTRA_LANE_B
R/W
0000 000
Program these register bits to enable extra lanes (even if the
selected JMODE does not require the lanes to be enabled).
EXTRA_LANE_B(n) enables Bn (n = 1 to 7). This register
enables the link layer clocks for the affected lanes. To also
enable the extra serializes set EXTRA_SER_B = 1.
0
EXTRA_SER_B
R/W
0
0: Only the link layer clocks for extra lanes are enabled.
1: Serializers for extra lanes are also enabled. Use this mode to
transmit data from the extra lanes.
Important notes:
Only change this register when JESD_EN = 0.
The bit-rate and mode of the extra lanes are set by the JMODE
and JTEST parameters.
This register does not override the PD_CH register, so ensure
that the link is enabled to use this feature.
To enable serializer n, the lower number lanes 0 to n-1 must
also be enabled, otherwise serializer n does not receive a clock.
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7.6.1.9 Digital Down Converter Registers (0x210-0x2AF)
Table 103. Overrange Registers
ADDRESS
RESET
ACRONYM
0x211
0xF2
OVR_T0
Overrange Threshold 0 Register
REGISTER NAME
Overrange Threshold 0 Register (address = 0x211) [reset
= 0xF2]
SECTION
0x212
0xAB
OVR_T1
Overrange Threshold 1 Register
Overrange Threshold 1 Register (address = 0x212) [reset
= 0xAB]
0x213
0x07
OVR_CFG
0x214-0x296
Undefined
RESERVED
0x297
Undefined
SPIN_ID
0x298-0x2AF
Undefined
RESERVED
Overrange Configuration Register
Overrange Configuration Register (address = 0x213)
[reset = 0x07]
RESERVED
—
Spin Identification Value
Spin Identification Register (address = 0x297) [reset =
Undefined]
RESERVED
—
7.6.1.9.1 Overrange Threshold 0 Register (address = 0x211) [reset = 0xF2]
Figure 143. Overrange Threshold 0 Register (OVR_T0)
7
6
5
4
3
2
1
0
OVR_T0
R/W-1111 0010
Table 104. OVR_T0 Field Descriptions
Bit
Field
Type
Reset
7-0
OVR_T0
R/W
1111 0010 Overrange threshold 0. This parameter defines the absolute
sample level that causes control bit 0 to be set. The detection
level in dBFS (peak) is:
20log10(OVR_T0 / 256)
Default: 0xF2 = 242 → –0.5 dBFS.
Description
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7.6.1.9.2 Overrange Threshold 1 Register (address = 0x212) [reset = 0xAB]
Figure 144. Overrange Threshold 1 Register (OVR_T1)
7
6
5
4
3
2
1
0
OVR_T1
R/W-1010 1011
Table 105. OVR_T1 Field Descriptions
Bit
Field
Type
Reset
7-0
OVR_T1
R/W
1010 1011 Overrange threshold 1. This parameter defines the absolute
sample level that causes control bit 1 to be set. The detection
level in dBFS (peak) is:
20log10(OVR_T1 / 256)
Default: 0xAB = 171 → –3.5 dBFS.
Description
7.6.1.9.3 Overrange Configuration Register (address = 0x213) [reset = 0x07]
Figure 145. Overrange Configuration Register (OVR_CFG)
7
6
5
4
3
OVR_EN
R/W-0
RESERVED
R/W-0000
2
1
OVR_N
R/W-111
0
Table 106. OVR_CFG Field Descriptions
(1)
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000 0
RESERVED
3
OVR_EN
R/W
0
Enables overrange status output pins when set high. The ORA0,
ORA1, ORB0, and ORB1 outputs are held low when OVR_EN is
set low. This register only effects the overrange output pins
(ORxx) and not the overrange status embedded in the data
samples.
2-0
OVR_N (1)
R/W
111
Program this register to adjust the pulse extension for the ORA0,
ORA1 and ORB0, ORB1 outputs. The minimum pulse duration
of the overrange outputs is 8 × 2OVR_N DEVCLK cycles.
Incrementing this field doubles the monitoring period.
Changing the OVR_N setting while JESD_EN=1 may cause the phase of the monitoring period to change.
7.6.1.10 Spin Identification Register (address = 0x297) [reset = Undefined]
Figure 146. Spin Identification Register (SPIN_ID)
7
6
RESERVED
R-000
5
4
3
2
SPIN_ID
R
1
0
Table 107. SPIN_ID Field Descriptions
100
Bit
Field
Type
Reset
Description
7-5
RESERVED
R
000
RESERVED
4-0
SPIN_ID
R
2
Spin identification value.
2 : ADC08DJ3200
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7.6.2 SYSREF Calibration Registers (0x2B0 to 0x2BF)
Table 108. SYSREF Calibration Registers
ADDRESS
RESET
ACRONYM
REGISTER NAME
SECTION
0x2B0
0x00
SRC_EN
SYSREF Calibration Enable Register
SYSREF Calibration Enable Register (address = 0x2B0)
[reset = 0x00]
0x2B1
0x05
SRC_CFG
0x2B2-0x2B4
Undefined
SRC_STATUS
0x2B5-0x2B7
0x00
TAD
0x2B8
0x00
0x2B9-0x2BF
Undefined
SYSREF Calibration Configuration
Register
SYSREF Calibration Configuration Register (address =
0x2B1) [reset = 0x05]
SYSREF Calibration Status
SYSREF Calibration Status Register (address = 0x2B2 to
0x2B4) [reset = Undefined]
DEVCLK Aperture Delay Adjustment
Register
DEVCLK Aperture Delay Adjustment Register (address =
0x2B5 to 0x2B7) [reset = 0x000000]
TAD_RAMP
DEVCLK Timing Adjust Ramp
Control Register
DEVCLK Timing Adjust Ramp Control Register (address
= 0x2B8) [reset = 0x00]
RESERVED
RESERVED
—
7.6.2.1 SYSREF Calibration Enable Register (address = 0x2B0) [reset = 0x00]
Figure 147. SYSREF Calibration Enable Register (SRC_EN)
7
6
5
4
RESERVED
R/W-0000 000
3
2
1
0
SRC_EN
R/W-0
Table 109. SRC_EN Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
SRC_EN
R/W
0
0: SYSREF calibration disabled; use the TAD register to
manually control the TAD[16:0] output and adjust the DEVCLK
delay (default)
1: SYSREF calibration enabled; the DEVCLK delay is
automatically calibrated; the TAD register is ignored
A 0-to-1 transition on SRC_EN starts the SYSREF calibration
sequence. Program SRC_CFG before setting SRC_EN. Ensure
that ADC calibration is not currently running before setting
SRC_EN.
0
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7.6.2.2 SYSREF Calibration Configuration Register (address = 0x2B1) [reset = 0x05]
Figure 148. SYSREF Calibration Configuration Register (SRC_CFG)
7
6
5
4
3
RESERVED
R/W-0000
2
1
SRC_AVG
R/W-01
0
SRC_HDUR
R/W-01
Table 110. SRC_CFG Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000 00
RESERVED
3-2
SRC_AVG
R/W
01
Specifies the amount of averaging used for SYSREF calibration.
Larger values increase calibration time and reduce the variance
of the calibrated value.
0: 4 averages
1: 16 averages
2: 64 averages
3: 256 averages
1-0
SRC_HDUR
R/W
01
Specifies the duration of each high-speed accumulation for
SYSREF Calibration. If the SYSREF period exceeds the
supported value, the calibration fails. Larger values increase
calibration time and support longer SYSREF periods. For a
given SYSREF period, larger values also reduce the variance of
the calibrated value.
0: 4 cycles per accumulation, max SYSREF period of 85
DEVCLK cycles
1: 16 cycles per accumulation, max SYSREF period of 1100
DEVCLK cycles
2: 64 cycles per accumulation, max SYSREF period of 5200
DEVCLK cycles
3: 256 cycles per accumulation, max SYSREF period of 21580
DEVCLK cycles
Max duration of SYSREF calibration is bounded by:
TSYSREFCAL (in DEVCLK cycles) = 256 × 19 × 4(SRC_AVG +
SRC_HDUR + 2)
7.6.2.3 SYSREF Calibration Status Register (address = 0x2B2 to 0x2B4) [reset = Undefined]
Figure 149. SYSREF Calibration Status Register (SRC_STATUS)
23
22
21
20
19
18
17
SRC_DONE
R
16
SRC_TAD[16]
R
RESERVED
R
15
14
13
12
11
SRC_TAD[15:8]
R
10
9
8
7
6
5
4
2
1
0
3
SRC_TAD[7:0]
R
Table 111. SRC_STATUS Field Descriptions
Field
Type
Reset
Description
23-18
Bit
RESERVED
R
Undefined
RESERVED
17
SRC_DONE
R
Undefined
This bit returns a 1 when SRC_EN = 1 and SYSREF calibration
is complete.
SRC_TAD
R
Undefined
This field returns the value for TAD[16:0] computed by the
SYSREF calibration. This field is only valid if SRC_DONE = 1.
16-0
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7.6.2.4 DEVCLK Aperture Delay Adjustment Register (address = 0x2B5 to 0x2B7) [reset = 0x000000]
Figure 150. DEVCLK Aperture Delay Adjustment Register (TAD)
23
22
21
15
14
7
6
20
RESERVED
R/W-0000 000
19
18
17
16
TAD_INV
R/W-0
13
12
11
TAD_COARSE
R/W-0000 0000
10
9
8
5
4
2
1
0
3
TAD_FINE
R/W-0000 0000
Table 112. TAD Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R/W
0000 000
RESERVED
TAD_INV
R/W
0
Invert DEVCLK by setting this bit equal to 1.
15-8
TAD_COARSE
R/W
0000 0000 This register controls the DEVCLK aperture delay adjustment
when SRC_EN = 0. Use this register to manually control the
DEVCLK aperture delay when SYSREF calibration is disabled. If
ADC calibration or JESD204B is running, TI recommends
gradually increasing or decreasing this value (1 code at a time)
to avoid clock glitches. See the Switching Characteristics table
for TAD_COARSE resolution.
7-0
TAD_FINE
R/W
0000 0000 See the Switching Characteristics table for TAD_FINE
resolution.
23-17
16
7.6.2.5 DEVCLK Timing Adjust Ramp Control Register (address = 0x2B8) [reset = 0x00]
Figure 151. DEVCLK Timing Adjust Ramp Control Register (TAD_RAMP)
7
6
5
4
RESERVED
R/W-0000 00
3
2
1
TAD_RAMP_RATE
R/W-0
0
TAD_RAMP_EN
R/W-0
Table 113. TAD_RAMP Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R/W
0000 00
RESERVED
1
TAD_RAMP_RATE
R/W
0
Specifies the ramp rate for the TAD[15:8] output when the
TAD[15:8] register is written when TAD_RAMP_EN = 1.
0: TAD[15:8] ramps up or down one code per 256 DEVCLK
cycles.
1: TAD[15:8] ramps up or down 4 codes per 256 DEVCLK
cycles.
0
TAD_RAMP_EN
R/W
0
TAD ramp enable. Set this bit if coarse TAD adjustments are
desired to ramp up or down instead of changing abruptly.
0: After writing the TAD[15:8] register the aperture delay is
updated within 1024 DEVCLK cycles
1: After writing the TAD[15:8] register the aperture delay ramps
up or down until the aperture delay matches the TAD[15:8]
register
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7.6.3 Alarm Registers (0x2C0 to 0x2C2)
Table 114. Alarm Registers
ADDRESS
RESET
ACRONYM
0x2C0
Undefined
ALARM
REGISTER NAME
0x2C1
0x1F
ALM_STATUS
Alarm Status Register
Alarm Status Register (address = 0x2C1) [reset = 0x1F]
0x2C2
0x1F
ALM_MASK
Alarm Mask Register
Alarm Mask Register (address = 0x2C2) [reset = 0x1F]
Alarm Interrupt Status Register
SECTION
Alarm Interrupt Register (address = 0x2C0) [reset =
Undefined]
7.6.3.1 Alarm Interrupt Register (address = 0x2C0) [reset = Undefined]
Figure 152. Alarm Interrupt Register (ALARM)
7
6
5
4
RESERVED
R
3
2
1
0
ALARM
R
Table 115. ALARM Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R
Undefined
RESERVED
ALARM
R
Undefined
This bit returns a 1 whenever any alarm occurs that is
unmasked in the ALM_STATUS register. Use ALM_MASK to
mask (disable) individual alarms. CAL_STATUS_SEL can be
used to drive the ALARM bit onto the CALSTAT output pin to
provide a hardware alarm interrupt signal.
0
7.6.3.2 Alarm Status Register (address = 0x2C1) [reset = 0x1F]
Figure 153. Alarm Status Register (ALM_STATUS)
7
6
RESERVED
R/W-000
5
4
PLL_ALM
R/W-1
3
LINK_ALM
R/W-1
2
REALIGNED_ALM
R/W-1
1
RESERVED
R/W-1
0
CLK_ALM
R/W-1
Table 116. ALM_STATUS Field Descriptions
104
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
RESERVED
4
PLL_ALM
R/W
1
PLL lock lost alarm. This bit is set whenever the PLL is not
locked. Write a 1 to clear this bit.
3
LINK_ALM
R/W
1
Link alarm. This bit is set whenever the JESD204B link is
enabled, but is not in the DATA_ENC state. Write a 1 to clear
this bit.
2
REALIGNED_ALM
R/W
1
Realigned alarm. This bit is set whenever SYSREF causes the
internal clocks (including the LMFC) to be realigned. Write a 1 to
clear this bit.
1
RESERVED
R/W
1
RESERVED
0
CLK_ALM
R/W
1
Clock alarm. This bit can be used to detect an upset to the
digital block and JESD204B clocks. This bit is set whenever the
internal clock dividers for the A and B channels do not match.
Write a 1 to clear this bit.
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7.6.3.3 Alarm Mask Register (address = 0x2C2) [reset = 0x1F]
Figure 154. Alarm Mask Register (ALM_MASK)
7
6
5
4
3
RESERVED
MASK_PLL_ALM
MASK_LINK_ALM
R/W-000
R/W-1
R/W-1
2
MASK_REALIGNED_
ALM
R/W-1
1
0
MASK_NCO_ALM
MASK_CLK_ALM
R/W-1
R/W-1
Table 117. ALM_MASK Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
RESERVED
4
MASK_PLL_ALM
R/W
1
When set, PLL_ALM is masked and does not impact the ALARM
register bit.
3
MASK_LINK_ALM
R/W
1
When set, LINK_ALM is masked and does not impact the
ALARM register bit.
2
MASK_REALIGNED_ALM
R/W
1
When set, REALIGNED_ALM is masked and does not impact
the ALARM register bit.
1
MASK_NCO_ALM
R/W
1
When set, NCO_ALM is masked and does not impact the
ALARM register bit.
0
MASK_CLK_ALM
R/W
1
When set, CLK_ALM is masked and does not impact the
ALARM register bit.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The ADC08DJ3200 can be used in a wide range of applications including radar, satellite communications, test
equipment (communications testers and oscilloscopes), and software-defined radios (SDRs). The wide input
bandwidth enables direct RF sampling to at least 8 GHz and the high sampling rate allows signal bandwidths of
greater than 2 GHz. The Typical Applications section describes one configuration that meets the needs of a
number of these applications.
8.2 Typical Applications
8.2.1 Wideband RF Sampling Receiver
LNA
LNA
Up to 16 Lanes
JESD204B
Antialias BPF
ADC A
JESD
204B
DDC
SYNC~
LNA
LNA
Antialias BPF
ADC B
JESD
204B
DDC
FPGA or ASIC
Clocking
Subsystem
User Control
Logic
SPI
LMK04832
Device Clock
÷
SYSREF
N÷
R÷
PFD
10-MHz
Reference
÷
Device Clock
÷
÷
SYSREF
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Figure 155. Typical Configuration for Wideband RF Sampling
8.2.1.1 Design Requirements
8.2.1.1.1 Input Signal Path
Use appropriate band-limiting filters to reject unwanted frequencies in the input signal path.
A 1:2 balun transformer is needed to convert the 50-Ω, single-ended signal to 100-Ω differential for input to the
ADC. The balun outputs can be either AC-coupled, or directly connected to the ADC differential inputs, which are
terminated internally to GND.
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Typical Applications (continued)
Drivers must be selected to provide any needed signal gain and that have the necessary bandwidth capabilities.
Baluns must be selected to cover the needed frequency range, have a 1:2 impedance ratio, and have acceptable
gain and phase balance over the frequency range of interest. Table 118 lists a number of recommended baluns
for different frequency ranges.
Table 118. Recommended Baluns
(1)
PART NUMBER
MANUFACTURER (1)
MINIMUM FREQUENCY (MHz)
MAXIMUM FREQUENCY (MHz)
BAL-0009SMG
Marki Microwave
0.5
9000
BAL-0208SMG
Marki Microwave
2000
8000
TCM2-43X+
Mini-Circuits
10
4000
TCM2-33WX+
Mini-Circuits
10
3000
B0430J50100AHF
Anaren
400
3000
See the Third-Party Products Disclaimer section.
8.2.1.1.2 Clocking
The ADC08DJ3200 clock inputs must be AC-coupled to the device to ensure rated performance. The clock
source must have extremely low jitter (integrated phase noise) to enable rated performance. Recommended
clock synthesizers include the LMX2594, LMX2592, and LMX2582.
The JESD204B data converter system (ADC plus FPGA) requires additional SYSREF and device clocks. The
LMK04828, LMK04826, and LMK04821 devices are suitable to generate these clocks. Depending on the ADC
clock frequency and jitter requirements, this device may also be used as the system clock synthesizer or as a
device clock and SYSREF distribution device when multiple ADC08DJ3200 devices are used in a system.
8.2.1.2 Detailed Design Procedure
Certain component values used in conjunction with the ADC08DJ3200 must be calculated based on system
parameters. Those items are covered in this section.
8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
AC-coupling capacitors are used in the input CLK± and JESD204B output data pairs. The capacitor values must
be large enough to address the lowest frequency signals of interest, but not so large as to cause excessively
long startup biasing times, or unwanted parasitic inductance.
The minimum capacitor value can be calculated based on the lowest frequency signal that is transferred through
the capacitor. Given a 50-Ω single-ended clock or data path impedance, good practice is to set the capacitor
impedance to be <1 Ω at the lowest frequency of interest. This setting ensures minimal impact on signal level at
that frequency. For the CLK± path, the minimum-rated clock frequency is 800 MHz. Therefore, the minimum
capacitor value can be calculated from:
ZC = 1/ (2 ´ p ´ ¦ CLK ´ C )
(4)
Setting Zc = 1 Ω and rearranging gives:
C = 1/ (2 ´ p ´ 800 MHz ´ 1 W ) = 199 pF
(5)
Therefore, a capacitance value of at least 199 pF is needed to provide the low-frequency response for the CLK±
path. If the minimum clock frequency is higher than 800 MHz, this calculation can be revisited for that frequency.
Similar calculations can be done for the JESD204B output data capacitors based on the minimum frequency in
that interface. Capacitors must also be selected for good response at high frequencies, and with dimensions that
match the high-frequency signal traces they are connected to. Capacitors of the 0201 size are frequently well
suited to these applications.
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8.2.1.3 Application Curves
The ADC08DJ3200 can be used in a number of different operating modes to suit multiple applications.
Figure 156 to Figure 157 describe operation with a 497.77-MHz input signal in the following configurations:
• 6.4-GSPS, single-input mode, JMODE5
• 6.4-GSPS, dual-input mode, JMODE7
Figure 156. FFT for 497.77-MHz Input Signal, 6.4 GSPS,
JMODE5
Figure 157. FFT for 497.77-MHz Input Signal, 3.2 GSPS,
JMODE7
8.2.2 Reconfigurable Dual-Channel 2.5-GSPS or Single-Channel 5.0-Gsps Oscilloscope
This section demonstrates the use of the ADC08DJ3200 in a reconfigurable oscilloscope. The oscilloscope can
operate as a dual-channel oscilloscope running at 2.5 GSPS or can be reconfigured through SPI programming
as a single-channel, 5-GSPS oscilloscope. This reconfigurable setup allows users to trade off the number of
channels and the sampling rate of the oscilloscope as needed without changing the hardware. Set the input
bandwidth to the desired maximum signal bandwidth through the use of an antialiasing, low-pass filter. Digital
filtering can then be used to reconfigure the analog bandwidth as required. For instance, the maximum
bandwidth can be set to 1 GHz for use during pulsed transient detection and then reconfigured to 100 MHz
through digital filtering for low-noise, sine-wave observation. Figure 158 shows the application block diagram.
LMH5401
Front Panel
Channel A
LMH6401
Programmable
Termination
JESD
204B
ADC A
DAC
LMH6559
OPA703
LMH5401
Front Panel
Channel B
Up to 16 Lanes
JESD204B
Antialias LPF
DC Offset
Adjustment
SYNC~
DAC8560
LMH6401
Antialias LPF
Programmable
Termination
JESD
204B
ADC B
DAC
LMH6559
OPA703
DC Offset
Adjustment
DAC8560
FPGA or ASIC
Clocking
Subsystem
User Control
Logic
SPI
LMK04832
Device Clock
÷
SYSREF
N÷
R÷
PFD
10-MHz
Reference
÷
Device Clock
÷
÷
SYSREF
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Figure 158. Typical Configuration for Reconfigurable Oscilloscope
108
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8.2.2.1 Design Requirements
8.2.2.1.1 Input Signal Path
Most oscilloscopes are required to be DC-coupled in order to monitor DC or low-frequency signals. This
requirement forces the design to use DC-coupled, fully differential amplifiers to convert from single-ended
signaling at the front panel to differential signaling at the ADC. This design uses two differential amplifiers. The
first amplifier shown in Figure 158 is the LMH5401 that converts from single-ended to differential signaling. The
LMH5401 interfaces with the front panel through a programmable termination network and has an offset
adjustment input. The amplifier has an 8-GHz, gain-bandwidth product that is sufficient to support a 1-GHz
bandwidth oscilloscope. A second amplifier, the LMH6401, comes after the LMH5401 to provide a digitally
programmable gain control for the oscilloscope. The LMH6401 supports a gain range from –6 dB to 26 dB in 1dB steps. If gain control is not necessary or is performed in a different location in the signal chain, then this
amplifier can be replaced with a second LMH5401 for additional fixed gain or omitted altogether.
The input of the oscilloscope contains a programmable termination block that is not covered in detail here. This
block enables the front-panel input termination to be programmed. For instance, many oscilloscopes allow the
termination to be programmed as either 50-Ω or 1-MΩ to meet the needs of various applications. A 75-Ω
termination can also be desired to support cable infrastructure use cases. This block can also contain an option
for DC blocking to remove the DC component of the external signal and therefore pass only AC signals.
A precision DAC is used to configure the offset of the oscilloscope front-end to prevent saturation of the analog
signal chain for input signals containing large DC offsets. The DAC8560 is shown in Figure 158 along with
signal-conditioning amplifiers OPA703 and LMH6559. The first differential amplifier, LMH5401, is driven by the
front panel input circuitry on one input, and the DC offset bias on the second input. The impedance of these
driving signals must be matched at DC and over frequency to ensure good even-order harmonic performance in
the single-ended to differential conversion operation. The high bandwidth of the LMH6559 allows the device to
maintain low impedance over a wide frequency range.
An antialiasing, low-pass filter is positioned at the input of the ADC to limit the bandwidth of the input signal into
the ADC. This amplifier also band-limits the front-end noise to prevent aliased noise from degrading the signal-tonoise ratio of the overall system. Design this filter for the maximum input signal bandwidth specified by the
oscilloscope. The input bandwidth can then be reconfigured through the use of digital filters in the FPGA or ASIC
to limit the oscilloscope input bandwidth to a bandwidth less than the maximum.
8.2.2.1.2 Clocking
The ADC08DJ3200 clock inputs must be AC-coupled to the device to ensure rated performance. The clock
source must have extremely low jitter (integrated phase noise) to enable rated performance. Recommended
clock synthesizers include the LMX2594, LMX2592, and LMX2582.
The JESD204B data converter system (ADC plus FPGA) requires additional SYSREF and device clocks. The
LMK04832, LMK04828, LMK04826, and LMK04821 devices are suitable to generate these clocks. Depending on
the ADC clock frequency and jitter requirements, this device can also be used as the system clock synthesizer or
as a device clock and SYSREF distribution device when multiple ADC08DJ3200 devices are used in a system.
8.2.2.1.3 ADC08DJ3200
The ADC08DJ3200 is ideally suited for oscilloscope applications. The ability to tradeoff channel count and
sampling speed allows designers to build flexible hardware to meet multiple needs. This flexibility saves
development time and cost, allows hardware reuse for various projects and enables software upgrade paths for
additional functionality. The low code-error rate eliminates concerns about undesired time domain glitches or
sparkle codes. This rate makes the ADC08DJ3200 a perfect fit for long-duration transient detection
measurements and reduces the probability of false triggers. The input common-mode voltage of 0 V allows the
driving amplifiers to use equal split power supplies that center the amplifier output common-mode voltage at 0 V
and eliminates the need for common-mode voltage shifting before the ADC inputs. The high input bandwidth of
the ADC08DJ3200 simplifies the design of the driving amplifier circuit and antialiasing, low-pass filter. The use of
dual-edge sampling (DES) in single-channel mode eliminates the need to change the clock frequency when
switching between dual- and single-channel modes and simplifies synchronization by relaxing the setup and hold
timing requirements of SYSREF. The tAD adjust circuit allows the user to time-align the sampling instances of
multiple ADC08DJ3200 devices.
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8.2.2.2 Application Curves
The following application curves demonstrate performance and results only of the ADC. The amplifier front-end is
not included in these measurements. The following configurations and measurements are shown in Figure 159 to
Figure 165:
• 8-bit, 5-GSPS, single-channel oscilloscope using JMODE4 (4 lanes at 12.5 Gbps)
– Idle-channel noise (no input)
– 40-MHz, square-wave time domain
– 200-MHz, sine-wave time domain
– 200-MHz, sine-wave frequency domain (FFT)
• 8-bit, 2.5-GSPS, dual-channel oscilloscope using JMODE6 (4 lanes at 12.5 Gbps)
– Idle-channel noise (no input)
– 40-MHz, square-wave (channel B) and 200-MHz, sine-wave (channel A) time domain
– 40-MHz, square-wave (channel B) time domain and 200-MHz, sine-wave (channel A) frequency domain
(FFT)
110
Figure 159. Idle-Channel Noise (No Input) for 5-GSPS,
Single-Channel Oscilloscope
Figure 160. 40-MHz, Square-Wave Time Domain for 5GSPS, Single-Channel Oscilloscope
Figure 161. 200-MHz, Sine-Wave Time Domain for 5-GSPS,
Single-Channel Oscilloscope
Figure 162. 200-MHz, Sine-Wave Frequency Domain (FFT)
for 5-GSPS, Single-Channel Oscilloscope
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Figure 163. Idle-Channel Noise (No Input) for 2.5-GSPS,
Dual-Channel Oscilloscope
Figure 164. 200-MHz, Sine-Wave (Channel A) and 40-MHz,
Square-Wave (Channel B) Time Domain for 5-GSPS,
Single-Channel Oscilloscope
Figure 165. 200-MHz, Sine-Wave (Channel A) Frequency Domain (FFT) and 40-MHz, Square-Wave (Channel B) Time Domain
for 5-GSPS, Single-Channel Oscilloscope
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8.3 Initialization Set Up
The device and JESD204 interface require a specific startup and alignment sequence. The general order of that
sequence is listed in the following steps.
1. Power-up or reset the device.
2. Apply a stable device CLK signal at the desired frequency.
3. Program JESD_EN = 0 to stop the JESD204B state machine and allow setting changes.
4. Program CAL_EN = 0 to stop the calibration state machine and allow setting changes.
5. Program the desired JMODE.
6. Program the desired KM1 value. KM1 = K–1.
7. Program SYNC_SEL as needed. Choose SYNCSE or timestamp differential inputs.
8. Configure device calibration settings as desired. Select foreground or background calibration modes and
offset calibration as needed.
9. Program CAL_EN = 1 to enable the calibration state machine.
10. Enable overrange via OVR_EN and adjust settings if desired.
11. Program JESD_EN = 1 to re-start the JESD204B state machine and allow the link to restart.
12. The JESD204B interface operates in response to the applied SYNC signal from the receiver.
13. Program CAL_SOFT_TRIG = 0.
14. Program CAL_SOFT_TRIG = 1 to initiate a calibration.
9 Power Supply Recommendations
The device requires two different power-supply voltages. 1.9 V DC is required for the VA19 power bus and 1.1 V
DC is required for the VA11 and VD11 power buses.
The power-supply voltages must be low noise and provide the needed current to achieve rated device
performance.
There are two recommended power supply architectures:
1. Step down using high-efficiency switching converters, followed by a second stage of regulation to provide
switching noise reduction and improved voltage accuracy.
2. Directly step down the final ADC supply voltage using high-efficiency switching converters. This approach
provides the best efficiency, but care must be taken to ensure switching noise is minimized to prevent
degraded ADC performance.
TI WEBENCH® Power Designer can be used to select and design the individual power supply elements needed:
see the WEBENCH® Power Designer
Recommended switching regulators for the first stage include the TPS62085, TPS82130, TPS62130A, and
similar devices.
Recommended Low Drop-Out (LDO) linear regulators include the TPS7A7200, TPS74401, and similar devices.
For the switcher only approach, the ripple filter must be designed with a notch frequency that aligns with the
switching ripple frequency of the DC-DC converter. Make a note of the switching frequency reported from
WEBENCH® and design the EMI filter and capacitor combination to have the notch frequency centered as
needed. Figure 166 and Figure 167 illustrate the two approaches.
112
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1.9 V
2.2 V
5 V - 12 V
Buck
FB
+
±
LDO
47 F
1.4 V
Buck
FB
47 F
Power
Good
GND
GND
VA19
10 F 0.1 F 0.1 F
GND
GND
VA11
1.1 V
FB
LDO
47 F
FB
47 F
GND
10 F 0.1 F 0.1 F
GND
GND
VD11
FB
10 F 0.1 F 0.1 F
GND
Copyright © 2018, Texas Instruments Incorporated
NOTE: FB = ferrite bead filter.
Figure 166. LDO Linear Regulator Approach Example
Ripple Filter
5 V - 12 V
Buck
FB
+
±
GND
VA19
1.9 V
Power
Good
FB
10 F 10 F 10 F
10 F 0.1 F 0.1 F
GND
GND
Ripple Filter
Buck
VA11
1.1 V
FB
FB
10 F 10 F 10 F
10 F 0.1 F 0.1 F
GND
GND
VD11
FB
10 F 0.1 F 0.1 F
GND
Copyright © 2018, Texas Instruments Incorporated
NOTE: Ripple filter notch frequency to match the fs of the buck converter.
NOTE: FB = ferrite bead filter.
Figure 167. Switcher-Only Approach Example
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9.1 Power Sequencing
The voltage regulators must be sequenced using the power-good outputs and enable inputs to ensure that the
Vx11 regulator is enabled after the VA19 supply is good. Similarly, as soon as the VA19 supply drops out of
regulation on power-down, the Vx11 regulator is disabled.
The general requirement for the ADC is that VA19 ≥ Vx11 during power-up, operation, and power-down.
TI also recommends that VA11 and VD11 are derived from a common 1.1-V regulator. This recommendation
ensures that all 1.1-V blocks are at the same voltage, and no sequencing problems exist between these supplies.
Also use ferrite bead filters to isolate any noise on the VA11 and VD11 buses from affecting each other.
10 Layout
10.1 Layout Guidelines
There are many critical signals that require specific care during board design:
1. Analog input signals
2. CLK and SYSREF
3. JESD204B data outputs:
1. Lower eight pairs operating at up to 12.8 Gbit per second
2. Upper eight pairs operating at up to 6.4 Gbit per second
4. Power connections
5. Ground connections
Items 1, 2, and 3 must be routed for excellent signal quality at high frequencies. Use the following general
practices:
1. Route using loosely coupled 100-Ω differential traces. This routing minimizes impact of corners and lengthmatching serpentines on pair impedance.
2. Provide adequate pair-to-pair spacing to minimize crosstalk.
3. Provide adequate ground plane pour spacing to minimize coupling with the high-speed traces.
4. Use smoothly radiused corners. Avoid 45- or 90-degree bends.
5. Incorporate ground plane cutouts at component landing pads to avoid impedance discontinuities at these
locations. Cut-out below the landing pads on one or multiple ground planes to achieve a pad size or stackup
height that achieves the needed 50-Ω, single-ended impedance.
6. Avoid routing traces near irregularities in the reference ground planes. Irregularities include ground plane
clearances associated with power and signal vias and through-hole component leads.
7. Provide symmetrically located ground tie vias adjacent to any high-speed signal vias.
8. When high-speed signals must transition to another layer using vias, transition as far through the board as
possible (top to bottom is best case) to minimize via stubs on top or bottom of the vias. If layer selection is
not flexible, use back-drilled or buried, blind vias to eliminate stubs.
In addition, TI recommends performing signal quality simulations of the critical signal traces before committing to
fabrication. Insertion loss, return loss, and time domain reflectometry (TDR) evaluations should be done.
The power and ground connections for the device are also very important. These rules must be followed:
1. Provide low-resistance connection paths to all power and ground pins.
2. Use multiple power layers if necessary to access all pins.
3. Avoid narrow isolated paths that increase connection resistance.
4. Use a signal, ground, or power circuit board stackup to maximum coupling between the ground and power
planes.
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10.2 Layout Example
Figure 168 to Figure 170 provide examples of the critical traces routed on the device evaluation module (EVM).
Figure 168. Top Layer Routing: Analog Inputs, CLK and SYSREF, DA0-3, DB0-3
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Layout Example (continued)
Figure 169. GND1 Cutouts to Optimize Impedance of Component Pads
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Layout Example (continued)
Figure 170. Bottom Layer Routing: Additional CLK Routing, DA4-7, DB4-7
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
WEBENCH® Power Designer
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• JESD204B multi-device synchronization: Breaking down the requirements
• LM95233 Dual Remote Diode and Local Temperature Sensor with SMBus Interface and TruTherm™
Technology
• LMX2594 15-GHz Wideband PLLatinum™ RF Synthesizer With Phase Synchronization and JESD204B
Support
• LMX2592 High Performance, Wideband PLLatinum™ RF Synthesizer With Integrated VCO
• LMX2582 High Performance, Wideband PLLatinum™ RF Synthesizer With Integrated VCO
• LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs
• TPS6208x 3-A Step-Down Converter With Hiccup Short-Circuit Protection In 2 × 2 QFN Package
• TPS82130 17-V Input 3-A Step-Down Converter MicroSiP™ Module with Integrated Inductor
• TPS6213x 3-V to17-V, 3-A Step-Down Converter In 3x3 QFN Package
• TPS7A7200 2-A, Fast-Transient, Low-Dropout Voltage Regulator
• TPS74401 3.0-A, Ultra-LDO with Programmable Soft-Start
• Direct RF-Sampling Radar Receiver for L-, S-, C-, and X-Band Using ADC12DJ3200 Reference Design
• ADC12DJ2700 Evaluation Module User's Guide
• Multi-Channel JESD204B 15 GHz Clocking Reference Design for DSO, Radar and 5G Wireless Testers
• LMH5401 8-GHz, Low-Noise, Low-Power, Fully-Differential Amplifier
• LMH6401 DC to 4.5 GHz, Fully-Differential, Digital Variable-Gain Amplifier
• DAC8560 16-Bit, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter With 2.5-V, 2-ppm/°C Internal
Reference
• OPA70x CMOS, Rail-to-Rail, I/O Operational Amplifiers
• LMH6559 High-Speed, Closed-Loop Buffer
• LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
118
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11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
22-Mar-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADC08DJ3200AAV
ACTIVE
FCBGA
AAV
144
1
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
ADC08DJ32
ADC08DJ3200AAVT
ACTIVE
FCBGA
AAV
144
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
ADC08DJ32
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
22-Mar-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADC08DJ3200AAVT
Package Package Pins
Type Drawing
FCBGA
AAV
144
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
24.4
Pack Materials-Page 1
10.3
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.3
2.5
16.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADC08DJ3200AAVT
FCBGA
AAV
144
250
213.0
191.0
55.0
Pack Materials-Page 2
PACKAGE OUTLINE
AAV0144A
FCBGA - 1.94 mm max height
SCALE 1.400
BALL GRID ARRAY
10.15
9.85
A
B
BALL A1 CORNER
10.15
9.85
( 8)
(0.68)
(0.5)
1.94 MAX
C
SEATING PLANE
NOTE 4
BALL TYP
0.405
TYP
0.325
0.2 C
8.8 TYP
(0.6) TYP
SYMM
0.8 TYP
(0.6) TYP
M
L
K
J
H
SYMM
8.8
TYP
G
F
E
D
0.51
144X
0.41
0.15
C A B
0.08
C NOTE 3
C
B
A
1
2
3
4
5
6
7
8
9
10
11 12
0.8 TYP
4219578/A 04/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.
4. Primary datum C and seating plane are defined by the spherical crowns of the solder balls.
www.ti.com
EXAMPLE BOARD LAYOUT
AAV0144A
FCBGA - 1.94 mm max height
BALL GRID ARRAY
(0.8) TYP
A
1
2
3
4
5
6
7
8
10
9
11
12
B
(0.8) TYP
C
D
144X ( 0.4)
E
F
SYMM
G
H
J
K
L
M
SYMM
LAND PATTERN EXAMPLE
SCALE:8X
( 0.4)
METAL
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
( 0.4)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219578/A 04/2016
NOTES: (continued)
5. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
AAV0144A
FCBGA - 1.94 mm max height
BALL GRID ARRAY
144X ( 0.4)
(0.8) TYP
A
1
2
3
4
5
6
7
8
9
10
11
12
B
(0.8)
TYP
C
D
E
F
SYMM
G
H
J
K
L
M
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:8X
4219578/A 04/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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