Texas Instruments | ADS7052 14-Bit, 1-MSPS, Single-Ended Input, Small-Size, Low-Power SAR ADC | Datasheet | Texas Instruments ADS7052 14-Bit, 1-MSPS, Single-Ended Input, Small-Size, Low-Power SAR ADC Datasheet

Texas Instruments ADS7052 14-Bit, 1-MSPS, Single-Ended Input, Small-Size, Low-Power SAR ADC Datasheet
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ADS7052
SBAS858 – DECEMBER 2017
ADS7052 14-Bit, 1-MSPS, Single-Ended Input, Small-Size, Low-Power SAR ADC
1 Features
3 Description
•
•
The ADS7052 device belongs to a family of pin-to-pin
compatible, high-speed, low-power, single-channel
successive-approximation register (SAR) type analogto-digital converters (ADCs). The device family
includes multiple resolutions, throughputs, and analog
input variants (see Table 1 for a list of devices).
1
•
•
•
•
•
•
•
1-MSPS Throughput
Small Package Size:
– X2QFN-8 Package (1.5 mm × 1.5 mm)
Unipolar Input Range: 0 V to AVDD
Wide Operating Range:
– AVDD: 1.65 V to 3.6 V
– DVDD: 1.65 V to 3.6 V (Independent of AVDD)
– Temperature Range: –40°C to +125°C
Excellent Performance:
– 14-Bit NMC DNL, ±2-LSB INL
– 74.5-dB SINAD at 2 kHz
– 72.5-dB SINAD at 200 kHz
Low Power Consumption:
– 1.5 mW at 1 MSPS With 3.3-V AVDD
– 160 µW at 100 kSPS With 3.3-V AVDD
– 40 µW at 100 kSPS With 1.8-V AVDD
Integrated Offset Calibration
SPI-Compatible Serial Interface: 24 MHz
JESD8-7A Compliant Digital I/O
2 Applications
•
•
•
•
•
•
•
•
Optical Encoders
Sonar Receivers
Fish Finders
I-Q Demodulators
Optical Line Cards and Modules
Thermal Imaging Cameras
Ultrasonic Flow Meters
Handheld Radios
The ADS7052 is a 14-bit, 1-MSPS SAR ADC that
supports a single-ended input in the range of 0 V to
AVDD, for AVDD in the range of 1.65 V to 3.6 V.
The internal offset calibration feature maintains
excellent offset specifications over the entire AVDD
and temperature operating range.
The device supports an SPI-compatible serial
interface that is controlled by the CS and SCLK
signals. The input signal is sampled with the CS
falling edge and SCLK is used for both conversion
and serial data output. The device supports a wide
digital supply range (1.65 V to 3.6 V), enabling direct
interfacing to a variety of host controllers. The
ADS7052 complies with the JESD8-7A standard for a
normal DVDD range (1.65 V to 1.95 V).
The ADS7052 is available in an 8-pin, small, X2QFN
package and is specified over the extended industrial
temperature range (–40°C to +125°C). The small
form-factor and extremely-low power consumption
make this device suitable for space-constrained and
battery-powered applications that require high-speed,
high-resolution data acquisition.
Device Information(1)
PART NAME
ADS7052
PACKAGE
BODY SIZE (NOM)
X2QFN (8)
1.50 mm × 1.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application
Simultaneous Sampling Circuit
Single ADC Circuit
Optical
SDO
+
ADC
ADC 1
SCLK
CS
HOST
SONAR
CS
ADC 2
Votlage/
Current
ADC Package Size
1.5 (L) x 1.5 (W) x 0.35 (H) mm
SCLK
SDO
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS7052
SBAS858 – DECEMBER 2017
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
7
7
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
7
Parameter Measurement Information ................ 14
8
Detailed Description ............................................ 15
8.4 Device Functional Modes........................................ 20
9
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Applications ................................................ 24
10 Power Supply Recommendations ..................... 31
10.1 AVDD and DVDD Supply Recommendations....... 31
10.2 Optimizing Power Consumed by the Device ........ 31
11 Layout................................................................... 32
11.1 Layout Guidelines ................................................. 32
11.2 Layout Example .................................................... 33
12 Device and Documentation Support ................. 34
12.1
12.2
12.3
12.4
12.5
12.6
12.7
7.1 Digital Voltage Levels ............................................. 14
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
34
35
35
13 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
2
DATE
REVISION
NOTES
December 2017
*
Initial release.
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5 Pin Configuration and Functions
8
AINM
RUG Package
8-Pin X2QFN
Top View
1
7
AINP
SDO
2
6
AVDD
SCLK
3
5
GND
4
CS
DVDD
Not to scale
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
CS
Digital input
2
SDO
Digital output
Chip-select signal, active low
3
SCLK
Digital input
4
DVDD
Supply
Digital I/O supply voltage
5
GND
Supply
Ground for power supply, all analog and digital signals are referred to this pin
6
AVDD
Supply
Analog power-supply input, also provides the reference voltage to the ADC
7
AINP
Analog input
Analog signal input, positive
8
AINM
Analog input
Analog signal input, negative
Serial data out
Serial clock
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6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
AVDD to GND
–0.3
3.9
V
DVDD to GND
–0.3
3.9
V
AINP to GND
–0.3
AVDD + 0.3
V
AINM to GND
–0.3
0.3
V
Input current to any pin except supply pins
–10
10
mA
Digital input voltage to GND
–0.3
DVDD + 0.3
V
Storage temperature, Tstg
–60
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
Electrostatic discharge
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
AVDD
Analog supply voltage range
1.65
3.3
3.6
UNIT
DVDD
Digital supply voltage range
1.65
1.8
3.6
V
TA
Operating free-air temperature
–40
25
125
°C
V
6.4 Thermal Information
ADS7052
THERMAL METRIC (1)
RUG (X2QFN)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
177.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.5
°C/W
RθJB
Junction-to-board thermal resistance
76.7
°C/W
ψJT
Junction-to-top characterization parameter
1
°C/W
ψJB
Junction-to-board characterization parameter
76.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at AVDD = 3.3 V, DVDD = 1.65 V to 3.6 V, fsample = 1 MSPS, and VAINM = 0 V (unless otherwise noted); minimum and
maximum values for TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
AVDD
V
AINP to GND
–0.1
AVDD + 0.1
AINM to GND
–0.1
0.1
ANALOG INPUT
Full-scale input voltage
span (1)
Absolute input voltage
range
CS
Sampling capacitance
V
16
pF
14
Bits
SYSTEM PERFORMANCE
Resolution
NMC
No missing codes
INL (2)
Integral nonlinearity
DNL
Differential nonlinearity
EO (2)
Offset error
dVOS/dT
Offset error drift with
temperature
EG (2)
Gain error
14
After calibration (4)
Bits
LSB (3)
–3.75
±2
3.75
–0.99
±0.5
1
LSB
–6
±1
6
LSB
1.75
–0.1
Gain error drift with
temperature
±0.01
ppm/°C
0.1
0.5
%FS
ppm/°C
SAMPLING DYNAMICS
tCONV
Conversion time
tACQ
Acquisition time
fSAMPLE
Maximum throughput
rate
18 × tSCLK
ns
230
ns
24-MHz SCLK, AVDD = 1.65 V to 3.6 V
1
Aperture delay
Aperture jitter, RMS
MHz
3
ns
12
ps
DYNAMIC CHARACTERISTICS
SNR
Signal-to-noise ratio (5)
THD
Total harmonic
distortion (5) (6)
AVDD = 3.3 V, fIN = 2 kHz
SFDR
BW(fp)
(1)
(2)
(3)
(4)
(5)
(6)
Signal-to-noise and
distortion (5)
Spurious-free dynamic
range (5)
Full-power bandwidth
74.9
73.7
fIN = 2 kHz
–92
fIN = 100 kHz
–90
fIN = 200 kHz
–87
fIN = 2 kHz
SINAD
71.5
AVDD = 2.5 V, fIN = 2 kHz
71.5
dB
74.8
fIN = 100 kHz
74.7
fIN = 200 kHz
74.5
fIN = 2 kHz
89.8
fIN = 100 kHz
91
fIN = 200 kHz
87
At –3 dB
dB
200
dB
dB
MHz
Ideal input span; does not include gain or offset error.
See Figure 31, Figure 29, and Figure 30 for statistical distribution data for INL, offset error, and gain error.
LSB means least significant bit.
See the OFFCAL State section for details.
All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale,
unless otherwise noted.
Calculated on the first nine harmonics of the input frequency.
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Electrical Characteristics (continued)
at AVDD = 3.3 V, DVDD = 1.65 V to 3.6 V, fsample = 1 MSPS, and VAINM = 0 V (unless otherwise noted); minimum and
maximum values for TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT/OUTPUT (CMOS Logic Family)
VIH
High-level input
voltage (7)
0.65 DVDD
DVDD + 0.3
V
VIL
Low-level input
voltage (7)
–0.3
0.35 DVDD
V
VOH
High-level output
voltage (7)
At Isource = 500 µA
0.8 DVDD
DVDD
At Isource = 2 mA
DVDD – 0.45
DVDD
VOL
Low-level output
voltage (7)
At Isink = 500 µA
0
0.2 DVDD
At Isink = 2 mA
0
0.45
V
V
POWER-SUPPLY REQUIREMENTS
AVDD
Analog supply voltage
1.65
3
3.6
V
DVDD
Digital I/O supply
voltage
1.65
3
3.6
V
AVDD = 3.3 V, fSAMPLE = 1 MSPS
IAVDD
IDVDD
(7)
(8)
6
Analog supply current
Digital supply current
450
500
AVDD = 3.3 V, fSAMPLE = 100 kSPS
46
50
AVDD = 3.3 V, fSAMPLE = 10 kSPS
5
AVDD = 1.8 V, fSAMPLE = 1 MSPS
230
Static current with CS and SCLK high
0.02
DVDD = 1.8 V, CSDO = 20 pF,
output code = 2AAAh (8)
250
DVDD = 1.8 V, static current with CS and
SCLK high
0.01
µA
µA
Digital voltage levels comply with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V; see the Parameter Measurement Information
section for details.
See the Estimating Digital Power Consumption section for details.
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6.6 Timing Requirements
all specifications are at AVDD = 1.65 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD-SDO = 20 pF (unless otherwise noted);
minimum and maximum values for TA = –40°C to +125°C; typical values at TA = 25°C
MIN
TYP
MAX
UNIT
tCLK
Time period of SCLK
41.66
ns
tsu_CSCK
tht_CKCS
Setup time: CS falling edge to SCLK falling edge
7
ns
Hold time: SCLK rising edge to CS rising edge
8
tph_CK
SCLK high time
0.45
0.55
tSCLK
tpl_CK
SCLK low time
0.45
0.55
tSCLK
tph_CS
CS high time
ns
15
ns
6.7 Switching Characteristics
all specifications are at AVDD = 1.65 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD-SDO = 20 pF (unless otherwise noted);
minimum and maximum values for TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tCYCLE (1)
Cycle time
tCONV
Conversion time
tden_CSDO
Delay time: CS falling edge to data enable
6.5
ns
td_CKDO
Delay time: SCLK rising edge to (next) data
valid on SDO
10
ns
tht_CKDO
SCLK rising edge to current data invalid
2.5
ns
tdz_CSDO
Delay time: CS rising edge to SDO going to
tri-state
5.5
ns
(1)
1000
ns
18 × tSCLK
ns
tCYCLE = 1 / fSAMPLE.
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Sample
A+1
Sample
A
tph_CS
tCYCLE
tACQ
tCONV
CS
SCLK
SDO
1
2
3
0
D13
15
D12
16
D0
17
0
0
18
0
Data Output for Sample A-1
Figure 1. Serial Transfer Frame
tCLK
tph_CK
CS
50%
tsu_CSCK
SCLK
SCLK
50%
td_CKDO
tht_CKCS
50%
tpl_CK
50%
SDO
tht_CKDO
tden_CSDO
tdz_CSDO
SDO
Figure 2. Timing Specifications
8
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6.8 Typical Characteristics
0
0
-50
-50
Amplitude (dB)
Amplitude (dB)
at TA = 25°C, AVDD = 3.3 V, DVDD = 1.8 V, fIN = 2 kHz, and fsample = 1 MSPS (unless otherwise noted)
-100
-100
-150
-150
-200
-200
0
100
200
300
fIN, Input Frequency (kHz)
400
0
500
100
D001
SNR = 74.6 dB, THD = –83.4 dB, ENOB = 12.1 bits
200
300
fIN, Input Frequency (kHz)
400
500
D002
SNR = 72.8 dB, THD = –97.8 dB, fIN = 100 kHz
Figure 3. Typical FFT
Figure 4. Typical FFT
0
76
SNR
SINAD
75
SNR, SINAD (dB)
Amplitude (dB)
-50
-100
-150
74
73
-200
0
100
200
300
fIN, Input Frequency (kHz)
400
72
-40
500
-7
D003
26
59
Free-Air Temperature (qC)
92
125
D005
SNR = 72.9dB, THD = –88.1 dB, fIN = 200 kHz
Figure 5. Typical FFT
Figure 6. SNR and SINAD vs Temperature
76
80
SNR
SINAD
SNR
SINAD
75
SNR, SINAD (dB)
SNR, SINAD (dB)
78
76
74
74
73
72
70
0
50
100
150
fIN, Input Frequency (kHz)
200
72
1.8
D006
Figure 7. SNR and SINAD vs Input Frequency
2.16
2.52
2.88
AVDD Voltage (V)
3.24
3.6
D007
Figure 8. SNR and SINAD vs Reference Voltage (AVDD)
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, DVDD = 1.8 V, fIN = 2 kHz, and fsample = 1 MSPS (unless otherwise noted)
-86
Total Harmonic Distortion (dB)
Total Harmonic Distortion (dB)
-83
-85
-87
-89
-91
-93
-40
-88
-90
-92
-94
-96
-7
26
59
Free-Air Temperature (qC)
92
125
0
50
D008
Figure 9. THD vs Temperature
Spurious-Free Dynamic Range (dB)
Total Harmonic Distortion (dB)
D010
Figure 10. THD vs Input Frequency
-82
-84
-86
-88
-90
1.8
2.16
2.52
2.88
AVDD Voltage (V)
3.24
97
94
91
88
85
-40
3.6
-7
D012
Figure 11. THD vs Reference Voltage (AVDD)
26
59
Free-Air Temperature (qC)
92
125
D009
Figure 12. SFDR vs Temperature
100
96
Spurious-Free Dynamic Range (dB)
Spurious-Free Dynamic Range (dB)
200
100
-80
97
94
91
88
85
0
50
100
150
fIN, Input Frequency (kHz)
200
94
92
90
88
86
1.8
2.16
D011
Figure 13. SFDR vs Input Frequency
10
100
150
fIN, Input Frequency (kHz)
2.52
2.88
AVDD Voltage (V)
3.24
3.6
D013
Figure 14. SFDR vs Reference Voltage (AVDD)
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Typical Characteristics (continued)
1
3
0.6
1.8
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
at TA = 25°C, AVDD = 3.3 V, DVDD = 1.8 V, fIN = 2 kHz, and fsample = 1 MSPS (unless otherwise noted)
0.2
-0.2
-0.6
-1
0.6
-0.6
-1.8
-3
0
3277
6554
9831
13108
16383
Code
0
3277
6554
9831
Figure 15. Typical DNL
Differential Nonlinearity (LSB)
Differential Nonlinearity (LSB)
Minimum
Maximum
0.6
0.2
-0.2
-0.6
-7
26
59
92
0.6
0.2
-0.2
-0.6
-1
1.8
125
2.16
D023
Free-Air Temperature (qC)
2.52
2.88
AVDD Voltage (V)
3.24
3.6
D024
Figure 18. DNL vs Reference Voltage
Figure 17. DNL vs Temperature
3
3
Minimum
Maximum
Minimum
Maximum
1.8
Integral Nonlinearity (LSB)
Integral Nonlinearity (LSB)
D020
1
Minimum
Maximum
0.6
-0.6
-1.8
-3
-40
16383
Figure 16. Typical INL
1
-1
-40
13108
Code
D019
-7
26
59
92
Free-Air Temperature (qC)
125
1.8
0.6
-0.6
-1.8
-3
1.8
D025
2.16
2.52
2.88
AVDD Voltage (V)
3.24
3.6
D026
Figure 20. INL vs Reference Voltage
Figure 19. INL vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, DVDD = 1.8 V, fIN = 2 kHz, and fsample = 1 MSPS (unless otherwise noted)
9
30000
Offset (LSB)
24000
Number of Hits
Calibrated
Uncalibrated
6
18000
12000
3
0
-3
6000
-6
-9
-40
0
8121
8122
8123
8124 8125
Code
8126
8127
8128
-7
D014
Figure 21. DC Input Histogram
0.06
Gain Error (%FS)
Offset (LSB)
D015
Calibrated
Uncalibrated
3
0
-3
0.02
-0.02
-0.06
-6
2.16
2.52
2.88
AVDD Voltage (V)
3.24
-0.1
-40
3.6
-7
D016
26
59
92
125
D017
Free-Air Temperature (qC)
Figure 23. Offset vs Reference Voltage (AVDD)
Figure 24. Gain Error vs Temperature
1
0.5
0.8
0.4
Supply Current (mA)
Supply Current (mA)
125
Figure 22. Offset vs Temperature
Calibrated
Uncalibrated
6
0.6
0.4
0.3
0.2
0.1
0.2
0
-7
26
59
Free-Air Temperature (qC)
92
125
0
D027
Figure 25. AVDD Current vs Temperature
12
92
0.1
9
0
-40
59
Free-Air Temperature (qC)
VIN = AVDD / 2
-9
1.8
26
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200
400
600
Throughput (kSPS)
800
1000
D028
Figure 26. AVDD Current vs Throughput
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Typical Characteristics (continued)
1
1000
0.8
800
IAVDD Static (nA)
Supply Current (mA)
at TA = 25°C, AVDD = 3.3 V, DVDD = 1.8 V, fIN = 2 kHz, and fsample = 1 MSPS (unless otherwise noted)
0.6
0.4
600
400
200
0.2
0
1.8
2.16
2.52
2.88
AVDD Voltage (V)
3.24
0
-40
3.6
-7
26
59
Free-Air Temperature (qC)
D029
92
125
D030
CS = DVDD
Figure 28. Static AVDD Current vs Temperature
800
2000
D031
4000 Devices
1
0.
08
06
0.
04
0.
0.
0
02
0.
.0
2
.0
4
-0
-0
-0
.1
6
5
4
3
2
1
0
-1
-2
0
-3
0
-4
500
-5
200
.0
6
1000
.0
8
400
1500
-0
600
-0
Frequency
2500
-6
Frequency
Figure 27. AVDD Current vs AVDD Voltage
1000
4000 Devices
Figure 29. Typical Offset Error Distribution
D032
Figure 30. Typical Gain Error Distribution
3000
Frequency
2400
1800
1200
600
4000 Devices
3
5
2.
2
1
1.
5
0
0.
5
-0
.5
-1
-2
-1
.5
-3
-2
.5
0
D033
Figure 31. Typical INL Distribution
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7 Parameter Measurement Information
7.1 Digital Voltage Levels
The device complies with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V. Figure 32 shows voltage
levels for the digital input and output pins.
Digital Output
DVDD
VOH
DVDD-0.45V
SDO
0.45V
VOL
0V
ISource= 2 mA, ISink = 2 mA,
DVDD = 1.65 V to 1.95 V
Digital Inputs
DVDD + 0.3V
VIH
0.65DVDD
CS
SCLK
0.35DVDD
-0.3V
VIL
DVDD = 1.65 V to 1.95 V
Figure 32. Digital Voltage Levels as per the JESD8-7A Standard
14
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8 Detailed Description
8.1 Overview
The ADS7052 device belongs to a family of pin-to-pin compatible, high-speed, low-power, single-channel
successive-approximation register (SAR) type analog-to-digital converters (ADCs). The device family includes
multiple resolutions, throughputs, and analog input variants (see Table 1 for a list of devices).
The ADS7052 is a 14-bit, 1-MSPS SAR ADC that supports a single-ended input in the range of 0 V to AVDD, for
AVDD in the range of 1.65 V to 3.6 V (see the Analog Input section for details on the analog input pins).
The internal offset calibration feature (see the OFFCAL State section) maintains excellent offset specifications
over the entire AVDD and temperature operating range.
The device supports an SPI-compatible serial interface that is controlled by the CS and SCLK signals. The input
signal is sampled with the CS falling edge and SCLK is used for both, conversion and serial data output (see the
Device Functional Modes section, Timing Requirements table, and Switching Characteristics table).
The device supports a wide digital supply range (1.65 V to 3.6 V), enabling direct interfacing to a variety of host
controllers. The ADS7052 complies with the JESD8-7A standard (see the Digital Voltage Levels section) for a
normal DVDD range (1.65 V to 1.95 V).
The ADS7052 is available in an 8-pin, small, X2QFN package (see the Mechanical, Packaging, and Orderable
Information section for more details) and is specified over the extended industrial temperature range (–40°C to
+125°C).
The small form-factor and extremely-low power consumption make this device suitable for space-constrained and
battery-powered applications that require high-speed, high-resolution data acquisition (see the Application
Information section).
8.2 Functional Block Diagram
AVDD
DVDD
GND
Offset
Calibration
AINP
CS
CDAC
Comparator
SCLK
Serial
Interface
AINM
SDO
SAR
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8.3 Feature Description
8.3.1 Product Family
The devices listed in Table 1 are all part of the same pin-to-pin compatible, high-speed, low-power, singlechannel SAR ADC family. This device family includes multiple different ADC resolutions, throughputs, and analog
input types to allow for greater flexibility in the end system. Devices in the same package are pin-compatible to
offer a scalable family of devices for varying levels of end-system performance. The ADCs with device numbers
ending in -Q1 are also AEC-Q100 qualified for automotive applications.
Table 1. Device Family Comparison
DEVICE NUMBER
RESOLUTION (Bits)
THROUGHPUT
(MSPS)
INPUT TYPE
PACKAGES (1)
ADS7040
8
1
Single-ended
X2QFN (8): 1.5 mm × 1.5 mm
VSSOP (8): 2.0 mm × 3.1 mm
ADS7041
10
1
Single-ended
X2QFN (8): 1.5 mm × 1.5 mm
VSSOP (8): 2.0 mm × 3.1 mm
ADS7042
12
1
Single-ended
X2QFN (8): 1.5 mm × 1.5 mm
VSSOP (8): 2.0 mm × 3.1 mm
ADS7043
12
1
Pseudo-differential
X2QFN (8): 1.5 mm × 1.5 mm
VSSOP (8): 2.0 mm × 3.1 mm
ADS7044
12
1
Fully-differential
X2QFN (8): 1.5 mm × 1.5 mm
VSSOP (8): 2.0 mm × 3.1 mm
ADS7029-Q1
8
2
Single-ended
VSSOP (8): 2.0 mm × 3.1 mm
ADS7039-Q1
10
2
Single-ended
VSSOP (8): 2.0 mm × 3.1 mm
ADS7049-Q1
12
2
Single-ended
VSSOP (8): 2.0 mm × 3.1 mm
ADS7046
12
3
Single-ended
X2QFN (8): 1.5 mm × 1.5 mm
ADS7047
12
3
Fully-differential
X2QFN (8): 1.5 mm × 1.5 mm
ADS7052
14
1
Single-ended
X2QFN (8): 1.5 mm × 1.5 mm
ADS7054
14
1
Fully-differential
X2QFN (8): 1.5 mm × 1.5 mm
ADS7056
14
2.5
Single-ended
X2QFN (8): 1.5 mm × 1.5 mm
ADS7057
14
2.5
Fully-differential
X2QFN (8): 1.5 mm × 1.5 mm
(1)
16
Devices listed in the same package are pin-compatible.
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8.3.2 Analog Input
The device supports a unipolar, single-ended analog input signal. Figure 33 shows a small-signal equivalent
circuit of the sample-and-hold circuit. The sampling switch is represented by a resistance (RS1 and RS2, typically
50 Ω) in series with an ideal switch (SW1 and SW2). The sampling capacitors, CS1 and CS2, are typically 16 pF.
AVDD
SW1
Rs1
AINP
Cs1
GND
V_BIAS
AVDD
Cs2
SW2
Rs2
AINM
GND
Figure 33. Equivalent Input Circuit for the Sampling Stage
During the acquisition process, both positive and negative inputs are individually sampled on CS1 and CS2,
respectively. During the conversion process, the device converts for the voltage difference between the two
sampled values: VAINP – VAINM.
Each analog input pin has electrostatic discharge (ESD) protection diodes to AVDD and GND. Keep the analog
inputs within the specified range to avoid turning the diodes on.
The full-scale analog input range (FSR) is 0 V to AVDD.
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8.3.3 Reference
The device uses the analog supply voltage (AVDD) as the reference voltage for the analog to digital conversion.
During the conversion process, the internal capacitors are switched to the AVDD pin as per the successive
approximation algorithm. A voltage reference must be selected with low temperature drift, high output current
drive and low output impedance. TI recommends a 3.3-µF (CAVDD), low equivalent series resistance (ESR)
ceramic capacitor between the AVDD and GND pins. This decoupling capacitor provides the instantaneous
charge required by the internal circuit during the conversion process and maintains a stable dc voltage on the
AVDD pin.
See the Power Supply Recommendations and Layout Example sections for component recommendations and
layout guidelines.
AVDD
CAVDD
GND
CDVDD
DVDD
Figure 34. Reference for the Device
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8.3.4 ADC Transfer Function
The device supports a unipolar, single-ended analog input signal. The output is in straight binary format.
Figure 35 and Table 2 show the ideal transfer characteristics for the device.
The least significant bit for the device is given by:
1 LSB = VREF / 2N
where:
•
•
VREF = Voltage applied between the AVDD and GND pins
N = 14
(1)
ADC Code (Hex)
PFSC
MC + 1
MC
NFSC+1
NFSC
VREF
2
1 LSB
VIN
V REF
2
VREF ± 1 LSB
1LSB
Single-Ended Analog Input
(AINP ± AINM)
Figure 35. Ideal Transfer Characteristics
Table 2. Transfer Characteristics
INPUT VOLTAGE (AINP – AINM)
CODE
DESCRIPTION
IDEAL OUTPUT CODE
(Hex)
≤ 1 LSB
NFSC
Negative full-scale code
0000
1 LSB to 2 LSBs
NFSC + 1
—
0001
VREF / 2 to VREF / 2 + 1 LSB
MC
Mid code
1FFF
VREF / 2 + 1 LSB to VREF / 2 + 2 LSB
MC + 1
—
2000
≥ VREF – 1 LSB
PFSC
Positive full-scale code
3FFF
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8.4 Device Functional Modes
The device supports a simple, SPI-compatible interface to the external host. On power-up, the device is in the
ACQ state. The CS signal defines one conversion and serial data transfer frame. A frame starts with a CS falling
edge and ends with a CS rising edge. The SDO pin is tri-stated when CS is high. With CS low, the clock
provided on the SCLK pin is used for conversion and data transfer. Output data are available on the SDO pin.
As shown in Figure 36, the device supports three functional states: acquisition (ACQ), conversion (CNV), and
offset calibration (OFFCAL). The device status depends on the CS and SCLK signals provided by the host
controller.
ACQ
Ca
lib
End of Conversion
OFFCAL
Falling Edge of CS
or
n
io
t
ra
lib f CS
a
p
tC eo
-U
fse Edg
er
f
w
O
Po
of ng
d isi
on
n
En R
io
at
br
i
l
Ca
ra
tio
Op n du
e r ri n
at g
io N
n
or
m
al
CONV
Figure 36. Functional State Diagram
8.4.1 ACQ State
In the ACQ state, switches SW1 and SW2 connected to the analog input pins close and the device acquires the
analog input signal on CS1 and CS2. The device enters ACQ state at power-up, at the end of every conversion,
and after completing the offset calibration. A CS falling edge takes the device from the ACQ state to the CNV
state.
The device consumes extremely low power from the AVDD and DVDD power supplies when in ACQ state.
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Device Functional Modes (continued)
8.4.2 CNV State
In the CNV state, the device uses the external clock to convert the sampled analog input signal to an equivalent
digital code as per the transfer function illustrated in Figure 35. The conversion process requires a minimum of
18 SCLK falling edges to be provided within the frame. After the end of conversion process, the device
automatically moves from the CNV state to the ACQ state. For acquisition of the next sample, a minimum time of
tACQ must be provided.
Figure 37 shows a detailed timing diagram for the serial interface. In the first serial transfer frame after power-up,
the device provides the first data as all zeros. In any frame, the clocks provided on the SCLK pin are also used to
transfer the output data for the previous conversion. A leading 0 is output on the SDO pin on the CS falling edge.
The most significant bit (MSB) of the output data is launched on the SDO pin on the rising edge after the first
SCLK falling edge. Subsequent output bits are launched on the subsequent rising edges provided on SCLK.
When all 14 output bits are shifted out, the device outputs 0's on the subsequent SCLK rising edges. The device
enters the ACQ state after 18 clocks and a minimum time of tACQ must be provided for acquiring the next sample.
If the device is provided with less than 18 SCLK falling edges in the present serial transfer frame, the device
provides an invalid conversion result in the next serial transfer frame.
Sample
A+1
Sample
A
tph_CS
tCYCLE
tACQ
tCONV
CS
SCLK
SDO
1
2
0
3
D13
15
D12
16
D0
17
0
0
18
0
Data Output for Sample A-1
Figure 37. Serial Interface Timing Diagram
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Device Functional Modes (continued)
8.4.3 OFFCAL State
In the offset calibration (OFFCAL) state, the sampling capacitors are disconnected from the analog input pins
(AINP and AINM) and the device calibrates and corrects for any internal offset errors. The offset calibration is
effective for all subsequent conversions until the device is powered off. An offset calibration cycle is
recommended at power-up and whenever there is a significant change in the operating conditions for the device
(such as in the AVDD voltage and operating temperature).
The host controller must provide a serial transfer frame as described in Figure 38 or in Figure 39 to enter the
OFFCAL state.
8.4.3.1 Offset Calibration on Power-Up
On power-up, the host must provide 24 SCLKs in the first serial transfer to enter the OFFCAL state. The device
provides 0's on SDO during offset calibration. For acquisition of the next sample, a minimum time of tACQ must be
provided.
If the host controller starts the offset calibration process but then pulls the CS pin high before providing 24
SCLKs, then the offset calibration process is aborted and the device enters the ACQ state. Figure 38 and
Table 3 provide the timing for offset calibration on power-up.
First
Sample
Next
Sample
tCYCLE
tACQ
CS
SCLK
SDO
1
2
0
4
3
0
24
0
0
0
0
Data Output for First Sample
Figure 38. Timing for Offset Calibration on Power-Up
Table 3. Timing Specifications for Offset Calibration on Power-Up (1)
MIN
tcycle
Cycle time for offset calibration on power-up
tACQ
Acquisition time
fSCLK
Frequency of SCLK
(1)
22
TYP
MAX
UNIT
24 × tCLK + tACQ
ns
230
ns
24
MHz
In addition to the timing specifications of Figure 38 and Table 3, the timing specifications described in Figure 2 and the Timing
Requirements table are also applicable for offset calibration on power-up.
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8.4.3.2 Offset Calibration During Normal Operation
During normal operation, the host must provide 64 SCLKs in the serial transfer frame to enter the OFFCAL state.
The device provides the conversion result for the previous sample during the first 18 SCLKs and 0's on SDO for
the rest of the SCLKs in the serial transfer frame. For acquisition of the next sample, a minimum time of tACQ
must be provided.
If the host controller provides more than 18 SCLKs but pulls the CS high before providing 64 SCLKs, then the
offset calibration process is aborted and the device enters the ACQ state. Figure 39 and Table 4 provide the
timing for offset calibration during normal operation.
Sample
A
Sample
A+1
tCYCLE
tACQ
CS
SCLK
1
2
0
SDO
D13
16
4
3
D12
D0
17
64
0
0
Data Output for Sample A-1
Figure 39. Timing for Offset Calibration During Normal Operation
Table 4. Timing Specifications for Offset Calibration During Normal Operation (1)
MIN
tcycle
Cycle time for offset calibration on power-up
tACQ
Acquisition time
fSCLK
Frequency of SCLK
(1)
TYP
MAX
UNIT
64 × tCLK + tACQ
ns
230
ns
24
MHz
In addition to the timing specifications of Figure 39 and Table 4, the timing specifications described in Figure 2 and the Timing
Requirements table are also applicable for offset calibration during normal operation.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The two primary supporting circuits required to maximize the performance of a high-precision, successive
approximation register (SAR) analog-to-digital converter (ADC) are the input driver and the reference driver
circuits. This section details some general principles for designing the input driver circuit, reference driver circuit,
and provides typical application circuits designed for the device.
9.2 Typical Applications
9.2.1 Single-Supply Data Acquisition With the ADS7052
Reference Driver
REF1933
(AVDD + 0.2V) to 5.5 V
VIN
VOUT
GND
1uF
3.3uF
AVDD
3.3V
OPA_VDD
33
±
VDD
VIN
+
SPI
OPA836
+
VSOURCE
Device
Host
Controller
±
680pF
GND
GND
ADC
Input Driver
Figure 40. DAQ Circuit: Single-Supply DAQ
9.2.1.1 Design Requirements
The goal of the circuit shown in Figure 40 is to design a single-supply data acquisition (DAQ) circuit based on the
ADS7052 with SNR greater than 74 dB and THD less than –85 dB for input frequencies of 2 kHz at a throughput
of 1 MSPS for applications such as low power data acquisition systems, sensor monitoring, and environmental
sensing.
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Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and charge
kickback filter. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a
high-precision ADC.
9.2.1.2.1 Low Distortion Charge Kickback Filter Design
Figure 41 shows the input circuit of a typical SAR ADC. During the acquisition phase, the SW switch closes and
connects the sampling capacitor (CSH) to the input driver circuit. This action introduces a transient on the input
pins of the SAR ADC. An ideal amplifier with 0 Ω of output impedance and infinite current drive can settle this
transient in zero time. For a real amplifier with non-zero output impedance and finite drive strength, this switched
capacitor load can create stability issues.
Charge Kickback Filter
-
RFLT
SAR ADC
SW
+
VIN
CSH
CFLT
f-3dB =
1
2 Πx RFLT x CFLT
Figure 41. Input Sample-and-Hold Circuit for a Typical SAR ADC
For ac signals, the filter bandwidth must be kept low to band-limit the noise fed into the ADC input, thereby
increasing the signal-to-noise ratio (SNR) of the system. Besides filtering the noise from the front-end drive
circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage
of the ADC. A filter capacitor, CFLT, is connected across the ADC inputs. This capacitor helps reduce the
sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold
capacitors during the acquisition process. As a rule of thumb, the value of this capacitor is at least 20 times the
specified value of the ADC sampling capacitance. For this device, the input sampling capacitance is equal to
16 pF. Thus, the value of CFLT is greater than 320 pF. Select a COG- or NPO-type capacitor because these
capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying
voltages, frequency, and time.
Driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design.
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Typical Applications (continued)
9.2.1.2.2 Input Amplifier Selection
The input amplifier bandwidth is typically much higher than the cutoff frequency of the charge kickback filter.
Thus, TI strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40°
phase margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some
amplifiers can require more bandwidth than others to drive similar filters. To learn more about the SAR ADC
input driver design, see the TI Precision Labs training video series.
For the application circuit of Figure 40, the OPA836 is selected for its high bandwidth (205 MHz), low noise
(4.6 nV/√Hz), high output drive capacity (45 mA), and fast settling response (22 ns for 0.1% settling).
9.2.1.2.3 Reference Circuit
The ADS70xx uses the analog supply voltage (AVDD) as the reference voltage for the analog to digital
conversion. During the conversion process, the internal capacitors are switched to the level of the AVDD pin as
per the successive approximation algorithm. A voltage reference must be selected with low temperature drift,
high output current drive and low output impedance. For this application, the REF1933 was selected as the
voltage reference and analog power supply for the ADC. The REF1933 has excellent temperature drift
performance (25 ppm/°C), good initial accuracy (0.1%), high output drive capability (25 mA), and low quiescent
current (360 µA). The REF1933 also provides a bias voltage output of half the reference voltage (VREF/2) which
can be used as the common mode input for the amplifier.
TI recommends a 3.3-µF (CAVDD), low equivalent series resistance (ESR) ceramic capacitor between the AVDD
and GND pins. This decoupling capacitor provides the instantaneous charge required by the internal circuit
during the conversion process and maintains a stable dc voltage on the AVDD pin.
9.2.1.3 Application Curve
Figure 42 provides the measurement result for the circuit described in Figure 40.
0
Amplitude (dB)
-50
-100
-150
-200
0
100
200
300
fIN, Input Frequency (kHz)
400
500
D001
SNR = 75.3 dB, THD = –90.1 dB, SINAD = 75 dB
Figure 42. Test Results for the ADS7052 and OPA836 for a 2-kHz Input
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Typical Applications (continued)
9.2.2 High Bandwidth (200 kHz) Data Acquisition With the ADS7052
Reference Driver
REF1933
(AVDD + 0.2V) to 5.5 V
VIN
VOUT
GND
1uF
3.3uF
499
AVDD
3.3V
+6V
499
10
±
VIN
AVDD
+
VIN
+
±
SPI
THS4031
Device
Host
Controller
VCM = 0.825V
-6V
470pF
GND
Input Driver
ADC
Figure 43. High Bandwidth DAQ Circuit
9.2.2.1 Design Requirements
Applications such as motor control feedback loops, motor encoders, global positioning systems (GPS), and
optical modules need analog-to-digital converters that are interfaced to high-frequency sensors (200 kHz to
1 MHz). The goal of the circuit described in Figure 43 is to design a circuit based on the ADS7052 with SNR
greater than 73 dB and THD less than –85 dB for input frequencies of 200 kHz at a throughput of 1 MSPS.
9.2.2.2 Detailed Design Procedure
To achieve a SINAD greater than 73 dB and THD less than –85 dB, the operational amplifier must have high
bandwidth in order to settle the input signal within the acquisition time of the ADC. The operational amplifier must
have low noise to keep the total system noise below 20% of the input-referred noise of the ADC. For the
application circuit shown in Figure 43, the THS4031 is selected for its high bandwidth (275 MHz), low total
harmonic distortion of –90 dB at 1 MHz, and ultra-low noise of 1.6 nV/√Hz. The THS4031 is powered up from
dual power supply (VDD = 6 V and VSS = –6 V).
For this application, the REF1933 was selected as the voltage reference and analog power supply for the ADC.
The REF1933 has excellent temperature drift performance (25 ppm/°C), good initial accuracy (0.1%), high output
drive capability (25 mA), and low quiescent current (360 µA). The REF1933 also provides a bias voltage output
of half the reference voltage (VREF / 2) that can be used as the common-mode input for the amplifier.
The SNR performance at higher input frequency is highly dependant on jitter on the sampling signal (CS). TI
recommends selecting a clock source that has very low jitter (< 20-ps RMS).
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Typical Applications (continued)
9.2.2.3 Application Curve
Figure 44 shows the FFT plot for the ADS7052 with a 200-kHz input frequency used for the circuit in Figure 43.
0
Amplitude (dB)
-50
-100
-150
-200
0
100
200
300
fIN, Input Frequency (kHz)
400
500
D003
SNR = 74.2 dB, THD = –90.4 dB, SINAD = 74 dB
Figure 44. Test Results for the ADS7052 and THS4031 for a 200-kHz Input
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Typical Applications (continued)
9.2.3 14-Bit, 10-kSPS DAQ Circuit Optimized for DC Sensor Measurements
AVDD
Sensor
RSOURCE
AVDD
AINP
+
TI Device
±
CFLT
AINM
GND
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Figure 45. Interfacing the Device Directly With Sensors
In applications where the input is very slow moving and the overall system ENOB is not a critical parameter, a
DAQ circuit can be designed without the input driver for the ADC. This type of a use case is of particular interest
for applications in which the primary goal is to achieve the absolute lowest power possible. Typical applications
that fall into this category are low-power sensor applications (such as temperature, pressure, humidity, gas, and
chemical).
9.2.3.1 Design Requirements
For this design example, use the parameters listed in Table 5 as the input parameters.
Table 5. Design Parameters
DESIGN PARAMETER
GOAL VALUE
Throughput
10 kSPS
SNR at 100 Hz
74 dB
THD at 100 Hz
–85 dB
SINAD at 100 Hz
73 dB
ENOB
12 bits
Power
20 µW
9.2.3.2 Detailed Design Procedure
The ADS7052 can be directly interfaced with sensors at lower throughput without the need of an amplifier buffer,
however, the output impedance of the sensor must be taken into account. The sensor must be capable of driving
the switched capacitor load of a SAR ADC and settling the analog input signal within the acquisition time of the
SAR ADC. Figure 45 shows the simplified circuit for a sensor as a voltage source with output impedance
(Rsource). As the output impedance of the sensor increases, the device requires more acquisition time to settle the
input signal to the desired accuracy.
The acquisition time of a SAR ADC (such as the ADS7052 ) can be increased by reducing throughput in the
following ways:
1. Reducing the SCLK frequency to reduce the throughput or
2. Keeping the SCLK fixed at the highest permissible value (that is, 24 MHz for the device) and increasing the
CS high time
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Table 6 lists the acquisition time for the above two cases for a throughput of 10 kSPS. Clearly, case 2 provides
more acquisition time for the input signal to settle.
Table 6. Acquisition Time With Different SCLK Frequencies
CONVERSION TIME
(= 18 × tSCLK)
ACQUISITION TIME
(= tcycle – tconv)
CASE
SCLK
tcycle
1
0.24 MHz
100 µs
75 µs
25 µs
2
24 MHz
100 µs
0.75 µs
99.25 µs
9.2.3.3 Application Curve
Figure 46 provides the results for ENOB achieved from the ADS7052 for case 2 at different throughputs with
different values of sensor output impedance.
12.5
ENOB (Bits)
12
11.5
11
10.5
33Ohm, 680pF
330Ohm, 680pF
3.3kOhm, 680pF
10kOhm, 680pF
20kOhm, 680pF
10
9.5
2
22
42
62
Sampling Speed(kSPS)
82
100
D039
Figure 46. Effective Number of Bits (ENOB) Achieved From the ADS7052 at Different Throughputs
Table 7 shows the results and performance summary for this 14-bit, 10-kSPS DAQ circuit application with a
sensor output impedance of 22 kΩ.
Table 7. Results and Performance Summary for a 14-Bit, 10-kSPS DAQ Circuit for DC Sensor
Measurements
30
DESIGN PARAMETER
GOAL VALUE
ACHIEVED RESULT
10 kSPS
Throughput
10 kSPS
SNR at 100 Hz
74 dB
75 dB
THD at 100 Hz
–85 dB
–89 dB
SINAD at 100 Hz
73 dB
74.3 dB
ENOB
12 bits
12.05 bits
Power
20 µW
17 µW
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10 Power Supply Recommendations
10.1 AVDD and DVDD Supply Recommendations
The device has two separate power supplies: AVDD and DVDD.
AVDD powers the analog blocks and is also used as the reference voltage for the analog-to-digital conversion.
Use a low-noise, low-dropout regulator (LDO) or a discrete reference to supply AVDD (see the Reference and
Application Information sections). Always set the AVDD supply to be greater than or equal to the maximum input
signal to avoid code saturation. Decouple the AVDD pin to the GND pin with a 3.3-µF ceramic decoupling
capacitor.
DVDD is used for the interface circuits. Decouple the DVDD pin to the GND pin with a 1-µF ceramic decoupling
capacitor. Figure 47 shows the decoupling recommendations.
AVDD
CAVDD
GND
CDVDD
DVDD
Figure 47. Power-Supply Decoupling
10.2 Optimizing Power Consumed by the Device
In order to best optimize the power consumed by the device, use the following design considerations:
• Keep the analog supply voltage (AVDD) in the specified operating range and equal to the maximum analog
input voltage.
• Keep the digital supply voltage (DVDD) in the specified operating range and at the lowest value supported by
the host controller.
• Reduce the load capacitance on the SDO output.
• Run the device at the optimum throughput. Power consumption reduces proportionally with the throughput.
10.2.1 Estimating Digital Power Consumption
The current consumption from the DVDD supply depends on the DVDD voltage, the load capacitance on the
SDO pin (CLOAD-SDO), and the output code, and can be calculated as:
IDVDD = CLOAD-SDO × V × f
where:
•
•
•
CLOAD-SDO = Load capacitance on the SDO pin
V = DVDD supply voltage
f = Frequency of transitions on the SDO output
(2)
The number of transitions on the SDO output depends on the output code, and thus changes with the analog
input. The maximum value of f occurs when data output on the SDO change on every SCLK (that is, for output
codes of 2AAAh or 1555h). With an output code of 2AAAh or 1555h, f = 7 MHz and when CLOAD-SDO = 20 pF and
DVDD = 1.8 V, IDVDD = 250 µA.
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11 Layout
11.1 Layout Guidelines
Figure 48 shows a typical connection diagram for the ADS7052.
AVDD
DVDD
CDVDD
CAVDD
RFLT
±
R
VDD
VIN
R
+
Device
+
VSOURCE
R
±
CFLT
GND
GND
Input Driver
Figure 48. Typical Connection Diagram
Figure 49 depicts a board layout example for the device for the typical connection diagram in Figure 48. The key
considerations for layout are:
• Use a solid ground plane underneath the device and partition the PCB into analog and digital sections
• Avoid crossing digital lines with the analog signal path and keep the analog input signals and the reference
input signals away from noise sources.
• The power sources to the device must be clean and well-bypassed. Use CAVDD decoupling capacitors in close
proximity to the analog (AVDD) power-supply pin.
• Use a CDVDD decoupling capacitor close to the digital (DVDD) power-supply pin.
• Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors.
• Connect the ground pin to the ground plane using a short, low-impedance path.
• Place the charge kickback filter components close to the device.
Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors are recommended because these
components provide the most stable electrical properties over voltage, frequency, and temperature changes.
32
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11.2 Layout Example
RFLT
CAVDD
AVDD
Plane
DVDD
GND
CFLT
AVDD
SDO
CS
AINM
AINP
CDVDD
SCLK
RAINM
GND
PLANE
Figure 49. Example Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
TI Precision Labs Training Video Series
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
Input Driver Amplifier (Single-Ended Inputs):
• OPAx836 Very-Low-Power, Rail-to-Rail Out, Negative-Rail In, Voltage-Feedback Operational Amplifiers
• THS403x 100-MHz Low-Noise High-Speed Amplifiers
• OPAx365 50-MHz, Zerø-Crossover, Low-Distortion, High CMRR, RRI/O, Single-Supply Operational
Amplifier
Input Driver Amplifier (Fully-Differential Inputs):
• THS4551 Low-Noise, Precision, 150-MHz, Fully Differential Amplifier
• OPAx836 Very-Low-Power, Rail-to-Rail Out, Negative-Rail In, Voltage-Feedback Operational Amplifiers
Reference Driver:
• REF19xx Low-Drift, Low-Power, Dual-Output, VREF and VREF / 2 Voltage References
• REF61xx High-Precision Voltage Reference With Integrated ADC Drive Buffer
Similar Devices:
• ADS7042 Ultra-Low Power, Ultra-Small Size, 12-Bit, 1-MSPS, SAR ADC
• ADS7049-Q1 Small-Size, Low-Power, 12-Bit, 2-MSPS, SAR ADC
Reference Designs:
• TI Design: Analog Front-End Reference Design for Imaging Using Time-Interleaved SAR ADCs With 73dB SNR, 7.5 MSPS
• Single-Ended to Differential Using an Op Amp and FDA for Bipolar Signals
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
34
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12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
RUG0008A
X2QFN - 0.4 mm max height
SCALE 7.500
PLASTIC QUAD FLATPACK - NO LEAD
1.55
1.45
B
A
PIN 1 INDEX AREA
1.55
1.45
C
0.4 MAX
SEATING PLANE
0.05
0.00
0.08 C
SYMM
2X
0.35
0.25
2X
4
3
(0.15)
TYP
0.45
0.35
5
SYMM
2X
1
4X 0.5
2X
7
1
4X
8
PIN 1 ID
(45 X0.1)
6X
0.4
0.3
0.25
0.15
0.3
0.2
0.1
0.05
C A
C
B
4222060/A 05/14/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
RUG0008A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.3)
2X (0.6)
8
6X (0.55)
1
7
4X (0.25)
SYMM
(1.3)
4X (0.5)
2X (0.2)
3
5
(R0.05) TYP
4
SYMM
(1.35)
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL
UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222060/A 05/14/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
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EXAMPLE STENCIL DESIGN
RUG0008A
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.3)
2X (0.6)
8
6X (0.55)
1
7
4X (0.25)
SYMM
(1.3)
4X (0.5)
2X (0.2)
3
5
4
SYMM
(1.35)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICKNESS
SCALE:25X
4222060/A 05/14/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Dec-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
ADS7052IRUGR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
X2QFN
RUG
8
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
9O
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jan-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADS7052IRUGR
Package Package Pins
Type Drawing
X2QFN
RUG
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
180.0
8.4
Pack Materials-Page 1
1.6
B0
(mm)
K0
(mm)
P1
(mm)
1.6
0.66
4.0
W
Pin1
(mm) Quadrant
8.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jan-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS7052IRUGR
X2QFN
RUG
8
3000
183.0
183.0
20.0
Pack Materials-Page 2
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