Texas Instruments | ADS7924 2.2 V, 12-Bit, 4-Channel, MicroPOWER Analog-to-Digital Converter With I2C Interface (Rev. C) | Datasheet | Texas Instruments ADS7924 2.2 V, 12-Bit, 4-Channel, MicroPOWER Analog-to-Digital Converter With I2C Interface (Rev. C) Datasheet

Texas Instruments ADS7924 2.2 V, 12-Bit, 4-Channel, MicroPOWER Analog-to-Digital Converter With I2C Interface (Rev. C) Datasheet
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ADS7924
SBAS482C – JANUARY 2010 – REVISED SEPTEMBER 2017
ADS7924 2.2 V, 12-Bit, 4-Channel, MicroPOWER
Analog-to-Digital Converter With I2C Interface
1 Features
3 Description
•
The ADS7924 is a four-channel, 12-bit, analog-todigital converter (ADC) with an I2C™ interface. With
its low-power ADC core, support for low-supply
operation, and a flexible measurement sequencer
that essentially eliminates power consumption
between conversions, the ADS7924 forms a complete
monitoring system for power-critical applications such
as battery-powered equipment and energy harvesting
systems.
1
•
•
•
Intelligent Monitoring:
– Auto-Sequencing of 4-Channel Multiplexer
– Individual Alarm Thresholds for Each Channel
– Programmable Scan Rate
MicroPOWER™ Monitoring:
– Four-Channel Scanning:
– Every 1 ms → 25 μW
– Every 10 ms → 5 μW
– < 1 µA of Power-Down Current
– Programmable Interrupt Pin Controls
Shutdown/Wakeup of the Microcontroller
– Auto Power-Down Control
– PWRCON Pin Allows Shutdown of External
Operational Amplifiers
Wide Supply Range:
– Analog Supply: 2.2 V to 5.5 V
– Digital Supply: 1.65 V to 5.5 V
Small Footprint: 3-mm × 3-mm WQFN
2 Applications
•
•
The ADS7924 features dedicated data registers and
onboard programmable digital threshold comparators
for each input. Alarm conditions can be programmed
that generate an interrupt. The combination of data
buffering, programmable threshold comparisons, and
alarm interrupts minimize the host microcontroller
time needed to supervise the ADS7924.
The four-channel input multiplexer (MUX) is routed
through external pins to allow a common signal
conditioning circuit to be used between the MUX and
ADC, thereby reducing overall component count. The
low-power ADC uses the analog supply as its
reference and can acquire and convert signals in only
10 μs. An onboard oscillator eliminates the need to
supply a master clock.
The ADS7924 is offered in a small 3-mm × 3-mm
WQFN and is fully specified for operation over the
industrial temperature range of –40°C to 85°C.
Portable and Battery-Powered Systems:
– Medical, Communications, Remote Sensor
Signal Monitoring, Power-Supply Monitoring
Energy Harvesting
Device Information(1)
PART NUMBER
ADS7924
PACKAGE
WQFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
MUX OUT
ADCIN
AVDD
DVDD
SDA
2
IC
Interface
CH0
CH1
CH2
4-Channel
MUX
SAR
ADC
Data Buffers,
Sequencer, and
Alarms
SCL
A0
INT
CH3
PWRCON
RESET
Oscillator
AGND
DGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS7924
SBAS482C – JANUARY 2010 – REVISED SEPTEMBER 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
I2C Timing Requirements..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 13
7.5 Programming........................................................... 20
7.6 Register Map........................................................... 26
8
Application and Implementation ........................ 33
8.1 Application Information............................................ 33
8.2 Typical Application ................................................. 39
9 Power Supply Recommendations...................... 41
10 Layout................................................................... 41
10.1 Layout Guidelines ................................................. 41
10.2 Layout Example .................................................... 41
11 Device and Documentation Support ................. 42
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
42
42
42
42
42
12 Mechanical, Packaging, and Orderable
Information ........................................................... 42
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2015) to Revision C
Page
•
Changed QFN to WQFN throughout document .................................................................................................................... 1
•
Changed direction of RESET arrow in Simplified Schematic figure....................................................................................... 1
•
Changed maximum operating temperature range in Absolute Maximum Ratings table ........................................................ 4
•
Changed direction of RESET arrow in Functional Block Diagram figure ............................................................................ 10
•
Changed description of bits 7:5 in INTCONFIG: Interrupt Configuration Register .............................................................. 30
Changes from Revision A (May 2010) to Revision B
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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5 Pin Configuration and Functions
(1)
DVDD
AVDD
ADCIN
MUXOUT
15
14
13
8
4
AGND
SDA
(1)
7
3
Pad
PWRCON
SCLK
Thermal
6
2
DGND
INT
5
1
A0
RESET
16
RTE Package
16-Pin WQFN
Top View
12
CH0
11
CH1
10
CH2
9
CH3
Connect to AGND.
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
RESET
Digital input
2
INT
Digital output
3
SCLK
Digital input
Serial clock input
4
SDA
Digital
input/output
Serial data
5
A0
Digital input
I2C address selection
External reset, active low
Interrupt pin, active low; generated when input voltage is beyond programmed threshold
6
DGND
Digital
7
PWRCON
Digital output
Digital ground
8
AGND
Analog
Analog ground
9
CH3
Analog input
Input channel 3
10
CH2
Analog input
Input channel 2
11
CH1
Analog input
Input channel 1
12
CH0
Analog input
Input channel 0
13
MUXOUT
Analog output
14
ADCIN
Analog input
15
AVDD
Analog
Analog supply
16
DVDD
Digital
Digital supply
Power control pin to control shutdown/power-up of external operational amplifier
Multiplexer output
ADC input
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted. (1)
MIN
MAX
UNIT
Supply voltage, AVDD to AGND
–0.3
6
V
Supply voltage, DVDD to DGND
–0.3
6
V
Supply voltage, DVDD to AVDD
AVDD ≥ DVDD
AGND to DGND
V
–0.3
0.3
V
Analog input voltage
AGND – 0.3
0.3
V
Digital input voltage with respect to DGND (SCL and SDA)
DGND – 0.3
6
V
Digital input voltage with respect to DGND (A0, RESET)
DGND – 0.3
DVDD + 0.3
V
Input current to all pins except supply pins
–10
10
mA
Maximum operating temperature
–40
85
°C
Storage temperature
–60
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
AVDD
Analog Supply Voltage
2.2
5.5
V
DVDD
Digital Supply Voltage
1.65
AVDD
V
6.4 Thermal Information
ADS7924
THERMAL METRIC (1)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
48.1
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
47.3
°C/W
RθJB
Junction-to-board thermal resistance
60.8
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
14.1
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
0.4
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Minimum and maximum specifications are at TA = –40°C to 85°C, 1.65 V < DVDD < 5.5 V, and 2.2 V < AVDD < 5.5 V.
Typical specifications are at TA = 25°C, AVDD = 5 V, and DVDD = 5 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input span
(CHX – AGND)
0
Input capacitance (1)
4
AVDD
V
10
pF
ADC sampling capacitance
15
MUX resistance
60
pF
Ω
Input channel crosstalk
85
dB
12
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
12
Integral linearity
Bits
–1.5
±0.5
1.5
LSBs
Differential linearity
–1
±0.6
1.5
LSBs
Offset error
–5
Offset error drift
5
0.01
Gain error
–0.2%
Gain error drift
–0.01%
0.2%
0.6
Noise (rms)
LSBs
LSB/°C
ppm/°C
0.125
LSB
SAMPLING DYNAMICS
Monitoring time/channel (2)
10
µs
CLOCK
Internal clock frequency variation
±20%
DIGITAL INPUT/OUTPUT
Logic family
CMOS
Logic level:
VIH (SDA, SCL, A0, RESET)
0.8 DVDD
DVDD + 0.3
VIL (SDA, SCL, A0, RESET)
DGND – 0.3
0.4
V
VI = DVDD or DGND
–10
10
μA
IOH = 100 μA, INT pin
0.8 DVDD
DVDD
V
IOH = 100 µA, PWRCON pin
0.8 AVDD
AVDD
V
DGND
0.4
Input current
II
VOH (PWRCON, INT)
VOL (PWRCON, INT, SDA)
IOL = 100 μA
Low-level output current
IOL
SDA pin, VOL = 0.6 V
Load capacitance
CB
SDA pin
Data format
V
V
3
mA
400
pF
5.5
V
Straight binary
POWER-SUPPLY REQUIREMENTS
Power-supply voltage:
DVDD (3)
1.65
AVDD
IAVDD (4)
2.2
tCYCLE = 2.5 ms, AVDD = 2.2 V
5
IPWRD, power-down current
5.5
V
8
μA
<1
μA
TEMPERATURE RANGE
Specified performance
(1)
(2)
(3)
(4)
–40
85
°C
CH0 to CH3 input pin capacitance.
Rate at which channels can be scanned. This is the minimum acquisition time (6 µs) and conversion time (4 µs).
DVDD cannot exceed AVDD.
See Figure 3 and Figure 4 for more information.
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6.6 I2C Timing Requirements
MIN
MAX
UNIT
0
0.4
MHz
fSCL
SCL operating frequency
tBUF
Bus free time between START and STOP condition
1.3
μs
tHDSTA
Hold time after repeated START condition.
After this period, the first clock is generated.
600
ns
tSUSTA
Repeated START condition setup time
600
ns
tSUSTO
Stop condition setup time
600
ns
tHDDAT
Data hold time
tSUDAT
Data setup time
tLOW
0
ns
100
ns
SCL clock low period
1300
ns
tHIGH
SCL clock high period
600
tF
Clock/data fall time
300
ns
tR
Clock/data rise time
300
ns
tVDDAT
Data valid time
0.9
μs
tVDACK
Data valid acknowledge time
tSP
Pulse width of spike that must be suppressed by the input filter
tVDDAT
tR
tHIGH
tVDACK
0
ns
0.9
μs
50
ns
tHDSTA
tF
tLOW
SCL
tSUDAT
tHDSTA
9th Clock
tSUSTO
tSUSTA
tSP
tHDDAT
SDA
tBUF
P
S
Sr
P
NOTE: S = Start, Sr = Repeated Start, and P = Stop.
Figure 1. I2C Timing Diagram
6
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6.7 Typical Characteristics
At TA = 25°C, unless otherwise noted.
1000
12
Auto-Single Mode
tCYCLE = 2.5ms
AVDD = DVDD = 5.0V
10
Fast I C Interface Mode
8
6
Analog Current
2
100
Auto-Scan Modes
(4-Channel Measurements)
10
4
Auto-Single Modes
(1-Channel Measurements)
Digital Current
0
-40.0 -25.5 -11.0
3.5
18.0
32.5
47.0
61.5
76.0
1
0.01
90.5 105.0
1
0.1
10
1000
100
Temperature (°C)
tCYCLE (ms)
Figure 2. Current vs Temperature
Figure 3. Average Power Dissipation vs Cycle Time
10
10000
AVDD = 5V
tPU = 0V
tACQ = 6ms
9
Analog Supply Current (mA)
1000
Power (mW)
AVDD = 2.2V
tPU = 0V
tACQ = 6ms
2
Power (mW)
Current (mA)
14
Auto-Scan Modes
(4-Channel Measurements)
100
Auto-Single Modes
(1-Channel Measurements)
10
Auto-Single Mode
tCYCLE = 2.5ms
8
7
6
5
4
3
2
1
1
0.01
0
1
0.1
10
100
2.0
1000
2.5
5.0
5.5
6.0
AVDD = 2.2V
-1
-2
-2
-3
-3
Gain Error (LSB)
Gain Error (LSB)
4.5
Figure 5. Analog Supply Current vs Supply Voltage
0
30 Units Across Two Lots
-1
4.0
AVDD Supply Voltage (V)
Figure 4. Average Power Dissipation vs Cycle Time
0
3.5
3.0
tCYCLE (ms)
-4
-5
-6
-7
Mean + s
Mean
Mean - s
-8
-9
-4
-5
-6
-7
-8
-9
-10
-10
2
3
4
6
5
-40.0 -25.5 -11.0
AVDD Supply Voltage (V)
3.5
18.0
32.5
47.0
61.5
76.0
90.5 105.0
Temperature (°C)
Figure 6. Typical Gain Error vs AVDD Voltage
Figure 7. Gain Error Drift
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Typical Characteristics (continued)
At TA = 25°C, unless otherwise noted.
5.0
3
AVDD = 2.2V
2
4.0
Offset Error (LSB)
Offset Error (LSB)
30 Units Across Two Lots
4.5
1
0
-1
Mean + s
Mean
Mean - s
3.5
3.0
2.5
2.0
1.5
1.0
-2
0.5
-3
0
18
-11
-40
47
76
105
2
AVDD Voltage (V)
Figure 8. Offset Error Drift, Typical
Figure 9. Typical Offset Error vs AVDD Voltage
1.5
2.0
AVDD = 2.2V
1.5
1.3
Linearity Error (LSB)
Frequency (% of Nominal)
1.4
1.2
1.1
1.0
0.9
0.8
0.7
1.0
0.5
0
-0.5
-1.0
-1.5
0.6
0.5
-2.0
2
5
4
3
6
0
512
1024
1536
AVDD Voltage (V)
2560
3072
3584
4096
Figure 11. Integral Nonlinearity
2.0
2.0
AVDD = 2.2V
AVDD = 5.0V
1.5
1.5
1.0
1.0
0.5
0.5
INL (LSB)
Linearity Error (LSB)
2048
Code
Figure 10. Internal Oscillator Frequency vs Voltage
0
-0.5
Maximum INL
0
-0.5
-1.0
-1.0
-1.5
-1.5
-2.0
-2.0
Minimum INL
INL shown is worst result over transfer function.
0
8
6
5
4
3
Temperature (° C)
512
1024
1536
2048
2560
3072
3584
4096
-40.0 -25.5 -11.0
3.5
18.0
32.5
47.0
61.5
76.0
90.5 105.0
Code
Temperature (°C)
Figure 12. Integral Nonlinearity
Figure 13. Integral Linearity Error Drift
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Typical Characteristics (continued)
At TA = 25°C, unless otherwise noted.
1.5
1.5
AVDD = 5V
AVDD = 2.2V
1.0
Linearity Error (LSB)
Linearity Error (LSB)
1.0
0.5
0
-0.5
-1.0
0.5
0
-0.5
-1.0
-1.5
-1.5
0
512
1024
1536
2048
3072
2560
3584
4096
0
1024
512
1536
Code
Figure 14. Differential Nonlinearity
1.5
2048
2560
3072
3584
4096
Code
Figure 15. Differential Nonlinearity
9000
AVDD = 2.2V
DC Input
AVDD = 2.2V
8000
1.0
6000
Maximum DNL
Count
0
Minimum DNL
-0.5
5000
4000
3000
2000
-1.0
1000
DNL shown is worst result over transfer function.
-1.5
2053
2052
Temperature (°C)
2051
0
90.5 105.0
2050
76.0
2049
61.5
2048
47.0
2047
32.5
2046
18.0
2045
3.5
2043
-40.0 -25.5 -11.0
2044
DNL (LSB)
7000
0.5
Code
At code center
Figure 16. Differential Nonlinearity vs Temperature
Figure 17. Noise Histogram
9000
(1)
DC Input
AVDD = 5V
8000
7000
Count
6000
5000
4000
3000
2000
1000
2053
2052
2051
2050
2049
2048
2047
2046
2045
2044
2043
0
Code
At code center
Figure 18. Noise Histogram
(1)
At code center.
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7 Detailed Description
7.1 Overview
The ADS7924 is a miniature, four-channel, multiplexed, 12-bit, analog-to-digital converter (ADC) with an I2C
serial interface. Functional Block Diagram shows a block diagram. The four-channel input multiplexer is routed
through external pins to allow a common signal conditioning block to be used for all four channels. The
PWRCON digital output can be used to shut down active circuitry used in the signal conditioning; see the
Application and Implementation section for additional details.
The successive-approximation-register (SAR) ADC performs a no-latency conversion on the selected input
channel and stores the data in a dedicated register. A digital threshold comparator with programmable upper and
lower limits can be enabled and used to create an alarm monitor. A dedicated interrupt output pin (INT) indicates
when an alarm occurs. Two I2C addresses are available and are selected with the dedicated digital input pin A0.
Both standard and fast mode formats for I2C are supported.
7.2 Functional Block Diagram
MUX OUT
ADCIN
AVDD
DVDD
Registers
RESET
CH0 Upper Limit
CH1 Upper Limit
CH2 Upper Limit
Control
and
Sequencer
IC
Interface
CH3 Upper Limit
CH0
CH0 Data
CH1
CH1 Data
CH2
Input
Multiplexer
SAR
ADC
SDA
SCL
A0
CH2 Data
CH3 Data
CH3
PWRCON
2
CH0 Lower Limit
INT
Comparator and
Alarm Detect
CH1 Lower Limit
CH2 Lower Limit
CH3 Lower Limit
AGND
Clock Oscillator
AGND
7.3 Feature Description
7.3.1 Multiplexer
The ADS7924 has a four-channel, single-ended input multiplexer. As Figure 19 illustrates, ESD diodes protect
the inputs. Make sure these diodes do not turn on by staying within the absolute input voltage range
specification. The MUXOUT pin can be connected to AGND within the multiplexer (for example, to provide a test
signal of 0 V or as part of a calibration procedure). See the PWRCONFIG: Power-Up Configuration Register
register in the Register Map section for more details
10
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Feature Description (continued)
MUXOUT
AVDD
CH0
AVDD
AGND
CH1
AVDD
AGND
CH2
AVDD
AGND
CH3
(1)
AGND
AGND
(1)
See the PWRCONFIG: Power-Up Configuration Register register in the Register Map section.
Figure 19. ADS7924 Multiplexer
7.3.2 ADC Input
The ADC Input (ADCIN) pin provides a single-ended input to the 12-bit successive approximation register (SAR)
ADC. This pin is protected with ESD diodes in the same way as the multiplexer inputs. While acquiring the signal
during the tACQ interval, the ADC sampling capacitor is connected to the ADCIN pin. While converting during the
tCONV interval, the sampling capacitor is disconnected from the ADCIN pin, and the conversion process
determines the voltage that was sampled.
7.3.3 Reference
The analog supply voltage (AVDD) is used as the reference. Power to the ADS7924 should be clean and well
bypassed. A 0.1-μF ceramic capacitor must be placed as close as possible to the ADS7924 package. In addition,
a 1-μF to 10-μF capacitor and a 5-Ω to 10-Ω series resistor may be used to low-pass filter a noisy supply.
7.3.4 Clock
The ADS7924 uses an internal clock. The clock speed determines the various timing settings such as conversion
time, acquisition time, and so forth.
7.3.5 Data Format
The ADS7924 provides 12 bits of data in unipolar format. The positive full-scale input produces an output code of
FFFh and a zero input produces an output code of 0h. The output clips at these codes for signals that either
exceed full-scale or go below '0'. Figure 20 illustrates code transitions versus input voltage.
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Feature Description (continued)
FFF
¼
800
7FE
¼
Output Code (Hex)
FFE
1LSB = AVDD/2
001
12
000
0 0.5LSB
¼
AVDD - 1.5LSB
AVDD
Input Voltage (VACDIN)
(1)
Excludes the effects of noise, INL, offset, and gain errors.
Figure 20. ADS7924 Code Transition Diagram(1)
7.3.6 ADC Conversion Timing
The ADS7924 provides a flexible timing arrangement to support a wide variety of measurement needs. Three
user-controlled timings include power up (tPU), acquisition (tACQ), and sleep (tSLEEP) plus a fixed conversion time
(tCONV).
7.3.6.1 Power-Up Time
The power-up time is allowed to elapse whenever the device has been shutdown in idle mode. Power-up time
can allow external circuits, such as an operational amplifier, between the MUXOUT and ADCIN pins to turn on.
The nominal time programmed by the PUTIME[4:0] register bits is given by Equation 1:
tPU = PWRUPTIME[4:0] × 2 μs
(1)
For example, if PWRUPTIME is set to 25 ('011001') then 50 μs is allowed to elapse before beginning the
acquisition time. If a power-up time is not required, set the bits to '0' to effectively bypass.
7.3.6.2 Acquisition Time
The acquisition time is allowed to elapse before beginning a conversion. During this time, the ADC acquires the
signal. The minimum acquisition time is 6 µs. The nominal time programmed by the ACQTIME[4:0] register bits is
given by Equation 2:
tACQ = (ACQTIME[4:0] × 2 μs) + 6 μs
(2)
For example, if ACQTIME is set to 30 ('011110') then 66 μs is allowed to acquire the input signal. If an
acquisition time greater than 6 μs is not required, set the bits to '0'.
7.3.6.3 Conversion Time
The conversion time is always 4 μs and cannot be programmed by the user.
7.3.6.4 Sleep Time
The sleep time is allowed to elapse after conversions in the Auto-Single with Sleep, Auto-Scan with Sleep, and
Auto-Burst Scan with Sleep modes. The nominal time programmed by the SLPTIME registers can be increased
by a factor of eight using the SLPMULT8 bit or decreased by a factor of four using the SLPDIV4 bit.
7.3.7 Interrupt Output (INT)
The ADS7924 offers a dedicated output pin (INT) for signaling an interrupt condition. The INT pin can be
configured to activate when the ADC is busy with a conversion, when data are ready for retrieval, or when an
alarm condition occurs; see the INTCONFIG: Interrupt Configuration Register register in the Register Map
section.
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Feature Description (continued)
To clear an interrupt from an alarm condition, read the INTCONFIG register (12h). To clear an interrupt from data
ready, read the data registers. The interrupt clears when the lower four bits are retrieved.
The INT pin can be configured to generate a static output (useful for a host controller monitoring for a level) or a
pulse output (useful for a host controller monitoring for a edge transition). When a pulse output is selected, the
nominal pulse width is 250 ns. The Interrupt Control Register should be read to clear the interrupt.
7.3.8 PWRCON
The PWRCON pin allows the user to synchronize the shutdown/wakeup of an external operational amplifier with
the ADC conversion cycle. This feature provides further power reduction and can be useful in applications where
the time difference between consecutive signal captures is large. The PWRCON pin can drive up to 3 mA of
current and its output voltage is the same as AVDD. This pin is controlled by the PWRCONFIG register.
7.3.9 Alarm
The ADS7924 offers an independent alarm function for each input channel. An 8-bit window comparator can be
enabled to test the ADC conversion result against an upper limit set by the ULR register and against a lower limit
set by the LLR register. If the conversion result is less than or equal to the LLR threshold value or greater than or
equal to the ULR threshold value, the comparator is tripped. There are separate upper and lower registers for
each input channel.
A programmable counter determines how many comparator trips it takes to generate an alarm. A separate
counter is used for each channel and is incremented whenever the comparator trips, either for the upper or lower
thresholds. That is, an ADC conversion result on channel 1 that exceeds the ULR threshold or falls below the
LLR threshold increments the counter for that channel. Figure 21 illustrates a conceptual diagram of the window
comparator and alarm circuitry.
When an alarm occurs, the INT pin can be configured to generate an interrupt. The channel that generated the
alarm can be read from the registers. A read of the Interrupt Control register clears the alarm register and also
resets the alarm counter.
7.4 Device Functional Modes
7.4.1 ADC Operating Modes
The ADS7924 offers multiple operating modes to support a variety of monitoring needs. Conversions can either
be started manually or set to automatically continue. The mode is set by writing to the MODE register, and
changes take effect as soon as the write completes. Table 1 gives a brief description of each mode.
7.4.1.1 Idle Mode
Use this mode to save power when not converting. All circuits are shut down.
7.4.1.2 Awake Mode
All circuits are operating in this mode and the ADC is ready to convert. When switching between modes, be sure
to first select the Awake mode and then switch to the desired mode. This procedure ensures the internal control
logic is properly synchronized.
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Device Functional Modes (continued)
Upper Limit Threshold
ULRx[7:0]
ADC
ALMCNT[2:0]
(2)
CHX Data
Window
Comparator
Counter X
(2)
X
(1)
Alarm for
Channel X
LLRx[7:0]
Lower Limit Threshold
(1)
The same ALMCNT value is used for all four window comparators.
(2)
X = 0 to 3.
Figure 21. Window Comparator and Alarm Conceptual Block Diagram
Table 1. Mode Descriptions
MODE
Idle
DESCRIPTION
All circuits shutdown; lowest power setting
Awake
All circuits awake and ready to convert
Manual-Single
Select input channel is converted once
Manual-Scan
All input channels are converted once
Auto-Single
One input channel is continuously converted
Auto-Scan
All input channels are continuously converted
Auto-Single with Sleep
One input channel is continuously converted with programmable sleep time between conversions
Auto-Scan with Sleep
All input channels are continuously converted with programmable sleep time between conversions
Auto-Burst Scan with
Sleep
All input channels are converted with minimal delay followed by a programmable sleep time
7.4.1.3 Manual-Single Mode
This mode converts the selected channel once; see Figure 22. After the ADC Mode Control register is written,
the power-up time (tPU) and acquisition time (tACQ) are allowed to elapse. tPU can be set to '0' to effectively
bypass if not needed. tACQ time is programmable through the ACQCONFIG register, bits[4:0]. Sleep time (tSLEEP)
is not used in this mode.
After the conversion completes, the device waits for a new mode to be set. This mode can be set to Idle to save
power. When tPU and tACQ are very short, the very short conversion time needed allows a read register operation
to be issued on the I2C bus immediately after the write operation that initiates this mode.
NOTE
tPU only applies to the first manual-single command.
If multiple conversions are needed, the manual-single mode can be reissued without requiring the awake mode
to be issued in between. Consecutive manual-single commands have no tPU period.
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Status
Input Multiplexer
Busy
Data Ready
PWRCON
Awake
Acquire
Selected
Channel
Convert
Selected
Channel
tPU
tACQ
tCONV
Awaiting
Mode
Selection
Selected Channel
(1)
(1)
(2)
(3)
(1)
Busy and data ready are internal signals shown as active high that can be routed to the INT pin for external
monitoring.
(2)
PWRCON is shown enabled and active high.
(3)
The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register.
Figure 22. Manual-Single Operation Example
7.4.1.4 Manual-Scan Mode
This mode converts all of the channels once, starting with the selected channel, as illustrated in Figure 23. After
the ADC Mode Control register is written, the power-up time (tPU) is allowed to elapse. This value can be set to
'0' to effectively bypass if not needed. Before each conversion, an acquisition time (tACQ) is allowed to elapse.
tACK time is programmable through the ACQCONFIG register, bits[4:0]. Sleep time (tSLEEP) is not used in this
mode. The input multiplexer is automatically incremented as the conversions complete. If, for example, the initial
selected channel is CH2, the conversion order is CH2, CH3, CH0, and CH1. Data from the conversions are
always put into the data register that corresponds to a particular channel. For example, CH2 data always goes in
register DATA2_H and DATA2_L regardless of conversion order. After all four conversions complete, the device
waits for a new mode to be set. This mode can be set to Idle afterwards to save power. The INT pin can be
configured to indicate the completion of each individual conversion or it can wait until all four finish. In either
case, the appropriate data register is updated after each conversion. These registers can be read at any time
afterwards. If multiple scan are needed, the manual-scan mode can be reissued without requiring the Awake
mode to be issued in between.
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Status
Input Multiplexer
Busy
Data Ready
PWRCON
www.ti.com
Awake
Acquire
First
Channel
Convert
First
Channel
Acquire
Second
Channel
Convert
Second
Channel
Acquire
Third
Channel
Convert
Third
Channel
Acquire
Fourth
Channel
Convert
Fourth
Channel
tPU
tACQ
tCONV
tACQ
tCONV
tACQ
tCONV
tACQ
tCONV
Selected Channel
Next Channel
Next Channel
Awaiting
Mode
Selection
Next Channel
(1)
(2)
(3)
(4)
(1)
Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring.
(2)
Data ready is an internal signal shown as active high and is enabled when all conversions are complete. It can be
routed to the INT pin for external monitoring.
(3)
PWRCON is shown enabled and active high.
(4)
The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register.
Figure 23. Manual-Scan Operation Example
7.4.1.5 Auto-Single Mode
This mode automatically converts the selected channel continuously; see Figure 24. After the ADC Mode Control
register is written, the power-up time (tPU) is allowed to elapse. This value can be set to '0' to effectively bypass if
not needed. Before the conversion, an acquisition time (tACQ) is allowed to elapse. tACQ time is programmable
through the ACQCONFIG register, bits[4:0]. Sleep time (tSLEEP) is not used in this mode. After the conversion
completes the cycle is repeated.
This mode can be used with the onboard digital comparator to monitor the status of an input signal with little
support needed from a host microcontroller. The conversion time is less than the I2C data retrieval time. TI
suggests stopping this mode by setting the mode to Idle or stopping the conversion by configuring the alarm to
do so, before retrieving data. The alarm can also be configured to continue the conversion even after an interrupt
is generated.
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Status
Awake
Acquire
Selected
Channel
Convert
Selected
Channel
Acquire
Selected
Channel
Convert
Selected
Channel
Acquire
Selected
Channel
Convert
Selected
Channel
tPU
tACQ
tCONV
tACQ
tCONV
tACQ
tCONV
Input Multiplexer
Selected Channel
(1)
(2)
Busy
PWRCON
(3)
(4)
(1)
Same channel is continuously converted.
(2)
Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring.
(3)
PWRCON is shown enabled and active high.
(4)
The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register.
Figure 24. Example of Auto-Single Operation
7.4.1.6 Auto-Scan Mode
This mode automatically converts all the channels continuously, starting with the selected channel, as shown in
Figure 25. After the ADC Mode Control register is written, the power-up time (tPU) is allowed to elapse. This value
can be set to '0' to effectively bypass if not needed. Before the conversion, an acquisition time (tACQ) is allowed to
elapse. tACQ time is programmable through the ACQCONFIG register, bits[4:0]. Sleep time (tSLEEP) is not used in
this mode. The input multiplexer is automatically incremented as the conversions complete. If, for example, the
initial selected channel is CH2, the conversion order is CH2, CH3, CH0, CH1, CH2, CH3, and so forth. until the
mode is stopped. Data from the conversions are always put into the data register that corresponds to a particular
channel. For example, CH2 data always go in register DATA2_H and DATA2_L regardless of conversion order.
This mode can be used with the onboard digital comparator to monitor the status of the input signals with little
support needed from a host microcontroller. TI suggests interrupting this mode and stopping the automatic
conversions, either by setting the mode to Idle or configuring the alarm to do so, before retrieving data.
Status
Input Multiplexer
Busy
PWRCON
Awake
Acquire
First
Channel
Convert
First
Channel
Acquire
Second
Channel
Convert
Second
Channel
Acquire
Third
Channel
Convert
Third
Channel
Acquire
Fourth
Channel
Convert
Fourth
Channel
Acquire
First
Channel
Convert
First
Channel
tPU
tACQ
tCONV
tACQ
tCONV
tACQ
tCONV
tACQ
tCONV
tACQ
tCONV
Selected Channel (First)
Next Channel
Next Channel
Next Channel
First Channel
(1)
(2)
(3)
(1)
Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring.
(2)
PWRCON is shown enabled and active high.
(3)
The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register.
Figure 25. Auto-Scan Operation Example
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7.4.1.7 Auto-Single With Sleep Mode
This mode automatically converts the selected channel repeatedly with a sleep interval between conversions, as
shown in Figure 26. After the ADC Mode Control register is written, the power-up time (tPU) is allowed to elapse.
This value can be set to '0' to effectively bypass if not needed. Before the conversion, an acquisition time (tACQ)
is allowed to elapse. tACQ time is programmable through the ACQCONFIG register, bits[4:0]. After the conversion,
sleep time (tSLEEP) is allowed to elapse and then the cycle repeats. The length of the sleep time is controlled by
register bits. During the sleep mode, power dissipation is minimal and the PWRCON output is always disabled.
This mode can be used with the onboard digital comparator to periodically monitor the status of an input signal
while saving power between conversions. Little support is needed from a host microcontroller. It is suggested to
stop this mode by setting the mode to Idle or stopping the conversion by configuring the alarm to do so, before
retrieving data. The length in time of the cycle (tCYCLE) sets the average power dissipation; see Figure 3 or
Figure 4.
tCYCLE
Status
Awake
tPU
Acquire
Selected
Channel
Convert
Selected
Channel
Sleep
tACQ
tCONV
tSLEEP
Input Multiplexer
Busy
PWRCON
Awake
tPU
Acquire
Selected
Channel
Convert
Selected
Channel
Sleep
tACQ
tCONV
tSLEEP
Selected Channel
Awake
tPU
Acquire
Selected
Channel
Convert
Selected
Channel
tACQ
tCONV
(1)
(2)
(3)
(4)
(1)
Same channel is continuously converted.
(2)
Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring.
(3)
PWRCON is shown enabled and active high.
(4)
The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register.
Figure 26. Auto-Single With Sleep Operation Example
7.4.1.8 Auto-Scan With Sleep Mode
This mode automatically converts all the channels repeatedly with a sleep interval between conversions, as
illustrated in Figure 27. After the ADC Mode Control register is written, the power-up time (tPU) is allowed to
elapse. This value can be set to '0' to effectively bypass if not needed. Before the first conversion of the selected
input, an acquisition time (tACQ) is allowed to elapse. tACQ time is programmable through the ACQCONFIG
register, bits[4:0]. After the conversion, a sleep time (tSLEEP) is allowed to elapse and then the cycle repeats. The
length of the sleep time is controlled by register bits. During the sleep mode, power dissipation is minimal and the
PWRCON output is always disabled. The input multiplexer is automatically incremented as the conversions
complete. If, for example, the initial selected channel is CH2, the conversion order is CH2, CH3, CH0, CH1, CH2,
CH3, and so forth until the mode is stopped. Data from the conversions are always put into the data register that
corresponds to a particular channel. For example, CH2 data always goes in register DATA2_H and DATA2_L
regardless of conversion order.
This mode can be used with the onboard digital comparator to periodically monitor the status of the input signals
while saving power between conversions. Little support is needed from a host microcontroller. TI suggests
stopping this mode by setting it to Idle or stopping the conversion by configuring the alarm to do so, before
retrieving data. The length in time of the cycle (tCYCLE) sets the average power dissipation; see Figure 3 or
Figure 4.
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tCYCLE
Status
Awake
tPU
Input Multiplexer
Busy
PWRCON
Acquire
First
Channel
Convert
First
Channel
Sleep
tACQ
tCONV
tSLEEP
Awake
tPU
Acquire
Second
Channel
Convert
Second
Channel
Sleep
tACQ
tCONV
tSLEEP
Selected Channel
Awake
tPU
Next Channel
Acquire
Third
Channel
Convert
Third
Channel
Sleep
tACQ
tCONV
tSLEEP
Next Channel
Awake
tPU
Acquire
Fourth
Channel
Convert
Fourth
Channel
tACQ
tCONV
Next Channel
(1)
(2)
(3)
(1)
Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring.
(2)
PWRCON is shown enabled and active high.
(3)
The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register.
Figure 27. Auto-Scan With Sleep Operation Example
7.4.1.9 Auto-Burst Scan With Sleep Mode
This mode automatically converts all the channels without delay followed by a sleep interval before the cycle
repeats, as illustrated in Figure 28. After the ADC Mode Control register is written, the power-up time (tPU) is
allowed to elapse. This value can be set to '0' to effectively bypass if not needed. Before the first conversion of
the selected input, an acquisition time (tACQ) is allowed to elapse. tACQ time is programmable through the
ACQCONFIG register, bits[4:0]. Afterwards, all four inputs are measured without delay. The input multiplexer is
automatically incremented as the conversions complete. If, for example, the initial selected channel is CH2, the
conversion order is CH2, CH3, CH0, and CH1. After the four conversions, a sleep time (tSLEEP) is allowed to
elapse and then the cycle repeats. The length of the sleep time is controlled by register bits. During the sleep
mode, power dissipation is minimal and the PWRCON output is always disabled. Data from the conversions are
always put into the data register that corresponds to a particular channel. For example, CH2 data always goes in
register DATA2_H and DATA2_L regardless of conversion order.
This mode can be used with the onboard digital comparator to periodically monitor the status of the input signals
while saving power between conversions. Little support is needed from a host microcontroller. TI suggests
interrupting this mode and stop the automatic conversions, either by setting the mode to Idle or configuring the
alarm to do so, before retrieving data. The length in time of the cycle (tCYCLE) sets the average power; see
Figure 3 or Figure 4.
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tCYCLE
Awake
Status
tPU
Input Multiplexer
Busy
PWRCON
Aquire and
Aquire and
Convert Third Convert Fourth
Channel
Channel
Aquire and
Convert First
Channel
Aquire and
Convert Second
Channel
tACQ + tCONV
tACQ + tCONV
tACQ + tCONV
Next Channel
Next Channel
Selected Channel (First)
tACQ + tCONV
Sleep
Awake
tSLEEP
tPU
Next Channel
Aquire and
Convert First
Channel
Aquire and
Convert Second
Channel
tACQ + tCONV
tACQ + tCONV
First Channel
Next Channel
(1)
(2)
(3)
(1)
Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring.
(2)
PWRCON is shown enabled and active high.
(3)
The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register.
Figure 28. Auto-Burst Scan With Sleep Operation Example
7.5 Programming
7.5.1 I2C Interface
The ADS7924 communicates through an I2C interface. I2C is a two-wire, open-drain interface that supports
multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines low by connecting
them to ground; they never drive the bus lines high. Instead, the bus wires are pulled high by pullup resistors, so
the bus wires are high when no device is driving them low. This way, two devices cannot conflict; if two devices
drive the bus simultaneously, there is no driver contention.
Communication on the I2C bus always takes place between two devices, one acting as the master and the other
as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the
master. Some I2C devices can act as masters or slaves, but the ADS7924 can only act as a slave device.
An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data are
transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the
appropriate level while SCL is low (a low on SDA indicates the bit is zero; a high indicates the bit is one). Once
the SDA line settles, the SCL line is brought high, then low. This pulse on SCL clocks the SDA bit into the
receiver shift register. If the I2C bus is held idle for more than 25 ms, the bus times out.
The I2C bus is bidirectional: the SDA line is used for both transmitting and receiving data. When the master reads
from a slave, the slave drives the data line; when the master sends to a slave, the master drives the data line.
The master always drives the clock line. The ADS7924 never drives SCL, because it cannot act as a master. On
the ADS7924, SCL is an input only.
Most of the time the bus is idle; no communication occurs, and both lines are high. When communication is
taking place, the bus is active. Only master devices can start a communication and initiate a START condition on
the bus. Normally, the data line is only allowed to change state while the clock line is low. If the data line
changes state while the clock line is high, it is either a START condition or a STOP condition. A START condition
occurs when the clock line is high and the data line goes from high to low. A STOP condition occurs when the
clock line is high and the data line goes from low to high.
After the master issues a START condition, it sends a byte that indicates which slave device it wants to
communicate with. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to
which it responds. The master sends an address in the address byte, together with a bit that indicates whether it
wishes to read from or write to the slave device.
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Programming (continued)
Every byte transmitted on the I2C bus, whether it is address or data, is acknowledged with an acknowledge bit.
When the master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the
slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA low. The master then sends a
clock pulse to clock the acknowledge bit. Similarly, when the master has finished reading a byte, it pulls SDA low
to acknowledge this to the slave. It then sends a clock pulse to clock the bit. (The master always drives the clock
line.)
A not-acknowledge is performed by simply leaving SDA high during an acknowledge cycle. If a device is not
present on the bus, and the master attempts to address it, it receives a not-acknowledge because no device is
present at that address to pull the line low.
When the master has finished communicating with a slave, it may issue a STOP condition. When a STOP
condition is issued, the bus becomes idle again. The master may also issue another START condition. When a
START condition is issued while the bus is active, it is called a repeated START condition.
See Figure 1 for a timing diagram illustrating the ADS7924 I2C transaction.
7.5.2 I2C Address Selection
The ADS7924 has one address pin, A0, that sets the I2C address. This pin can be connected to ground or VDD,
allowing two addresses to be selected with one pin as shown in Table 2. The state of the address pin A0 is
sampled continuously.
Table 2. A0 Pin Connection and Corresponding Slave
Address
A0 PIN
SLAVE ADDRESS
Ground
1001000
DVDD
1001001
7.5.3 I2C Speed Modes
The ADS7924 supports the I2C standard and fast modes. Standard mode allows a clock frequency of up to
100 kHz and fast mode permits a clock frequency of up to 400 kHz.
7.5.4 Slave Mode Operations
The ADS7924 can act as either slave receivers or slave transmitters. As a slave device, the ADS7924 cannot
drive the SCL line.
7.5.4.1 Receive Mode
In slave receive mode, the first byte transmitted from the master to the slave is the address with the R/W bit low.
This byte allows the slave to be written to. The next byte transmitted by the master is the register pointer byte.
The ADS7924 then acknowledges receipt of the register pointer byte. The next two bytes are written to the
address given by the register pointer. The ADS7924 acknowledges each byte sent. Register bytes are sent with
the most significant byte first, followed by the least significant byte.
7.5.4.2 Transmit Mode:
In slave transmit mode, the first byte transmitted by the master is the 7-bit slave address followed by the high
R/W bit. This byte places the slave into transmit mode and indicates that the ADS7924 is being read from. The
next byte transmitted by the slave is the most significant byte of the register that is indicated by the register
pointer. This byte is followed by an acknowledgment from the master. The remaining least significant byte is then
sent by the slave and is followed by an acknowledgment from the master. The master may terminate
transmission after any byte by not acknowledging or issuing a START or STOP condition.
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7.5.5 Writing the Registers
To access a write register from the ADS7924, the master must first write the appropriate value to the Pointer
address. The Pointer address is written directly after the slave address byte, low R/W bit, and a successful slave
acknowledgment. After the Pointer address is written, the slave acknowledges and the master issues a STOP or
a repeated START condition. The MSB of the pointer address is the increment (INC) bit. When set to '1', the
register address is automatically incremented after every register write which allows convenient writing of multiple
registers. Set INC to '0' when writing a single register. Figure 29 and Figure 30 illustrate timing examples.
1
9
1
9
SCL
¼
SDA
1
0
0
1
0
0
A0(1)
0(2)
R/W
Start By
Master
0
0
P4(3)
P3
P2
P1
ACK By
ADS7924
P0
¼
ACK By
ADS7924
Frame 2 Pointer Address Byte
Frame 1 Slave Address Byte
1
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
ACK By
ADS7924
Stop By
Master
Frame 3 Register Data Byte
(1)
The value of A0 is determined by the A0 pin.
(2)
When INC is set to '0', the address pointer remains unchanged after a read.
(3)
Bits P[4:0] point to the register to be written.
Figure 29. Writing a Single Register Timing Diagram
22
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1
9
9
1
SCL
¼
1
SDA
0
0
1
0
0
A0(1)
1
R/W
Start By
Master
(2)
0
0
P4
(3)
P3
P2
P1
P0
ACK By
ADS7924
¼
ACK By
ADS7924
Frame 2 Pointer Address Byte
Frame 1 Slave Address Byte
1
9
1
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
ACK By
ADS7924
Frame 3 Register Data Byte 1
D1
D0
ACK By
ADS7924
Stop By
Master
Frame 4 Register Data Byte N
(1)
The value of A0 is determined by the A0 pin.
(2)
When INC is set to '1', the address pointer automatically increments for multiple register writes.
(3)
Bits P[4:0] point to the storing register to be written.
Figure 30. Writing Multiple Registers Timing Diagram
7.5.6 Reading the Registers
To read a specific register from the ADS7924, the master must first write the appropriate value to the pointer
address. The pointer address is written directly after the slave address byte, low R/W bit, and a successful slave
acknowledgment. The MSB of the pointer address is the INC bit. When set to '1', the register address is
automatically incremented after every register read which allows convenient reading of multiple registers. Set
INC to '0' when reading a single register.
The master may issue a START condition and send the slave address byte with the R/W bit high to begin the
read. If the previously selected register is to be read again, then updating the pointer address is unnecessary.
Figure 31 to Figure 33 provide examples of register reads.
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1
9
1
9
SCL
¼
SDA
1
0
0
1
0
0
A0
(1)
0
R/W
Start By
Master
(2)
0
0
P4
(3)
P3
P2
P1
P0
ACK By
ADS7924
ACK By
ADS7924
Stop By
Master
Frame 2 Pointer Address Byte
Frame 1 Slave Address Byte
1
9
1
9
SCL
(Continued)
SDA
(Continued)
1
0
0
0
1
0
A0
(1)
R/W
Start By
Master
D7
D6
D5
D4
D3
D2
ACK By
ADS7924
D1
D0
ACK By
From
ADS7924
Master
(2)
Frame 4 Data Byte
Frame 3 Slave Address Byte
(1)
The value of A0 is determined by the A0 pin.
(2)
When INC is set to '0', the address pointer remains unchanged after a read.
(3)
Bits P[4:0] point to the register to be read.
Figure 31. Reading a Single Register Timing Diagram
1
9
1
9
SCL
SDA
1
0
0
1
0
0
A0
(1)
Start By
Master
R/W
D7
D6
D5
D3
D2
D1
ACK By
ADS7924
Frame 1 Slave Address Byte
(1)
D4
D0
ACK By
ADS7924
Stop By
Master
Frame 2 Register Data Byte
The value of A0 is determined by the A0 pin.
Figure 32. Reading a Previously Addressed Register Timing Diagram
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1
9
1
9
SCL
¼
SDA
1
0
0
1
0
0
A0
(1)
R/W
Start By
Master
1
(2)
0
0
P4
(3)
P3
P2
P1
P0
ACK By Repeated Start
ADS7924
By Master
ACK By
ADS7924
Frame 1 Slave Address Byte
Frame 2 Pointer Address Byte
1
9
1
9
SCL
(Continued)
SDA
(Continued)
1
0
0
0
1
0
A0
(1)
D7
R/W
Start By
Master
D6
D5
D4
D3
D2
D1
D0
From
ADS7924
ACK By
ADS7924
ACK By
Master
(2)
Frame 4 Data Byte 1
Frame 3 Slave Address Byte
1
9
1
9
SCL
(Continued)
SDA
(Continued)
D7
Start By
Master
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
ACK By
Master
From
ADS7924
Frame 5 Register Data Byte 2
D4
D3
D2
D1
From
ADS7924
D0
1
NACK By
Master
(2)
Stop
By Master
Frame 6 Register Data Byte N
(1)
The value of A0 is determined by the A0 pin.
(2)
When INC is set to '1', the address pointer automatically increments for multiple register reads.
(3)
Bits P[4:0] point to the register to be read.
Figure 33. Reading Multiple Registers Timing Diagram
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7.6 Register Map
The ADS7924 operation is controlled through a set of registers. Collectively, the registers contain all the
information needed to configure the part. Table 3 shows the register map.
Table 3. Register Map
RESET
VALUE
ADDRESS
REGISTER
00h
MODECNTRL
00h
MODE5
MODE4
MODE3
MODE2
MODE1
MODE0
SEL/ID1
SEL/ID0
01h
INTCNTRL
X0h
ALRM_ST3
ALRM_ST2
ALRM_ST1
ALRM_ST0
AEN/ST3
AEN/ST2
AEN/ST1
AEN/ST0
02h
DATA0_U
XXh
DATA0[11]
DATA0[10]
DATA0[9]
DATA0[8]
DATA0[7]
DATA0[6]
DATA0[5]
DATA0[4]
03h
DATA0_L
XXh
DATA0[3]
DATA0[2]
DATA0[1]
DATA0[0]
0
0
0
0
04h
DATA1_U
XXh
DATA1[11]
DATA1[10]
DATA1[9]
DATA1[8]
DATA1[7]
DATA1[6]
DATA1[5]
DATA1[4]
05h
DATA1_L
XXh
DATA1[3]
DATA1[2]
DATA1[1]
DATA1[0]
0
0
0
0
06h
DATA2_U
XXh
DATA2[11]
DATA2[10]
DATA2[9]
DATA2[8]
DATA2[7]
DATA2[6]
DATA2[5]
DATA2[4]
07h
DATA2_L
XXh
DATA2[3]
DATA2[2]
DATA2[1]
DATA2[0]
0
0
0
0
08h
DATA3_U
XXh
DATA3[11]
DATA3[10]
DATA3[9]
DATA3[8]
DATA3[7]
DATA3[6]
DATA3[5]
DATA3[4]
09h
DATA3_L
XXh
DATA3[3]
DATA3[2]
DATA3[1]
DATA3[0]
0
0
0
0
0Ah
ULR0
XXh
ULR0[7]
ULR0[6]
ULR0[5]
ULR0[4]
ULR0[3]
ULR0[2]
ULR0[1]
ULR0[0]
0Bh
LLR0
XXh
LLR0[7]
LLR0[6]
LLR0[5]
LLR0[4]
LLR0[3]
LLR0[2]
LLR0[1]
LLR0[0]
0Ch
ULR1
XXh
ULR1[7]
ULR1[6]
ULR1[5]
ULR1[4]
ULR1[3]
ULR1[2]
ULR1[1]
ULR1[0]
0Dh
LLR1
XXh
LLR1[7]
LLR1[6]
LLR1[5]
LLR1[4]
LLR1[3]
LLR1[2]
LLR1[1]
LLR1[0]
0Eh
ULR2
XXh
ULR2[7]
ULR2[6]
ULR2[5]
ULR2[4]
ULR2[3]
ULR2[2]
ULR2[1]
ULR2[0]
0Fh
LLR2
XXh
LLR2[7]
LLR2[6]
LLR2[5]
LLR2[4]
LLR2[3]
LLR2[2]
LLR2[1]
LLR2[0]
10h
ULR3
XXh
ULR3[7]
ULR3[6]
ULR3[5]
ULR3[4]
ULR3[3]
ULR3[2]
ULR3[1]
ULR3[0]
11h
LLR3
XXh
LLR3[7]
LLR3[6]
LLR3[5]
LLR3[4]
LLR3[3]
LLR3[2]
LLR3[1]
LLR3[0]
12h
INTCONFIG
E0h
AIMCNT2
AIMCNT1
AIMCNT0
INTCNFG1
INTCNFG0
BUSY/INT
INTPOL
INTTRIG
13h
SLPCONFIG
00h
0
CONVCTRL
SLPDIV4
SLPMULT8
0
SLPTIME2
SLPTIME1
SLPTIME0
14h
ACQCONFIG
00h
0
0
0
ACQTIME4
ACQTIME3
ACQTIME2
ACQTIME1
ACQTIME0
15h
PWRCONFIG
00h
CALCNTL
PWRCONPOL
PWRCONEN
PWRUPTIME4
PWRUPTIME3
PWRUPTIME2
PWRUPTIME1
PWRUPTIME0
RESET
18h
(A0 = 0)
19h
(A0 = 1)
RST/ID7
RST/ID6
RST/ID5
RST/ID4
RST/ID3
RST/ID2
RST/ID1
RST/ID0
16h
26
BIT 7
BIT 6
BIT 5
BIT 4
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BIT 3
BIT 2
BIT 1
BIT 0
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Figure 34. MODECNTRL: ADC Mode Control Register (Address = 00h)
7
MODE5
Bits[7:2]
6
MODE4
4
MODE2
3
MODE1
2
MODE0
1
SEL/ID1
0
SEL/ID0
MODE[5:0]: Mode control
000000
100000
110000
110010
110001
110011
111001
111011
111111
Bits[1:0]
5
MODE3
= Idle mode (default)
= Awake mode
= Manual-Single mode
= Manual-Scan mode
= Auto-Single mode
= Auto-Scan mode
= Auto-Single with Sleep mode
= Auto-Scan with Sleep mode
= Auto-Burst Scan with Sleep mode
SEL/ID[1:0]: Channel selection
When read, these bits indicate the last channel converted.
When writing to these bits, select which input appears on MUXOUT:
00 = Channel 0 is selected
01 = Channel 1 is selected
10 = Channel 2 is selected
11 = Channel 3 is selected (unless the CALCNTRL bit is set to '1')
Figure 35. INTCNTRL: Interrupt Control Register (Address = 01h)
7
ALRM_ST3
Bits[7:4]
6
ALRM_ST2
5
ALRM_ST1
4
ALRM_ST0
3
AEN/ST3
2
AEN/ST2
1
AEN/ST1
0
AEN/ST0
ALRM_ST[3:0]: Alarm status (read-only)
Reading these bits indicates the alarm status for the channels. These bits are never masked—they always report the alarm
status even when the alarm is not enabled by the corresponding AEN/ST bits.
Bit 7 = Channel 3 alarm status, '1' indicates an alarm condition
Bit 6 = Channel 2 alarm status, '1' indicates an alarm condition
Bit 5 = Channel 1 alarm status, '1' indicates an alarm condition
Bit 4 = Channel 0 alarm status, '1' indicates an alarm condition
Bits[3:0]
AEN/ST[3:0]: Alarm enable
Writing to these bits enables the alarm for the corresponding channel.
Reading these bits returns the status of the alarm for the corresponding channel when enabled. Reading returns a '0' when
the alarm in not enabled.
Bit 3 = Channel 3 alarm enable, 1 = enabled (default = 0)
Bit 2 = Channel 2 alarm enable, 1 = enabled (default = 0)
Bit 1 = Channel 1 alarm enable, 1 = enabled (default = 0)
Bit 0 = Channel 0 alarm enable, 1 = enabled (default = 0)
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Each input channel has individual registers to buffer the conversion data. The 12 bits are stored in two registers:
the upper register stores the eight most significant bits; the lower register stores the lower four least significant
bits. The data registers are always updated with the corresponding input channel regardless of the order of
conversion. For example, DATA0_U and DATA0_L always contain the results of the latest conversion of CH0.
Figure 36. DATA0_U: Conversion Data for Channel 0, Upper Bits Register (Address = 02h)
7
DATA0[11]
(MSB)
6
DATA0[10]
5
DATA0[9]
4
DATA0[8]
3
DATA0[7]
2
DATA0[6]
1
DATA0[5]
0
DATA0[4]
Figure 37. DATA0_L: Conversion Data for Channel 0, Lower Bits Register (Address = 03h)
7
DATA0[3]
6
DATA0[2]
5
DATA0[1]
4
DATA0[0]
(LSB)
3
0
2
0
1
0
0
0
Figure 38. DATA1_U: Conversion Data for Channel 1, Upper Bits Register (Address = 04h)
7
DATA1[11]
(MSB)
6
DATA1[10]
5
DATA1[9]
4
DATA1[8]
3
DATA1[7]
2
DATA1[6]
1
DATA1[5]
0
DATA1[4]
Figure 39. DATA1_L: Conversion Data for Channel 1, Lower Bits Register (Address = 05h)
7
DATA1[3]
6
DATA1[2]
5
DATA1[1]
4
DATA1[0]
(LSB)
3
0
2
0
1
0
0
0
Figure 40. DATA2_U: Conversion Data for Channel 2, Upper Bits Register (Address = 06h)
7
DATA2[11]
(MSB)
6
DATA2[10]
5
DATA2[9]
4
DATA2[8]
3
DATA2[7]
2
DATA2[6]
1
DATA2[5]
0
DATA2[4]
Figure 41. DATA2_L: Conversion Data for Channel 2, Lower Bits Register (Address = 07h)
7
DATA2[3]
6
DATA2[2]
5
DATA2[1]
4
DATA2[0]
(LSB)
3
0
2
0
1
0
0
0
Figure 42. DATA3_U: Conversion Data for Channel 3, Upper Bits Register (Address = 08h)
7
DATA3[11]
(MSB)
6
DATA3[10]
5
DATA3[9]
4
DATA3[8]
3
DATA3[7]
2
DATA3[6]
1
DATA3[5]
0
DATA3[4]
Figure 43. DATA3_L: Conversion Data for Channel 3, Lower Bits Register (Address = 09h)
7
DATA3[3]
28
6
DATA3[2]
5
DATA3[1]
4
DATA3[0]
(LSB)
3
0
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2
0
1
0
0
0
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Input channel has individual upper and lower threshold registers. Each register is eight bits with the least
significant bit weight equal to AVDD/256. The comparator is tripped when the input signal exceeds the value of
the upper limit register or falls below the lower limit register.
Figure 44. ULR0: Upper Limit Threshold for Channel 0 Comparator Register (Address = 0Ah)
7
ULR0[7] (MSB)
6
ULR0[6]
5
ULR0[5]
4
ULR0[4]
3
ULR0[3]
2
ULR0[2]
1
ULR0[1]
0
ULR0[0] (LSB)
Figure 45. LLR0: Lower Limit Threshold for Channel 0 Comparator Register (Address = 0Bh)
7
LLR0[7] (MSB)
6
LLR0[6]
5
LLR0[5]
4
LLR0[4]
3
LLR0[3]
2
LLR0[2]
1
LLR0[1]
0
LLR0[0] (LSB)
Figure 46. ULR1: Upper Limit Threshold for Channel 1 Comparator Register (Address = 0Ch)
7
ULR1[7] (MSB)
6
ULR1[6]
5
ULR1[5]
4
ULR1[4]
3
ULR1[3]
2
ULR1[2]
1
ULR1[1]
0
ULR1[0] (LSB)
Figure 47. LLR1: Lower Limit Threshold for Channel 1 Comparator Register (Address = 0Dh)
7
LLR1[7] (MSB)
6
LLR1[6]
5
LLR1[5]
4
LLR1[4]
3
LLR1[3]
2
LLR1[2]
1
LLR1[1]
0
LLR0[0] (LSB)
Figure 48. ULR2: Upper Limit Threshold for Channel 2 Comparator Register (Address = 0Eh)
7
ULR2[7] (MSB)
6
ULR2[6]
5
ULR2[5]
4
ULR2[4]
3
ULR2[3]
2
ULR2[2]
1
ULR2[1]
0
ULR2[0] (LSB)
Figure 49. LLR2: Lower Limit Threshold for Channel 2 Comparator Register (Address = 0Fh)
7
LLR2[7] (MSB)
6
LLR2[6]
5
LLR2[5]
4
LLR2[4]
3
LLR2[3]
2
LLR2[2]
1
LLR2[1]
0
LLR2[0] (LSB)
Figure 50. ULR3: Upper Limit Threshold for Channel 3 Comparator Register (Address = 10h)
7
ULR3[7] (MSB)
6
ULR3[6]
5
ULR3[5]
4
ULR3[4]
3
ULR3[3]
2
ULR3[2]
1
ULR3[1]
0
ULR3[0] (LSB)
Figure 51. LLR3: Lower Limit Threshold for Channel 3 Comparator Register (Address = 11h)
7
LLR3[7] (MSB)
6
LLR3[6]
5
LLR3[5]
4
LLR3[4]
3
LLR3[3]
2
LLR3[2]
1
LLR3[1]
0
LLR3[0] (LSB)
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Figure 52. INTCONFIG: Interrupt Configuration Register (Address = 12h)
7
ALMCNT2
Bits[7:5]
6
ALMCNT1
5
ALMCNT0
4
INTCNFG2
3
INTCNFG1
2
INTCNFG0
1
INTPOL
0
INTTRIG
ALMCNT[2:0]: Alarm count
These bits set the number of times the comparator threshold limit (either upper or lower) must be exceeded to generate an
alarm.
000 = Every conversion generates an alarm
001 = Exceeding the threshold limit 1 time generates an alarm condition
010 = Exceeding the threshold limit 2 times generates an alarm condition
011 = Exceeding the threshold limit 3 times generates an alarm condition
100 = Exceeding the threshold limit 4 times generates an alarm condition
101 = Exceeding the threshold limit 5 times generates an alarm condition
110 = Exceeding the threshold limit 6 times generates an alarm condition
111 = Exceeding the threshold limit 7 times generates an alarm condition
Bits[4:2]
INTCNFG[2:0]: INT output pin configuration
These bits determine which signal is output on INT. They also select the conversion control event; see the CONVCTRL bit
in the SLPCONFIG register. The configuration of these bits is shown in Table 4.
Table 4. INT Pin Configuration
BIT SETTING
INT PIN CONFIGURATION
CONVERSION CONTROL EVENT
000
Alarm
Alarm
001
Busy
Alarm
010
Data ready: one conversion completed
Data ready: one conversion complete
011
Busy
Data ready: one conversion complete
100
Do not use
—
101
Do not use
—
110
Data ready: all four conversions complete
Data ready: four conversions complete
111
Busy
Data ready: four conversions complete
Bit 1
INTPOL: INT pin polarity
0 = Active low (default)
1 = Active high
Bit 0
INTTRIG: INT output pin signaling
0 = Static signal for use with level triggering (default)
1 = Pulse signal for use with edge triggering
30
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Figure 53. SLPCONFIG: Sleep Configuration Register (Address = 13h)
7
0
6
CONVCTRL
5
SLPDIV4
Bit 7
Always write '0'
Bit 6
CONVCTRL: Conversion control
4
SLPMULT8
3
0
2
SLPTIME2
1
SLPTIME1
0
SLPTIME0
This bit determines the conversion status after a conversion control event; see the INTCNFG bits in the INTCONFIG
register.
0 = Conversions continue, independent of the control event status (default)
1 = Conversions are stopped as soon as a control event occurs; the event must be cleared to resume conversions
Bit 5
SLPDIV4: Sleep time 4x divider
This bit sets the speed of the sleep clock.
0 = Sleep time divider is '1' (default)
1 = Sleep time divider is '4'
Bit 4
SLPMULT8: Sleep time 8x multiplier
0 = Sleep time multiplier is '1' (default)
1 = Sleep time multiplier is '8'
Bit 3
Always write '0'
Bits[2:0]
SLPTIME[2:0]: Sleep time setting
000 = 2.5 ms (default)
001 = 5 ms
010 = 10 ms
011 = 20 ms
100 = 40 ms
101 = 80 ms
110 = 160 ms
111 = 320 ms
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Figure 54. ACQCONFIG: Acquire Configuration Register (Address = 14h)
7
0
6
0
5
0
Bits[7:5]
Always write '0'
Bits[4:0]
ACQTIME[4:0]: Signal acquire time
4
ACQTIME4
3
ACQTIME3
2
ACQTIME2
1
ACQTIME1
0
ACQTIME0
These bits set the time to acquire the signal before a conversion (default = 0).
tACQ = ACQTIME[4:0] × 2 μs + 6 µs
Figure 55. PWRCONFIG: Power-Up Configuration Register (Address = 15h)
7
CALCNTL
Bit 7
6
PWRCONPOL
5
PWRCONEN
4
PWRUPTIME4
3
PWRUPTIME3
2
PWRUPTIME2
1
PWRUPTIME1
0
PWRUPTIME0
CALCNTL: Calibration control
0 = Setting CH3 in the Mode Control register selects the CH3 input to be routed to the MUXOUT pin. (default)
1 = Setting CH3 in the Mode Control register connects the MUXOUT pin to AGND.
Bit 6
PWRCONPOL: PWRCON pin polarity
0 = Active low (default)
1 = Active high
Bit 5
PWRCONEN: PWRCON enable
0 = The PWRCON pin is disabled (default)
1 = The PWRCON pin is always enabled
Bits[4:0]
PWRUPTIME[4:0]: Power-up time setting
These bits set the power-up time (default = 0).
tPWR = PWRUPTIME[4:0] × 2 μs.
Figure 56. Reset: Software Reset and Device ID Register (Address = 16h)
7
RST/ID7
6
RST/ID6
5
RST/ID5
4
RST/ID4
3
RST/ID3
2
RST/ID2
1
RST/ID1
0
RST/ID0
A read of this register returns the device ID when A0 determines the last bit of the device ID (0001100A0).
A write to this register of 10101010 generates a software reset of the ADS7924.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The ADS7924 device provides a break-out point in the signal path between the multiplexer output and the ADC
input for external signal conditioning, if desired. Typical uses include adding an operational amplifier, such as the
TLV2780, along with an RC filter circuit. Different application circuits are described in following sections.
8.1.1 Using an Operational Amplifier Between Multiplexer Output and ADC Input
Adding an operational amplifier provides a high input impedance to the sensor source and buffers the capacitive
ADC input from high-impedance sensor circuits, as shown in Figure 57. High-impedance input signals can be
momentarily disrupted when coupled directly to a capacitive input like that of a sampling ADC. This disruption
can create errors when sampling. The use of an operational amplifier is recommended in these cases.
SHDN
TLV2780
AVDD
1mF
16
DVDD
14
15
AVDD
3kW
2
CH1
INT
ADS7924
CH3
SDA
MSP430
Microcontroller
4
5
8
3
A0
SCL
DGND
CH2
AGND
9
3kW
1
6
10
DVDD
RESET
PWRCON
11
CH0
7
12
ADCIN
Sensor Signals
MUXOUT
13
1mF
Figure 57. Sensor Data Acquisition With TLV2780 Buffer Amplifier
8.1.2 Using an Operational Amplifier and RC Filter Between Multiplexer Output and ADC Input
Placing an RC low-pass filter in the signal path allows for filtering out noise. The RC component values should
allow for sufficient settling time when changing from channel to channel. The time required for a full-scale input
signal to settle to within 1LSB of a 12-bit ADC is given by Equation 3:
Settling Time = R × C × ln(212)
(3)
RX and C form a low-pass filter for removing sensor and noise from other sources at the operational amplifier
input pin. The low-pass bandwidth is given by Equation 4:
f–3dB = 1/(2πRC)
(4)
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Application Information (continued)
The f–3dB should be chosen so that the signals of interest are within half of the programmable sampling
frequency. The noise bandwidth is given by Equation 5:
fNB = 1/(4RC)
(5)
This term should be set to reduce noise bandwidth but still allow for enough settling time. The ADS7924 has
internal registers ACQCONFIG (address = 14h), PWRCONF (address = 15h), and SLPCONFIG (address = 13h)
that can be programmed to slow down the channel-to-channel power up, acquisition, and sleep periods if needed
to allow for a longer settling time requirement.
In Figure 58, R is the sum of the sensor output impedance RSENSOR, the internal MUX resistance RMUX
(approximately 60 Ω), and external resistor RX. The primary benefit of having the filter at the input of the
operational amplifier is that the amplifier does not have to drive the filter, which can cause instability with large
capacitor values that may be needed to filter noise to low levels.
The TLV2780 typically powers up from a shutdown state in 800 ns. This period is well within the ADS7924
minimum acquisition time of 6μs. Setting the PWRCONFIG register (address = 15h) allows for more time if
another operational amplifier with a shutdown feature is used.
SHDN
TLV2780
AVDD
RX
C
16
DVDD
14
15
AVDD
3kW
3kW
2
INT
ADS7924
CH3
SDA
4
5
8
MSP430
Microcontroller
3
A0
SCL
DGND
CH2
AGND
9
DVDD
RESET
6
10
1mF
1
CH1
PWRCON
11
CH0
7
12
ADCIN
Sensor Signals
MUXOUT
13
1mF
NOTE: f–3dB BW = 159 kHz, R = 1 kΩ, and C = 1 nF where R = RMUX + RSENSOR + RX.
Figure 58. Sensor Data Acquisition With Filter and TLV2780 Buffer Amplifier
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Application Information (continued)
8.1.3 Using an RC Filter Between Multiplexer Output and ADC Input
For applications where low-output impedance signals are provided for the ADS7924 inputs, a simple RC filter
may suffice, as shown in Figure 59.
CX
AVDD
RX
16
DVDD
15
AVDD
14
2
INT
ADS7924
CH3
SDA
MSP430
Microcontroller
4
5
6
8
3
A0
SCL
DGND
CH2
AGND
9
3kW
RESET
PWRCON
10
3kW
1
CH1
7
11
CH0
ADCIN
13
12
MUXOUT
Sensor Signals
DVDD
1mF
1mF
NOTE: f–3dB BW = 159 kHz, R = 1 kΩ, and C = 1 nF where R = RMUX + RSENSOR + RX, C = CX + CADCIN, RMUX is
approximately 60 Ω, and CADCIN is approximately 15 pF.
Figure 59. Sensor Data Acquisition With Filter Only
CX should be greater than 200 pF, if possible. When coupled directly to the ADC input, using a capacitor with this
value allows for faster settling when scanning between channels.
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Application Information (continued)
8.1.4 Operational Amplifier With Filter and Gain Option Between Multiplexer Output and ADC Input
Both filtering and gain are added in Figure 60. Gain is given by Equation 6:
Gain = 1 + R1/R2
where
•
R is the sum of the sensor output impedance RSENSOR, the internal MUX resistance RMUX (approximately 60 Ω),
and the external resistor RX.
(6)
R2
R1
SHDN
TLV2780
AVDD
RX
C
1mF
DVDD
14
15
AVDD
3kW
RESET
2
CH1
INT
ADS7924
CH3
SDA
MSP430
Microcontroller
4
5
8
3
A0
SCL
DGND
CH2
AGND
9
3kW
1
6
10
CH0
PWRCON
11
7
12
ADCIN
13
MUXOUT
Sensor Signals
16
1mF
DVDD
NOTE: f–3dB BW = 159 kHz, R = 1 kΩ, and C = 1 nF where R = RMUX + RSENSOR + RX, and RMUX is approximately 60 Ω.
Gain = 1 + R1 / R2.
Figure 60. Sensor Data Acquisition With Gain Set Resistors, Filter, and TLV2780 Buffer Amplifier
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Application Information (continued)
8.1.5 Driving an RC Filter With an Operational Amplifier Between Multiplexer Output and ADC Input
A filter can be placed at the output of the operational amplifier, as shown in Figure 61. Ensure that the
operational amplifier is capable of driving the RC filter circuit without the operational amplifier becoming unstable.
One of the benefits of this circuit is that the operational amplifier noise is filtered along with sensor and other
system noise right at the ADC input pin.
SHDN
C
R
TLV2780
AVDD
1mF
16
DVDD
14
15
AVDD
3kW
3kW
RESET
2
CH1
INT
ADS7924
CH3
SDA
MSP430
Microcontroller
4
5
8
3
A0
SCL
DGND
CH2
AGND
9
DVDD
1
6
10
CH0
PWRCON
11
7
12
ADCIN
Sensor Signals
MUXOUT
13
1mF
NOTE: C = 200 pF, R = 1 kΩ, and the capacitance at the ADCIN pin is approximately 15 pF.
Figure 61. Sensor Data Acquisition With an Operational Amplifier Driving an RC Filter
8.1.6 Average Power Consumption
With its fast conversion time and programmable sleep time with near-zero power, the ADS7924 allows periodic
monitoring of the inputs with a very low average power dissipation, especially as the monitoring interval
increases. The average current required can be calculated as the weighed average of the currents consumed
during the power up, acquisition, converting, and sleep periods using Equation 7.
IPUtPU + IACQtACQ + ICONVtCONV + ISLEEPtSLEEP
IAVERAGE =
tCYCLE
(7)
As
•
•
•
•
•
an example, calculate the average current in the following configuration:
Mode programmed to Auto-Scan with Sleep
Power-up time (tPU) programmed to '0'
Acquisition time (tACQ) programmed to 6 μs
Sleep time (tSLEEP) programmed to 2.5 ms
AVDD = 2.2 V
Looking at Figure 27, the cycle time is seen to equal tCYCLE = 4tPU + 4tACQ + 4tCONV + 4tSLEEP = 4(0) + 4(6 μs) +
4(4 μs) + 4(2.5 ms) = 10.04 ms.
Table 5 lists the supply current for different supply voltages and operating conditions. Using the data for 2.2 V
with the calculated cycle time in Equation 7 gives the following average current:
0 + (270mA)(4)(6ms) + (400mA)(4)(4ms) + (1.25mA)(4)(2.5ms)
IAVERAGE =
= 2.5mA
10.04ms
(8)
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Application Information (continued)
Table 5. Supply Current for Various Operating Conditions
STATUS
Idle
AVDD
5V
3.3 V
2.7 V
2.2 V
1 µA
1 µA
1 µA
1 µA
Awake
45 µA
25 µA
20 µA
15 µA
Acquiring
315 µA
285 µA
275 µA
270 µA
Converting
730 µA
520 µA
450 µA
400 µA
Sleeping
3 µA
2 µA
1.5 µA
1.25 µA
The acquisition, conversion, and sleep times are multiplied by 4 because these are repeated four times in one
cycle when in auto-scan with sleep mode.
Average power dissipation for the previous configuration where all four inputs are monitored every 10 ms is
(2.2 V)(2.5 μA) = 5.5 μW.
Figure 3 and Figure 4 plot Equation 7 to help illustrate the relationship between cycle time and average power
dissipation.
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8.2 Typical Application
Figure 62 shows a 0-V to 10-V Input DAQ Circuit with a DC accuracy of 0.1%.
+5V
+5V
+3.3V
AVDD
DVDD
499
OPA313
2.2 nF
ADCIN
MUXOUT
20k
I2C
Interface
ADS7924
+
±
CH0
0-10 V
+
±
20k
CH1
4 Channel MUX
20k
0-10 V
SAR ADC
+
±
20k
0-10 V
+
±
0-10 V
20k
Data Buffers,
Sequencer
and Alarms
CH2
CH3
20k
20k
AGND
20k
Figure 62. 0-V to 10-V Input DAQ Circuit
8.2.1 Design Requirements
Table 6 shows the design parameters for this typical application.
Table 6. Design Parameters
DESIGN PARAMETER
DESIGN GOAL
Throughput
100 SPS
DC Accuracy
0.1%
Full Scale Step Settling
20 µs
DC Noise at input of ADC
200 µV RMS
Input Impedance
40 kΩ
8.2.2 Detailed Design Procedure
8.2.2.1 Setting the Throughput
The throughput was set by selecting a sleep time of 40 ms, sleep divider of 4 and acquisition time of 6 µs.
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8.2.2.2 Selecting the Operational Amplifier
The key parameters for selecting the operational amplifier for this circuit are noise, offset voltage and input bias
current. The offset voltage and input bias current affect the DC accuracy whereas the noise of the amplifier
increases the total noise at the input of ADC, the total noise at the input of ADC (Vn) can be calculated by
Equation 9. Vn must be less than 200-µV RMS for this circuit design.
V1 f _AMP_PP 2 2
Œ
e n_RMS u uf
6.6
2
Vn
VN2 _ ADC
3dB
where
•
•
•
•
en_RMS is the input voltage noise density of the amplifier.
VN_ADC is the DC noise of the ADC. For ADS7924 , DC Noise is specified as 0.125 LSB RMS.
V 1/f_AMP_PP is the peak to peak low-frequency noise at the input of amplifier.
f-3dB is the bandwidth of RC filter at the output of amplifier.
(9)
OPA313 is selected for this design for its low noise (25 nv/√Hz), low offset voltage (0.5 mV) and low input bias
current (0.2 pA).
8.2.2.3 Selecting the RC Filter
The RC filter at the output of amplifier affect full scale settling time and noise at the input of ADC. Full scale
settling time can be calculated using Equation 3 and the noise at input of ADC can be calculated using
Equation 9. A value of 499 Ω and 2.2 nF is used for achieving the full scale settling time of 20 µs and total DC
noise of less than 200 µV RMS.
8.2.3 Application Curves
2048
0.1
0.08
1536
0.04
Number of Hits
Error (% FSR)
0.06
0.02
0
-0.02
-0.04
1024
512
-0.06
-0.08
-0.1
0
1
2
3
4
5
6
7
8
9
10
Input Voltage (V)
Max Error = -0.0035%
11
12
0
2014
2015
2017
C00
Min Error = -0.067%
Sigma = 0.05
Figure 63. Error vs Input Voltage
40
2016
Output Code
C001
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Figure 64. Number of Hits vs Output Code
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9 Power Supply Recommendations
The device has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is used
for the interface circuits. DVDD supply voltage cannot exceed the AVDD supply voltage. The Power supply pins
of the device must be decoupled with 1-μF ceramic bypass capacitors. The AVDD supply also defines the fullscale input range of the device. Always set the AVDD supply to be greater than or equal to the maximum input
signal to avoid saturation of codes.
10 Layout
10.1 Layout Guidelines
Figure 65 provides an example layout for the device. Use a ground plane underneath the device and partition the
PCB into analog and digital sections. Avoid crossing digital lines with the analog signal path and keep the analog
input signals and the reference input signals away from noise sources. In Figure 65, the analog signals are
routed on the rightside of the device and the digital signals are routed on the left side of the device.
The power sources to the device must be clean and well-bypassed. Use 1-μF ceramic bypass capacitors in close
proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the AVDD and
DVDD pins and the bypass capacitors. Connect all ground pins to the ground plane using short, low-impedance
paths. The AVDD supply voltage for the device also functions as a reference for the device. Place the decoupling
capacitor for AVDD close to the device AVDD pin and connect this capacitor to the device pins with thick copper
tracks.
10.2 Layout Example
Analog Pins
Digital Pins
ADCIN
MUXOUT
GND
14
13
1 PF 1 PF
16
15
RESET
1
12
CH0
INT
2
11
CH1
SCLK
3
10
CH2
SDA
4
9
CH3
GND
A0
5
6
GND
7
8
PWRCON
Thermal PAD
GND
Figure 65. Example Layout
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
MicroPOWER, E2E are trademarks of Texas Instruments.
I2C is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, see the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Sep-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS7924IRTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
7924
ADS7924IRTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
7924
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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13-Sep-2017
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Sep-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS7924IRTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS7924IRTET
WQFN
RTE
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Sep-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS7924IRTER
WQFN
RTE
16
3000
367.0
367.0
35.0
ADS7924IRTET
WQFN
RTE
16
250
210.0
185.0
35.0
Pack Materials-Page 2
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