Texas Instruments | DAC8551 16-Bit, Ultralow-Glitch, Voltage-Output Digital‑to‑Analog Converter (Rev. E) | Datasheet | Texas Instruments DAC8551 16-Bit, Ultralow-Glitch, Voltage-Output Digital‑to‑Analog Converter (Rev. E) Datasheet

Texas Instruments DAC8551 16-Bit, Ultralow-Glitch, Voltage-Output Digital‑to‑Analog Converter (Rev. E) Datasheet
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DAC8551
SLAS429E – APRIL 2005 – REVISED JUNE 2017
DAC8551 16-Bit, Ultralow-Glitch, Voltage-Output Digital‑‑to‑‑Analog Converter
1 Features
3 Description
•
•
•
•
•
•
•
•
The DAC8551 is a small, low-power, voltage output,
16-bit digital-to-analog converter (DAC). It is
monotonic, provides good linearity, and minimizes
undesired code-to-code transient voltages. The
DAC8551 uses a versatile 3-wire serial interface that
operates at clock rates to 30 MHz and is compatible
with standard SPI™, QSPI™, Microwire™, and digital
signal processor (DSP) interfaces.
1
•
•
•
•
•
Relative Accuracy: 8LSB
Glitch Energy: 0.1 nV-s
MicroPower Operation: 140 μA at 2.7 V
Power-On Reset to Zero
Power Supply: 2.7 V to 5.5 V
16-Bit Monotonic
Settling Time: 10 μs to ±0.003% FSR
Low-Power Serial Interface with
Schmitt-Triggered Inputs
On-Chip Output Buffer Amplifier with
Rail-to-Rail Operation
Power-Down Capability
Binary Input
SYNC Interrupt Facility
Drop-In Compatible With DAC85x1
and DAC8550 (2's Complement Input)
The DAC8551 requires an external reference voltage
to set its output range. The DAC8551 incorporates a
power-on-reset circuit that ensures the DAC output
powers up at 0 V and remains there until a valid write
takes place to the device. The DAC8551 contains a
power-down feature, accessed over the serial
interface, that reduces the current consumption of the
device to 200 nA at 5 V.
The low-power consumption of this device in normal
operation makes it ideally suited for portable, batteryoperated equipment. The power consumption is 0.38
mW at 2.7 V, reducing to less than 1 μW in
power‑down mode.
2 Applications
•
•
•
•
•
•
For additional flexibilty, see the DAC8550 (SLAS476),
a 2's complement-input counterpart to the DAC8551.
Process Control
Data Acquisition Systems
Closed-Loop Servo-Control
PC Peripherals
Portable Instrumentation
Programmable Attenuation
Device Information(1)
PART NUMBER
DAC8551
PACKAGE
VSSOP (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
VDD
VFB
VREF
Ref (+)
VOUT
16-Bit DAC
16
DAC Register
16
SYNC
SCLK
Shift Register
PWD Control
Resistor
Network
DIN
GND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC8551
SLAS429E – APRIL 2005 – REVISED JUNE 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Characteristics...............................................
Typical Characteristics ..............................................
Detailed Description ............................................ 16
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
16
16
16
18
7.5 Programming........................................................... 18
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 21
8.3 System Examples ................................................... 23
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (February 2017) to Revision E
Page
•
Changed the VIL Test Conditions From: VDD = 5 V To: 3 V ≤ VDD ≤ 5.5 V and From: VDD = 3 V To: 2.7 V ≤ VDD < 3 V
in the Electrical Characteristics .............................................................................................................................................. 6
•
Changed the VIH Test Conditions From: VDD = 5 V To: 3 V ≤ VDD ≤ 5.5 V and From: VDD = 3 V To: 2.7 V ≤ VDD < 3 V
in the Electrical Characteristics .............................................................................................................................................. 6
Changes from Revision C (March 2016) to Revision D
Page
•
Relative accuracy DAC8551, Deleted the TYP value of ± 3, Changed the MAX value From: ±8 To: ±12 in the
Electrical Characteristics ....................................................................................................................................................... 5
•
Relative accuracy DAC8551A, Deleted the TYP value of ± 3, Changed the MAX value From: ±8 To: ±16 in the
Electrical Characteristics ....................................................................................................................................................... 5
•
Changed Differential nonlinearity Test Conditions From: 16-bit monotonic To: three separate entries in the Electrical
Characteristics ....................................................................................................................................................................... 5
•
Changed Input LOW voltage 5 V MAX value From: 0.8 To: 0.3 X VDD in the Electrical Characteristics .............................. 6
•
Changed Input LOW voltage 3 V MAX value From: 0.6 To: 0.1 X VDD in the Electrical Characteristics .............................. 6
•
Changed Input HIGH voltage 5 V MIN value From: 2.4 To:0.7 X VDD in the Electrical Characteristics ................................ 6
•
Changed Input HIGH voltage 3 V MIN value From: 2.1 To:0.9 X VDD in the Electrical Characteristics ................................ 6
Changes from Revision B (October 2006) to Revision C
Page
•
Removed Packaging/Ordering Information table.................................................................................................................... 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
2
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SLAS429E – APRIL 2005 – REVISED JUNE 2017
5 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
VDD
1
VREF
2
8
GND
7
DIN
DAC8551
VFB
3
6
SCLK
VOUT
4
5
SYNC
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock
input. Schmitt-Trigger logic input.
DIN
7
I
GND
8
GND
SCLK
6
I
Serial clock input. Data can be transferred at rates up to 30-MHz Schmitt-Trigger logic input.
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data.
When SYNC goes LOW, it enables the input shift register and data is transferred in on the falling edges
of the following clocks. The DAC is updated following the 24th clock (unless SYNC is taken HIGH before
this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored
by the DAC8551). Schmitt-Trigger logic input.
Ground reference point for all circuitry on the part
SYNC
5
I
VDD
1
PWR
VFB
3
I
Feedback connection for the output amplifier. For voltage output operation, tie to VOUT externally.
VOUT
4
O
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
VREF
2
I
Reference voltage input
Power supply input, 2.7 V to 5.5 V
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6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN
MAX
Input voltage
GND
–0.3
6
V
Digital input voltage
GND
–0.3
VDD + 0.3
V
Output voltage
GND
–0.3
VDD + 0.3
V
–40
105°C
°C
150°C
°C
150
°C
Operating temperature
Junction temperature, TJ
Storage temperature, Tstg
(1)
–65
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage (VDD to GND)
NOM
MAX
UNIT
2.7
5.5
V
Digital input voltage (DIN, SCLK, and SYNC)
0
VDD
V
VREF
Reference input voltage
0
VDD
V
VFB
Output amplifier feedback input
TA
Operating ambient temperature
105
°C
VOUT
V
–40
6.4 Thermal Information
DAC8551
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
206
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
44
°C/W
RθJB
Junction-to-board thermal resistance
94.2
°C/W
ψJT
Junction-to-top characterization parameter
10.2
°C/W
ψJB
Junction-to-board characterization parameter
92.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VDD = 2.7 V to 5.5 V and –40°C to 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC8551
±12
LSB
DAC8551A
±16
LSB
2.5 V ≤ VREF ≤ 5.5 V, 0°C ≤ TA ≤ 105°C
±1
LSB
4.2 V < VREF ≤ 5.5 V, -40°C ≤ TA ≤ 105°C
±1
LSB
2.5 V ≤ VREF ≤ 4.2 V, -40°C ≤ TA ≤ 0°C
±2
LSB
STATIC PERFORMANCE (1)
Resolution
Relative accuracy
Differential nonlinearity
Zero-code error
Full-scale error
Gain error
PSRR
16
Measured by line passing through
codes 485 and 64741 at VREF = 5
V, codes 970 and 63947 at
VREF = 2.5 V
±2
±12
mV
±0.05%
±0.5%
FSR
DAC8551
±0.02%
±0.15%
FSR
DAC8551A
±0.02%
±0.2%
Measured by line passing through codes 485 and 64741
Measured by line passing through
codes 485 and 64741
Bits
FSR
Zero-code error drift
±5
μV/°C
Gain temperature coefficient
±1
ppm of
FSR/°C
Power-supply rejection ratio
RL = 2 kΩ, CL = 200 pF
0.75
mV/V
OUTPUT CHARACTERISTICS (2)
Output voltage range
Output voltage settling time
0
To ±0.003% FSR, 0200h to FD00h, RL = 2 kΩ,
0 pF < CL < 200 pF
8
RL = 2 kΩ, CL = 50 pF
Slew rate
Capacitive load stability
RL = ∞
RL = 2 kΩ
10
μs
12
μs
V/μs
470
pF
1000
pF
1 LSB change around major carry
0.1
Digital feedthrough
50 kΩ series resistance on digital lines
0.1
DC output impedance
At mid-code input
Power-up time
V
1.8
Code change glitch impulse
Short-circuit current
VREF
nV-s
Ω
1
VDD = 5 V
50
VDD = 3 V
20
Coming out of power-down mode, VDD = 5 V
2.5
Coming out of power-down mode, VDD = 3 V
5
mA
μs
AC PERFORMANCE
SNR
Signal-to-noise ratio
BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz,
1st 19 harmonics removed for SNR calculation
95
dB
THD
Total harmonic distortion
BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz,
1st 19 harmonics removed for SNR calculation
–85
dB
SFDR
Spurious-free dynamic range
BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz,
1st 19 harmonics removed for SNR calculation
87
dB
SINAD
Signal to noise and distortion
BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz,
1st 19 harmonics removed for SNR calculation
84
dB
VREF = VDD = 5 V
40
75
μA
VREF = VDD = 3.6 V
30
45
μA
REFERENCE INPUT
Reference current
Reference input range
0
Reference input impedance
(1)
(2)
VDD
125
V
kΩ
Linearity calculated using a reduced codes range of 485 and 64741 at VREF = 5V, codes 970 and 63947 at VREF = 2.5V; output
unloaded, 100mV headroom between reference and supply
Specified by design and characterization; not production tested.
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Electrical Characteristics (continued)
VDD = 2.7 V to 5.5 V and –40°C to 105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUTS (2)
Input current
VIL
Input LOW voltage
VIH
Input HIGH voltage
±1
μA
3 V ≤ VDD ≤ 5.5 V
0.3 X VDD
2.7 V ≤ VDD < 3 V
0.1 X VDD
3 V ≤ VDD ≤ 5.5 V
0.7 X VDD
2.7 V ≤ VDD < 3 V
0.9 X VDD
V
V
Pin capacitance
3
pF
5.5
V
POWER REQUIREMENTS
VDD
IDD
Supply voltage
Supply current
2.7
Normal mode, input code = 32768,
no load, does not include
reference current
All power-down modes,
VIH = VDD and VIL = GND
IOUT/IDD Power efficiency
VDD = 3.6 V to 5.5 V,
VIH = VDD and
VIL = GND
160
VDD = 2.7 V to 3.6 V,
VIH = VDD and
VIL = GND
140
240
VDD = 3.6 V to 5.5 V
0.2
2
VDD = 2.7 V to 3.6 V
0.05
2
6
μA
ILOAD = 2 mA, VDD = 5 V
Specified performance
temperature
μA
89%
–40
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250
105
°C
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6.6 Timing Characteristics
VDD = 2.7 V to 5.5 V, all specifications –40°C to 105°C (unless otherwise noted) (1) (2)
PARAMETER
TEST CONDITIONS
t1 (3)
SCLK cycle time
t2
SCLK HIGH time
t3
SCLK LOW time
t4
SYNC to SCLK rising edge setup time
t5
Data setup time
t6
Data hold time
t7
24th SCLK falling edge to SYNC rising edge
t8
Minimum SYNC HIGH time
t9
24th SCLK falling edge to SYNC falling edge
(1)
(2)
(3)
MIN
VDD = 2.7 V to 3.6 V
50
VDD = 3.6 V to 5.5 V
33
VDD = 2.7 V to 3.6 V
13
VDD = 3.6 V to 5.5 V
13
VDD = 2.7 V to 3.6 V
22.5
VDD = 3.6 V to 5.5 V
13
VDD = 2.7 V to 3.6 V
0
VDD = 3.6 V to 5.5 V
0
VDD = 2.7 V to 3.6 V
5
VDD = 3.6 V to 5.5 V
5
VDD = 2.7 V to 3.6 V
4.5
VDD = 3.6 V to 5.5 V
4.5
VDD = 2.7 V to 3.6 V
0
VDD = 3.6 V to 5.5 V
0
VDD = 2.7 V to 3.6 V
50
VDD = 3.6 V to 5.5 V
33
VDD = 2.7 V to 5.5 V
100
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH) / 2.
See Figure 1.
Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.
t9
t1
SCLK
1
24
t8
t3
t4
t2
t7
SYNC
t6
t5
DIN
DB23
DB0
DB23
Figure 1. Serial Write Operation
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6.7 Typical Characteristics
6.7.1 VDD = 5 V
At TA = 25°C (unless otherwise noted)
6
4
2
0
-2
-4
-6
LE (LSB)
VDD = 5V, VREF = 4.99V
1.0
1.0
0.5
0.5
DLE (LSB)
DLE (LSB)
LE (LSB)
6
4
2
0
-2
-4
-6
0
-0.5
-1.0
0
-0.5
-1.0
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
Figure 2. Linearity Error and Differential Linearity Error vs
Digital Input Code (–40°C)
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
Figure 3. Linearity Error and Differential Linearity Error vs
Digital Input Code
10
VDD = 5V
VREF = 4.99V
VDD = 5V, VREF = 4.99V
5
Error (mV)
LE (LSB)
6
4
2
0
-2
-4
-6
1.0
DLE (LSB)
VDD = 5V, VREF = 4.99V
0
0.5
0
-0.5
-5
-1.0
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
-40
40
80
120
Temperature (°C)
Figure 4. Linearity Error and Differential Linearity Error vs
Digital Input Code (105°C)
Figure 5. Zero-Scale Error vs Temperature
0
6
VDD = 5V
VREF = 4.99V
5
DAC Loaded with FFFFh
VOUT (mV)
Error (mV)
4
-5
3
VDD = 5.5V
VREF = VDD - 10mV
2
1
DAC Loaded with 0000h
0
-10
-40
8
0
40
80
120
0
2
4
6
8
Temperature (°C)
I(SOURCE/SINK) (mA)
Figure 6. Full-Scale Error vs Temperature
Figure 7. Source and Sink Current Capability
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VDD = 5 V (continued)
At TA = 25°C (unless otherwise noted)
300
250
VDD = VREF = 5V
250
VREF = VDD = 5V
200
IDD (mA)
IDD (mA)
200
Reference Current Included
150
150
100
100
50
50
0
0
0
-40
8192 16384 24576 32768 40960 49152 57344 65536
80
Figure 8. Supply Current vs Digital Input Code
Figure 9. Power-Supply Current vs Temperature
1.0
VREF = VDD
Reference Current Included, No Load
Power-Down Current (mA)
260
240
IDD (mA)
50
Temperature (°C)
300
280
20
-10
Digital Input Code
220
200
180
160
140
110
VREF = VDD
0.8
0.6
0.4
0.2
120
100
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3.1
VDD (V)
3.5
4.3
4.7
5.1
5.5
VDD (V)
Figure 10. Supply Current vs Supply Voltage
Figure 11. Power-Down Current vs Supply Voltage
1800
TA = 25°C, SCL Input (all other inputs = GND)
VDD = VREF = 5.5V
1600
Trigger Pulse 5V/div
1400
IDD (mA)
1200
1000
800
VDD = 5V
VREF = 4.096V
From Code: D000
To Code: FFFF
600
400
Rising Edge
1V/div
200
0
0
1
2
3
4
VLOGIC (V)
Figure 12. Supply Current vs Logic Input Voltage
5
Zoomed Rising Edge
1mV/div
Time (2ms/div)
Figure 13. Full-Scale Settling Time, 5-V Rising Edge
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VDD = 5 V (continued)
At TA = 25°C (unless otherwise noted)
Trigger Pulse 5V/div
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: FFFF
To Code: 0000
Rising
Edge
1V/div
Falling
Edge
1V/div
Zoomed Falling Edge
1mV/div
VDD = 5V
VREF = 4.096V
From Code: 4000
To Code: CFFF
Zoomed Rising Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 14. Full-Scale Settling Time, 5-V Falling Edge
Figure 15. Half-Scale Settling Time, 5-V Rising Edge
VDD = 5V
VREF = 4.096V
From Code: CFFF
To Code: 4000
Falling
Edge
1V/div
VOUT (500mV/div)
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (400ns/div)
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
Figure 17. Glitch Energy: 5-V, 1-LSB Step, Rising Edge
VOUT (500mV/div)
VOUT (500mV/div)
Figure 16. Half-Scale Settling Time, 5-V Falling Edge
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
Time (400ns/div)
Time (400ns/div)
Figure 18. Glitch Energy: 5-V, 1-LSB Step, Falling Edge
10
Figure 19. Glitch Energy: 5-V, 16-LSB Step, Rising Edge
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VDD = 5 V (continued)
At TA = 25°C (unless otherwise noted)
VOUT (5mV/div)
VOUT (500mV/div)
VDD = 5V
VREF = 4.096V
From Code: 8010
To Code: 8000
Glitch: 0.08nV-s
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 20. Glitch Energy: 5-V, 16-LSB Step, Falling Edge
Figure 21. Glitch Energy: 5-V, 256-LSB Step, Rising Edge
-40
VDD = 5V
VREF = 4.9V
-1dB FSR Digital Input
fS = 1MSPS
Measurement Bandwidth = 20kHz
-50
-60
THD (dB)
VOUT (5mV/div)
VDD = 5V
VREF = 4.096V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
-70
THD
-80
-90
2nd Harmonic
3rd Harmonic
-100
0
1
2
Time (400ns/div)
Figure 22. Glitch Energy: 5-V, 256-LSB Step, Falling Edge
98
5
VDD = 5V
VREF = 4.096V
fOUT = 1kHz
f
= 1MSPS
-10
-30
CLK
Gain (dB)
SNR (dB)
94
4
Figure 23. Total Harmonic Distortion vs Output Frequency
VREF = VDD = 5V
-1dB FSR Digital Input
fS = 1MSPS
Measurement Bandwidth = 20kHz
96
3
fOUT (kHz)
92
90
-50
-70
88
-90
86
-110
84
-130
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.5
0
5
10
15
20
Frequency (kHz)
fOUT (kHz)
Figure 24. Signal-to-Noise Ratio vs Output Frequency
Figure 25. Power Spectral Density
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VDD = 5 V (continued)
At TA = 25°C (unless otherwise noted)
350
VDD = 5V
VREF = 4.99V
Code = 7FFFh
No Load
Voltage Noise (nV/ÖHz)
300
250
200
150
100
100
1k
10k
100k
Frequency (Hz)
Figure 26. Output Noise Density
6.7.2 VDD = 2.7 V
6
4
2
0
-2
-4
-6
LE (LSB)
1.0
1.0
0.5
0.5
0
-0.5
-1.0
8192
16384 24576 32768 40960 49152
Digital Input Code
6
4
2
0
-2
-4
-6
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
Figure 28. Linearity Error and differential Linearity Error vs
Digital Input Code
10
VDD = 2.7V
VREF = 2.69V
VDD = 2.7V, VREF = 2.69V
5
Error (mV)
LE (LSB)
0
-0.5
57344 65536
Figure 27. Linearity Error and Differential Linearity Error
vs Digital Input Code (–40°C)
1.0
DLE (LSB)
VDD = 2.7V, VREF = 2.69V
-1.0
0
0.5
0
0
-0.5
-5
-1.0
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
-40
40
80
120
Temperature (°C)
Figure 29. Linearity Error and Differential Linearity Error
vs Digital Input Code (105°C)
12
6
4
2
0
-2
-4
-6
VDD = 2.7V, VREF = 2.69V
DLE (LSB)
DLE (LSB)
LE (LSB)
At TA = 25°C (unless otherwise noted)
Figure 30. Zero-Scale Error vs Temperature
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VDD = 2.7 V (continued)
At TA = 25°C (unless otherwise noted)
5
3.0
VDD = 2.7V
VREF = 2.69V
2.5
DAC Loaded with FFFFh
2.0
VOUT (mV)
Error (mV)
0
1.5
VDD = 2.7V
VREF = VDD - 10mV
1.0
-5
0.5
DAC Loaded with 0000h
0
-10
0
-40
40
80
0
120
4
6
8
I(SOURCE/SINK) (mA)
Figure 31. Full-Scale Error vs Temperature
Figure 32. Source and Sink Current Capability
180
250
VDD = VREF = 2.7V
160
2
Temperature (°C)
10
VREF = VDD = 2.7V
200
140
Reference Current Included
IDD (mA)
IDD (mA)
120
100
80
150
100
60
40
50
20
0
0
8192 16384 24576 32768 40960 49152 57344 65536
0
-40
-10
20
50
80
110
Digital Input Code
Temperature (°C)
Figure 33. Supply Current vs Digital Input Code
Figure 34. Power-Supply Current vs Temperature
800
TA = 25°C, SCL Input (all other inputs = GND)
VDD = VREF = 2.7V
700
Trigger Pulse 2.7V/div
600
Rising
Edge
0.5V/div
IDD (mA)
500
400
VDD = 2.7V
VREF = 2.5V
From Code: 0000
To Code: FFFF
300
200
100
Zoomed Rising Edge
1mV/div
0
0
0.5
1.0
1.5
2.0
2.5 2.7
Time (2ms/div)
VLOGIC (V)
Figure 35. Supply Current vs Logic Input Voltage
Figure 36. Full-Scale Settling Time: 2.7-V Rising Edge
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VDD = 2.7 V (continued)
At TA = 25°C (unless otherwise noted)
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
VDD = 2.7V
VREF = 2.5V
From Code: FFFF
To Code: 0000
Zoomed Falling Edge
1mV/div
Falling
Edge
0.5V/div
VDD = 2.7V
VREF = 2.5V
From Code: 4000
To Code: CFFF
Rising
Edge
0.5V/div
Time (2ms/div)
Zoomed Rising Edge
1mV/div
Time (2ms/div)
Figure 37. Full-Scale Settling Time: 2.7-V Falling Edge
Figure 38. Half-Scale Settling Time: 2.7-V Rising Edge
VDD = 2.7V
VREF = 2.5V
From Code: CFFF
To Code: 4000
Falling
Edge
0.5V/div
VOUT (200mV/div)
Trigger Pulse 2.7V/div
VDD = 2.7V
VREF = 2.5V
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (400ns/div)
VDD = 2.7V
VREF = 2.5V
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
Figure 40. Glitch Energy: 2.7-V, 1-LSB Step, Rising Edge
VOUT (200mV/div)
VOUT (200mV/div)
Figure 39. Half-Scale Settling Time: 2.7-V Falling Edge
VDD = 2.7V
VREF = 2.5V
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
Time (400ns/div)
Time (400ns/div)
Figure 41. Glitch Energy: 2.7-V, 1-LSB Step, Falling Edge
14
Figure 42. Glitch Energy: 2.7-V, 16-LSB Step, Rising Edge
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VDD = 2.7 V (continued)
At TA = 25°C (unless otherwise noted)
VOUT (5mV/div)
VOUT (200mV/div)
VDD = 2.7V
VREF = 2.5V
From Code: 8010
To Code: 8000
Glitch: 0.12nV-s
Time (400ns/div)
Time (400ns/div)
Figure 43. Glitch Energy: 2.7-V, 16-LSB Step, Falling Edge
VOUT (5mV/div)
VDD = 2.7V
VREF = 2.5V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Figure 44. Glitch Energy: 2.7-V, 256-LSB Step, Rising Edge
VDD = 2.7V
VREF = 2.5V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Figure 45. Glitch Energy: 2.7-V, 256-LSB Step, Falling Edge
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7 Detailed Description
7.1 Overview
The DAC8551 is a small, low-power, voltage output, single-channel, 16-bit, DAC. The device is monotonic by
design, provides excellent linearity, and minimizes undesired code-to-code transient voltages. The DAC8551
uses a versatile, three-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with
standard SPI, QSPI, Microwire, and digital signal processor (DSP) interfaces.
7.2 Functional Block Diagram
VDD
VFB
VREF
Ref (+)
VOUT
16-Bit DAC
16
DAC Register
16
SYNC
SCLK
Shift Register
Resistor
Network
PWD Control
DIN
GND
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 DAC Section
The DAC8551 architecture consists of a string DAC followed by an output buffer amplifier. Figure 46 shows a
block diagram of the DAC architecture.
VREF
50kW
50kW
VFB
62kW
DAC
Register
REF (+)
Register String
REF (-)
VOUT
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 46. DAC8551 Architecture
The input coding to the DAC8551 is straight binary, so the ideal output voltage is given by:
D IN
VO =
´ VREF
65536
where
•
16
DIN = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535 (1)
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Feature Description (continued)
7.3.1.1 Resistor String
The resistor string section is shown in Figure 47. It is simply a string of resistors, each of value R. The code
loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the
output amplifier by closing one of the switches connecting the string to the amplifier. Monotonicity is ensured
because of the string resistor architecture.
7.3.1.2 Output Amplifier
The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of
0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink
capabilities of the output amplifier can be seen in the Typical Characteristics section VDD = 5 V. The slew rate is
1.8 V/μs with a full-scale setting time of 8 μs with the output unloaded.
The inverting input of the output amplifier is brought out to the VFB pin. This configuration allows for better
accuracy in critical applications by tying the VFB point and the amplifier output together directly at the load. Other
signal conditioning circuitry may also be connected between these points for specific applications.
VREF
RDIVIDER
VREF
2
R
R
To Output Amplifier
(2x Gain)
R
R
Figure 47. Resistor String
7.3.2 Power-On Reset
The DAC8551 contains a power-on-reset circuit that controls the output voltage during power up. On power up,
the DAC registers are filled with zeros and the output voltages are 0 V; they remain that way until a valid write
sequence is made to the DAC. The power-on reset is useful in applications where it is important to know the
state of the output of the DAC while it is in the process of powering up.
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7.4 Device Functional Modes
7.4.1 Power-Down Modes
The DAC8551 supports four separate modes of operation. These modes are programmable by setting two bits
(PD1 and PD0) in the control register. Table 1 shows how the state of the bits corresponds to the mode of
operation of the device.
Table 1. Operating Modes
PD1 (DB17)
PD0 (DB16)
0
0
Normal operation
OPERATING MODE
0
1
Output typically 1 kΩ to GND
1
0
Output typically 100 kΩ to GND
1
1
High-Z
Power-down modes
When both bits are set to '0', the device works normally with its typical current consumption of 200 μA at 5 V.
However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only
does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a
resistor network of known values. This configuration has the advantage that the output impedance of the device
is known while it is in power-down mode. There are three different options. The output is connected internally to
GND through a 1-kΩ resistor, a 100-kΩ resistor, or it is left open-circuited (High-Z). The output stage is illustrated
in Figure 48.
VFB
Resistor
String
DAC
Amplifier
Power-Down
Circuitry
VOUT
Resistor
Network
Copyright © 2016, Texas Instruments Incorporated
Figure 48. Output Stage During Power-Down
All analog circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit power-down is typically 2.5 μs for VDD = 5 V, and 5
μs for VDD = 3 V. See Typical Characteristics for more information.
7.5 Programming
7.5.1 Serial Interface
The DAC8551 has a 3-wire serial interface (SYNC, SCLK, and DIN), which is compatible with SPI, QSPI, and
Microwire interface standards, as well as most DSPs. See Figure 1 for an example of a typical write sequence.
The write sequence begins by bringing the SYNC line LOW. Data from the DIN line are clocked into the 24-bit
shift register on each falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the
DAC8551 compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is
clocked in and the programmed function is executed (that is, a change in DAC register contents and/or a change
in the mode of operation).
At this point, the SYNC line may be kept LOW or brought HIGH. In either case, it must be brought HIGH for a
minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write
sequence. As previously mentioned, it must be brought HIGH again just before the next write sequence.
18
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Programming (continued)
7.5.2 Input Shift Register
The input shift register is 24 bits wide, as shown in Figure 49. The first six bits are unused bits. The next two bits
(PD1 and PD0) are control bits that control which mode of operation the part is in (normal mode or any one of
three power-down modes). A more complete description of the various modes is located in Power-Down Modes.
The next 16 bits are the data bits. These bits are transferred to the DAC register on the 24th falling edge of
SCLK.
23 22 21 20 19 18 17
16
15
14
13
12
11
10
Unused
PD1 PD0 D15 D14 D13 D12 D11 D10
9
D9
8
D8
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
Figure 49. DAC8551 Data Input Register Format
7.5.3 SYNC Interrupt
In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the DAC is
updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, it acts as an
interrupt to the write sequence. The shift register is reset, and the write sequence is seen as invalid. Neither an
update of the DAC register contents nor a change in the operating mode occurs, as shown in Figure 50.
24th Falling Edge
24th Falling Edge
CLK
SYNC
DIN
DB23
DB80
DB23
DB80
Valid Write Sequence: Output Updates
on the 24th Falling Edge
Figure 50. SYNC Interrupt Facility
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The low-power consumption of the DAC8551 lends itself to applications such as loop-powered control where the
current dissipation of each device is critical. The low power consumption also allows the DAC8551 to be powered
using only a precision reference for increased accuracy. The low-power operation coupled with the ultra-low
power power-down modes also make the DAC8551 a great choice for battery and portable applications.
8.1.1 Bipolar Operation Using the DAC8551
The DAC8551 has been designed for single-supply operation, but a bipolar output range is also possible using
the circuit in Figure 51. The circuit shown gives an output voltage range of ±VREF. Rail-to-rail operation at the
amplifier output is achievable using an OPA703 as the operational amplifier. See CMOS, Rail-to-Rail, I/O
Operational Amplifiers (SBOS180) for more information.
VREF
R2
10kW
+6V
R1
10kW
OPA703
5V
VFB
VREF
10mF
DAC8551
VOUT
–6V
0.1mF
Three-Wire
Serial Interface
Copyright © 2016, Texas Instruments Incorporated
Figure 51. Bipolar Output Range
The output voltage for any input code can be calculated as follows:
é
æ R 2 öù
æ D ö æ R1 + R 2 ö
VO = ê VREF ´ ç
´ç
÷ - VREF ´ ç
÷ú
÷
è 65536 ø è R 1 ø
è R 1 ø ûú
ëê
where
•
D is the input code in decimal (0–65535)
With VREF = 5 V, R1 = R2 = 10 kΩ.
æ 10 ´ D ö
VO = ç
÷-5 V
è 65536 ø
(2)
(3)
Using this example, an output voltage range of ±5 V—with 0000h corresponding to a –5-V output and FFFFh
corresponding to a 5-V output—can be achieved. Similarly, using VREF = 2.5 V, a ±2.5-V output voltage range
can be achieved.
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8.2 Typical Application
8.2.1 Loop-Powered, 2-Wire, 4-mA to 20-mA Transmitter With XTR116
VREG
C2 || C3
0.1001 µF
XTR116
Vref
U1
V+
R1
102.4 kΩ
Vref
DAC8551
VOUT
Reference
C1
2.2 µF
R2
49.9 W
V+
V+
Regulator
V+
IIN
+
B
U2
R3
25.6 kΩ
Q1
Q1
RLIM
IRET
2475 Ω
E
25 Ω
IO
Return
Copyright © 2016, Texas Instruments Incorporated
Figure 52. Loop-Powered Transmitter
8.2.1.1 Design Requirements
This design is commonly referred to as a loop-powered, or 2-wire, 4-mA to 20-mA transmitter. The transmitter
has only two external input terminals: a supply connection and an output, or return, connection. The transmitter
communicates back to its host, typically a PLC analog input module, by precisely controlling the magnitude of its
return current. In order to conform to the 4-mA to 20-mA communication standard, the complete transmitter must
consume less than 4 mA of current. The DAC8551 enables the accurate control of the loop current from 4 mA to
20 mA in 16-bit steps.
8.2.1.2 Detailed Design Procedure
Although it is possible to recreate the loop-powered circuit using discrete components, the XTR116 provides
simplicity and improved performance due to the matched internal resistors. The output current can be modified if
necessary by looking using Equation 4.
æ V ´ Code VREG
+
I OUT (Code) = ç refN
ç 2 ´ R3
R1
è
ö æ
ö
÷ ´ ç 1 + 2475 W ÷
÷ è
25 W ø
ø
(4)
See 2-wire, 4-mA to 20-mA Transmitter, EMC/EMI Tested Reference Design (TIDUAO7) for more information. It
covers in detail the design of this circuit as well as how to protect it from EMC/EMI tests.
8.2.1.3 Application Curves
Total unadjusted error (TUE) is a good estimate for the performance of the output as shown in Figure 53. The
linearity of the output or INL is in Figure 54.
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Typical Application (continued)
10
0.1
Integral Nonlinearity (LSBs)
Total Unadjusted Error (%FSR)
8
0.05
0
-0.05
6
4
2
0
-2
-4
-6
-8
-10
-0.1
0
10k
20k
30k
40k
Code
50k
0
60k 65535
10k
20k
D001
Figure 53. Total Unadjusted Error
30k
40k
Code
50k
60k 65535
D002
Figure 54. Integral Nonlineareity
8.2.2 Using the REF02 as a Power Supply for the DAC8551
+15V
+5V
REF02
285mA
SYNC
Three-Wire
Serial
Interface
SCLK
DAC8551
VOUT = 0V to 5V
DIN
Copyright © 2016, Texas Instruments Incorporated
Figure 55. REF02 as a Power Supply to the DAC8551
8.2.2.1 Design Requirements
Due to the extremely low supply current required by the DAC8551, an alternative option is to use the REF02 to
supply the required voltage to the device, as illustrated in Figure 55. See +5V Precision Voltage Reference
(SBVS003) for more inforation.
8.2.2.2 Detailed Design Procedure
This configuration is especially useful if the power supply is quite noisy or if the system supply voltages are at
some value other than 5 V. The REF02 outputs a steady supply voltage for the DAC8551. If the REF02 is used,
the current it needs to supply to the DAC8551 is 200 μA. This configuration is with no load on the output of the
DAC. When a DAC output is loaded, the REF02 also needs to supply the current to the load.
The total typical current required (with a 5-kΩ load on the DAC output) is:
5V
200 µA +
= 1.2 mA
5 kW
(5)
The load regulation of the REF02 is typically 0.005%/mA, resulting in an error of 299 μV for the 1.2-mA current
drawn from it. This value corresponds to a 3.9-LSB error.
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8.3 System Examples
8.3.1 Microprocessor Interfacing
8.3.1.1 DAC8551 to 8051 Interface
Figure 56 shows a serial interface between the DAC8551 and a typical 8051-type microcontroller.
The interface is setup with the TXD of the 8051 drives SCLK of the DAC8551, while RXD drives the serial data
line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case,
port line P3.3 is used. When data are to be transmitted to the DAC8551, P3.3 is taken LOW. The 8051 transmits
data in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3
is left LOW after the first eight bits are transmitted, then a second write cycle is initiated to transmit the second
byte of data. P3.3 is taken HIGH following the completion of the third write cycle. The 8051 outputs the serial
data in a format that has the LSB first. The DAC8551 requires data with the MSB as the first bit received. The
8051 transmit routine must therefore take this into account, and mirror the data as needed.
80C51/80L51(1)
DAC8554(1)
P3.3
SYNC
TXD
SCLK
RXD
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 56. DAC8551 to 80C51 or 80L51 Interface
8.3.1.2 DAC8551 to Microwire Interface
Figure 57 shows an interface between the DAC8551 and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and is clocked into the DAC8551 on the rising edge of the SK
signal.
MicrowireTM
DAC8554(1)
CS
SYNC
SK
SCLK
SO
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 57. DAC8551 to Microwire Interface
8.3.1.3 DAC8551 to 68HC11 Interface
Figure 58 shows a serial interface between the DAC8551 and the 68HC11 microcontroller. SCK of the 68HC11
drives the SCLK of the DAC8551, while the MOSI output drives the serial data line of the DAC. The SYNC signal
is derived from a port line (PC7), similar to the 8051 diagram.
68HC11(1)
DAC8551(1)
PC7
SYNC
SCK
SCLK
MOSI
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 58. DAC8551 to 68HC11 Interface
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System Examples (continued)
The 68HC11 should be configured so that its CPOL bit is '0' and its CPHA bit is '1'. This configuration causes
data appearing on the MOSI output to be valid on the falling edge of SCK. When data are being transmitted to
the DAC, the SYNC line is held LOW (PC7). Serial data from the 68HC11 are transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. (Data are transmitted MSB first.) In order to load data to
the DAC8551, PC7 is left LOW after the first eight bits are transferred, then a second and third serial write
operation are performed to the DAC. PC7 is taken HIGH at the end of this procedure.
9 Power Supply Recommendations
The DAC8551 can operate within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to VDD
should be well-regulated and low-noise. Switching power supplies and DCDC converters often have highfrequency glitches or spikes riding on the output voltage. In addition, digital components can create similar highfrequency spikes. This noise can easily couple into the DAC output voltage through various paths between the
power connections and analog output. TI recommends including a 1-µF to 10-µF capacitor and 0.1-µF bypass
capacitor in order to further minimize noise from the power supply. The current consumption on the VDD pin, the
short-circuit current limit, and the load current for the device is listed in Electrical Characteristics. The power
supply must meet the aforementioned current requirements.
10 Layout
10.1 Layout Guidelines
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies.
The DAC8551 offers single-supply operation, and it often is used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and
the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output.
Due to the single ground pin of the DAC8551, all return currents, including digital and analog return currents for
the DAC, must flow through a single point. Ideally, GND would be connected directly to an analog ground plane.
This plane would be separate from the ground connection for the digital components until they were connected at
the power-entry point of the system.
As with the GND connection, VDD should be connected to a 5-V power-supply plane or trace that is separate
from the connection for digital logic until they are connected at the power-entry point. TI recommends an
additional 1-μF to 10-μF capacitor and 0.1-μF bypass capacitor. In some situations, additional bypassing may be
required, such as a 100-μF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all
designed to essentially low-pass filter the 5-V supply, removing the high-frequency noise.
10.2 Layout Example
1
2
3
4
8
7
6
5
Figure 59. Layout Diagram
24
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DAC8551
DAC8551
www.ti.com
SLAS429E – APRIL 2005 – REVISED JUNE 2017
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• 2-wire, 4-mA to 20-mA Transmitter, EMC/EMI Tested Reference Design, TIDUAO7
• +5V Precision Voltage Reference, SBVS003
• CMOS, Rail-to-Rail, I/O Operational Amplifiers, SBOS180
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2005–2017, Texas Instruments Incorporated
Product Folder Links: DAC8551
25
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC8551IADGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 105
D81
DAC8551IADGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 105
D81
DAC8551IADGKTG4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 105
D81
DAC8551IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 105
D81
DAC8551IDGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 105
D81
DAC8551IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 105
D81
DAC8551IDGKTG4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 105
D81
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC8551 :
• Automotive: DAC8551-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
DAC8551IADGKR
VSSOP
DGK
8
DAC8551IADGKT
VSSOP
DGK
DAC8551IDGKR
VSSOP
DGK
DAC8551IDGKT
VSSOP
DGK
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC8551IADGKR
VSSOP
DGK
8
2500
350.0
350.0
43.0
DAC8551IADGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
DAC8551IDGKR
VSSOP
DGK
8
2500
350.0
350.0
43.0
DAC8551IDGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
Pack Materials-Page 2
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