Texas Instruments | LM98714 Three Channel, 16-Bit, 45 MSPS Analog Front End With LVDS/CMOS Output and Integrated CCD/CIS Sensor Timing Generator (Rev. B) | Datasheet | Texas Instruments LM98714 Three Channel, 16-Bit, 45 MSPS Analog Front End With LVDS/CMOS Output and Integrated CCD/CIS Sensor Timing Generator (Rev. B) Datasheet

Texas Instruments LM98714 Three Channel, 16-Bit, 45 MSPS Analog Front End With LVDS/CMOS Output and Integrated CCD/CIS Sensor Timing Generator (Rev. B) Datasheet
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LM98714
SNAS254B – OCTOBER 2006 – REVISED APRIL 2017
LM98714 Three Channel, 16-Bit, 45 MSPS Analog Front End With LVDS/CMOS Output and
Integrated CCD/CIS Sensor Timing Generator
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
LVDS/CMOS Outputs
LVDS/CMOS Pixel Rate Input Clock or ADC Input
Clock
CDS or S/H Processing for CCD or CIS Sensors
Independent Gain/Offset Correction for Each
Channel
Digital Black Level Correction Loop for Each
Channel
Programmable Input Clamp Voltage
Flexible CCD/CIS Sensor Timing Generator
Key Specifications
– Maximum Input Level: 1.2 or 2.4 Volt Modes
– (Both with + or – Polarity Option)
– ADC Resolution: 16-Bit
– ADC Sampling Rate: 45 MSPS
– INL: ±23 LSB (Typ)
– Channel Sampling Rate: 15/22.5/30 MSPS
– PGA Gain Steps: 256 Steps
– PGA Gain Range: 0.7 to 7.84x
– Analog DAC Resolution: ±9 Bits
– Analog DAC Range: ±300 mV or ±600 mV
– Digital DAC Resolution: ±6 Bits
– Digital DAC Range: –1024 LSB to + 1008 LSB
– SNR: –74dB (at 0 dB PGA Gain)
– Power Dissipation: 505 mW (LVDS) 610 mW
(CMOS)
– Operating Temp: 0 to 70°C
– Supply Voltage: 3.3 V Nominal (3.0 V to 3.6 V
Range)
Multi-Function Peripherals
Facsimile Equipment
Flatbed or Handheld Color Scanners
High-Speed Document Scanner
3 Description
The LM98714 is a fully integrated, high performance
16-Bit, 45 MSPS signal processing solution for digital
color copiers, scanners, and other image processing
applications. High-speed signal throughput is
achieved with an innovative architecture utilizing
Correlated Double Sampling (CDS), typically
employed with CCD arrays, or Sample and Hold
(S/H) inputs (for Contact Image Sensors and CMOS
image sensors). The signal paths utilize 8 bit
Programmable Gain Amplifiers (PGA), a ±9-Bit offset
correction DAC and independently controlled Digital
Black Level correction loops for each input. The PGA
and offset DAC are programmed independently
allowing unique values of gain and offset for each of
the three inputs. The signals are then routed to a 45
MHz high performance analog-to-digital converter
(ADC). The fully differential processing channel
shows exceptional noise immunity, having a very low
noise floor of –74dB. The 16-bit ADC has excellent
dynamic performance making the LM98714
transparent in the image reproduction chain.
Device Information(1)
PART NUMBER
LM98714
PACKAGE
TSSOP (48)
BODY SIZE (NOM)
12.50 mm × 6.1 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
System Block Diagram
CCD/CIS Sensor
Analog Front End
SPI
LM98714
Image Processor/ASIC
Data Output
Sensor Drivers
CCD Timing
Generator
Motor
Controllers
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM98714
SNAS254B – OCTOBER 2006 – REVISED APRIL 2017
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
AC Timing Specifications .......................................... 9
Typical Characteristics ............................................ 11
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2
7.3
7.4
7.5
7.6
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
12
13
53
60
62
8
Application and Implementation ........................ 87
9
Device and Documentation Support.................. 88
8.1 Typical Application ................................................. 87
9.1
9.2
9.3
9.4
9.5
9.6
Documentation Support .......................................... 88
Receiving Notification of Documentation Updates.. 88
Community Resources............................................ 88
Trademarks ............................................................. 88
Electrostatic Discharge Caution .............................. 88
Glossary .................................................................. 88
10 Mechanical, Packaging, and Orderable
Information ........................................................... 88
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (January 2014) to Revision B
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
•
Changed the maximum values for the CMOS clock high and low input current parameters in the Electrical
Characteristics table ............................................................................................................................................................... 6
Changes from Original (October 2006) to Revision A
Page
•
Added content to complete full data sheet. ........................................................................................................................... 1
•
Deleted the reference to Reflow Temperature Profile specifications from the Absolute Maximum Ratings table ................. 5
2
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SNAS254B – OCTOBER 2006 – REVISED APRIL 2017
5 Pin Configuration and Functions
DGG Package
48-Pin TSSOP
Top View
CLK3
1
48
CLK4
CLK2
2
47
VC
CLK1
3
46
DGND
SH
4
45
CLK5
RESET
5
44
CLK6
SH_R
6
43
CLK7
SDIO
7
42
CLK8
SCLK
8
41
CLK9
SEN
9
40
CLKOUT/CLK10
AGND
10
39
VD
VA
11
38
DGND
VREFB
12
37
DOUT0/TXOUT0-
VREFT
13
36
DOUT1/TXOUT0+
VA
14
35
DOUT2/TXOUT1-
AGND
15
34
DOUT3/TXOUT1+
VCLP
16
33
DOUT4/TXOUT2-
VA
17
32
DOUT5/TXOUT2+
AGND
18
31
DOUT6/TXCLK-
48 Pin TSSOP
(not to scale)
OSR
19
30
DOUT7/TXCLK+
AGND
20
29
INCLK-
OSG
21
28
INCLK+
AGND
22
27
DVB
OSB
23
26
VR
AGND
24
25
DGND
Pin Functions
PIN
I/O (1)
TYPE (1)
RES. (1)
CLK3
O
D
PU
Configurable sensor control output.
CLK2
O
D
PD
Configurable sensor control output.
3
CLK1
O
D
PU
Configurable sensor control output.
4
SH
O
D
PD
Sensor - Shift or transfer control signal for CCD and CIS sensors.
5
RESET
I
D
PU
Active-low master reset. NC when function not being used.
6
SH_R
I
D
PD
External request for an SH pulse.
7
SDIO
I/O
D
8
SCLK
I
D
PD
Serial Interface shift register clock.
9
SEN
I
D
PU
Active-low chip enable for the Serial Interface.
10
AGND
—
P
—
Analog ground return.
11
VA
—
P
—
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
12
VREFB
O
A
—
Bottom of ADC reference. Bypass with a 0.1μF capacitor to ground.
13
VREFT
O
A
—
Top of ADC reference. Bypass with a 0.1μF capacitor to ground.
14
VA
—
P
—
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
15
AGND
—
P
—
Analog ground return.
NO.
NAME
1
2
(1)
DESCRIPTION
Serial Interface Data Input
I = Input, O = Output, IO = Bi-directional, P = Power, D = Digital, A = Analog, PU = Pullup with an internal resistor, PD = Pulldown with
an internal resistor.
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Pin Functions (continued)
PIN
I/O (1)
TYPE (1)
RES. (1)
DESCRIPTION
VCLP
IO
A
—
Input Clamp Voltage. Normally bypassed with a 0.1μF, and a 4.7μF capacitor to AGND. An external
reference voltage may be applied to this pin.
VCLP
IO
A
—
Input Clamp Voltage. Normally bypassed with a 0.1μF , and a 10μF capacitor to AGND. An external
reference voltage may be applied to this pin.
17
VA
—
P
—
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
18
AGND
—
P
—
Analog ground return.
19
OSR
I
A
—
Analog input signal. Typically sensor Red output AC-coupled through a capacitor.
20
AGND
P
—
Analog ground return.
21
OSG
A
—
Analog input signal. Typically sensor Green output AC-coupled through a capacitor.
22
AGND
P
—
Analog ground return.
23
OSB
I
A
—
Analog input signal. Typically sensor Blue output AC-coupled through a capacitor.
24
AGND
—
P
—
Analog ground return.
25
DGND
—
P
—
Digital ground return.
26
VR
—
P
—
Power supply input for internal voltage reference generator. Bypass this supply pin with a 0.1μF
capacitor.
27
DVB
O
D
—
Digital Core Voltage bypass. Not an input. Bypass with 0.1μF capacitor to DGND.
28
INCLK+
I
D
—
Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock is selected
when pin 29 is held at DGND, otherwise clock is configured for LVDS operation.
INCLK-
I
D
—
Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock.
O
D
—
Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS Mode.
O
D
—
Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS Mode.
O
D
—
Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS Mode.
O
D
—
Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS Mode.
O
D
—
Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS Mode.
O
D
—
Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS Mode.
O
D
—
Bit 1 of the digital video output bus in CMOS Mode, LVDS Data Out0+ in LVDS Mode.
O
D
—
Bit 0 of the digital video output bus in CMOS Mode, LVDS Data Out0- in LVDS Mode.
NO.
NAME
16
16
29
30
31
32
33
34
35
36
37
DOUT7/
TXCLK+
DOUT6/
TXCLKDOUT5/
TXOUT2+
DOUT4/
TXOUT2DOUT3/
TXOUT1+
DOUT2/
TXOUT1DOUT1/
TXOUT0+
DOUT0/
TXOUT0-
I
38
DGND
—
P
—
Digital ground return.
39
VD
—
P
—
Power supply for the digital circuits. Bypass this supply pin with 0.1μF capacitor. A single 4.7μF
capacitor should be used between the supply and the VD, VR and VC pins.
40
CLKOUT/
CLK10
O
D
PD
Output clock for registering output data when using CMOS outputs, or configurable sensor control
output.
41
CLK9
O
D
PD
Configurable sensor control output.
42
CLK8
O
D
PD
Configurable sensor control output.
43
CLK7
O
D
PD
Configurable sensor control output.
44
CLK6
O
D
PU
Configurable sensor control output.
45
CLK5
O
D
PD
Configurable sensor control output.
46
DGND
—
P
—
Digital ground return.
47
VC
—
P
—
Power supply for the sensor control outputs. Bypass this supply pin with 0.1μF capacitor.
48
CLK4
O
D
PD
Configurable sensor control output.
4
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6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
and
(2)
MIN
MAX
UNIT
4.2
V
–0.3
VA + 0.3
V
–0.3
VA + 0.3
V
2
V
Supply voltage (VA,VR,VD,VC)
Voltage on any input pin (not to exceed 4.2 V)
(3)
Voltage on any output pin (except DVB and not to exceed 4.2 V)
DVB output pin voltage
Input current at any pin other than supply pins
(4)
±25
mA
Package input current (except supply pins) (4)
±50
mA
Package dissipation at TA = 25°C (5)
1.89
W
150
°C
150
°C
Maximum junction temperature (TA)
−65
Storage temperature, Tstg
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are measured with respect to AGND = DGND = 0 V, unless otherwise specified.
The analog inputs are protected as shown below. Input voltage magnitudes beyond the supply rails will not damage the device, provided
the current is limited per note 3. However, input errors will be generated If the input goes above VA and below AGND.
VA
I/O
To Internal Circuitry
AGND
(4)
(5)
When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be
limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the
power supplies with an input current of 25 mA to two.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature,
TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX – TA)/θJA. The values for maximum power dissipation
listed above will be reached only when the device is operated in a severe fault condition (for example, when input or output pins are
driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
2500
Machine model (MM)
V
250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
See
(1)
MIN
(1)
NOM
MAX
UNIT
All supply voltages
3
3.6
V
Operating temperature
0
70
°C
All voltages are measured with respect to AGND = DGND = 0 V, unless otherwise specified.
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6.4 Thermal Information
LM98714
THERMAL METRIC (1)
DGG (TSSOP)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
66
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
—
°C/W
RθJB
Junction-to-board thermal resistance
—
°C/W
ψJT
Junction-to-top characterization parameter
—
°C/W
ψJB
Junction-to-board characterization parameter
—
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
The following specifications apply for VA = VD = VR = VC = 3.3 V, CL = 10 pF, and fINCLK = 15 MHz, TA = 25°C, unless
otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
CMOS Digital Input DC Specifications (RESETb, SH_R, SCLK, SENb)
VIH
Logical 1 input voltage
VIL
Logical 0 input voltage
2
0.8
RESET, VIH = VD
IIH
Logical 1 input current
SH_R, SCLK, VIH = VD
SEN, VIH = VD
RESET, VIL = DGND
IIL
Logical 0 input current
V
SH_R, SCLK, VIL = DGND
SEN, VIL = DGND
V
235
nA
70
μA
130
nA
70
μA
235
nA
70
μA
CMOS Digital Output DC Specifications (SH, CLK1 to CLK10, CMOS Data Outputs)
VOH
Logical 1 output voltage
IOUT = –0.5 mA
VOL
Logical 0 output voltage
IOUT = 1.6 mA
IOS
Output short circuit current
IOZ
CMOS output TRI-STATE current
2.95
V
0.25
VOUT = DGND
16
VOUT= VD
mA
–20
VOUT = DGND
20
VOUT = VD
V
nA
–25
CMOS Digital Input/Output DC Specifications (SDIO)
IIH
Logical 1 input current
VIH = VD
90
nA
IIL
Logical 0 input current
VIL = DGND
90
nA
LVDS/CMOS Clock Receiver DC Specifications (INCLK+ and INCLK- Pins)
VIHL
Differential LVDS clock
high threshold voltage
RL = 100 W, VCM (LVDS Input
Common Mode Voltage) = 1.25 V
VILL
Differential LVDS clock
low threshold voltage
RL = 100 W, VCM (LVDS Input
Common Mode Voltage) = 1.25 V
VIHC
CMOS clock
high threshold voltage
INCLK- = DGND
VILC
CMOS clock
low threshold voltage
INCLK- = DGND
IIHL
IILC
100
–100
mV
mV
2
V
0.8
V
CMOS clock input high current
330
μA
CMOS clock input low current
–160
μA
450
mV
LVDS Output DC Specifications
VOD
(1)
6
Differential output voltage
RL = 100 Ω
180
328
Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
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Electrical Characteristics (continued)
The following specifications apply for VA = VD = VR = VC = 3.3 V, CL = 10 pF, and fINCLK = 15 MHz, TA = 25°C, unless
otherwise specified.
PARAMETER
TEST CONDITIONS
VOS
LVDS output offset voltage
RL = 100 Ω
IOS
Output short circuit current
VOUT = 0 V, RL = 100 Ω
MIN
TYP (1)
MAX
1.17
1.23
1.3
UNIT
V
7.9
mA
Power Supply Specifications
IA
IR
VA analog supply current
VR digital supply current
VA Normal State
60
97
125
VA Low Power State (Powerdown)
12
23
32
VR Normal State (LVDS Outputs)
30
64
75
mA
CMOS Output Data Format
15
47
55
mA
LVDS Output Data Format with Data
Outputs Disabled
LVDS Output Data Format
ID
VD digital output driver supply
current
IC
VC CCD timing generator output
driver supply current
PWR
Average power dissipation
mA
47
mA
0.05
mA
CMOS Output Data Format
(ATE Loading of CMOS Outputs >
50 pF)
12
40
mA
Typical sensor outputs: SH,
CLK1=Φ1A, CLK2=Φ2A, CLK3=ΦB,
CLK4=ΦC, CLK5=RS, CLK6=CP
(ATE Loading of CMOS Outputs >
50 pF)
0.5
12
mA
LVDS Output Data Format
350
505
650
mW
CMOS Output Data Format (ATE
Loading of CMOS Outputs > 50 pF)
380
610
700
mW
Input Sampling Circuit Specifications
VIN
Input voltage level
CDS Gain=1x, PGA Gain=1x
2.3
CDS Gain=2x, PGA Gain= 1x
1.22
Source Followers Off
CDS Gain = 1x
OSX = VA (OSX = AGND)
IIN_SH
Sample and hold mode input
leakage current
Source Followers Off
CDS Gain = 2x
OSX = VA (OSX = AGND)
Source Followers On
CDS Gain = 2x
OSX = VA (OSX = AGND)
CSH
Sample/hold mode
equivalent input capacitance
(see Figure 5)
IIN_CDS
CDS mode input leakage current
RCLPIN
CLPIN switch resistance
(OSX to VCLP Node in Figure 2)
50
70
(–70)
(–40)
75
105
(–105)
(–75)
–200
–10
200
–200
–16
200
CDS Gain = 1x
2.5
CDS Gain = 2x
4
Source Followers Off
OSX = VA (OSX = AGND)
Vp-p
μA
μA
nA
pF
–300
7
300
–300
(–25)
300
16
50
nA
Ω
VCLP Reference Circuit Specifications
VCLP DAC resolution
4
VCLP DAC step size
VVCLP
ISC
Bits
0.16
V
VCLP DAC voltage minimum output
VCLP Config.
Register = 0001 0000b
0.14
0.26
0.43
V
VCLP DAC voltage maximum output
VCLP Config.
Register = 0001 1111b
2.38
2.68
2.93
V
Resistor ladder enabled
VCLP Config.
Register = 0010 xxxxb
1.54
VA / 2
1.73
V
VCLP DAC short circuit output
current
VCLP Config.
Register = 0001 xxxxb
30
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Electrical Characteristics (continued)
The following specifications apply for VA = VD = VR = VC = 3.3 V, CL = 10 pF, and fINCLK = 15 MHz, TA = 25°C, unless
otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
Black Level Offset DAC Specifications
Resolution
10
Monotonicity
Offset Adjustment Range Referred
to AFE Input
CDS Gain = 1x
Minimum DAC Code = 0x000
Maximum DAC Code = 0x3FF
–614
CDS Gain = 2x
Minimum DAC Code = 0x000
Maximum DAC Code = 0x3FF
–307
Offset adjustment range referred to
AFE output
Minimum DAC Code = 0x000
Maximum DAC Code = 0x3FF
DAC LSB step size
CDS Gain = 1x
Referred to AFE Output
DNL
Differential nonlinearity
INL
Integral nonlinearity
Bits
Ensured by characterization
mV
614
mV
307
–16000
–18200
16000
18200
1.2
LSB
mV
(32)
(LSB)
–0.95
3.25
LSB
–3.1
2.65
LSB
PGA Specifications
Gain Resolution
8
Monotonicity
Maximum gain
Minimum gain
Bits
Ensured by characterization
CDS Gain = 1x
7.18
7.9
8.77
CDS Gain = 1x
17.1
17.9
18.9
V/V
dB
CDS Gain = 1x
0.56
0.7
0.82
V/V
CDS Gain = 1x
–5
–3
–1.72
dB
Gain (V/V) = (196/(280-PGA Code))
PGA function
Channel matching
Gain (dB) = 20LOG10(196/(280PGA Code))
Minimum PGA Gain
3%
Maximum PGA Gain
12.7%
ADC Specifications
VREFT
Top of reference
2.07
V
VREFB
Bottom of reference
0.89
V
VREFT VREFB
Differential reference voltage
1.07
Overrange output code
1.18
1.29
V
65535
Underrange output code
0
Digital Offset DAC Specifications
Resolution
Digital offset DAC LSB step size
Offset adjustment range
referred to AFE output
Referred to AFE Output
7
Bits
16
LSB
Min DAC Code =7b0000000
–1024
Mid DAC Code =7b1000000
0
Max DAC Code = 7b1111111
LSB
1008
Full Channel Performance Specifications
DNL
Differential nonlinearity
INL
Integral nonlinearity
8
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–0.99
0.8 / –0.6
2.55
LSB
–73
±23
78
LSB
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Electrical Characteristics (continued)
The following specifications apply for VA = VD = VR = VC = 3.3 V, CL = 10 pF, and fINCLK = 15 MHz, TA = 25°C, unless
otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
Minimum PGA Gain
Noise floor
MAX
UNIT
–79
dB
7.2
LSB RMS
–74
PGA Gain = 1x
13
Maximum PGA Gain
Channel-to-channel crosstalk
TYP (1)
dB
30
LSB RMS
–56
dB
104
LSB RMS
Mode 3
47
Mode 2
16
LSB
6.6 AC Timing Specifications
The following specifications apply for VA = VD = VR = VC = 3.3 V, CL = 10 pF, and fINCLK = 15 MHz, TA = 25°C, unless
otherwise specified.
MIN
TYP (1)
MAX
UNIT
Input Clock Timing Specifications
fINCLK
Tdc
Input Clock Frequency
Mode 3, INCLK = PIXCLK (Pixel
Rate Clock)
15
Mode 2, INCLK = PIXCLK (Pixel
Rate Clock)
22.5
Mode 1, INCLK = PIXCLK (Pixel
Rate Clock)
30
Mode 3, INCLK = ADCCLK (ADC
Rate Clock)
5
45
Mode 2, INCLK = ADCCLK (ADC
Rate Clock)
5
45
Mode 1, INCLK = ADCCLK (ADC
Rate Clock)
5
30
Input Clock Duty Cycle
40/60%
50/50%
MHz
MHz
60/40%
Full Channel Latency Specifications
tSHFP
tLAT3
tLAT2
tLAT1
(1)
SH out to first sampled pixel
PIXPHASE0
3
Figure 11 (Mode 3)
PIXPHASE1
3 3/7
Figure 12 (Mode 2)
PIXPHASE2
4
Figure 13 (Mode 1)
PIXPHASE3
4 3/7
PIXPHASE0
19
PIXPHASE1
18 4/7
PIXPHASE2
18
PIXPHASE3
17 4/7
3 channel mode pipeline delay
Figure 45 (LVDS)
Figure 50 (CMOS)
2 channel mode pipeline delay
Figure 46 (LVDS)
Figure 51(CMOS)
1 channel mode pipeline delay
Figure 47 (LVDS)
Figure 52(CMOS)
PIXPHASE0
18
PIXPHASE1
17 4/7
PIXPHASE2
17
PIXPHASE3
16 4/7
PIXPHASE0
16
PIXPHASE1
15 4/7
PIXPHASE2
15
PIXPHASE3
14 4/7
TADC
TADC
TADC
TADC
Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
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AC Timing Specifications (continued)
The following specifications apply for VA = VD = VR = VC = 3.3 V, CL = 10 pF, and fINCLK = 15 MHz, TA = 25°C, unless
otherwise specified.
MIN
tSHFD
SH out to first valid data
(tSHFP + tLATx)
TYP (1)
Mode 3
22
Mode 2
21
Mode 1
19
MAX
UNIT
TADC
SH_R Timing Specifications (Figure 41)
tSHR_S
SH_R setup time
1.28
ns
tSHR_H
SH_R hold time
2.25
ns
2
ns
LVDS Output Timing Specifications (Figure 44)
TXvalid
TX output data valid window
TXpp0
TXCLK to pulse position 0
TXpp1
TXCLK to pulse position 1
TXpp2
TXCLK to pulse position 2
TXpp3
TXCLK to pulse position 3
TXpp4
TXCLK to pulse position 4
TXpp5
TXCLK to pulse position 5
TXpp6
TXCLK to pulse position 6
fINCLK = 45 MHz
INCLK = ADCCLK
(ADC Rate Clock)
LVDS Output
Specifications not tested in
production.
Min/Max ensured by design,
characterization and statistical
analysis.
0.013
ns
3.093
ns
6.238
ns
9.613
ns
12.663
ns
15.762
ns
18.982
ns
CMOS Output Timing Specifications
tCRDO
CLKOUT rising edge to CMOS
output data
fINCLK = 45 MHz, INCLK = ADCCLK,
(ADC Rate Clock)
–2.83
2.7
ns
tCFDO
CLKOUT Falling edge to CMOS
output data
fINCLK = 45 MHz, INCLK = ADCCLK,
(ADC Rate Clock)
–2.83
2.7
ns
Serial Interface Timing Specifications
fSCLK
Input clock frequency
fSCLK ≤ fINCLK
INCLK = PIXCLK
(Pixel Rate Clock)
Mode 3/2/1
15/22.5/30
MHz
fSCLK ≤ fINCLK
INCLK = ADCCLK
(ADC Rate Clock)
Mode 3/2/1
45/45/30
MHz
SCLK duty cycle
50/50
ns
tIH
Input hold time
tIS
Input setup time
tSENSC
SCLK start time after SEN low
tSCSEN
SEN high after last SCLK rising
edge
2.82
ns
tSENW
SEN pulse width
tOD
Output delay time
tHZ
Data output to High Z
10
INCLK must be active during serial
interface commands.
1
ns
4
ns
1.25
ns
4
TINCLK
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14.6
ns
0.5
TSCLK
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6.7 Typical Characteristics
18
17
16
15
14
13
Gain (V/V) =
(196/(280-PGA Code))
12
11
Overall PGA Gain
10
9
Gain (dB) =
20LOG10(196/(280-PGA Code))
8
7
6
5
4
3
2
1
0
-1 0
32
64
96
128
160
192
224
-2
-3
-4
PGA Register Value
Overall Gain (dB)
Overall Gain (V/V)
Figure 1. PGA Gain vs. PGA Gain Code
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7 Detailed Description
7.1 Overview
The LM98714 is a 16-bit, three-input, complete Analog Front End (AFE) for digital color copier and Multi-Function
Peripheral (MFP) applications. The system block diagram of the LM98714, shown in Functional Block Diagram
highlights the main features of the device. Each input has its own Input Bias and Clamping Network which are
routed through a selectable Sample/Hold (S/H) or Correlated Double Sampler (CDS) amplifier. A ±9-Bit Offset
DAC applies independent offset correction for each channel. A -3 to 17.9dB Programmable Gain Amplifier (PGA)
applies independent gain correction for each channel. The LM98714 also provides independent Digital Black
Level Correction Feedback Loops for each channel. The Black Level Correction Loop can be configured to run in
Manual Mode (where the user inputs their own values of DAC offset) or in Automatic Mode where the LM98714
calculates each channel’s Offset DAC value during optical black pixels and then adjusts the Offset register
accordingly. The signals are routed to a single high performance 16-bit, 45 MHz analog-to-digital converter.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Input Clock Introduction
The clock input to the LM98714 can be a differential LVDS clock on the INCLK+ and INCLK- pins or a CMOS
level clock applied to the INCLK+ pin with the INCLK- pin connected to DGND. The external clock signal format
is auto sensed internally. In addition to the two available level formats, the input clock can be applied at the Pixel
frequency (PIXCLK) or at the ADC frequency (ADCCLK). The LM98714 can perform internal clock multiplication
when a Pixel frequency clock is applied, or no multiplication when an ADC frequency clock is applied. The
internal configuration registers need to be written to perform the proper setup of the input clock. Table 1 shows
the available input clock configurations for each operating mode.
Table 1. Input Clock Configurations
AFE Mode
Mode 3
Mode 2
Mode 1
Input Clock Type
Internal
Multiplier
INCLK
Max Freq.
Configuration Register Settings
INCLK = Pixel Freq. (PIXCLK)
3x
15 MHz
PIXCLK Configuration: Main Config Reg 1, Bit[2] = 1'b1
INCLK = ADC Freq. (ADCCLK)
1x
45 MHz
ADCCLK Configuration: Main Config Reg 1, Bit[2] = 1'b0
INCLK = Pixel Freq. (PIXCLK)
2x
22.5 MHz
PIXCLK Configuration: Main Config Reg 1, Bit[2] = 1'b1
INCLK = ADC Freq. (ADCCLK)
1x
45 MHz
ADCCLK Configuration: Main Config Reg 1, Bit[2] = 1'b0
INCLK = Pixel Freq. = ADC Freq
(ADCCLK = PIXCLK in Mode 1)
1x
30MHz
Main Config Reg 1, Bit[2] = 1'bx
7.3.2 Modes of Operation
The LM98714 can be configured to operate in several different operating modes. The following sections are a
brief introduction to these modes of operation. A more rigorous explanation of the operating modes is contained
in the Modes of Operation section. including input sampling diagrams for each mode as well as a description of
the operating conditions.
7.3.2.1 Mode 3 - Three Channel Input/Synchronous Pixel Sampling
OSB, OSG, and OSR inputs are sampled synchronously at a pixel rate. The sampled signals are processed with
each channel’s offset and gain adjusted independently via the control registers. The order in which pixels are
processed from the input to the ADC is fully programmable and is synchronized by the SH pulse. In this mode,
the maximum channel speed is 15MSPS per channel with the ADC running at 45MSPS yielding a three color
throughput of 45MSPS.
7.3.2.2 Mode 2 - Two Channel Input/Synchronous Pixel Sampling
Mode 2 is useful for CCD sensors with a Black and White mode with Even and Odd outputs. In its default
configuration, Mode 2 samples the Even output via the OSB channel input, and the Odd output via the OSG
channel input. Sampling of the Even and Odd pixels is performed synchronously at a maximum sample rate of
22.5MSPS per input with the ADC running at 45MSPS.
7.3.2.3 Mode 1a - One Channel Input/One, Two, Three, Four, or Five Color Sequential Line Sampling
In Mode 1a, all pixels are processed through a single input (OSR, OSG, or OSB) chosen through the control
register setup. This mode is useful in applications where only one input channel is used. The selected input is
programmable through the control register. If more than one color is being sent to the input, the user can
configure the OSR channel to utilize up to five offset and gain coefficients for up to five different lines of color
pixels. The SH pulse at the beginning of each line sequences the DAC and PGA coefficients as configured in the
control registers. In this mode, the maximum channel speed is 30MSPS per channel with the ADC running at
30MSPS.
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7.3.2.4 Mode 1b - One Channel Input Per Line/Sequential Line (Input) Sampling/Three Channel
Processing
In Mode 1b the OSR, OSG, and OSB inputs are sampled one input per line with the input selection being
sequenced to the next color by an SH pulse. This mode is useful with sensors that output whole lines of pixels of
a single color. The order in which the inputs are sampled is fully programmable. Sequencing from one channel to
the next is triggered by the SH pulse. The first SH pulse after this mode is set (or reset) sets up the first
programmed input for gain and offset and initiates sampling through that input alone. The next SH pulse switches
the active input to the second channel indicated by the configuration registers. This sequencing with SH pulses
continues to the third input and then continuously loops through the inputs. In this mode, the maximum channel
speed is 30MSPS per channel with the ADC running at 30MSPS.
7.3.3 Input Bias and Clamping
VA
VA
VBIAS
Input Bias Enable
Main Configuration 1, Bit[6]
SAMPLE
20kΩ
OSR or
OSG or
OSB
Source Follower Enable
Main Configuration 1, Bit[7]
20kΩ
CS
Auto CLPIN Enable
Input Clamp Control, Bit[1]
SAMPLE
CLPIN
AGND
HOLD
VA
VA
VBIAS
CLPIN Gating Enable
Input Clamp Control, Bit[0]
CLAMP
1kΩ
VCLP
CS
1kΩ
VCLP
DAC
Sampling Mode Select
(CDS or Sample/Hold Mode)
Main Configuration 1, Bit[4]
Pixel rate switches to sample OS signal and reference voltages.
Optional line rate switch to clamp OS input to VCLP node.
AGND
Static switches controlled by Configuration Registers
VCLP Reference Select
VCLP Configuration, Bits[5:4]
SAMPLE, CLAMP, HOLD, CLPIN are internally generated timing signals.
Figure 2. Input Bias and Clamping Diagram
The inputs to the LM98714 are typically AC coupled through a film capacitor and can be sampled in either
Sample and Hold Mode (S/H Mode) or Correlated Double Sampling Mode (CDS Mode). In either mode, the DC
bias point for the LM98714 side of the AC coupling capacitor is set using the circuit of Figure 2 which can be
configured to operate in a variety of different modes.
A typical CCD waveform is shown in Figure 3. Also shown in Figure 3 is an internal signal “SAMPLE” which can
be used to “gate” the CLPIN signal so that it only occurs during the “signal” portion of the CCD pixel waveform.
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SH
Dummy Pixels
Invalid
Pixels
Optical Black Pixels
Valid Pixels
OSX
Auto CLPIN Position Register
Page 0, Reg. 6, Bits[7:0]
Input Clamp Control Register
Page 0, Reg. 5, Bits[3:2]
(Auto CLPIN Width)
CLPIN
SAMPLE
CLPINGATED
Figure 3. Typical CCD Waveform and LM98714 Input Clamp Signal (CLPIN)
SAMPLE
OSR or
OSG or
OSB
CPAR
CS
HOLD
CLAMP
VCLP
CPAR
CS
Figure 4. Sample and Hold Mode Simplified Input Diagram
Proper DC biasing of the CCD waveform in Sample and Hold mode is critical for realizing optimal operating
conditions. In Sample/Hold mode, the Signal Level of the CCD waveform is compared to the DC voltage on the
VCLP pin. In order to fully utilize the range of the input circuitry, it is desirable to cause the Black Level signal
voltage to be as close to the VCLP voltage as possible, resulting in a near zero scale output for Black Level
pixels.
In Sample/Hold Mode, the DC bias point of the input pin is typically set by actuating the input clamp switch (see
Figure 2) during optical black pixels which connects the input pins to the VCLP pin DC voltage. The signal
controlling this switch is an auto-generated pulse, CLPIN. CLPIN is generated with a programmable pixel delay
with respect to SH and a programmable pixel width. These parameters are available through the serial interface
control registers.
Actuating the input clamp will force the average value of the CCD waveform to be centered around the VCLP DC
voltage. During Optical Black Pixels, the CCD output has roughly three components. The first component of the
pixel is a “Reset Noise” peak followed by the Reset (or Pedestal) Level voltage, then finally the Black Level
voltage signal. Taking the average of these signal components will result in a final “clamped” DC bias point that
is close to the Black Level signal voltage.
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To provide a more precise DC bias point (i.e. a voltage closer to the Black Level voltage), the CLPIN pulse can
be “gated” by the internally generated SAMPLE clock. This resulting CLPINGATED signal is the logical “AND” of
the SAMPLE and CLPIN signals as shown in Figure 3. By using the CLPINGATED signal, the higher Reset Noise
peak will not be included in the clamping period and only the average of the Reset Level and Black Level
components of the CCD waveform will be centered around VCLP.
OSR or
OSG or
OSB
fPIXEL
CSH
VCLP
Figure 5. Equivalent Input Switched Capacitance S/H Mode
In Sample and Hold Mode, the impedance of the analog input pins is dominated by the switched capacitance of
the CDS/Sample and Hold amplifier. The amplifier switched capacitance, shown as CS in Figure 4, and internal
parasitic capacitances can be estimated by a single capacitor switched between the analog input and the VCLP
reference pin for Sample and Hold mode. During each pixel cycle, the modeled capacitor, CSH, is charged to the
OSX-VCLP voltage then discharged. The average input current at the OSX pin can be calculated knowing the
input signal amplitude and the frequency of the pixel. If the application requires AC coupling of the CCD output to
the LM98714 analog inputs, the Sample and Hold Mode input bias current may degrade the DC bias point of the
coupling capacitor. To overcome this, Input Source Follower Buffers are available to isolate the larger Sample
and Hold Mode input bias currents from the analog input pin (as discussed in the following section). As shown in
Figure 6, the input bias current is much lower for CDS mode, eliminating the need for the source follower buffers.
7.3.3.1 CDS Mode
SAMPLE
OSR or
OSG or
OSB
CPAR
CS
HOLD
CLAMP
CPAR
CS
Figure 6. CDS Mode Simplified Input Diagram
Correlated Double Sampling mode does not require as precise a DC bias point as does Sample and Hold mode.
This is due mainly to the nature of CDS itself, that is, the Video Signal voltage is referenced to the Reset Level
voltage instead of the static DC VCLP voltage. The common mode voltage of these two points on the CCD
waveform have little bearing on the resulting differential result. However, the DC bias point does need to be
established to ensure the CCD waveform’s common mode voltage is within rated operating ranges.
The CDS mode biasing can be performed in the same way as described in the Sample/Hold Mode Biasing
section, or, an alternative method is available which precludes the need for a CLPIN pulse. Internal resistor
dividers can be switched in across the OSR, OSG, and/or OSB inputs to provide the DC bias voltage.
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SAMPLE
IBIAS
OSR or
OSG or
OSB
CS
CPAR
HOLD
CLAMP
CS
CPAR
Figure 7. CDS Mode Input Bias Current
Unlike in Sample and Hold Mode, the input bias current in CDS Mode is relatively small. Due to the architecture
of CDS switching, the average charge loss or gain on the input node is ideally zero over the duration of a pixel.
This results in a much lower input bias current, whose main source is parasitic impedances and leakage
currents. As a result of the lower input bias current in CDS Mode, maintaining the DC Bias point the input node
over the length of a line will require a much smaller AC input coupling capacitor.
7.3.3.2 Input Source Follower Buffers
The OSR, OSG, OSB inputs each have an optional Source Follower Buffer which can be selected with Main
Configuration Register 1, Bit[7]. These source followers provide a much higher impedance seen at the inputs. In
some configurations, such as Sample and Hold Mode with AC coupled inputs, the DC bias point of the input
nodes must remain as constant as possible over the entire length of the line to ensure a uniform comparison to
reference level (VCLP in this case). The Source Followers effectively isolate the AC input coupling capacitor from
the switched capacitor network internal to the LM98714’s Sample and Hold/CDS Amplifier. This results in a
greatly reduced charge loss or gain on the AC Input coupling capacitor over the length of a line, thereby
preserving its DC bias point.
The Source Followers should only be used in the 1.2 V input range (i.e. Main Configuration Register 2, Bit[4] = 1,
CDS Gain = 2x). Using the Source Followers in the 2.4 V (i.e. Main Configuration Register 2, Bit[4] = 0, CDS
Gain = 1x). input range will result in a loss of performance (mainly linearity performance at the high and low ends
of the input range).
7.3.3.3 VCLP DAC
The VCLP pin provides the reference level for incoming signals in Sample and Hold Mode. The pin’s voltage can
be set by one of three sources by writing to the VCLP Configuration Register on register page 0. By default, the
VCLP pin voltage is established by an internal resistor divider which sets the voltage to VA/2. The resistor ladder
can be disconnected and the pin driven externally by the application.
The most flexible method of setting the VCLP voltage is using the internal VCLP DAC buffer. The DAC is
connected by setting the VCLP Configuration register Bit[5:4] to 2b’01. The DAC has a four bit “offset binary”
format which is summarized in Table 2. The DAC output has an approximate swing of ±1.2 V.
Table 2. VCLP DAC Format
VCLP Configuration [3:0]
Typical VCLP Output
0
-Full Scale
0111
Mid Scale - LSB
1000
Mid Scale
1001
Mid Scale + 1 LSB
1111
+Full Scale
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7.3.4 Coarse Pixel Phase Alignment
Precise placement of the CCD video signal sampling point is a critical aspect in any typical imaging application.
Many factors such as logic gate propagation delays and signal skew increase the difficulty in properly aligning
the CCD pixel output signals with the AFE input sampling points. The LM98714 provides two powerful features to
aid the system level designer in properly sampling the CCD video signal under a large range of conditions. The
first feature, discussed in this section, is the Coarse Pixel Phase Alignment block. As the name implies, this block
provides a very coarse range of timing adjustment to align the phase of the CCD Pixel output with the phase of
the LM98714 sample circuit. The second feature, discussed on the Internal Sample Timing section, is the block
which is designed for fine tuning of the sampling points within the selected Coarse Pixel Alignment Phase. A
small portion of a typical imaging application is shown in Figure 8.
SH
φ1Α
LM98714 CCD
Timing Generator
Outputs
φ2Α
OS3
CCD/CIS
Sensor
OS2
LM98714
Output Data Bus
OS1
Input Clock
(INCLK)
Figure 8. Typical AFE/CCD Interface
As shown in the diagram, the LM98714 provides the timing signals to drive the CCD using external logic gates to
drive the high capacitance CCD clock pins. The pixels are shifted out of the CCD, through the emitter follower
buffers and received by the LM98714 inputs for processing.
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In an ideal application, depicted in Figure 9, the Pixel output signal would be in phase with the timing signals that
drove the CCD. The LM98714 input sampling clocks (CLAMP and SAMPLE) are adjustable within a pixel period.
By default, the pixel period (or pixel “phase”) is defined to be in line with the input clock. As shown in the ideal
case in Figure 9, CLAMP and SAMPLE can be properly adjusted to their ideal positions within the pixel phase,
shown below at the stable region near the end of the pedestal and data phases.
INCLK (Pixel Rate)
In an ideal application, the LM98714 CCD Timing generator outputs would be phase aligned
with the input clock;
φ1A output from LM98714
CCD Timing generator
the output of discrete logic on the application board would have no signal skew or delay;
φ1A input at CCD
(after inverter)
and the CCD pixel output would have no delay with respect to
its input clock.
Pixel output from CCD
Ideal CCD reference
level sample point
Ideal CCD data level
sample point
CLAMP
(internal pixel reference
level sampling clock)
SAMPLE
(internal pixel data level
sampling clock)
CLAMP and SAMPLE fine adjust window
PIXPHASE0
(default “coarse’ pixel phase)
By default, the LM98714's internal sampling clocks (CLAMP and SAMPLE) are adjustable
within PIXPHASE0, an internal pixel rate clock which is in phase with the input clock.
Figure 9. Clock Alignment in an Ideal Application
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In a real system however, propagation delays exist in all stages of the signal chain. These propagation delays
will lead to a shift in the CCD Pixel outputs with respect to the LM98714 input clock. The phase shift of the CCD
Pixel output, demonstrated in Figure 10, can lead to significant sample timing issues if not properly corrected.
INCLK (Pixel Rate)
The LM98714 internal clock tree creates a small amount of
delay in the CCD Timing generator outputs.
φ1A output from LM98714
CCD Timing generator
Application board discrete logic also creates propagation delay
with respect to the input clock.
φ1A input at CCD
(after inverter)
Finally, the CCD propagation delay further shifts the Pixel
signal input to the LM98714 from the input clock.
Pixel output from CCD
Maximum fine adjust
not good enough for
default PIXPHASE,
CLAMP and SAMPLE
are too early due to
propagation delays.
CLAMP
(internal pixel reference
level sampling clock)
SAMPLE
(internal pixel data level
sampling clock)
PIXPHASE0
(default “coarse’ pixel phase)
Default CLAMP fine
adjust window
Default SAMPLE
fine adjust window
Default CLAMP fine
adjust window
Figure 10. CCD Output Phase Shift in a Real Application
In the default mode, the LM98714 sampling is performed during a clock period whose phase is aligned with the
input clock (ignoring any clock tree skew for the moment). The actual sampling clocks are adjustable within the
clock period, as shown in Figure 10 (shown for CDS mode in the diagram) and further described in the Internal
Sample Timing section. As shown in the diagram, the delay of the CCD Pixel output is shifted far enough that the
fine CLAMP and SAMPLE clocks cannot be placed in a stable portion of the waveform. To remedy this situation,
the LM98714’s Coarse Pixel Phase Alignment feature allows the designer to shift the entire phase of the analog
front end with respect to the input clock. This allows the designer to choose one of four sampling phases which
best matches the delay in the external circuitry. Once the “Coarse Pixel Phase” has been chosen, the designer
can then fine tune the sampling clocks using the fine adjustment (see Internal Sample Timing).
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The four available Coarse Pixel Phases (PIXPHASE0 - PIXPHASE3) are depicted in Figure 11 (Mode 3),
Figure 12 (Mode 2) and Figure 13 (Mode 1). Also shown in the diagrams are the external input clock (INCLK)
and a typical CCD output delayed from the input clock.
TADCCLK
INCLK = ADCCLK
TPIXCLK
INCLK = PIXCLK
tSHFP
SH
(Output from CCD
Timing Generator)
fSYSCLK = 7 * fADCCLK = 21 * fPIXCLK
(In Mode 3)
SYSCLK
(Internal system clock)
tPIXPHASE0 = TSYSCLK * 0
PIXPHASE0 (default)
Main Configutation Reg 1
Bit[1:0] = 2'b00
tPIXPHASE1 = TSYSCLK * 3
PIXPHASE1
Main Configutation Reg 1
Bit[1:0] = 2'b01
tPIXPHASE2 = TSYSCLK * 7
PIXPHASE2
Main Configutation Reg 1
Bit[1:0] = 2'b10
tPIXPHASE3 = TSYSCLK * 10
PIXPHASE3
Main Configutation Reg 1
Bit[1:0] = 2'b11
tCCD Output = ?
CCD Output
(Input to AFE)
The CCD output will usually have a measurable delay with respect to the input clock to the AFE. The AFE’s internal samplingocks
cl are based on one of four PIXPHASE clocks. These
PIXPHASE settings provide coarse adjustment of the internal AFE clock domain to best match the phase of the incoming CCD signal
. Fine adjustment of the sampling clocks is discussed
in another section. In this example above, PIXPHASE2 appears to provide the closest match for the incoming CCD signal.
Figure 11. Mode 3 Coarse Pixel Adjustment
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Figure 12. Mode 2 Coarse Pixel Phase Adjustment
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Figure 13. Mode 1 Coarse Pixel Phase Adjustment
7.3.5 Internal Sample Timing
A typical CCD input signal is depicted in Figure 14 and Figure 15. Also shown are the internally generated
SAMPLE and CLAMP pulses. These signals provide the sampling points of the input signal (OSX). The timing of
SAMPLE and CLAMP is derived from an internal system clock (SYSCLK).
The pixel’s reference level input (depicted as VREF) is captured by the falling edge of the CLAMP pulse. In
Sample/Hold Mode the VREF input is a sample of the VCLP DC voltage. In CDS Mode the CLAMP pulse samples
the pedestal Level of the CCD output waveform.
The pixel’s signal level input (depicted as VSIG) is captured by the SAMPLE pulse. In either Sample/Hold or CDS
Mode, the VSIG input is the signal level of the CCD output waveform.
The LM98714 provides fine adjustment of the CLAMP and SAMPLE pulse placement within the pixel period. This
allows the user to program the optimum location of the CLAMP and SAMPLE falling edges. In CDS mode, both
CLAMP and SAMPLE are independently adjustable for each channel in use. In Sample/Hold mode, CLAMP is
coincident with SAMPLE by default, but is also independently adjustable. The available fine tuning locations for
CLAMP and SAMPLE are shown in Figure 16 through Figure 21 for each sampling mode (CDS or S/H) and
channel mode (3, 2, or 1 Channel).
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Figure 14. Pixel Sampling in CDS Mode
Figure 15. Pixel Sampling in S/H Mode
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Figure 16. 3 Channel (Mode 3) CLAMP Timing
Figure 17. 3 Channel (Mode 3) SAMPLE Timing
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Figure 18. 2 Channel (Mode 2) CLAMP Timing
26
Figure 19. 2 Channel (Mode 2) SAMPLE Timing
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Figure 20. 1 Channel (Mode 1) CLAMP Timing
Figure 21. 1 Channel (Mode 1) SAMPLE Timing
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7.3.6 Automatic Black Level Correction Loop
CCD signal processors require a reference level for the proper handling of input signals; this reference level is
commonly referred to as the black level. The LM98714 provides an Automatic Black Level Correction Loop as
shown in Figure 22. The timing for this function is shown in Figure 23. The loop can be disabled and the Black
Level Offset DAC registers programmed manually if desired.
Figure 22. Black Level Correction Loop
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The loop is intended to be used prior to scanning the page or during the first several lines at the beginning of a
scan. The loop calibrates the channel offset such that the ADC outputs the desired code for Optical Black Pixels.
In automatic mode, the pixels used to calibrate the offset should be Optical Black pixels represented by the
internal “BLKCLP” pulse in Figure 23.
7.3.6.1 Black Level Offset DAC
The offset level registers store the DAC value required to meet the respective channel’s black level output. While
using the Auto Black Level Correction Loop, the DAC registers are re-written as required every line the loop is
enabled.
7.3.6.2 Black Level Clamp (BLKCLP)
The BLKCLP pulse can be synchronized by either the falling edge of the SH pulse or the CLPIN pulse (both
shown in Figure 23). The automatic BLKCLP pulse will begin “n” number of pixel periods after the falling edge of
the reference pulse where “n” is the Auto Black Level Clamp Position register. The reference point is
programmed by the BLKCLP Mode Select Bits[1:0] within the Black Level Clamp Control register. The BLKCLP
pulse should not be programmed coincident to the CLPIN pulse (if the CLPIN pulse is being used).
Figure 23. Black Level Correction Timing
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7.3.6.3 Pixel Averaging
In order to obtain a snapshot of the current value for black (for comparison with the desired level of black) the
ADC output is sampled upon activation of BLKCLP. Since a single optical black pixel is unlikely to be an accurate
representation of the black level, a number of adjacent pixels are averaged. The number of pixels sampled is
programmable by the Pixel Averaging Bit[5:4] within the Black Level Clamp Control register. The ability to select
the number of pixels to be averaged (4, 8, 16, or 32 per line) provides greater flexibility allowing the LM98714 to
be used with different CCDs having differing number of black pixels.
7.3.6.4 Target Black Level
The Target Black Level registers define a 10-bit word that specifies an ADC output (on the 12 bit level)
corresponding to the desired optical black output code (ignoring the four LSBs of the 16 Bit ADC output). In other
words, one Target Black Level LSB corresponds to sixteen ADC LSBs. Assertion of the BLKCLP signal activates
the digital black clamp loop and the black level is steered toward the value stored in the output black level
register. The digital black clamp loop is only limited in it’s range by the offset DAC’s range.
Once the correct number of pixels have been averaged, the value is subtracted from the Target Black Level and
an error value is produced.
7.3.6.5 Offset Integration
Each time the BLKCLP signal is activated, the average ADC output of several black pixels is compared to the
Target Black Level producing an error value. This error value is not directly added (or subtracted) to the Black
Level Offset register, rather, the value applied is a programmable fraction of this error. This has the effect of
slowing down the offset convergence resulting in a calculation for offset that is less susceptible to noise. The
scaling factor is stored in the Offset integration Bits[3:2] of the Black Level Clamp Control register. The scaling
values are divided-by-8, 16, 32, or 64. Divide-by-8 provides the quickest convergence of the loop (for use when
the number of lines available for calibration is limited) and Divide-by-64 the longest (for use when using an large
number of lines to converge).
7.3.6.6 Line Averaging
The Auto Black level Correction Loop can be run for 15 lines, 31 lines, 63 lines, or infinite (every line). The Line
Averaging Bits[7:6] found in the lack Level Clamp Control register set the number of lines that the loop will run
after the Start of Scan. The recommended use of the Auto Black Level Correction Loop is in a calibration period
prior to moving the sensor down the page or during the first several lines of the page. By experimenting with the
Line Averaging and Offset Integration bits with no sensor illumination (black pixels), the proper settings for the
Auto Black Level Correction Loop are determined when the ADC output converges to the Target Black Level
value. If the loop converges with the 15, 31, or 63 line setting, the loop can remain enabled. The loop does not
update the Black Level Offset DAC once the number of lines since “Start of Scan” has passed. If the loop
requires more than 63 lines to converge (i.e. requires Line Averaging = infinite), it is recommended to disable the
loop after convergence has been reached. In the “infinite” setting, the loop will continuously update the Black
Level Offset registers as long as the loop is enabled throughout the entire scan.
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7.3.7 Internal Timing Generation
A flexible internal timing generator is included to provide clocking signals to CCD and CIS sensors. A block
diagram of the CCD Timing Generator is shown in Figure 24.
Figure 24. CCD Timing Generator Block Diagram
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Examples of the various operating modes and settings are shown following. The detailed pixel timing is
somewhat dependent on the operating modes of the AFE circuitry regarding the number of adjustment points for
the on and off points of the different timing outputs.
NOTE
In addition to the timing adjustments shown, the polarity of all sensor clock signals can be
adjusted by register control.
Figure 25. Sensor Timing Control - Pixel Details - 1 Pixel per Phi
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Figure 26. Sensor Timing Control - Pixel Details - 2 Pixels per Phi
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Figure 27. Sensor Timing SH Pulse Details
Figure 28. Sensor Timing Mode Pin Output Details - Static High/Low
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Figure 29. Sensor Timing Mode Pin Output Details - Active Programmed Transition
Figure 30. Lamp Control Timing - 1 Line Mode (Monochrome)
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Figure 31. Lamp Control Timing - 1 Line Mode
Figure 32. Lamp Control Timing - 2 Line Sequence
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Figure 33. Lamp Control Timing - 3 Line Sequence
Figure 34. Lamp Control Timing - 3 Line Sequence - IR Enhancement Example
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Figure 35. Lamp Control Timing - 4 Line Sequence
Color + IR1 Example
Figure 36. Lamp Control Timing - 4 Line Sequence
Color + IR2 Example
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Figure 37. Lamp Control Timing - 5 Line Sequence
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7.3.7.1 Pix Signal Generator OR/NOR Modes
As shown in Figure 24, the PIX signal generators outputs can be used in their normal form and sent to the
LM98714 output pins, or, they can be sent through an additional layer of OR and NOR logic to provide a number
of clocking variations. The OR and NOR combinations of multiple PIX signals can be useful for such modes as
pixel lumping, or other modes where more complicated phi clocks are required.
The OR and NOR functions are chosen through the PIX OR/NOR Control 1 and PIX OR/NOR Control 2 registers
on Page 4 of the serial interface register map. When all of the OR/NOR control bits are 0 (default) the PIX
signals are sent directly from the pix signal generators to the output pins configured by the Output Mapping
Control registers (register Page 3). When an OR/NOR control bit is set to 1, the OR or NOR product of multiple
pix signal generators is routed to the output pin described in the register details.
7.3.7.2 SH2 and SH3 Generation
In some sensors, there is a requirement for up to three “SH” type signals. The LM98714 CCD Timing Generator
can be configured to produce optional SH signals as shown in Figure 38, these SH signals (SH2 and SH3) toggle
every other line and are coincident with the original SH pulse.
Figure 38. SH2 and SH3 Generation
The “Start Scan (BOS)” request bit is used to begin the proper sequence of CCD Timing outputs at the beginning
of a scan. The first line of pixels are being processed by the CCD during the first integration period (after the first
SH). The BOS signal (internal to the LM98714) occurs at the second SH to signal when the first line of pixels are
actually shifting out of the CCD and in to the AFE. The SH2 pulse is synchronized with the BOS signal and
continues to toggle on an every other line basis. The SH3 signal occurs on opposite lines from SH2.
The SH2 and SH3 signals are available in place of the Lamp IR1 and Lamp IR2 outputs respectively. The routing
of SH2 and SH3 is depicted in Figure 24. The use of SH2 and SH3 is selected by the SH2/SH3 Control register
(0x0F) on Page 4 of the register map.
Figure 39. Sensor Control Outputs
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Table 3 shows a number of example mappings of the sensor timing signals to the sensor control CLKn outputs.
Several typical timings are shown here, but any timing generator signal can be mapped to any of the CLKn
outputs, providing maximum flexibility.
Table 3. Sensor Timing Mappings Examples
Sensor Control Output
Example A
Example B
Example C
Example D
Example E
Example F
SH
SH
SH
SH
SH
SH
SH
CLK1
PIX1(PHI1)
PIX1(PHI1)
PIX1(PHI1)
PIX1(PHI1)
PIX1(PHI1)
PIX1(PHI1)
CLK2
PIX2(PHI2)
PIX2(PHI2)
PIX2(PHI2)
PIX2(PHI2)
PIX2(PHI2)
PIX2(PHI2)
CLK3
PIX3(RS)
PIX3(RS)
PIX3(RS)
PIX3(RS)
PIX3(PHI3)
PIX3(RS)
CLK4
PIX4(CP)
PIX4(CP)
LAMPR
PIX4(CP)
PIX4(PHI4)
PIX4(CP)
CLK5
LAMPR
LAMPR
LAMPG
LAMPR
PIX5(PHI5)
CB[0]
CLK6
LAMPG
LAMPG
LAMPB
LAMPG
PIX6(PHI6)
CB[1]
CLK7
LAMPB
LAMPB
LAMPIR1
LAMPB
PIX7(RS)
CB[2]
CLK8
MODE
LAMPIR1
LAMPIR2
LAMPIR1
PIX8(CP)
CB[3]
CLK9
PIX5(PHI3)
LAMPIR2
MODE
LAMPIR2
MODE
CLKOUT/CLK10
(MODE)
PIX5(PHI3)
CB[4]
CLKOUT
These examples can be used for any customer need, but typical applications would be as follows:
In Examples A, B and C, only 10 sensor control outputs are used. This is to allow the CLKOUT/CLK10 pin to be
used as a timing reference for the image output data when the outputs are in CMOS mode.
Example A: Used with most CCD or CIS sensors, including new sensors with 3 PHI clock inputs. Will support up
to 3 color LED lamps. Supports CCD sensors with switchable resolution through the MODE control output.
Example B: Used in applications where up to 2 additional IR lamps are used in addition to the R, G, B lamps. No
resolution MODE output is available.
Example C: Used where no CP pulse is needed, but 5 lamp outputs are needed as well as a MODE sensor
resolution control pin.
In Examples D and E, the CLK10 output is also used. These modes are not available when the image data
outputs are operating in CMOS mode.
Example D: Provides both PHI3 output and 5 LED lamp outputs. Does not provide MODE output for resolution
control.
Example E: Provides 5 LED lamp outputs, and the MODE output for sensor resolution control.
7.3.8 CCD Timing Generator Master/Slave Modes
The internal CCD Timing generator is capable of operating in Master Mode or in Slave Mode. The Master/Slave
operation is configured with the SH Mode Register (Register 0x00 on Page 2). In either Master or Slave Mode,
control bit data can be sent to the output of the LM98714 to indicate when each new scan is starting as well as
pixel information such as color, type (active, black, dummy, etc.), and the beginning of each line.
7.3.8.1 Master Timing Generator Mode
In Master Timing Mode, the LM98714 controls the entire CCD Timing Generator based on a Start Scan Bit (Main
Configuration Register 2, Bit[0] is the “Start Scan” or “BOS/Beginning of Scan” bit). The Start Scan bit is set by
the user to request a new scan. This bit is a self clearing register bit written to the serial interface. When
received, the LM98714 controls where and when each new line of the scan begins and ends based on the CCD
Timing Generator register settings. The scan is enabled as long as the Active/Standby bit is low. The period of
the line (integration time) is controlled by the SH Width setting (SH Pulse Width Register) and the Line End
setting (Line End MSB and Line End LSB registers).
7.3.8.2 Slave Timing Generator Mode
In Slave Timing Mode, the LM98714 CCD Timing Generator is controlled by the external SH_R pin. Each new
line of a scan is initiated by an SH_R pulse. The period of the line (integration time) is mainly controlled by the
period of the incoming SH_R signal.
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Figure 40. SH_R Input to SH Output Latency Diagram
Figure 41. SH_R to INCLK (PIXCLK or ADCCLK) Timing
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Figure 42. CCD Timing Generator Pixel Position Definition
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7.3.9 LVDS Output Mode
7.3.9.1 LVDS Output Format
Figure 43. LVDS Output Bit Alignment and Data Format
7.3.9.2 LVDS Output Timing Details
Figure 44. LVDS Data Output Mode Specification Diagram
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7.3.9.3 LVDS Control Bit Coding
The 5 control bits included in the LVDS data stream are coded as follows:
The "active" and "black" pixel tags are programmable tags that the LM98714 provides in order to identify how
many pixels have been processed since the falling edge of SH.
Which pixels are given "active" and "black" CB tags is controlled by Page 4, registers 0x08 through 0x0D (Optical
Black Pixels Start, Optical Black Pixels End, Start of Valid Pixels, and End of Valid Pixels).
The LM98714 counts the number of pixel periods after the falling edge of SH: If the number of pixel periods after
the falling edge of SH is between "optical black pixels start" and "optical black pixels end" the CB bits will indicate
that the pixel is a black pixel. If the number of pixel periods after the falling edge of SH is between "start of valid
pixels" and "end of valid pixels" the CB bits will indicate that the pixel is an active pixel.
Table 4.
CB[4]
Description
0
Not the beginning of line
1
Beginning of Line
(This bit is high for as many pixels as SH pulse is active)
Table 5.
CB[3:0]
Description
0
Dummy Pixels
1
Red Active Pixels
10
Green Active Pixels
11
Blue Active Pixels
100
IR1 Active Pixels
101
IR2 Active Pixels
110
Red Black Pixels
111
Green Black Pixels
1000
Blue Black Pixels
1001
IR1 Black Pixels
1010
IR2 Black Pixels
1111
Beginning of Scan
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7.3.9.4 LVDS Data Latency Diagrams
Figure 45. Mode 3 LVDS Data Latency
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Figure 46. Mode 2 LVDS Data Latency
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Figure 47. Mode 1 LVDS Data Latency
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7.3.9.5 LVDS Test Modes
The LVDS test modes present several different data patterns to the input of the LVDS serializer block. All 21 bits
are used and there is no control bit coding present. The SH signal resets the LVDS test pattern and the pattern
will resume only after SH is deasserted. If no SH signal is sent, the pattern continues indefinitely.
7.3.9.5.1 Test Mode 1 - Worst Case Transitions
This test mode provides an LVDS output with the maximum possible transitions. This mode is useful for system
EMI evaluations, and for ATE timing tests.
The effective data values are an alternating pattern between 21’b101010101010101010101 (0x155555) and
21’b010101010101010101010 (0x0AAAAA). This test pattern resets to 0x155555 after the SH signal.
Figure 48. LVDS Test Pattern
7.3.9.5.2 Test Mode 2 - Ramp
This mode provides LVDS data that progresses from 0x00000 to the full scale output 0x1FFFFF incrementing by
1 per LVDS Clock. When the LVDS ramp test pattern is selected, the ramp begins immediately and counts from
zero to the full scale value, and then repeats.
7.3.9.5.3 Test Mode 3 - Fixed Output Data
This mode allows a fixed data value to be output. The value is set via. Upcounter Register 1, 2 and 3. The 21 bit
value taken from these registers is repetitively sent out over the LVDS link. This is useful for system debugging
of the LVDS link and receiver circuitry.
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7.3.10 CMOS Output Mode
7.3.10.1 CMOS Output Data Format
Figure 49. CMOS Data Output Format (Mode 3 Shown)
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7.3.11 CMOS Output Data Latency Diagrams
Figure 50. Mode 3 CMOS Output Latency
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Figure 51. Mode 2 CMOS Output Latency
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Figure 52. Mode 1 CMOS Output Latency
7.4 Device Functional Modes
Table 6 lists the register settings for the modes of operation.
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Table 6. Modes Of Operation Register Settings Table
Operating Mode
Sampling Input
Signal
Path
Output Sequencing
Mode 3 and 2 = Pixel Seq
Mode 1 = Color Line Seq
Main
Config.
Main Config. Register 0
Reg. 3
Mode
Color
Order
Color Seq. Length
Bit [3]
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Mode3-RGB Forward
OSR||OSG||OSB
RGB
PixelR→PixelG→PixelB→
x
1
1
1
1
0
0
0
1
Mode3-RGB Reverse
OSR||OSG||OSB
RGB
PixelB→PixelG→PixelR→
x
1
1
1
1
1
0
0
1
Mode2-RG Forw.
OSR||OSG
RG
PixelR→PixelG→
x
1
0
0
0
0
0
0
1
Mode2-RG Rev.
OSR||OSG
RG
PixelG→PixelR→
x
1
0
0
0
1
0
0
1
Mode2-GB Forw.
OSG||OSB
GB
PixelG→PixelB→
x
1
0
0
1
0
0
0
1
Mode2-GB Rev.
OSG||OSB
GB
PixelB→PixelG→
x
1
0
0
1
1
0
0
1
Mode2-RB Forw.
OSR||OSB
RB
PixelR→PixelB→
x
1
0
1
0
0
0
0
1
Mode2-RB Rev.
OSR||OSB
RB
PixelB→PixelR→
x
1
0
1
0
1
0
0
1
Mode1-R Mono
OSR
R
Color Line Seq: 1→1→1→1→1→
x
0
1
0
0
0
0
0
1
Mode1a-R 2 Color For.
OSR
R
Color Line Seq: 1→2→1→2→1→
0
0
1
0
0
0
0
1
0
Mode1a-R 2 Color Rev
OSR
R
Color Line Seq: 2→1→2→1→2→
0
0
1
0
0
1
0
1
0
Mode1a-R 3 Color For.
OSR
R
Color Line Seq: 1→2→3→1→2→
0
0
1
0
0
0
0
1
1
Mode1a-R 3 Color Rev
OSR
R
Color Line Seq: 3→2→1→3→2→
0
0
1
0
0
1
0
1
1
Mode1a-R 4 Color For.
OSR
R
Color Line Seq: 1→2→3→4→1→
0
0
1
0
0
0
1
0
0
Mode1a-R 4 Color Rev
OSR
R
Color Line Seq: 4→3→2→1→4→
0
0
1
0
0
1
1
0
0
Mode1a-R 5 Color For.
OSR
R
Color Line Seq: 1→2→3→4→5→
0
0
1
0
0
0
1
0
1
Mode1a-R 5 Color Rev
OSR
R
Color Line Seq: 5→4→3→2→1→
0
0
1
0
0
1
1
0
1
Mode1a-G Mono
OSG
G
Color Line Seq: 1→1→1→1→1→
1
0
1
0
1
0
0
0
1
Mode1a-B Mono
OSB
B
Color Line Seq: 1→1→1→1→1→
1
0
1
1
0
0
0
0
1
Mode1b-RGB Forward
OSR→OSG→OSB
RGB
LineR→LineG→LineB→
1
0
0
1
1
0
x
x
x
Mode1b-RGB Reverse
OSB→OSG→OSR
RGB
LineR→LineG→LineB→
1
0
0
1
1
1
x
x
x
54
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7.4.1 Mode 3 - Three Channel Input/Synchronous Pixel Sampling
In Mode 3, the OSR, OSG, and OSB input channels are sampled synchronously. The sampled input signals are
then processed in parallel through their respective channels with each channel offset and gain adjusted by their
respective control registers. The signals are then routed through a 3-1 MUX to the ADC. The order in which
pixels are processed through the MUX to the ADC is programmable (OSR-OSG-OSB, or OSB-OSG-OSR) and is
synchronized by the SH pulse.
COLOR1DAC[9:0]
COLOR2DAC[9:0]
COLOR3DAC[9:0]
COLOR4DAC[9:0]
COLOR5DAC[9:0]
OSR
Black
Level
Offset
DAC
5:1
MUX
CDS
or
Sample/Hold
Amplifier
Input Bias/
Clamping
Black
Level
Offset
DAC
COLOR2DAC[9:0]
OSG
Black
Level
Offset
DAC
Input Bias/
Clamping
5:1
MUX
PGA
COLOR2PGA[7:0]
CDS
or
Sample/Hold
Amplifier
Input Bias/
Clamping
COLOR3DAC[9:0]
OSB
COLOR1PGA[7:0]
COLOR2PGA[7:0]
COLOR3PGA[7:0]
COLOR4PGA[7:0]
COLOR5PGA[7:0]
PGA
3:1
MUX
COLOR3PGA[7:0]
CDS
or
Sample/Hold
Amplifier
PGA
Figure 53. Synchronous Three Channel Pixel Mode Signal Routing
Table 7. Mode 3 Operating Details
Detail
Channels Active
OSB & OSG & OSR
Channel Sample Rate
3 channel synchronous pixel sampling.
15
ADC Sample Rate
fADC: fINCLK
MSPS per Channel (max)
45
MSPS (max)
Internal 3x Clock Selected
3:01
fINCLK = 15 MHz (max)
Internal 1x Clock Selected
1:01
fINCLK = 45 MHz (max)
SH Signal --> R-G-B-R-G-B-R-G-B→
Output Sequencing
or
SH Signal --> B-G-R-B-G-R-B-G-R→
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7.4.2 Mode 2 - Two Channel Input/Synchronous Pixel Sampling
Mode 2 is useful for CCD sensors with a Black and White line with Even and Odd pixels. In its default
configuration, Mode 2 samples Even sensor pixels via the Blue Channel Input, and Odd sensor pixels via the
Green Channel Input. The selection of Even/Odd inputs can be changed through the serial interface registers.
Sampling of the Even and Odd inputs is performed synchronously.
Figure 54. Mode 2 Signal Routing
Table 8. Mode 2 Operating Details
Detail
OSG and OSB (Default)
or
OSR and OSG
or
OSB and OSR
Channels Active
Channel Sample Rate
22.5
MSPS per Channel (max)
ADC Sample Rate
fADC: fINCLK
Output Sequencing
56
Two inputs synchronously processed as Even and Odd
Pixels. Channel inputs are configurable.
45
MSPS (max)
Internal 2x Clock Selected
2:01
fINCLK = 22.5 MHz (max)
Internal 1x Clock Selected
1:01
fINCLK = 45 MHz (max)
SH Signal --> Even-Odd-Even-Odd-Even-Odd-Even→
or
SH Signal --> Odd-Even-Odd-Even-Odd-Even-Odd→
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7.4.3 Mode 1a - One Channel Input/One, Two, Three, Four, Or Five Color Sequential Line Sampling
In Mode 1a, all pixels are processed through a single input (OSR, OSG, or OSB) chosen through the control
register setup. This mode is useful in applications where only one input channel is used. The selected input is
programmable through the control register. If more than one color is being sent to the input, the user can
configure the OSR channel to utilize up to five offset and gain coefficients for up to five different lines of color
pixels. The SH pulse at the beginning of each line sequences the DAC and PGA coefficients as configured in the
control registers. In this mode, the maximum channel speed is 30MSPS per channel with the ADC running at
30MSPS.
COLOR1DAC[9:0]
COLOR2DAC[9:0]
COLOR3DAC[9:0]
COLOR4DAC[9:0]
COLOR5DAC[9:0]
OSR
Input Bias/
Clamping
Black
Level
Offset
DAC
5:1
MUX
CDS
or
Sample/Hold
Amplifier
Black
Level
Offset
DAC
COLOR2DAC[9:0]
OSG
Input Bias/
Clamping
Black
Level
Offset
DAC
Input Bias/
Clamping
5:1
MUX
PGA
COLOR2PGA[7:0]
CDS
or
Sample/Hold
Amplifier
COLOR3DAC[9:0]
OSB
COLOR1PGA[7:0]
COLOR2PGA[7:0]
COLOR3PGA[7:0]
COLOR4PGA[7:0]
COLOR5PGA[7:0]
PGA
3:1
MUX
COLOR3PGA[7:0]
CDS
or
Sample/Hold
Amplifier
PGA
Up to “Five Color” line sequences shown thru OS R input. “Single Color” sequences also selectable
thru the OSG and OS B inputs.
Figure 55. Mode 1a Signal Routing
Table 9. Mode 1a Operating Details
Detail
Channels Active
OSR
Channel Sample Rate
30
ADC Sample Rate
fADC: fINCLK
One color active per line.
Internal 1x Clock Selected
MSPS per Channel (max)
30
MSPS (max)
1:01
fINCLK = 30MHz (max)
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Table 9. Mode 1a Operating Details (continued)
Detail
SH Signal → Color 1→Color 1→Color 1→Color 1→Color 1→
→SH Signal → Color 2→Color 2→Color 2→Color 2→Color 2→
→SH Signal → Color 3→Color 3→Color 3→Color 3→Color 3→
→SH Signal → Color 4→Color 4→Color 4→Color 4→Color 4→
→SH Signal → Color 5→Color 5→Color 5→Color 5→Color 5→
Output Sequencing
or
SH Signal → Color 5→Color 5→Color 5→Color 5→Color 5→
→SH Signal → Color 4→Color 4→Color 4→Color 4→Color 4→
→SH Signal → Color 3→Color 3→Color 3→Color 3→Color 3→
→SH Signal → Color 2→Color 2→Color 2→Color 2→Color 2→
→SH Signal → Color 1→Color 1→Color 1→Color 1→Color 1→
58
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7.4.4 Mode 1b - One Channel Color Input Per Line/Sequential Line (Input) Sampling/Three Channel
Processing
In Mode 1b, the OSR, OSG, and OSB inputs are sampled sequentially and processed through their respective
channels. This mode allows an entire line of Red, Green, or Blue Pixels to be sampled before sequencing to the
next input. This mode is useful with sensors that output whole lines of pixels of a single color. The order in which
the channels are sampled is fully programmable. Actual switching from channel to channel is triggered by an SH
pulse. The first SH pulse after this mode is set (or reset) sets up the first programmed channel for gain and offset
and initiates sampling through that channel alone. The next SH pulse switches the active channel to the second
channel indicated by the configuration registers. This sequencing with SH pulses continues to the third channel
and then continuously loops through the channels.
COLOR1DAC[9:0]
COLOR2DAC[9:0]
COLOR3DAC[9:0]
COLOR4DAC[9:0]
COLOR5DAC[9:0]
CDS
or
Sample/Hold
Amplifier
Input Bias/
Clamping
OSR
5:1
MUX
PGA
Black
Level
Offset
DAC
COLOR3DAC[9:0]
3:1
MUX
COLOR3PGA[7:0]
CDS
or
Sample/Hold
Amplifier
Input Bias/
Clamping
OSB
COLOR2PGA[7:0]
CDS
or
Sample/Hold
Amplifier
Input Bias/
Clamping
5:1
MUX
PGA
Black
Level
Offset
DAC
COLOR2DAC[9:0]
OSG
COLOR1PGA[7:0]
COLOR2PGA[7:0]
COLOR3PGA[7:0]
COLOR4PGA[7:0]
COLOR5PGA[7:0]
Black
Level
Offset
DAC
PGA
Figure 56. Mode 1b Signal Routing
Table 10. Mode 1b Operating Details
Detail
Channels Active
One channel active per line. Active channel is sequenced by
SH pulse at start of new line.
OSB or OSG or OSR
Channel Sample Rate
30
MSPS per Channel (max)
ADC Sample Rate
fADC: fINCLK
Internal 1x Clock Selected
30
MSPS (max)
1:01
fINCLK = 30MHz (max)
SH Signal → R-R-R-R-R-R-R-R-R-R-R-R-R→
→SH Signal → G-G-G-G-G-G-G-G-G-G-G-G-G→
→SH Signal → B-B-B-B-B-B-B-B-B-B-B-B-B-B→
Output Sequencing
or
SH Signal → B-B-B-B-B-B-B-B-B-B-B-B-B-B→
→SH Signal → G-G-G-G-G-G-G-G-G-G-G-G-G→
→SH Signal → R-R-R-R-R-R-R-R-R-R-R-R-R→
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7.5 Programming
7.5.1 Serial Interface
A serial interface is used to write and read the configuration registers. The interface is a three wire interface
using SCLK, SEN, and SDIO connections. The main input clock (INCLK) to the LM98714 must be active during
all Serial Interface commands.
7.5.1.1 Writing To The Serial Registers
To write to the serial registers, the timing diagram shown in Figure 57 must be met. First, SEN is toggled low.
The LM98714 assumes control of the SDIO pin during the first eight clocks of the command. During this period,
data is clocked out of the device at the rising edge of SCLK. The eight bit value clocked out is the contents of the
previously addressed register, regardless if the previous command was a read or a write. At the rising edge of
ninth clock, the LM98714 releases control of the SDIO pin. At the falling edge of the ninth clock period, the
master should assume control of the SDIO pin and begin issuing the new command. SDIO is clocked into the
LM98714 at the rising edge of SCLK. The remaining bits are composed of the “write” command bit (a zero), two
device address bits (zeros for the LM98714), five bit register address to be written, and the eight bit register
value to be written. When SEN toggles high, the register is written to, and the LM98714 now functions with this
new data.
Figure 57. Serial Write
60
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Programming (continued)
7.5.1.2 Reading The Serial Registers
To read to the serial registers, the timing diagram shown in Figure 58 must be met. First, SEN is toggled low.
The LM98714 assumes control of the SDIO pin during the first eight clocks of the command. During this period,
data is clocked out of the device at the rising edge of SCLK. The eight bit value clocked out is the contents of the
previously addressed register, regardless if the previous command was a read or a write. At the rising edge of
ninth clock, the LM98714 releases control of the SDIO pin. At the falling edge of the ninth clock period, the
master should assume control of the SDIO pin and begin issuing the new command. SDIO is clocked into the
LM98714 at the rising edge of SCLK. The remaining bits are composed of the “read” command bit (a one), two
device address bits (zeros for the LM98714), five bit register address to be read, and the eight bit “don’t care”
bits. When SEN toggles high, the register is not written to, but its contents are staged to be outputted at the
beginning of the next command.
Figure 58. Serial Read
7.5.1.3 Serial Interface Timing Details
Figure 59. Serial Interface Specification Diagram
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7.6 Register Maps
7.6.1 Configuration Registers
The LM98714 operation is very flexible to support a wide variety of sensors and system designs. This flexibility is
controlled through configuration registers which are first summarized, then described in full in the following
tables. Because the serial interface only allows 5 address bits, a register paging system is used to support the
larger number of required registers.
A page register is present at the highest address (1Fh or 11111b). The power on default setting of the page
register is 00. Writing other values to this register allows the other pages to be accessed. The page register is
mirrored, and is accessible at the highest address on each page.
Figure 60 shows the proper sequence of operation for the LM98714.
Figure 60. LM98714 Proper Sequence of Operation
62
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Table 11. Page 0 Register Table - Main Analog Front End Configuration
Address
(Binary)
Register/Bit Description
Register Title (Mnemonic)
Default (Binary)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note: The active register page is selected by writing the desired value to the page select register 1Fh. This register is mirrored on all register pages.
Page 0
00000
Page Register 1F = 0000 0000
Main Configuration 0
1111 0001
Operating Mode Select
Source Follower
Enable
Input Bias Enable
Input Polarity
Sampling Mode
Select
Output Format
PIXCLK/ ADCCLK
Config.
Active/ Standby
Gain Mode Select
Output Enable
Power-down
00001
Main Configuration 1
0101 0000
00010
Main Configuration 2
0000 0000
00011
Main Configuration 3
0000 0111
00100
Main Configuration 4
0000 0000
Not Used
00101
Input Clamp Control
0000 0000
Not Used
00110
Auto CLPIN Position
0010 0111
00111
VCLP Configuration
0010 0000
01000
Black Level Clamp Control
0000 0000
01001
Auto Black Level Clamp Position
0000 0000
Not Used
01010
Target Black Level MSB
0010 0000
MSB
01011
Target Black Level LSB
0000 0000
01100
OSR CLAMP Control
0000 0000
Not Used
CLAMPR Position
01101
OSG CLAMP Control
0000 0000
Not Used
CLAMPG Position
01110
OSB CLAMP Control
0000 0000
Not Used
01111
OSR SAMPLE Control
0000 0000
Not Used
SAMPLER Position
10000
OSG SAMPLE Control
0000 0000
Not Used
SAMPLEG Position
10001
OSB SAMPLE Control
0000 0000
Not Used
10010
Upcounter Register 1
0000 0000
10011
Upcounter Register 2
0000 0000
10100
Upcounter Register 3
0000 0000
Not Used
Pixel Phase Clock Select
Soft Reset
Processing
Channel Override
Reserved
Upcount Enable
LVDS Test Mode
Auto CLPIN Width
Auto CLPIN Enable
MSB
Start Scan
CLPIN Gating
LSB
Not Used
VCLP Reference Select
Line Averaging
VCLP DAC Bits
Pixel Averaging
Offset Integration
BLKCLP Mode Select
MSB
LSB
LSB+2
Not Used
LSB+1
LSB
LSB+1
LSB
CLAMPB Position
SAMPLEB Position
Count Value LSBs
Count Value Middle 8 Bits
Not Used
Count Value MSBs
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
0000 0100
Page Register
0000 0000
Reserved (program all zeros)
LSB+2
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Table 12. Page 1 Register Table - Offset and Gain Settings
Address
(Binary)
Register/Bit Description
Register Title (Mnemonic)
Default (Binary)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note: The active register page is selected by writing the desired value to the page select register 1Fh. This register is mirrored on all register pages.
Page 1
Page Register 1F = 0000 0001
00000
Color 1 PGA
0101 0100
MSB
LSB
00001
Color 2 PGA
0101 0100
MSB
LSB
00010
Color 3 PGA
0101 0100
MSB
LSB
00011
Color 4 PGA
0101 0100
MSB
LSB
00100
Color 5 PGA
0101 0100
MSB
LSB
00101
Color 1 Black Level Offset DAC MSB
1000 0000
MSB
LSB+2
00110
Color 1 Black Level Offset DAC LSB
0000 0000
00111
Color 2 Black Level Offset DAC MSB
1000 0000
01000
Color 2 Black Level Offset DAC LSB
0000 0000
01001
Color 3 Black Level Offset DAC MSB
1000 0000
01010
Color 3 Black Level Offset DAC LSB
0000 0000
01011
Color 4 Black Level Offset DAC MSB
1000 0000
01100
Color 4 Black Level Offset DAC LSB
0000 0000
01101
Color 5 Black Level Offset DAC MSB
1000 0000
01110
Color 5 Black Level Offset DAC LSB
0000 0000
01111
Color 1 Digital Offset
0100 0000
Not Used
MSB
LSB
10000
Color 2 Digital Offset
0100 0000
Not Used
MSB
LSB
10001
Color 3 Digital Offset
0100 0000
Not Used
MSB
LSB
10010
Color 4 Digital Offset
0100 0000
Not Used
MSB
LSB
10011
Color 5 Digital Offset
0100 0000
Not Used
MSB
LSB
Not Used
LSB+1
MSB
LSB
LSB+2
Not Used
LSB+1
MSB
LSB
LSB+2
Not Used
LSB+1
MSB
LSB
LSB+2
Not Used
LSB+1
MSB
LSB
LSB+2
Not Used
LSB+1
LSB
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
64
0000 0100
Page Register
0000 0000
Reserved (program all zeros)
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LSB+2
LSB+1
LSB
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Table 13. Page 2 Register Table - CCD/CIS Timing Generator Control 1
Address
(Binary)
Register/Bit Description
RegisterTitle (Mnemonic)
Default (Binary)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note: The active register page is selected by writing the desired value to the page select register 1Fh. This register is mirrored on all register pages.
Page 2
Page Register 1F = 0000 0010
00000
SH Mode
0000 0000
SH Output Enable
SH Source Select
00001
SH Pulse Width
0010 0111
SH Mode
SH Delay
00010
PIX1/2 Control
1100 1000
PIX1 Activity
PIX1 Polarity
PIX1 Frequency
PIX1 Activity During
SH
PIX2 Activity
PIX2 Polarity
PIX2 Frequency
PIX2 Activity During
SH
00011
PIX3/4 Control
1000 1000
PIX3 Activity
PIX3 Polarity
PIX3 Frequency
PIX3 Activity During
SH
PIX4 Activity
PIX4 Polarity
PIX4 Frequency
PIX4 Activity During
SH
00100
PIX5/6 Control
0000 0000
PIX5 Activity
PIX5 Polarity
PIX5 Frequency
PIX5 Activity During
SH
PIX6 Activity
PIX6 Polarity
PIX6 Frequency
PIX6 Activity During
SH
00101
PIX7/8 Control
0000 0000
PIX7 Activity
PIX7 Polarity
PIX7 Frequency
PIX7 Activity During
SH
PIX8 Activity
PIX8 Polarity
PIX8 Frequency
PIX8 Activity During
SH
00110
Line Clamp Enable
0000 0000
PIX8 Line Clamp
Enable
PIX7 Line Clamp
Enable
PIX6 Line Clamp
Enable
PIX5 Line Clamp
Enable
PIX4 Line Clamp
Enable
PIX3 Line Clamp
Enable
PIX2 Line Clamp
Enable
PIX1 Line Clamp
Enable
00111
PIX1 Start
0000 0000
Reserved
MSB
LSB
01000
PIX1 End
0001 0101
Reserved
MSB
LSB
01010
PIX2 Start
0000 0000
Reserved
MSB
LSB
01011
PIX2 End
0001 0101
Reserved
MSB
LSB
01101
PIX3 Start
0000 1011
Reserved
MSB
LSB
01110
PIX3 End
0000 1101
Reserved
MSB
LSB
10000
PIX4 Start
0001 0000
Reserved
MSB
LSB
10001
PIX4 End
0001 0011
Reserved
MSB
LSB
10011
PIX5 Start
0000 0000
Reserved
MSB
LSB
10100
PIX5 End
0000 0000
Reserved
MSB
LSB
10110
PIX6 Start
0000 0000
Reserved
MSB
LSB
10111
PIX6 End
0000 0000
Reserved
MSB
LSB
11001
PIX7 Start
0000 0000
Reserved
MSB
LSB
11010
PIX7 End
0000 0000
Reserved
MSB
LSB
11100
PIX8 Start
0000 0000
Reserved
MSB
LSB
11101
PIX8 End
0000 0000
Reserved
MSB
LSB
SH Pulse Width
01001
01100
01111
10010
10101
11000
11011
CMOS Data Mode
11110
0000 0000
Reserved
CLK10/ CLKOUT
CLK9/ CB[4]
CLK8/ CB[3]
CLK7/ CB[2]
CLK6/ CB[1]
CLK5/ CB[0]
LSB+2
LSB+1
LSB
Status Bit Enable
11111
Page Register
0000 0000
Reserved (program all zeros)
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Table 14. Page 3 Register Table - CCD/CIS Timing Generator Control 2
Address
(Binary)
Register/Bit Description
Register Title (Mnemonic)
Default (Binary)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note: The active register page is selected by writing the desired value to the page select register 1Fh. This register is mirrored on all register pages.
Page 3
66
Page Register 1F = 0000 0011
00000
Output Mapping
CLK1/CLK2
0000 0000
Output Mapping for CLK1 Pin
Output Mapping for CLK2 Pin
00001
Output Mapping
CLK3/CLK4
0000 0000
Output Mapping for CLK3 Pin
Output Mapping for CLK4 Pin
00010
Output Mapping
CLK5/CLK6
0000 0000
Output Mapping for CLK5 Pin
Output Mapping for CLK6 Pin
00011
Output Mapping
CLK7/CLK8
0000 0000
Output Mapping for CLK7 Pin
Output Mapping for CLK9 Pin
00100
Output Mapping
CLK9/(CLKOUT/ CLK10)
0000 0000
Output Mapping for CLK9 Pin
Output Mapping for CLKOUT/CLK10 Pin
00101
Illumination Mode
0000 0000
00110
Line 1 Lamp Selection
00111
Line 2 Lamp Selection
LAMPR
Normal
State
LAMPG
Normal
State
LAMPB
Normal
State
LampIR1
Normal
State
LampIR2
Normal
State
0000 0000
Red Lamp
Enable
Green Lamp
Enable
Blue Lamp
Enable
IR1 Lamp Enable
IR2 Lamp Enable
0000 0000
Red Lamp
Enable
Green Lamp
Enable
Blue Lamp
Enable
IR1 Lamp Enable
IR2 Lamp Enable
Green Lamp
Enable
Blue Lamp
Enable
IR1 Lamp Enable
IR2 Lamp Enable
Reserved
SH/LAMP
Overlap
Enable
01000
Line 3 Lamp Selection
0000 0000
Red Lamp
Enable
01001
Line 4 Lamp Selection
0000 0000
Red Lamp
Enable
Green Lamp
Enable
Blue Lamp
Enable
IR1 Lamp Enable
IR2 Lamp Enable
Red Lamp
Enable
Green Lamp
Enable
Blue Lamp
Enable
IR1 Lamp Enable
IR2 Lamp Enable
SH_OR Enable
MSB
01010
Line 5 Lamp Selection
0000 0000
01011
LAMPR On - MSB
0000 0000
01100
LAMPR On - LSB
0001 0001
01101
LAMPR Off - MSB
0000 0011
01110
LAMPR Off - LSB
0000 0110
01111
LAMPG On - MSB
0000 0000
010000
LAMPG On - LSB
0001 0010
10001
LAMPG Off - MSB
0000 0011
10010
LAMPG Off - LSB
0000 0000
10011
LAMPB On - MSB
0000 0000
10100
LAMPB On - LSB
0001 0011
10101
LAMPB Off - MSB
0000 0011
10110
LAMPB Off - LSB
0011 0000
10111
LAMPIR1 On - MSB
0000 0000
11000
LAMPIR1 On - LSB
0001 0100
11001
LAMPIR1 Off - MSB
0000 0011
11010
LAMPIR1 Off - LSB
0011 0000
11011
LAMPIR2 On - MSB
0000 0000
11100
LAMPIR2 On - LSB
0001 0101
Reserved
LSB
Reserved
MSB
LSB
Reserved
SH_OR Enable
MSB
LSB
Reserved
MSB
LSB
Reserved
SH_OR Enable
MSB
LSB
Reserved
MSB
LSB
Reserved
SH_OR Enable
MSB
LSB
Reserved
MSB
LSB
Reserved
SH_OR Enable
MSB
LSB
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Table 14. Page 3 Register Table - CCD/CIS Timing Generator Control 2 (continued)
Register/Bit Description
Address
(Binary)
Register Title (Mnemonic)
11101
LAMPIR2 Off - MSB
0000 0011
11110
LAMPIR2 Off - LSB
0011 0000
11111
Page Register
0000 0000
Default (Binary)
Bit 7
Bit 6
Bit 5
Reserved
Bit 4
Bit 3
Bit 2
Bit 1
LSB+2
LSB+1
Bit 0
MSB
LSB
Reserved (program all zeros)
LSB
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Table 15. Page 4 Register Table - CCD/CIS Timing Generator Control 3
Address
(Binary)
Register/Bit Description
Register Title (Mnemonic)
Default (Binary)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note: The active register page is selected by writing the desired value to the page select register 1Fh. This register is mirrored on all register pages.
Page 4
68
Page Register 1F = 0000 0100
00000
Mode On - MSB
0000 0010
00001
Mode On - LSB
0000 0000
00010
Mode Off - MSB
0000 0011
00011
Mode Off - LSB
0000 0001
00100
Optical Black Pixels Start
0000 0000
MSB
00101
Optical Black Pixels End
0000 0000
MSB
00110
Start of Valid Pixels - MSB
0000 0000
00111
Start of Valid Pixels - LSB
0000 0001
01000
End of Valid Pixels - MSB
0011 1111
01001
End of Valid Pixels - LSB
1111 1110
01010
Line End - MSB
0011 1111
01011
Line End - LSB
1111 1111
01100
Sample Timing Monitor 1
1111 1111
01101
Sample Timing Monitor 2
1111 1111
01110
Sample Timing Monitor 3
1111 1111
01111
SH2/SH3 Control
0000 0000
10000
PIX OR/NOR Control 1
0000 0000
10001
PIX OR/NOR Control 2
0000 0000
11111
Page Register
0000 0000
Reserved
MSB
Reserved
MSB
LSB
LSB
LSB
LSB
Reserved
MSB
Reserved
MSB
Reserved
MSB
LSB
LSB
LSB
SH3 Select
Reserved (program all zeros)
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SH2 Select
LSB+2
LSB+1
LSB
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Table 16. Page 5 Register Table - CCD/CIS Timing Generator Control 4
Address
(Binary)
Register/Bit Description
Register Title (Mnemonic)
Default (Binary)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSB+2
LSB+1
LSB
Note: The active register page is selected by writing the desired value to the page select register 1Fh. This register is mirrored on all register pages.
Page 5
Page Register 1F = 0000 0101
00000
PIX1/SH On Guardbands
0000 1111
PIX1 On Guardband
00001
PIX1/SH Off Guardbands
0000 0111
PIX1 Off Guardband
00010
PIX2/SH On Guardbands
0000 1111
PIX2 On Guardband
00011
PIX2/SH Off Guardbands
0000 0111
PIX2 Off Guardband
00100
PIX3/SH On Guardbands
0000 1111
PIX3 On Guardband
00101
PIX3/SH Off Guardbands
0000 0111
PIX3 Off Guardband
00110
PIX4/SH On Guardbands
0000 1111
PIX4 On Guardband
00111
PIX4/SH Off Guardbands
0000 0111
PIX4 Off Guardband
01000
PIX5/SH On Guardbands
0000 1111
PIX5 On Guardband
01001
PIX5/SH Off Guardbands
0000 0111
PIX5 Off Guardband
01010
PIX6/SH On Guardbands
0000 1111
PIX6 On Guardband
01011
PIX6/SH Off Guardbands
0000 0111
PIX6 Off Guardband
01100
PIX7/SH On Guardbands
0000 1111
PIX7 On Guardband
01101
PIX7/SH Off Guardbands
0000 0111
PIX7 Off Guardband
01110
PIX8/SH On Guardbands
0000 1111
PIX8 On Guardband
01111
PIX8/SH Off Guardbands
0000 0111
11111
Page Register
0000 0000
PIX8 Off Guardband
Reserved (program all zeros)
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7.6.2 Register Definition
Table 17. Register Descriptions
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
Description
Page 0 Registers
[7:0]
Main Configuration Register 0
Mode Select Bits.
11 Mode 3 (Default) (3 Channel Mode)
[7:6]
10 Mode 2 (2 Channel Mode)
01 Mode 1a (1 Channel Mode, 1 Channel sampled for all lines)
00 Mode 1b (3 Channel Line rate mode, 1 Channel sampled per line)
Color Select Bits. Used to determine the inputs sampled during a scan.
11 All three channels sampled (Default)
[5:4]
10 Mode 2 = OSR & OSB Mode 1 = OSB
01 Mode 2 = OSG & OSB Mode 1 = OSG
00 Mode 2 = OSR & OSG Mode 1 = OSR
0
0 0000
Main Configuration 0
Color Order. Configures the sequence of the pixel processing.
1111 0001
[3]
0 Forward (default)
1 Reverse
Color Sequence Length. Used in Mode 1a only to determine the number of lines of colors
sequenced during a scan.
111 Not valid
110 Not Valid
101 Five color (line) sequence
[2:0]
100 Four color (line) sequence
011 Three color (line) sequence
010 Two color (line) sequence
001 One color (line) sequence (Default)
000 Not Valid
70
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Table 17. Register Descriptions (continued)
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
[7:0]
Description
Main Configuration Register 1
Source Follower Enable.
[7]
0 Disable (Default)
1 Enable
Input Bias Enable. Enables the Input Bias Resistor ladder.
[6]
0 Disable
1 Enable (Default)
Input Polarity. Configures the polarity mode of the input signal.
[5]
0 Negative going input relative to reference (Default)
1 Positive going input relative to reference
Sampling Mode Select.
[4]
0 Sample and Hold Mode
1 Correlated Double Sampling Mode (Default)
Output Format.
[3]
0
0 0001
Main Configuration 1
0 LVDS (Default)
1 CMOS
0101 0000
PIXCLK/ADCCLK Configuration. Selects appropriate multiplier for given input clock
frequency.
Mode 3: ADC Frequency = 3x Pixel Frequency
Mode 2: ADC Frequency = 2x Pixel Frequency
Mode 1: ADC Frequency = 1x Pixel Frequency
[2]
0 ADCCLK User supplies ADC rate clock, LM98714 performs no multiplication
1 PIXCLK User supplies Pixel rate clock, LM98714 performs clock multiplication
Mode 3: PIXCLK internally multiplied by 3 to get ADC clock
Mode 2: PIXCLK internally multiplied by 2 to get ADC clock
Mode 1: PIXCLK = ADCCLK. This bit is not used for Mode 1
[1:0]
Pixel Phase Clock Select. Coarse adjustment for Pixel phase relative to INCLK. Useful in
systems where Pixel inputs arrive with significant delay relative to INCLK.
00 PIXPHASE0. Pixel phase aligned with INCLK
01 PIXPHASE1. Pixel phase delayed by (TADC Clock* 3/7)
10 PIXPHASE2. Pixel phase delayed by (TADC Clock)
11 PIXPHASE3. Pixel phase delayed by (TADC Clock * (1 + 3/7))
[7:0]
Main Configuration 2
[7:6]
Not Used
[5]
Active/Standby
Gain Mode Select. Selects either a 1x or 2x gain mode in the CDS/Sample/Hold Block.
[4]
0 1x Gain in the CDS/Sample/Hold Block (Default)
1 2x Gain in the CDS/Sample/Hold Block
Output Enable. Enables the Data Output pins.
[3]
0
0 0010
Main Configuration 2
0 Disabled (Default)
0000 0000
1 Enable
Powerdown
[2]
0 Device fully powered (Default)
1 Powerdown. Power down of major analog blocks
[1]
Software Reset. Performs a system reset when set to a 1. Self clearing.
Start Scan (BOS)
[0]
0 Ready (Default)
1 Start Scan. Control bit is self clearing
[7:0]
Main Configuration 3
[7:4]
Not Used
Processing Channel Override. Used in Mode 1 to determine the analog processing path for
the selected inputs.
0
0 0011
Main Configuration 3
0000 0111
[3]
0 Multiplex all selected inputs into the Red Channel analog path (Default)
1 Process each selected input through its respective analog path
[2:0]
Reserved
Set to 111
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Table 17. Register Descriptions (continued)
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
Description
[7:0]
Main Configuration 4
[7:4]
Not Used
[3]
Upcount Enable
LVDS Test Mode. Activates LVDS test pattern output (when in LVDS output mode only).
000 Normal operation, no test pattern output (Default)
0
0 0100
Main Configuration 4
001 Test pattern 1: Alternating pattern between 0x155555 and 0x0AAAAA
0000 0000
010 Test pattern 2: If Upcount Enable Bit set, count from 21h000000 to 21h 1FFFFF
[2:0]
011 Test pattern 3. Output Static Count value found represented by the three Upcounter
Registers found on page 0
Reg 0x14 Bits[4:0] = Count Values 5 MSBs
Reg 0x13 Bits[7:0] = Count Values 8 Middle Bits
Reg 0x12 Bits[7:0] = Count Values 8 LSBs
[7:0]
Input Clamp Control (CLPIN) Configuration Register
[7:4]
Reserved
Auto CLPIN Width. Width in Pixels of the Auto generated CLPIN pulse.
00 4 Pixels (Default)
[3:2]
01 8 Pixels
10 16 Pixels
11 32 Pixels
0
0 0101
Input Clamp Control
0000 0000
Auto CLPIN Enable.
0 Auto CLPIN Disabled
[1]
CLPIN Pulse generation Disabled (Default)
1 Auto CLPIN
CLPIN generated internally with a programmable delay from SH
CLPIN Gating Enable.
[0]
0 Auto CLPINGATED not gated by SAMPLE (default)
1 Auto CLPINGATED gated by SAMPLE (= logical and of CLPIN and SAMPLE)
0
0 0110
Auto CLPIN Position
[7:0]
Auto CLPIN Pulse Position Register
[7:0]
Auto CLPIN Pulse Position. Number of pixels in which Auto CLPIN pulse is delayed, relative
to the falling edge of SH.
[7:0]
VCLP Configuration Register
[7:6]
Reserved
0010 0111
VCLP Reference Select.
00 External Bias (No Internal Connection to Ladder Resistors or DAC)
0
0 0111
VCLP Configuration
0010 0000
[5:4]
01 Internal VCLP DAC connection only
10 Internal Resistor Ladder connection only (Default)
11 Reserved
[3:0]
72
4 Bit nibble for VCLP Reference DAC value.
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Table 17. Register Descriptions (continued)
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
[7:0]
Description
Black Level Correction Circuitry Configuration Register
Line Averaging. Number of Lines that the correction loop will run. Line Counter is reset during
any write to this register. A line beginning is defined by the SH pulse.
00 Infinite (Default)
[7:6]
01 15 Lines
10 31 Lines
11 63 Lines
Pixel Averaging. Number of Black Level Pixels averaged by the correction loop.
00 4 Pixels
[5:4]
01 8 Pixels
10 16 Pixels
0
0 1000
Black Level Clamp Control
0000 0000
11 32 Pixels
Offset Integration.
00 Divide by 8
[3:2]
01 Divide by 16
10 Divide by 32
11 Divide by 64
BLKCLP Mode Select. If Auto Black Clamp pulse is enabled, Offset DAC registers are read
only.
00 Auto Black Clamp Circuitry Disabled (default)
[1:0]
01 Auto Black Clamp pulse delayed from falling edge of SH pulse
10 Auto Black Clamp pulse delayed from falling edge of CLPIN pulse
11 Reserved
[7]
0
0
0
0
0
0
0 1001
0 1010
0 1011
0 1100
0 1101
0 1110
Auto Black Level Clamp
Position
0000 0000
Target Black Level MSB
0010 0000
Target Black Level LSB
0000 0000
OSR CLAMP Control
0000 0000
OSG CLAMP Control
0000 0000
OSB CLAMP Control
0000 0000
OS R SAMPLE Control
0000 0000
Black Level Clamp Position. Number of pixels in which Auto Black pulse is delayed, relative to
selected trigger source.
[7:0]
The 8 MSBs of the 10 Bit target output code for black pixels when using the Auto Black Level
Correction loop.
[7:0]
The target output code for black pixels when using the Auto Black Level Correction loop
[7:2]
Reserved
[1:0]
The 2 LSBs of the 10 Bit target output code for black pixels when using the Auto Black Level
Correction loop.
[7:5]
Not Used
[4:0]
CLAMPR Position. A value of 0 will force the position of this pulse to be at the mode
dependant default.
[7:5]
Not Used
[4:0]
CLAMPG Position. A value of 0 will force the position of this pulse to be at the mode
dependant default.
[7:5]
Not Used
[4:0]
CLAMPB Position. A value of 0 will force the position of this pulse to be at the mode
dependant default.
[7]
0
0 1111
[6:0]
[7]
0
1 0000
OSG SAMPLE Control
0000 0000
OSB SAMPLE Control
0000 0000
Page Register
0000 0000
[6:0]
[7]
0
0
1 0001
1 1111
Reserved
[6:0]
Not Used
SAMPLER Position. A value of 0 will force the position of this pulse to be at the mode
dependant default.
Not Used
SAMPLEG Position. A value of 0 will force the position of this pulse to be at its mode
dependant default.
Not Used
[6:0]
SAMPLEB Position. A value of 0 will force the position of this pulse to be at its mode
dependant default.
[7:0]
Used to select desired page of registers being accessed.
Page 1 Registers
The eight bit byte selected by the 5:1 PGA MUX in Mode 1a during Color 1 lines.
1
0 0000
Color 1 PGA
0101 0100
[7:0]
In Mode 1b, Mode 2 or Mode 3, the register used to define the PGA setting for the OSR input.
The eight bit byte selected by the 5:1 PGA MUX in Mode 1a during Color 2 lines.
1
0 0001
Color 2 PGA
0101 0100
[7:0]
In Mode 1b, Mode 2 or Mode 3, the register used to define the PGA setting for the OSG input.
The eight bit byte selected by the 5:1 PGA MUX in Mode 1a during Color 3 lines.
1
0 0010
Color 3 PGA
0101 0100
[7:0]
In Mode 1b, Mode 2 or Mode 3, the register used to define the PGA setting for the OSB input.
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Table 17. Register Descriptions (continued)
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
Description
The eight bit byte selected by the 5:1 PGA MUX in Mode 1a during Color 4 lines.
1
0 0011
Color 4 PGA
0101 0100
[7:0]
Not used in Mode 1b, Mode 2 or Mode 3.
The eight bit byte selected by the 5:1 PGA MUX in Mode 1a during Color 5 lines.
1
0 0100
Color 5 PGA
0101 0100
[7:0]
Not used in Mode 1b, Mode 2 or Mode 3.
The MSBs selected by the 5:1 DAC MUX in Mode 1a during Color 1 lines.
1
1
0 0101
0 0110
Color 1 Black Level DAC MSB
Color 1 Black Level DAC LSB
1000 0000
[7:0]
In Mode 1b/c, Mode 2 or Mode 3, the register used to define the DAC setting for the OSR
input. The DAC value is in offset Binary format.
[7:0]
Color 1 Black Level DAC LSB
[7:2]
Not Used
0000 0000
The LSBs selected by the 5:1 DAC MUX in Mode 1a during Color 1 lines.
[1:0]
In Mode 1b, Mode 2 or Mode 3, the register used to define the DAC setting for the OSR input.
The DAC value is in offset Binary format.
The MSBs selected by the 5:1 DAC MUX in Mode 1a during Color 2 lines.
1
1
0 0111
0 1000
Color 2 Black Level DAC MSB
Color 2 Black Level DAC LSB
1000 0000
[7:0]
In Mode 1b, Mode 2 or Mode 3, the register used to define the DAC setting for the OSG input.
The DAC value is in offset Binary format.
[7:0]
Color 2 Black Level DAC LSB
[7:2]
Not Used
0000 0000
The LSBs selected by the 5:1 DAC MUX in Mode 1a during Color 2 lines.
[1:0]
In Mode 1b, Mode 2 or Mode 3, the register used to define the DAC setting for the OSG input.
The DAC value is in offset Binary format.
The MSBs selected by the 5:1 DAC MUX in Mode 1a during Color 3 lines.
1
1
0 1001
0 1010
Color 3 Black Level DAC MSB
Color 3 Black Level DAC LSB
1000 0000
[7:0]
In Mode 1b, Mode 2 or Mode 3, the register used to define the DAC setting for the OSB input.
The DAC value is in offset Binary format.
[7:0]
Color 3 Black Level DAC LSB
[7:2]
Not Used
0000 0000
The LSBs selected by the 5:1 DAC MUX in Mode 1a during Color 3 lines.
[1:0]
In Mode 1b, Mode 2 or Mode 3, the register used to define the DAC setting for the OSB input.
The DAC value is in offset Binary format.
The MSBs selected by the 5:1 DAC MUX in Mode 1a during Color 4 lines.
1
0 1011
Color 4 Black Level DAC MSB
1000 0000
[7:0]
Not used in Mode 1b, Mode 2 or Mode 3. The DAC value is in offset Binary format.
1
0 1100
Color 4 Black Level DAC LSB
[7:0]
Color 4 Black Level DAC LSB
[7:2]
Not Used
0000 0000
The LSBs selected by the 5:1 DAC MUX in Mode 1a during Color 4 lines.
[1:0]
Not used in Mode 1b, Mode 2 or Mode 3. The DAC value is in offset Binary format.
The MSBs selected by the 5:1 DAC MUX in Mode 1a during Color 5 lines.
1
0 1101
Color 5 Black Level DAC MSB
1000 0000
[7:0]
Not used in Mode 1b, Mode 2 or Mode 3. The DAC value is in offset Binary format.
1
0 1110
Color 5 Black Level DAC LSB
[7:0]
Color 5 Black Level DAC LSB
[7:2]
Not Used
0000 0000
The LSBs selected by the 5:1 DAC MUX in Mode 1a during Color 5 lines.
[1:0]
Not used in Mode 1b/c, Mode 2 or Mode 3. The DAC value is in offset Binary format.
[7:0]
[7]
1
0 1111
Color 1 Digital Offset
0100 0000
1 0000
Color 2 Digital Offset
The Digital Offset applied to the ADC result in Mode 1a during Color 1 lines.
In Mode 1b/c, Mode 2 or Mode 3, the register used to define the Digital Offset setting for the
OSR input. The DAC value is in offset Binary format.
[7:0]
Color 2 Digital Offset
0100 0000
1 0001
Color 3 Digital Offset
The Digital Offset applied to the ADC result in Mode 1a during Color 2 lines.
In Mode 1b/c, Mode 2 or Mode 3, the register used to define the DAC setting for the OSG
input. The DAC value is in offset Binary format.
[7:0]
Color 3 Digital Offset
0100 0000
1 0010
Color 4 Digital Offset
Not Used
The Digital Offset applied to the ADC result in Mode 1a during Color 3 lines.
[6:0]
In Mode 1b/c, Mode 2 or Mode 3, the register used to define the DAC setting for the OSB
input. The DAC value is in offset Binary format.
[7:0]
Color 4 Digital Offset
[7]
1
Not Used
[6:0]
[7]
1
Not Used
[6:0]
[7]
1
Color 1 Digital Offset
Not Used
0100 0000
The Digital Offset applied to the ADC result in Mode 1a during Color 4 lines.
[6:0]
Not used in Mode 1b/c, Mode 2 or Mode 3. The DAC value is in offset Binary format.
74
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Table 17. Register Descriptions (continued)
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
[7:0]
[7]
1
1 0011
Color 5 Digital Offset
Description
Color 5 Digital Offset
Not Used
0100 0000
The Digital Offset applied to the ADC result in Mode 1a during Color 5 lines.
[6:0]
Not used in Mode 1b/c, Mode 2 or Mode 3. The DAC value is in offset Binary format.
1
1 1111
Page Register
0000 0000
[7:0]
Used to select desired page of registers being accessed.
Page 2 Registers
SH Output Enable.
[7]
0 Enable SH Output
1 SH Output Tristate
SH Master/Slave Select.
[6]
2
0 0000
SH Mode
0 External SH_R input. CCD Timing Generator runs in Slave mode, with SH triggered by an
external pulse on the SH_R pin.
1 Auto generated SH. CCD Timing Generator runs in Master mode, with SH generated
internally with a programmable period and width.
0000 0000
SH Output Mode.
00 SH Output = SH
[5:4]
01 SH Output = SH
10 SH Output = 0
11 SH Output = 1
SH Delay from SH_R
[3:0]
Additional delay
SH Pulse Width
2
0 0001
SH Pulse Width
0010 0111
[7:0]
SH Pulse Width = (2 * [7:0]) + 1
PIX1 Activity
[7]
0 Disabled
1 Enabled
PIX1 Polarity
[6]
0 Normal - Low when off
1 Inverted - High when off
PIX1 Frequency
[5]
0 Pixel Rate
1 1/2 Pixel Rate
PIX1 Activity During SH
[4]
0 Inactive
1 Active
2
0 0010
PIX1/2 Control
1100 1000
PIX2 Activity
[3]
0 Disabled
1 Enabled
PIX2 Polarity
[2]
0 Normal - Low when off
1 Inverted - High when off
PIX2 Frequency
[1]
0 Pixel Rate
1 1/2 Pixel Rate
PIX2 Activity During SH
[0]
0 Inactive
1 Active
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Table 17. Register Descriptions (continued)
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
Description
PIX3 Activity
[7]
0 Disabled
1 Enabled
PIX3 Polarity
[6]
0 Normal - Low when off
1 Inverted - High when off
PIX3 Frequency
[5]
0 Pixel Rate
1 1/2 Pixel Rate
PIX3 Activity During SH
[4]
0 Inactive
1 Active
2
0 0011
PIX3/4 Control
1000 1000
PIX4 Activity
[3]
0 Disabled
1 Enabled
PIX4 Polarity
[2]
0 Normal - Low when off
1 Inverted - High when off
PIX4 Frequency
[1]
0 Pixel Rate
1 1/2 Pixel Rate
PIX4 Activity During SH
[0]
0 Inactive
1 Active
PIX5 Activity
[7]
0 Disabled
1 Enabled
PIX5 Polarity
[6]
0 Normal - Low when off
1 Inverted - High when off
PIX5 Frequency
[5]
0 Pixel Rate
1 1/2 Pixel Rate
PIX5 Activity During SH
[4]
0 Inactive
1 Active
2
0 0100
PIX5/6 Control
0000 0000
PIX6 Activity
[3]
0 Disabled
1 Enabled
PIX6 Polarity
[2]
0 Normal - Low when off.
1 Inverted - High when off.
PIX6 Frequency
[1]
0 Pixel Rate
1 1/2 Pixel Rate
PIX6 Activity During SH
[0]
0 Inactive
1 Active
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Table 17. Register Descriptions (continued)
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
Description
PIX7 Activity
[7]
0 Disabled
1 Enabled
PIX7 Polarity
[6]
0 Normal - Low when off
1 Inverted - High when off
PIX7 Frequency
[5]
0 Pixel Rate
1 1/2 Pixel Rate
PIX7 Activity During SH
[4]
0 Inactive
1 Active
2
0 0101
PIX7/8 Control
0000 0000
PIX8 Activity
[3]
0 Disabled
1 Enabled
PIX8 Polarity
[2]
0 Normal - Low when off
1 Inverted - High when off
PIX8 Frequency
[1]
0 Pixel Rate
1 1/2 Pixel Rate
PIX8 Activity During SH
[0]
0 Inactive
1 Active
PIX8 Line Clamp Enable. Enables single Line Clamp pulse per line from PIX8.
[7]
0 Disabled. PIX generator functions as normal.
1 Enabled. PIX generates a single clock per line for Line Clamp function.
PIX7 Line Clamp Enable. Enables single Line Clamp pulse per line from PIX7.
[6]
0 Disabled. PIX generator functions as normal.
1 Enabled. PIX generates a single clock per line for Line Clamp function.
PIX6 Line Clamp Enable. Enables single Line Clamp pulse per line from PIX6.
[5]
0 Disabled. PIX generator functions as normal.
1 Enabled. PIX generates a single clock per line for Line Clamp function.
PIX5 Line Clamp Enable. Enables single Line Clamp pulse per line from PIX5.
0 Disabled. PIX generator functions as normal.
[4]
1 Enabled. PIX generates a single clock per line for Line Clamp function.
2
0 0110
Line Clamp Enable
0000 0000
PIX4 Line Clamp Enable. Enables single Line Clamp pulse per line from PIX4.
0 Disabled. PIX generator functions as normal.
[3]
1 Enabled. PIX generates a single clock per line for Line Clamp function.
PIX3 Line Clamp Enable. Enables single Line Clamp pulse per line from PIX3.
0 Disabled. PIX generator functions as normal.
[2]
1 Enabled. PIX generates a single clock per line for Line Clamp function.
PIX2 Line Clamp Enable. Enables single Line Clamp pulse per line from PIX2.
0 Disabled. PIX generator functions as normal.
[1]
1 Enabled. PIX generates a single clock per line for Line Clamp function.
PIX1 Line Clamp Enable. Enables single Line Clamp pulse per line from PIX1.
0 Disabled. PIX generator functions as normal.
[0]
1 Enabled. PIX generates a single clock per line for Line Clamp function.
[7]
2
0 0111
PIX1 Start
0000 0000
[6:0]
2
0 1000
PIX1 End
0001 0101
[6:0]
[7]
Reserved. Set to 0.
PIX1 on point. Defines when the PIX1 signal turns on within the pixel period. Can be set to
any available edge within the pixel period. (For 1/2 frequency signals, the count can be any
available edge within 2 pixel periods)
Reserved. Set to 0.
PIX1 off point. Defines when the PIX1 signal turns off within the pixel period. Can be set to
any available edge within the pixel period. (For 1/2 frequency signals, the count can be any
available edge within 2 pixel periods)
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Table 17. Register Descriptions (continued)
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
[7]
2
0 1010
PIX2 Start
0000 0000
[6:0]
2
0 1011
PIX2 End
0001 0101
[6:0]
[7]
[7]
2
0 1101
PIX3 Start
0000 1011
[6:0]
2
0 1110
PIX3 End
0000 1101
[6:0]
2
1 0000
PIX4 Start
0001 0000
[6:0]
2
1 0001
PIX4 End
0001 0011
[6:0]
2
1 0011
PIX5 Start
0000 0000
[6:0]
2
1 0100
PIX5 End
0000 0000
[6:0]
2
1 0110
PIX6 Start
0000 0000
[6:0]
2
1 0111
PIX6 End
0000 0000
[6:0]
2
1 1001
PIX7 Start
0000 0000
[6:0]
2
1 1010
PIX7 End
0000 0000
[6:0]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
2
1 1100
PIX8 Start
0000 0000
[6:0]
2
1 1101
PIX8 End
0000 0000
[6:0]
[7]
Description
Reserved. Set to 0.
PIX2 on point. Defines when the PIX2 signal turns on within the pixel period. Can be set to
any available edge within the pixel period. (For 1/2 frequency signals, the count can be any
available edge within 2 pixel periods)
Reserved. Set to 0.
PIX2 off point. Defines when the PIX2 signal turns off within the pixel period. Can be set to
any available edge within the pixel period. (For 1/2 frequency signals, the count can be any
available edge within 2 pixel periods)
Reserved. Set to 0.
PIX3 on point. Defines when the PIX3 signal turns on within the pixel period. Can be set to
any available edge within the pixel period. (For 1/2 frequency signals, the count can be any
available edge within 2 pixel periods)
Reserved. Set to 0.
PIX3 off point. Defines when the PIX3 signal turns off within the pixel period. Can be set to
any available edge within the pixel period. (For 1/2 frequency signals, the count can be any
available edge within 2 pixel periods)
Reserved. Set to 0.
PIX4 on point. Defines when the PIX4 signal turns on within the pixel period. Can be set to
any available edge within the pixel period. (For 1/2 frequency signals, the count can be any
available edge within 2 pixel periods)
Reserved. Set to 0.
PIX4 off point. Defines when the PIX4 signal turns off within the pixel period. Can be set to
any available edge within the pixel period. (For 1/2 frequency signals, the count can be any
available edge within 2 pixel periods)
Reserved. Set to 0.
PIX5 on point. Defines when the PIX5 signal turns on within the pixel period. Can be set to
any available edge within the pixel period. (For 1/2 frequency signals, the count can be any
available edge within 2 pixel periods)
Reserved. Set to 0.
PIX5 off point. Defines when the PIX5 signal turns off within the pixel period. Can be set to
any available edge within the pixel period. (For 1/2 frequency signals, the count can be any
available edge within 2 pixel periods)
Reserved. Set to 0.
PIX6 on point. Defines when the PIX6 signal turns on within the pixel period. Can be set to
any available edge within the pixel period. (For 1/2 frequency signals, the count can be any
available edge within 2 pixel periods)
Reserved. Set to 0.
PIX6 off point. Defines when the PIX6 signal turns off within the pixel period. Can be set to
any available edge within the pixel period. (For 1/2 frequency signals, the count can be any
available edge within 2 pixel periods)
Reserved. Set to 0.
PIX7 on point. Defines when the PIX7 signal turns on within the pixel period. Can be set to
any available edge within the pixel period. (For 1/2 frequency signals, the count can be any
available edge within 2 pixel periods)
Reserved. Set to 0.
PIX7 off point. Defines when the PIX7 signal turns off within the pixel period. Can be set to
any available edge within the pixel period. (For 1/2 frequency signals, the count can be any
available edge within 2 pixel periods)
Reserved. Set to 0.
PIX8 on point. Defines when the PIX8 signal turns on within the pixel period. Can be set to
any available edge within the pixel period. (For 1/2 frequency signals, the count can be any
available edge within 2 pixel periods)
Reserved. Set to 0
PIX8 off point. Defines when the PIX8 signal turns off within the pixel period. Can be set to
any available edge within the pixel period. (For 1/2 frequency signals, the count can be any
available edge within 2 pixel periods)
Reserved. Set to 000
[7:6]
2
2
78
1 1110
1 1111
CMOS Data Mode Status Bit
Enable
Page Register
0000 0000
0000 0000
When mapping the CLK5 to CLK10 pins as either CLKOUT or CB outputs, the Sample Timing
Monitor 1 (Page 4, Register 0x0C) cannot be used.
[5]
0 - CLK10 mapped normally, 1- CLK10 = CLKOUT
[4]
0 - CLK9 mapped normally, 1- CLK9 = CB[4] status bit
[3]
0 - CLK8 mapped normally, 1- CLK8 = CB[3] status bit
[2]
0 - CLK7 mapped normally, 1- CLK7 = CB[2] status bit
[1]
0 - CLK6 mapped normally, 1- CLK6 = CB[1] status bit
[0]
0 - CLK5 mapped normally, 1- CLK5 = CB[0] status bit
[7:0]
Used to select desired page of registers being accessed.
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Table 17. Register Descriptions (continued)
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
Description
Page 3 Registers
Setting CLKn =
0000 Tristate
0001 PIX1
0010 PIX2
[7:4]
CLK 1
0011 PIX3
0100 PIX4
0101 PIX5
3
0 0000
Output Mapping CLK1/CLK2
This register sets which timing
signal is present on the
respective CLKn output pin.
0110 PIX6
0000 0000
0111 PIX7
1000 PIX8
1001 LAMPR
1010 LAMPG
[3:0]
CLK 2
1011 LAMPB
1100 LAMPIR1
1101 LAMPIR2
1110 MODE
1111 SH
Setting CLKn =
0000 Tristate
0001 PIX1
0010 PIX2
[7:4]
CLK 3
0011 PIX3
0100 PIX4
0101 PIX5
3
0 0001
Output Mapping CLK3/CLK4
This register sets which timing
signal is present on the
respective CLKn output pin.
0110 PIX6
0000 0000
0111 PIX7
1000 PIX8
1001 LAMPR
1010 LAMPG
[3:0]
CLK 4
1011 LAMPB
1100 LAMPIR1
1101 LAMPIR2
1110 MODE
1111 SH
Setting CLKn =
0000 Tristate
0001 PIX1
0010 PIX2
[7:0]
CLK 5
0011 PIX3
0100 PIX4
0101 PIX5
3
0 0010
Output Mapping CLK5/CLK6
This register sets which timing
signal is present on the
respective CLKn output pin.
0110 PIX6
0000 0000
0111 PIX7
1000 PIX8
1001 LAMPR
1010 LAMPG
[3:0]
CLK 6
1011 LAMPB
1100 LAMPIR1
1101 LAMPIR2
1110 MODE
1111 SH
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Table 17. Register Descriptions (continued)
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
Description
Setting CLKn =
0000 Tristate
0001 PIX1
0010 PIX2
[7:0]
CLK 7
0011 PIX3
0100 PIX4
0101 PIX5
3
0 0011
Output Mapping CLK7/CLK8
This register sets which timing
signal is present on the
respective CLKn output pin.
0110 PIX6
0000 0000
0111 PIX7
1000 PIX8
1001 LAMPR
1010 LAMPG
[3:0]
CLK 8
1011 LAMPB
1100 LAMPIR1
1101 LAMPIR2
1110 MODE
1111 SH
Setting CLKn =
0000 Tristate
0001 PIX1
0010 PIX2
[7:4]
CLK 9
0011 PIX3
0100 PIX4
0101 PIX5
3
0 0100
Output Mapping CLK9/CLK10
This register sets which timing
signal is present on the
respective CLKn output pin.
0110 PIX6
0000 0000
0111 PIX7
1000 PIX8
1001 LAMPR
1010 LAMPG
[3:0]
CLK 10
1011 LAMPB
1100 LAMPIR1
1101 LAMPIR2
1110 MODE
1111 SH
[7]
LAMPR Normal State
0 = Low, 1 = High
[6]
LAMPG Normal State
0 = Low, 1 = High
[5]
LAMPB Normal State
0 = Low, 1 = High
3
0 0101
Illumination Mode (see also
AFE color modes)
LampIR1 Normal State
0000 0000
[4]
0 = Low, 1 = High
LampIR2 Normal State
[3]
0 = Low, 1 = High
[2:1]
Reserved
SH/LAMP Overlap Enable
[0]
0 Disabled
1 Overlap Enabled
80
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Table 17. Register Descriptions (continued)
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
[7:5]
Description
Reserved. Set to 000
Red Lamp Enable
[4]
0 Red Disabled
1 Red Enabled
Green Lamp Enable
[3]
0 Green Disabled
1 Green Enabled
Blue Lamp Enable
3
0 0110
Line 1 Lamp Selection
0000 0000
[2]
0 Blue Disabled
1 Blue Enabled
IR1 Lamp Enable
[1]
0 IR1 Disabled
1 IR1 Enabled
IR2 Lamp Enable
[0]
0 IR2 Disabled
1 IR2 Enabled
[7:5]
Reserved. Set to 000
Red Lamp Enable
[4]
0 Red Disabled
1 Red Enabled
Green Lamp Enable
[3]
0 Green Disabled
1 Green Enabled
Blue Lamp Enable
3
0 0111
Line 2 Lamp Selection
0000 0000
[2]
0 Blue Disabled
1 Blue Enabled
IR1 Lamp Enable
[1]
0 IR1 Disabled
1 IR1 Enabled
IR2 Lamp Enable
[0]
0 IR2 Disabled
1 IR2 Enabled
[7:5]
Reserved. Set to 000
Red Lamp Enable
[4]
0 Red Disabled
1 Red Enabled
Green Lamp Enable
[3]
0 Green Disabled
1 Green Enabled
Blue Lamp Enable
3
0 1000
Line 3 Lamp Selection
0000 0000
[2]
0 Blue Disabled
1 Blue Enabled
IR1 Lamp Enable
[1]
0 IR1 Disabled
1 IR1 Enabled
IR2 Lamp Enable
[0]
0 IR2 Disabled
1 IR2 Enabled
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Table 17. Register Descriptions (continued)
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
[7:5]
Description
Reserved. Set to 000
Red Lamp Enable
[4]
0 Red Disabled
1 Red Enabled
Green Lamp Enable
[3]
0 Green Disabled
1 Green Enabled
Blue Lamp Enable
3
0 1001
Line 4 Lamp Selection
0000 0000
[2]
0 Blue Disabled
1 Blue Enabled
IR1 Lamp Enable
[1]
0 IR1 Disabled
1 IR1 Enabled
IR2 Lamp Enable
[0]
0 IR2 Disabled
1 IR2 Enabled
[7:5]
Reserved. Set to 000
Red Lamp Enable
[4]
0 Red Disabled
1 Red Enabled
Green Lamp Enable
[3]
0 Green Disabled
1 Green Enabled
Blue Lamp Enable
3
0 1010
Line 5 Lamp Selection
0000 0000
[2]
0 Blue Disabled
1 Blue Enabled
IR1 Lamp Enable
[1]
0 IR1 Disabled
1 IR1 Enabled
IR2 Lamp Enable
[0]
0 IR2 Disabled
1 IR2 Enabled
[7:5]
Reserved. Set to 000
LAMPR SH_OR Enable
[4]
3
0 1011
LAMPR On MSB
0 No ORing
0000 0000
1 LAMPR uses SH_OR function
[3:0]
LAMPR On Time Most Significant Bits
This selects the pixel count at which the LAMPR output goes high.
3
0 1100
LAMPR On LSB
0001 0001
[7:0]
This selects the pixel count at which the LAMPR output goes high.
[7:4]
3
0 1101
LAMPR Off MSB
LAMPR On Time Least Significant Byte
0000 0011
[3:0]
Reserved. Set to 0000
LAMPR Off Time Most Significant Bits
This selects the pixel count at which the LAMPR output goes low.
3
0 1110
LAMPR Off LSB
0000 0110
[7:0]
LAMPR Off Time Least Significant Byte
This selects the pixel count at which the LAMPR output goes low.
[7:5]
Reserved. Set to 000
LAMPG SH_OR Enable.
[4]
3
0 1111
LAMPG On MSB
0 No ORing
0000 0000
1 LAMPG uses SH_OR function
[3:0]
LAMPG On Time Most Significant Bits.
This selects the pixel count at which the LAMPR output goes high.
3
82
1 0000
LAMPG On LSB
0001 0010
[7:0]
LAMPG On Time Least Significant Byte
This selects the pixel count at which the LAMPR output goes high.
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Table 17. Register Descriptions (continued)
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
[7:4]
3
1 0001
LAMPG Off MSB
0000 0011
[3:0]
Description
Reserved. Set to 0000
LAMPG Off Time Most Significant Bits
This selects the pixel count at which the LAMPR output goes low.
3
1 0010
LAMPG Off LSB
0000 0000
[7:0]
LAMPG Off Time Least Significant Byte
This selects the pixel count at which the LAMPR output goes low.
[7:5]
Reserved. Set to 000
LAMPB SH_OR Enable
[4]
3
1 0011
LAMPB On MSB
0 No ORing
0000 0000
1 LAMPB uses SH_OR function
[3:0]
LAMPB On Time Most Significant Bits
This selects the pixel count at which the LAMPR output goes high.
3
1 0100
LAMPB On LSB
0001 0011
[7:0]
This selects the pixel count at which the LAMPR output goes high.
[7:4]
3
1 0101
LAMPB Off MSB
LAMPB On Time Least Significant Byte
0000 0011
[3:0]
Reserved. Set to 0000
LAMPB Off Time Most Significant Bits
This selects the pixel count at which the LAMPR output goes low.
3
1 0110
LAMPB Off LSB
0011 0000
[7:0]
LAMPB Off Time Least Significant Byte
This selects the pixel count at which the LAMPR output goes low.
[7:5]
Reserved. Set to 000
LAMPIR1 SH_OR Enable
[4]
3
1 0111
LAMPIR1 On MSB
0 No ORing
0000 0000
1 LAMPIR1 uses SH_OR function
LAMPIR1 On Time Most Significant Bits
[3:0]
This selects the pixel count at which the LAMPR output goes high.
LAMPIR1 On Time Least Significant Byte
3
1 1000
LAMPIR1 On LSB
0001 0100
[7:0]
This selects the pixel count at which the LAMPR output goes high.
[7:4]
3
1 1001
LAMPIR1 Off MSB
0000 0011
Reserved. Set to 0000
LAMPIR1 Off Time Most Significant Bits
[3:0]
This selects the pixel count at which the LAMPR output goes low.
LAMPIR1 Off Time Least Significant Byte
3
1 1010
LAMPIR1 Off LSB
0011 0000
[7:0]
This selects the pixel count at which the LAMPR output goes low.
[7:5]
Reserved. Set to 000
LAMPIR2 SH_OR Enable.
[4]
3
1 1011
LAMPIR2 On MSB
0 No ORing
0000 0000
1 LAMPIR2 uses SH_OR function
LAMPIR2 On Time Most Significant Bits.
[3:0]
This selects the pixel count at which the LAMPR output goes high.
LAMPIR2 On Time Least Significant Byte
3
1 1100
LAMPIR2 On LSB
0001 0101
[7:0]
This selects the pixel count at which the LAMPR output goes high.
[7:4]
3
1 1101
LAMPIR2 Off MSB
0000 0011
Reserved. Set to 0000
LAMPIR2 Off Time Most Significant Bits
[3:0]
This selects the pixel count at which the LAMPR output goes low.
LAMPIR2 Off Time Least Significant Byte
3
1 1110
LAMPIR2 Off LSB
0011 0000
[7:0]
3
1 1111
Page Register
0000 0000
[7:0]
This selects the pixel count at which the LAMPR output goes low.
Used to select desired page of registers being accessed.
Page 4 Registers
[7:4]
4
0 0000
Mode On MSB
0000 0010
Reserved. Set to 0000
Mode On Time Most Significant Bits
[3:0]
This selects the pixel count at which the Mode output goes high.
Mode On Time Least Significant Byte
4
0 0001
Mode On LSB
0000 0000
[7:0]
This selects the pixel count at which the Mode output goes high.
[7:4]
4
0 0010
Mode Off MSB
0000 0011
Reserved. Set to 0000
Mode Off Time Most Significant Bits
[3:0]
This selects the pixel count at which the Mode output goes low.
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Table 17. Register Descriptions (continued)
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
Description
Mode Off Time Least Significant Byte
4
0 0011
Mode Off LSB
0000 0001
[7:0]
This selects the pixel count at which the Mode output goes low.
Starting point for optical black clamping
4
0 0100
Optical Black Pixels Start
0000 0000
[7:0]
nnnnnnnn - n pixels (0-255)
End point for optical black clamping
4
0 0101
Optical Black Pixels End
0000 0000
[7:0]
nnnnnnnn - n pixels (0-255)
[7:6]
4
0 0110
Start of Valid Pixels - MSB
0000 0000
Reserved. Set to 00
Start of Valid Pixels - Most Significant Bits.
[5:0]
Selects the pixel count where the data status bits begin to indicate valid pixels.
Start of Valid Pixels - Least Significant Bits.
4
0 0111
Start of Valid Pixels - LSB
0000 0000
[7:0]
Selects the pixel count where the data status bits begin to indicate valid pixels.
[7:6]
4
0 1000
End of Valid Pixels - MSB
0011 1111
Reserved. Set to 00
End of Valid Pixels - Most Significant Bits.
[5:0]
Selects the pixel count where the data status bits stop indicating valid pixels.
End of Valid Pixels - Least Significant Bits.
4
0 1001
End of Valid Pixels - LSB
1111 1110
[7:0]
Selects the pixel count where the data status bits stop indicating valid pixels.
[7:6]
4
0 1010
Line End - MSB
Reserved. Set to 00.
Line End Value - Most Significant 6 Bits
0011 1111
[5:0]
Selects the pixel count where the current line is ended and the next one begins. Controls the
integration time of one line and the period between SH pulses.
Line End Value Least Significant Byte
4
0 1011
Line End - LSB
1111 1111
[7:0]
Selects the pixel count where the current line is ended and the next one begins. Controls the
integration time of one line and the period between SH pulses.
n pixels (0 - 16383)
Enables Sample and Clamp timing signals to be observed on one of the sensor timing control
outputs. This function overrides any other settings for sensor control signal mapping.
[7:0]
Important Note: Sample Timing Monitor 1 cannot be used if the CMOS Data Mode
Status Bit Enable Register (Page 2, Register 0x1E) is being programmed to map
CLKOUT to CLK10 or any Control Bit to CLK5-CLK9. Sample Timing Monitors 2 and 3
are not effected by this limitation.
Upper 4 bits select timing signal to be monitored.
0000 Sample Red
0001 Clamp Red
0010 Sample Green
[7:4]
0011 Clamp Green
0100 Sample Blue
0101 Clamp Blue
4
0 1100
Sample Timing Monitor 1
1111 No signal monitored
1111 1111
Lower 4 bits select which output pin is used as a monitor.
0000 CLK1
0001 CLK2
0010 CLK3
0011 CLK4
0100 CLK5
[3:0]
0101 CLK6
0110 CLK7
0111 CLK8
1000 CLK9
1001 CLKOUT/CLK10
1111 All outputs normal
84
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Table 17. Register Descriptions (continued)
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
Description
[7:0]
Enables Sample and Clamp timing signals to be observed on one of the sensor timing control
outputs. This function overrides any other settings for sensor control signal mapping.
Upper 4 bits select timing signal to be monitored.
0000 Sample Red
0001 Clamp Red
0010 Sample Green
[7:4]
0011 Clamp Green
0100 Sample Blue
0101 Clamp Blue
1111 No signal monitored
Lower 4 bits select which output pin is used as a monitor.
4
0 1101
Sample Timing Monitor 2
1111 1111
0000 CLK1
0001 CLK2
0010 CLK3
0011 CLK4
0100 CLK5
[3:0]
0101 CLK6
0110 CLK7
0111 CLK8
1000 CLK9
1001 CLKOUT/CLK10
1111 All outputs normal
[7:0]
Enables Sample and Clamp timing signals to be observed on one of the sensor timing control
outputs. This function overrides any other settings for sensor control signal mapping.
Upper 4 bits select timing signal to be monitored.
0000 Sample Red
0001 Clamp Red
0010 Sample Green
[7:4]
0011 Clamp Green
0100 Sample Blue
0101 Clamp Blue
1111 No signal monitored
Lower 4 bits select which output pin is used as a monitor.
4
0 1110
Sample Timing Monitor 3
1111 1111
0000 CLK1
0001 CLK2
0010 CLK3
0011 CLK4
0100 CLK5
[3:0]
0101 CLK6
0110 CLK7
0111 CLK8
1000 CLK9
1001 CLKOUT/CLK10
1111 All outputs normal
[7:0]
Controls the optional SH2 and SH3 output signals. These signals can override the Lamp IR1
and Lamp IR2 outputs if additional SH signals are required.
[7:4]
Not Used.
SH3 Output Select.
[3]
4
0 1111
SH2/SH3 Control
0000 0000
0 Lamp IR2 output is programmed from Lamp IR2 Generator
1 Lamp IR2 output is SH3
SH2 Output Select.
[2]
0 Lamp IR1 output is programmed from Lamp IR1 Generator
1 Lamp IR1 output is SH2
[1:0]
Not Used
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Table 17. Register Descriptions (continued)
Page
Address
(Binary)
Register
Title
Default
(Binary)
Bit No.
Description
[7:0]
Controls the optional OR and NOR operations on the PIX generator outputs as described
below. These signals can override the normal PIX generator outputs to pro vide OR and NOR
functionality for uses such as Pixel Lumping. If multiple functions are selected, the order of
priority from highest to lowest is PIX OR/NOR Control 1 Bit[0] to Bit [7], then PIX OR/NOR
Control 2 Bit[0] to Bit[7] (i.e PIX OR/NOR Control 1 Bit[7] has a higher priority on the PIX5
output than PIX OR/NOR Control 2 Bit[0] or Bit[2]).
For reference purposes, the normal, unmodified PIX generator outputs are named pix1
through pix8 (lower case) and the final signal prior to the CLK pins are named PIX1 through
PIX8 (upper case).
4
1 0000
PIX OR/NOR Control 1
0000 0000
[0]
0 No effect (default); 1 PIX1 = ~(pix1 || pix2)
[1]
0 No effect (default); 1 PIX2 = (pix1 || pix2)
[2]
0 No effect (default); 1 PIX2 = ~(pix2 || pix3)
[3]
0 No effect (default); 1 PIX3 = (pix2 || pix3)
[4]
0 No effect (default); 1 PIX3 = ~(pix3 || pix4)
[5]
0 No effect (default); 1 PIX4 = (pix3 || pix4)
[6]
0 No effect (default); 1 PIX4 = ~(pix4 || pix5)
[7]
0 No effect (default); 1 PIX5 = (pix4 || pix5)
[7:0]
Controls the optional OR and NOR operations on the PIX generator outputs as described
below. These signals can override the normal PIX generator outputs to pro vide OR and NOR
functionality for uses such as Pixel Lumping. If multiple functions are selected, the order of
priority from highest to lowest is PIX OR/NOR Control 1 Bit[0] to Bit [7], then PIX OR/NOR
Control 2 Bit[0] to Bit[7] (i.e PIX OR/NOR Control 1 Bit[7] has a higher priority on the PIX5
output than PIX OR/NOR Control 2 Bit[0] or Bit[2]).
For reference purposes, the normal, unmodified PIX generator outputs are named pix1
through pix8 (lower case) and the final signal prior to the CLK pins are named PIX1 through
PIX8 (upper case).
4
4
1 0001
1 1111
PIX OR/NOR Control 2
Page Register
0000 0000
0000 0000
[0]
0 No effect (default); 1 PIX5 = ~(pix5 || pix6)
[1]
0 No effect (default); 1 PIX6 = (pix5 || pix6)
[2]
0 No effect (default); 1 PIX5 = ~(pix4 || pix5 || pix6)
[3]
0 No effect (default); 1 PIX6 = (pix4 || pix5 || pix6)
[4]
0 No effect (default); 1 PIX7 = ~(pix3 || pix7 || pix8)
[5]
0 No effect (default); 1 PIX8 = (pix3 || pix7 || pix8)
[6]
0 No effect (default); 1 PIX7 = ~(pix7 || pix8)
[7]
0 No effect (default); 1 PIX8 = (pix7 || pix8)
[7:0]
Used to select desired page of registers being accessed.
Page 5 Registers
86
5
0 0000
PIX1/SH On Guardbands
0000 1111
[7:0]
PIX1 on guardband. Number of pixel periods from end of SH pulse to start of PIX1.
5
0 0001
PIX1/SH Off Guardbands
0000 0111
[7:0]
PIX1 off guardband. Number of pixel periods before start of SH pulse that PIX1 stops.
5
0 0010
PIX2/SH On Guardbands
0000 1111
[7:0]
PIX2 on guardband. Number of pixel periods from end of SH pulse to start of PIX2.
5
0 0011
PIX2/SH Off Guardbands
0000 0111
[7:0]
PIX2 off guardband. Number of pixel periods before start of SH pulse that PIX2 stops.
5
0 0100
PIX3/SH On Guardbands
0000 1111
[7:0]
PIX3 on guardband. Number of pixel periods from end of SH pulse to start of PIX3.
5
0 0101
PIX3/SH Off Guardbands
0000 0111
[7:0]
PIX3 off guardband. Number of pixel periods before start of SH pulse that PIX3 stops.
5
0 0110
PIX4/SH On Guardbands
0000 1111
[7:0]
PIX4 on guardband. Number of pixel periods from end of SH pulse to start of PIX4.
5
0 0111
PIX4/SH Off Guardbands
0000 0111
[7:0]
PIX4 off guardband. Number of pixel periods before start of SH pulse that PIX4 stops.
5
0 1000
PIX5/SH On Guardbands
0000 1111
[7:0]
PIX5 on guardband. Number of pixel periods from end of SH pulse to start of PIX5.
5
0 1001
PIX5/SH Off Guardbands
0000 0111
[7:0]
PIX5 off guardband. Number of pixel periods before start of SH pulse that PIX5 stops.
5
0 1010
PIX6/SH On Guardbands
0000 1111
[7:0]
PIX6 on guardband. Number of pixel periods from end of SH pulse to start of PIX6.
5
0 1011
PIX6/SH Off Guardbands
0000 0111
[7:0]
PIX6 off guardband. Number of pixel periods before start of SH pulse that PIX6 stops.
5
0 1100
PIX7/SH On Guardbands
0000 1111
[7:0]
PIX7 on guardband. Number of pixel periods from end of SH pulse to start of PIX7.
5
0 1101
PIX7/SH Off Guardbands
0000 0111
[7:0]
PIX7 off guardband. Number of pixel periods before start of SH pulse that PIX7 stops.
5
0 1110
PIX8/SH On Guardbands
0000 1111
[7:0]
PIX8 on guardband. Number of pixel periods from end of SH pulse to start of PIX8.
5
0 1111
PIX8/SH Off Guardbands
0000 0111
[7:0]
PIX8 off guardband. Number of pixel periods before start of SH pulse that PIX8 stops.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Typical Application
Serial Interface and device
Flexible CCD Timing Gener
control bus
ator Outputs
+3.3V
CLK3
CLK2
CLK1
SH
CCD Clock
Driver(s)
1
2
3
4
CLK3
CLK2
CLK1
SH
5
6
7
8
9
RESET
SH_R
SDIO
SCLK
SEN
LM98714
0.1uF
0.1uF
10
11
12
13
14
15
16
17
0.1uF
Image
Sensor
Clock
Inputs
0.1uF
0.1uF
AGND
VA
VREFB
VREFT
VA
AGND
VCLP
VA
0.1uF
CLK4
VC
DGND
CLK5
CLK6
CLK7
CLK8
CLK9
CLKOUT_CLK10
48
47
46
45
44
43
42
41
40
VD
DGND
39
38
D0_TXOUT0D1_TXOUT0+
D2_TXOUT1D3_TXOUT1+
D4_TXOUT2D5_TXOUT2+
D6_TXCLKD7_TXCLK+
37
36
35
34
33
32
31
30
INCLKINCLK+
29
28
DVB
VR
DGND
27
26
25
CLK4
0.1uF
+3.3V
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
Ribbon
Cable
+3.3V
(2)
TXOUT0TXOUT0+
0.1uF
TXOUT1TXOUT1+
TXOUT2TXOUT2+
TXCLKTXCLK+
+3.3V
18
19
20
21
22
23
24
Connector
Connector
4.7uF
LVDS
Deserial izer
(DS90CR218A
or equiv.)
ASIC
(1)R_cmos_clk
AGND
OSr
AGND
OSg
AGND
OSb
AGND
(1)
0 Ohm
R_lvds_clk
100 Ohm
0.1uF
(2)
INCLKINCLK+
+3.3V
0.1uF
CLOCK Gen
CCD or CIS
Image Sensor
Copyright © 2017, Texas Instruments Incorporated
(1)
If using an LVDS input clock, terminate the clock at the pins with a 100-Ω resistor and remove the 0-Ω resistor from
INCLK- to ground.
If using a CMOS input clock, short the INCLK- pin to ground and remove the 100-Ω LVDS termination resistor.
(2)
Maintain 100-Ω impedance for all LVDS differential pair paths.
Figure 61. Typical Application Diagram
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9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Device Support
9.1.1.1 Development Support
For development support see the LM98714 IBIS Model.
9.1.2 Related Documentation
For related documentation see the following:
AN-1538 Interfacing Texas Instruments DS90CR218A and LM98714
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
9.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
9.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
88
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Product Folder Links: LM98714
PACKAGE OPTION ADDENDUM
www.ti.com
27-Nov-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM98714BCMT/NOPB
ACTIVE
TSSOP
DGG
48
38
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
0 to 70
LM98714
BCMT
LM98714BCMTX/NOPB
ACTIVE
TSSOP
DGG
48
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
0 to 70
LM98714
BCMT
LM98714CCMT/NOPB
ACTIVE
TSSOP
DGG
48
38
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
0 to 70
LM98714
CCMT
LM98714CCMTX/NOPB
ACTIVE
TSSOP
DGG
48
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
0 to 70
LM98714
CCMT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Nov-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM98714BCMTX/NOPB
TSSOP
DGG
48
1000
330.0
24.4
8.6
13.2
1.6
12.0
24.0
Q1
LM98714CCMTX/NOPB
TSSOP
DGG
48
1000
330.0
24.4
8.6
13.2
1.6
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM98714BCMTX/NOPB
TSSOP
DGG
48
1000
367.0
367.0
45.0
LM98714CCMTX/NOPB
TSSOP
DGG
48
1000
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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