Texas Instruments | DACx551-Q1 Automotive 16-, 12-Bit, Ultralow-Glitch, Voltage-Output DAC (Rev. C) | Datasheet | Texas Instruments DACx551-Q1 Automotive 16-, 12-Bit, Ultralow-Glitch, Voltage-Output DAC (Rev. C) Datasheet

Texas Instruments DACx551-Q1 Automotive 16-, 12-Bit, Ultralow-Glitch, Voltage-Output DAC (Rev. C) Datasheet
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DAC8551-Q1, DAC6551-Q1
SLASEB8C – FEBRUARY 2016 – REVISED NOVEMBER 2016
DACx551-Q1 Automotive 16-, 12-Bit, Ultralow-Glitch, Voltage-Output DAC
1 Features
3 Description
•
•
The DAC8551-Q1 and DAC6551-Q1 are small, lowpower, voltage-output, 16- and 12-bit digital-to-analog
converters
(DACs)
qualified
for
automotive
applications. The DACx551-Q1 devices provide good
linearity and minimize undesired code-to-code
transient voltages. The devices use a versatile 3-wire
serial interface that operates at clock rates to 30 MHz
and is compatible with standard SPI, QSPI,
Microwire, and digital signal-processor (DSP)
interfaces.
1
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
Relative Accuracy:
– DAC8551-Q1 (16-Bit): 4 LSB INL
– DAC6551-Q1 (12-Bit): 0.3 LSB INL
Ultralow Glitch Impulse: 0.1 nV-s
Settling Time: 8 μs to ±0.003% FSR
Power Supply: 3 V to 5.5 V
Power-On Reset to Zero Scale
MicroPower Operation: 160 μA at 5 V
Low-Power Serial Interface With SchmittTriggered Inputs
On-Chip Output Buffer Amplifier With Rail-to-Rail
Operation
Power-Down Capability
Binary Input
SYNC Interrupt Facility
Available in a Tiny VSSOP-8 Package
The DACx551-Q1 devices power consumption is only
800 µW at 5 V, reducing to less than 4 μW in powerdown mode. The DACx551-Q1 devices are available
in a VSSOP-8 package.
Device Information(1)
PART NUMBER
DAC8551-Q1
DAC6551-Q1
PACKAGE
VSSOP (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
The DACx551-Q1 devices require an external
reference voltage to set the output range. The
devices incorporate a power-on-reset circuit that
ensures the DAC output powers up at 0 V and
remains there until a valid write to the device takes
place. The devices contain a power-down feature,
accessed over the serial interface, that reduces the
current consumption to 800 nA at 5 V.
Automotive Radar
Automotive Sensors
Functional Block Diagram
VREF
VFB
Ref (+)
DAC
VOUT
VDD
DAC Register
GND
SYNC
SCLK
Shift Register
PWD Control
Resistor
Network
DIN
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC8551-Q1, DAC6551-Q1
SLASEB8C – FEBRUARY 2016 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
5
5
5
5
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements...............................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 15
7.5 Programming .......................................................... 16
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Applications ................................................ 17
8.3 System Examples .................................................. 20
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Revision B (November 2016) to Revision C
Page
•
Added device DAC6551-Q1 to the data sheet ....................................................................................................................... 1
•
Changed the data sheet Title From: DAC8551-Q1 Automotive 16-Bit... To: DACx551-Q1 Automotive 16-, 12-Bit... ........... 1
•
Changed Relative Accuracy in the Features section ............................................................................................................. 1
•
Updated the Description to include the DAC6551-Q1 device ............................................................................................... 1
•
Added DAC6551-Q1 to the Thermal Table ........................................................................................................................... 5
•
Added separate lines for the DAC6551-Q1 and DAC8551-Q1 devices for Resolution, Relative accuracy, and
Differential nonlinearity in the Electrical Characteristics table................................................................................................ 5
•
Changed Note 1 of the Electrical Characteristics table .......................................................................................................... 6
•
Updated the Overview section to include the DAC6551-Q1 device .................................................................................... 13
•
Changed Equation 1............................................................................................................................................................. 13
•
Changed the definitions of in the "where:" statement for Equation 1 ................................................................................... 14
•
Deleted a sentence from the Resistor String section: "Monotonicity is ennsured because of the string resistor
archietecture."....................................................................................................................................................................... 14
•
Added Figure 31 .................................................................................................................................................................. 16
•
Updated the Application Information section to include the DAC6551-Q1 device .............................................................. 17
•
Updated the Using the REF02 As a Power Supply for the DACx551-Q1 Device section to include the DAC6551-Q1
device .................................................................................................................................................................................. 19
•
Updated the System Examples section to include the DAC6551-Q1 device ...................................................................... 20
•
Updated the Power Supply Recommendations section to include the DAC6551-Q1 device ............................................. 21
•
Updated the Layout Guidelines section to include the DAC6551-Q1 device ...................................................................... 21
2
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SLASEB8C – FEBRUARY 2016 – REVISED NOVEMBER 2016
Changes from Revision A (March 2016) to Revision B
Page
•
Changed Relative Accuracy in the Features section ............................................................................................................. 1
•
Changed power supply voltage in the Features section ....................................................................................................... 1
•
Changed voltage for VDD in the Pin Functions table ............................................................................................................. 4
•
Changed supply voltage in the Recommended Operating Conditions table ......................................................................... 5
•
Changed values in the Thermal Information table.................................................................................................................. 5
•
Changed supply voltage in the conditions statement of the Electrical Characteristics table ................................................ 5
•
Removed two rows and all test conditions in the LOGIC INPUTS section of the Electrical Characteristics table................. 6
•
Changed supply voltage in the POWER REQUIREMENTS section of the Electrical Characteristics table ......................... 6
•
Changed test conditions for supply current in the POWER REQUIREMENTS section of the Electrical Characteristics
table ....................................................................................................................................................................................... 6
•
Changed VDD in the condition statement and test conditions of the Timing Requirements (1) (2) section ................................ 7
•
Changed MIN value for SCLK low time in the Timing Requirements (1) (2) section ................................................................ 7
•
Added text in the Application Information section ................................................................................................................ 17
•
Changed supply voltage in the Power Supply Recommendations section .......................................................................... 21
•
Added new Receiving Notification of Documentation Updates section................................................................................ 22
Changes from Original (February 2016) to Revision A
•
Page
Changed data sheet from PRODUCT PREVIEW to PRODUCTON DATA .......................................................................... 1
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DAC8551-Q1, DAC6551-Q1
SLASEB8C – FEBRUARY 2016 – REVISED NOVEMBER 2016
www.ti.com
5 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
V
V
DD
REF
V
V
FB
OUT
1
8
GND
2
7
D
3
6
SCLK
4
5
SYNC
IN
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock
input. Schmitt-trigger logic input.
DIN
7
I
GND
8
GND
SCLK
6
I
Serial clock input. Data can be transferred at rates up to 30 MHz. Schmitt-trigger logic input.
Level-triggered control input (active-low). This is the frame synchronization signal for the input data. SYNC
going low enables the input shift register, and data is transferred in on the falling edges of the following
clocks. The DAC is updated following the 24th clock (unless SYNC is taken high before this edge, in which
case the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the device).
Schmitt-trigger logic input.
Ground reference point for all circuitry on the device
SYNC
5
I
VDD
1
PWR
VFB
3
I
Feedback connection for the output amplifier. For voltage output operation, tie to VOUT externally.
VOUT
4
O
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
VREF
2
I
Reference voltage input
Power supply input, 3 V to 5.5 V
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
–0.3
6
V
–0.3
VDD + 0.3
V
VOUT to GND
–0.3
VDD + 0.3
V
VREF to GND
–0.3
VDD + 0.3
V
VFB to GND
–0.3
VDD + 0.3
V
Junction temperature range, TJ max
–65
150
°C
Storage temperature, Tstg
–65
150
°C
VDD to GND
Digital input voltage to GND
(1)
4
DIN, SCLK and SYNC
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SLASEB8C – FEBRUARY 2016 – REVISED NOVEMBER 2016
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
All pins
±500
Corner pins (1, 4, 5, and 8)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
Supply voltage
VDD to GND
3
5.5
V
DIN, SCLK and SYNC
0
VDD
V
0
VDD
V
DIGITAL INPUTS
Digital input voltage
REFERENCE INPUT
VREF Reference input voltage
AMPLIFIER FEEDBACK INPUT
VFB
Output amplifier feedback input
VOUT
V
TEMPERATURE RANGE
TA
Operating ambient temperature
–40
125
°C
6.4 Thermal Information
DAC8551-Q1
DAC6551-Q1
THERMAL METRIC (1)
UNIT
DGK (VSSOP)
8 PINS
RθJA
Junction-to-ambient thermal resistance
173.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
65.4
°C/W
RθJB
Junction-to-board thermal resistance
94.2
°C/W
ψJT
Junction-to-top characterization parameter
10.2
°C/W
ψJB
Junction-to-board characterization parameter
92.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
VDD = 3 V to 5.5 V, VREF = VDD and TA = –40°C to 125°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE (1)
Resolution
Relative accuracy
Differential nonlinearity
DAC8551-Q1
16
DAC6551-Q1
12
DAC8551-Q1
±4
±16
DAC6551-Q1
±0.3
±1
DAC8551-Q1
±0.35
±2
DAC6551-Q1
±0.02
±1
Offset error
LSB
LSB
±1
±15
mV
Full-scale error
±0.05
±0.5
% of FSR
Gain error
±0.02
±0.2
% of FSR
Offset error drift
Gain temperature coefficient
(1)
Bits
±5
μV/°C
±1
ppm of
FSR/°C
Linearity calculated using a reduced code range of 485 to 64,741 (16-bit); 30 to 4,046 (12-bit); output unloaded.
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Electrical Characteristics (continued)
VDD = 3 V to 5.5 V, VREF = VDD and TA = –40°C to 125°C, unless otherwise noted.
PARAMETER
PSRR
Power-supply rejection ratio
TEST CONDITIONS
MIN
RL = 2 kΩ, CL = 200 pF
TYP
MAX
0.75
UNIT
mV/V
OUTPUT CHARACTERISTICS (2)
Output voltage range
Output voltage settling time
0
To ±0.003% FSR, 0200h to FD00h
RL = 2 kΩ, 0 pF < CL < 200 pF
8
Slew rate
Capacitive load stability
VREF
RL = ∞
RL = 2 kΩ
V
μs
1.4
V/μs
470
pF
1000
pF
Code change glitch impulse
1 LSB change around major carry
0.1
nV-s
Digital feedthrough
50 kΩ series resistance on digital lines
0.1
nV-s
DC output impedance
At mid-code input
1
Ω
Short-circuit current
VDD = 3 V to 5.5 V
35
mA
AC PERFORMANCE
SNR
Signal-to-noise ratio
THD
Total harmonic distortion
SFDR
Spurious-free dynamic range
SINAD
Signal to noise and distortion
BW = 20 kHz, VDD = 5 V, VREF = 4.5 V, fOUT = 1 kHz
First 19 harmonics removed for SNR calculation
84
dB
–80
dB
84
dB
76
dB
REFERENCE INPUT
Reference current
VREF = VDD = 5.5 V
50
VREF = VDD = 3.6 V
25
Reference input range
0
Reference input impedance
μA
VDD
125
V
kΩ
LOGIC INPUTS (2)
Input current
VINL
Input low voltage
VINH
Input high voltage
±1
μA
0.3×VDD
0.7×VDD
Pin capacitance
V
V
3
pF
POWER REQUIREMENTS
VDD
IDD
Supply voltage
Supply current
3
5.5
Normal mode, midscale code, no load, does not include
reference current. VIH = VDD and VIL = GND,
VDD = 3.6 V to 5.5 V
160
250
Normal mode, midscale code, no load, does not include
reference current. VIH = VDD and VIL = GND,
VDD = 3 V to 3.6 V
110
240
All power-down modes, VIH = VDD and VIL = GND,
VDD = 3.6 V to 5.5 V
0.8
3
All power-down modes, VIH = VDD and VIL = GND,
VDD = 3 V to 3.6 V
0.5
3
V
μA
POWER EFFICIENCY
IOUT / IDD
ILOAD = 2 mA, VDD = 5 V
89%
TEMPERATURE RANGE
TA
(2)
6
Ambient temperature
–40
125
°C
Specified by design and characterization; not production tested.
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6.6
SLASEB8C – FEBRUARY 2016 – REVISED NOVEMBER 2016
Timing Requirements (1) (2)
VDD = 3 V to 5.5 V and TA = –40°C to 125°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
fSCLK Serial clock frequency
t1
SCLK cycle time
t2
SCLK high time
t3
SCLK low time
t4
SYNC to SCLK rising edge setup time
t5
Data setup time
t6
Data hold time
t7
24th SCLK falling edge to SYNC rising edge
t8
Minimum SYNC high time
t9
24th SCLK falling edge to SYNC falling edge
(1)
(2)
MIN
NOM
MAX
VDD = 3 V to 3.6 V
25
VDD = 3.6 V to 5.5 V
30
VDD = 3 V to 3.6 V
40
VDD = 3.6 V to 5.5 V
34
VDD = 3 V to 3.6 V
13
VDD = 3.6 V to 5.5 V
13
VDD = 3 V to 3.6 V
13
VDD = 3.6 V to 5.5 V
13
VDD = 3 V to 3.6 V
0
VDD = 3.6 V to 5.5 V
0
VDD = 3 V to 3.6 V
5
VDD = 3.6 V to 5.5 V
5
VDD = 3 V to 3.6 V
5
VDD = 3.6 V to 5.5 V
5
VDD = 3 V to 3.6 V
0
VDD = 3.6 V to 5.5 V
0
VDD = 3 V to 3.6 V
50
VDD = 3.6 V to 5.5 V
34
VDD = 3 V to 5.5 V
50
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH) / 2.
See the Serial-Write-Operation Timing Diagram.
6.7 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Power-up time
TYP
2.5
Coming out of power-down mode,
VDD = 3.3 V
5
MAX
UNIT
µs
t9
t1
SCLK
MIN
Coming out of power-down mode,
VDD = 5 V
1
24
t8
t3
t4
t2
t7
SYNC
t6
t5
DIN
DB23
DB0
DB23
Figure 1. Serial-Write-Operation Timing Diagram
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6.8 Typical Characteristics
At TA = 25°C, VDD = 5 V unless otherwise noted.
1.0
1.0
0.5
0.5
0
-0.5
-1.0
8192
16384 24576 32768 40960 49152
Digital Input Code
0
-0.5
57344 65536
Figure 2. Linearity Error and Differential Linearity Error vs
Digital Input Code (–40°C)
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
Figure 3. Linearity Error and Differential Linearity Error vs
Digital Input Code (25°C)
10
6
4
2
0
-2
-4
-6
VDD = 5 V
VREF = 4.99 V
VDD = 5V, VREF = 4.99V
5
Error (mV)
LE (LSB)
VDD = 5V, VREF = 4.99V
-1.0
0
1.0
DLE (LSB)
6
4
2
0
-2
-4
-6
LE (LSB)
VDD = 5V, VREF = 4.99V
DLE (LSB)
DLE (LSB)
LE (LSB)
6
4
2
0
-2
-4
-6
0
0.5
0
-0.5
-5
-1.0
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
-50
0
-25
25
50
100
75
125
Temperature (°C)
Figure 4. Linearity Error and Differential Linearity Error vs
Digital Input Code (125°C)
Figure 5. Offset Error vs Temperature
0
6
VDD = 5 V
VREF = 4.99 V
5
DAC Loaded with FFFFh
VOUT (mV)
Error (mV)
4
-5
3
VDD = 5.5V
VREF = VDD - 10mV
2
1
DAC Loaded with 0000h
0
-10
-50
8
-25
0
25
50
75
100
125
0
2
4
6
8
Temperature (°C)
I(SOURCE/SINK) (mA)
Figure 6. Full-Scale Error vs Temperature
Figure 7. Source and Sink Current Capability
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Typical Characteristics (continued)
At TA = 25°C, VDD = 5 V unless otherwise noted.
250
300
VREF = VDD = 5 V
VDD = VREF = 5V
250
200
IDD (mA)
IDD (mA)
200
Reference Current Included
150
150
100
100
50
50
0
0
0
8192 16384 24576 32768 40960 49152 57344 65536
-50
0
25
50
75
100
125
Temperature (°C)
Figure 8. Supply Current vs Digital Input Code
Figure 9. Power-Supply Current vs Temperature
300
1
VREF = VDD
Reference Current Included, No Load
280
VREF = VDD
Power-Down Current (PA)
260
240
IDD (mA)
-25
Digital Input Code
220
200
180
160
140
120
0.8
0.6
0.4
0.2
100
3
3.5
4
4.5
5
5.5
0
3
VDD (V)
3.5
4
4.5
5
VDD (V)
Figure 10. Supply Current vs Supply Voltage
5.5
D010
Figure 11. Power-Down Current vs Supply Voltage
1800
TA = 25°C, SCL Input (all other inputs = GND)
VDD = VREF = 5.5V
1600
Trigger Pulse 5V/div
1400
IDD (mA)
1200
1000
VDD = 5V
VREF = 4.096V
From Code: D000
To Code: FFFF
800
600
400
Rising Edge
1V/div
200
Zoomed Rising Edge
1mV/div
0
0
1
2
3
4
VLOGIC (V)
Time (2ms/div)
5
Figure 13. Full-Scale Settling Time: 5-V Rising Edge
Figure 12. Supply Current vs Logic Input Voltage
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Typical Characteristics (continued)
At TA = 25°C, VDD = 5 V unless otherwise noted.
Trigger Pulse 5V/div
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: FFFF
To Code: 0000
Falling
Edge
1V/div
Rising
Edge
1V/div
Zoomed Falling Edge
1mV/div
VDD = 5V
VREF = 4.096V
From Code: 4000
To Code: CFFF
Zoomed Rising Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 14. Full-Scale Settling Time: 5-V Falling Edge
Figure 15. Half-Scale Settling Time: 5-V Rising Edge
VDD = 5V
VREF = 4.096V
From Code: CFFF
To Code: 4000
Falling
Edge
1V/div
VOUT (500mV/div)
Trigger Pulse 5V/div
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Time (400ns/div)
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
Figure 17. Glitch Impulse: 5 V, 1-LSB Step, Rising Edge
VOUT (500mV/div)
VOUT (500mV/div)
Figure 16. Half-Scale Settling Time: 5-V Falling Edge
Time (400ns/div)
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
Time (400ns/div)
Figure 18. Glitch Impulse: 5 V, 1-LSB Step, Falling Edge
10
VDD = 5V
VREF = 4.096V
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
Figure 19. Glitch Impulse: 5 V, 16-LSB Step, Rising Edge
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Typical Characteristics (continued)
At TA = 25°C, VDD = 5 V unless otherwise noted.
VOUT (5mV/div)
VOUT (500mV/div)
VDD = 5V
VREF = 4.096V
From Code: 8010
To Code: 8000
Glitch: 0.08nV-s
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 20. Glitch Impulse: 5 V, 16-LSB Step, Falling Edge
Figure 21. Glitch Impulse: 5 V, 256-LSB Step, Rising Edge
-40
VDD = 5V
VREF = 4.9V
-1dB FSR Digital Input
fS = 1MSPS
Measurement Bandwidth = 20kHz
-50
-60
THD (dB)
VOUT (5mV/div)
VDD = 5V
VREF = 4.096V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
-70
THD
-80
-90
2nd Harmonic
3rd Harmonic
-100
Time (400ns/div)
0
1
2
3
4
5
fOUT (kHz)
Figure 22. Glitch Impulse: 5 V, 256-LSB Step, Falling Edge
Figure 23. Total Harmonic Distortion vs Output Frequency
98
VREF = VDD = 5V
-1dB FSR Digital Input
fS = 1MSPS
Measurement Bandwidth = 20kHz
96
-30
CLK
Gain (dB)
SNR (dB)
94
VDD = 5V
VREF = 4.096V
fOUT = 1kHz
f
= 1MSPS
-10
92
90
-50
-70
88
-90
86
-110
84
-130
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.5
0
5
10
15
20
Frequency (kHz)
fOUT (kHz)
Figure 24. Signal-to-Noise Ratio vs Output Frequency
Figure 25. Power Spectral Density
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Typical Characteristics (continued)
At TA = 25°C, VDD = 5 V unless otherwise noted.
350
VDD = 5V
VREF = 4.99V
Code = 7FFFh
No Load
Voltage Noise (nV/ÖHz)
300
250
200
150
100
100
1k
10k
100k
Frequency (Hz)
Figure 26. Output Noise Density
12
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7 Detailed Description
7.1 Overview
The DAC8551-Q1 and DAC6551-Q1 are
converters (DACs) qualified for automotive
minimize undesired code-to-code transient
operates at clock rates to 30 MHz and is
processor (DSP) interfaces.
small, low-power, voltage-output, 16- and 12-bit digital-to-analog
applications. The DACx551-Q1 devices provide good linearity and
voltages. The devices use a versatile 3-wire serial interface that
compatible with standard SPI, QSPI, Microwire, and digital signal
The DACx551-Q1 devices require an external reference voltage to set the output range. The devices incorporate
a power-on-reset circuit that ensures the DAC output powers up at 0 V and remains there until a valid write to the
device takes place. The devices contain a power-down feature, accessed over the serial interface, that reduces
the current consumption to 800 nA at 5 V.
The DACx551-Q1 devices power consumption is only 800 µW at 5 V, reducing to less than 4 μW in power-down
mode. The DACx551-Q1 devices are available in a VSSOP-8 package.
7.2 Functional Block Diagram
VREF
VFB
Ref (+)
DAC
VOUT
VDD
DAC Register
GND
SYNC
Shift Register
SCLK
Resistor
Network
PWD Control
DIN
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7.3 Feature Description
7.3.1 DAC Section
The DACx551-Q1 architecture consists of a string DAC followed by an output buffer amplifier. Figure 27 shows a
block diagram of the DAC architecture.
VREF
50kW
50kW
VFB
62kW
DAC
Register
REF (+)
Register String
REF (-)
VOUT
GND
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Figure 27. DACx551-Q1 Architecture
The input coding to the DACx551-Q1 is straight binary, so the ideal output voltage is given by:
D
VOUT = nIN
´ VREF
2 -1
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Feature Description (continued)
where:
• n = resolution in bits; 12 (DAC6551-Q1) or 16 (DAC8551-Q1)
• DIN = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 2n-1.
7.3.1.1 Resistor String
The resistor string section is shown in Figure 28. It is simply a string of resistors, each of value R. The code
loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the
output amplifier by closing one of the switches connecting the string to the amplifier.
VREF
RDIVIDER
VREF
2
R
R
To Output Amplifier
(2x Gain)
R
R
Figure 28. Resistor String
7.3.1.2 Output Amplifier
The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of
0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink
capabilities of the output amplifier can be seen in the Typical Characteristics. The slew rate is 1.4 V/μs with a fullscale setting time of 8 μs with the output unloaded.
The inverting input of the output amplifier is brought out to the VFB pin. This configuration allows for better
accuracy in critical applications by tying the VFB point and the amplifier output together directly at the load. Other
signal conditioning circuitry may also be connected between these points for specific applications.
7.3.2 Power-On Reset
The DACx551-Q1 contains a power-on-reset circuit that controls the output voltage during power up. On power
up, the DAC registers are filled with zeros and the output voltages are 0 V; they remain that way until a valid
write sequence is made to the DAC. The power-on reset is useful in applications where it is important to know
the state of the output of the DAC while it is in the process of powering up.
14
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7.4 Device Functional Modes
7.4.1 Power-Down Modes
The DACx551-Q1 supports four separate modes of operation. These modes are programmable by setting two
bits (PD1 and PD0) in the control register. Table 1 shows how the state of the bits corresponds to the mode of
operation of the device.
Table 1. Operating Modes
PD1 (DB17)
PD0 (DB16)
0
0
Normal operation
OPERATING MODE
—
—
Power-down modes
0
1
Output typically 1 kΩ to GND
1
0
Output typically 100 kΩ to GND
1
1
High-Z
When both bits are set to 0, the device works normally with its typical current consumption of 160 μA at 5 V.
However, for the three power-down modes, the supply current falls to 800 nA at 5 V. Not only does the supply
current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of
known values. This configuration has the advantage that the output impedance of the device is known while it is
in power-down mode. There are three different options. The output is connected internally to GND through a
1‑kΩ resistor, a 100-kΩ resistor, or it is left open-circuited (High-Z). The output stage is illustrated in Figure 29.
VFB
Resistor
String
DAC
Amplifier
Power-Down
Circuitry
VOUT
Resistor
Network
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Figure 29. Output Stage During Power Down
All analog circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power down. The time to exit power-down is typically 2.5 μs for VDD = 5 V, and
5 μs for VDD = 3 V. See the Typical Characteristics for more information.
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7.5 Programming
The DAC8551-Q1 and DAC6551-Q1 devices have a 3-wire serial interface (SYNC, SCLK, and DIN), which is
compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See the Serial Write
Operation Timing Diagram section for an example of a typical write sequence.
The input shift register is 24 bits wide, as shown in Figure 30 and Figure 31. The first six bits are don't care bits.
The next two bits (PD1 and PD0) are control bits that control which mode of operation the part is in (normal
mode or any one of three power-down modes). A more complete description of the various modes is located in
the Power-Down Modes section. The next 16 bits are the left aligned data bits. These bits are transferred to the
DAC register on the 24th falling edge of SCLK.
DB23
X X
X
X
X
X
PD1
PD0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
DB0
D0
D1
D0
0
0
0
DB0
0
Figure 30. DAC8551-Q1 Data-Input Register Format
DB23
X X
X
X
X
X
PD1
PD0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
Figure 31. DAC6551-Q1 Data-Input Register Format
The write sequence begins by bringing the SYNC line low. Data from the DIN line are clocked into the 24-bit shift
register on each falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the devices
compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is clocked in and
the programmed function is executed (that is, a change in DAC register contents and/or a change in the mode of
operation).
At this point, the SYNC line may be kept low or brought high. In either case, it must be brought high for a
minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write
sequence. As previously mentioned, it must be brought high again just before the next write sequence.
7.5.1
SYNC Interrupt
In a normal write sequence, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is
updated on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, it acts as an
interrupt to the write sequence. The shift register is reset, and the write sequence is seen as invalid. Neither an
update of the DAC register contents nor a change in the operating mode occurs, as shown in Figure 32.
24th Falling Edge
24th Falling Edge
CLK
SYNC
DIN
DB23
DB80
DB23
DB80
Valid Write Sequence: Output Updates
on the 24th Falling Edge
Figure 32. SYNC Interrupt Facility
16
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DAC8551-Q1 and DAC6551-Q1 devices are AEC-Q100 qualified, low-power, ultralow-glitch, 16-bit and 12bit DACs, respectively. The wide temperature range, low-power consumption and very low glitch of the devices
make them a great choice for automotive applications such as radar and sensor conditioning.
8.2 Typical Applications
8.2.1
Loop-Powered 2-Wire 4-mA to 20-mA Transmitter With XTR116
VREG
C2 || C3
0.1001 µF
Vref
U1
V+
R1
102.4 kΩ
Vref
DAC8551
VOUT
C1
2.2 µF
R2
49.9 W
XTR116
V+
V+
Regulator
Reference
V+
IIN
+
B
U2
R3
25.6 kΩ
Q1
Q1
RLIM
IRET
2475 Ω
E
25 Ω
IO
Return
Copyright © 2016, Texas Instruments Incorporated
Figure 33. Loop-Powered Transmitter
8.2.1.1 Design Requirements
This design is commonly referred to as a loop-powered, or 2-wire, 4 mA to 20 mA transmitter. The transmitter
has only two external input terminals: a supply connection and an output, or return, connection. The transmitter
communicates back to its host, typically a PLC analog input module, by precisely controlling the magnitude of its
return current. In order to conform to the 4 mA to 20 mA communication standard, the complete transmitter must
consume less than 4 mA of current. The DAC8551-Q1 device enables the accurate control of the loop current
from 4 mA to 20 mA in 16-bit steps.
8.2.1.2 Detailed Design Procedure
Although it is possible to recreate the loop-powered circuit using discrete components, the XTR116 provides
simplicity and improved performance due to the matched internal resistors. The output current can be modified if
necessary by looking using Equation 2.
æ V ´ Code VREG
+
I OUT (Code) = ç refN
ç 2 ´ R3
R1
è
ö æ
ö
÷ ´ ç 1 + 2475 W ÷
÷ è
25 W ø
ø
(2)
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Typical Applications (continued)
For more details of this application, see 2-wire, 4-20mA Transmitter, EMC/EMI Tested Reference Design
(TIDUAO7). It covers in detail the design of this circuit as well as how to protect it from EMC/EMI tests.
8.2.1.3
Application Curves
Total unadjusted error (TUE) is a good estimate for the performance of the output as shown in Figure 34. The
linearity of the output or INL is in Figure 35.
10
0.1
Integral Nonlinearity (LSBs)
Total Unadjusted Error (%FSR)
8
0.05
0
-0.05
6
4
2
0
-2
-4
-6
-8
-10
-0.1
0
10k
20k
30k
40k
Code
50k
0
60k 65535
10k
20k
D001
Figure 34. Total Unadjusted Error
30k
40k
Code
50k
60k 65535
D002
Figure 35. Integral Nonlineareity
8.2.2 Bipolar Operation Using the DAC8551-Q1 Device
The DAC8551-Q1 device has been designed for single-supply operation, but a bipolar output range is also
possible using the circuit in Figure 36. The circuit shown gives an output voltage range of ±VREF. Rail-to-rail
operation at the amplifier output is achievable using an OPA703 as the output amplifier.
VREF
6V
R1
10 kW
R2
10 kW
OPA703
DAC8551-Q1
VREF
10 mF
5V
VFB
VOUT
–6 V
0.1 mF
Three-Wire
Serial Interface
Figure 36. Bipolar Output Range
The output voltage for any input code can be calculated as follows:
é
æ R 2 öù
æ D ö æ R1 + R 2 ö
VO = ê VREF ´ ç
´ç
÷ - VREF ´ ç
÷ú
÷
è 65536 ø è R 1 ø
è R 1 ø ûú
ëê
(3)
where D represents the input code in decimal (0–65,535)
with VREF = 5V, R1 = R2 = 10 kΩ.
æ 10 ´ D ö
VO = ç
÷-5 V
è 65536 ø
18
(4)
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Using this example, an output voltage range of ±5 V with 0000h corresponding to a –5 V output and FFFFh
corresponding to a 5 V output can be achieved. Similarly, using VREF = 2.5 V, a ±2.5 V output voltage range can
be achieved.
8.2.3 Using the REF02 As a Power Supply for the DACx551-Q1
Due to the extremely low supply current required by the DACx551-Q1, an alternative option is to use a precision
reference such as the REF02 device to supply the required voltage to the device, as illustrated in Figure 37.
15 V
5V
REF02
285 mA
SYNC
Three-Wire
Serial
Interface
SCLK
DACx551-Q1
VOUT = 0 V to 5 V
DIN
Figure 37. REF02 As a Power Supply to the DACx551-Q1
This configuration is especially useful if the power supply is quite noisy or if the system supply voltages are at
some value other than 5 V. The REF02 device outputs a steady supply voltage for the device. If the REF02
device is used, the current it must supply to the device is 200 μA. This configuration is with no load on the output
of the DAC. When a DAC output is loaded, the REF02 also must supply the current to the load.
The total current required (with a 5 kΩ load on the DAC output) is:
200mA ) 5V + 1.2mA
5kW
(5)
The load regulation of the REF02 is typically 0.005%/mA, resulting in an error of 299 μV for the 1.2 mA current
drawn from it. This value corresponds to a 3.9 LSB error.
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8.3 System Examples
8.3.1 Interface From the DACx551-Q1 to 8051
See Figure 38 for a serial interface between the DACx551-Q1 and a typical 8051-type microcontroller. The setup
for the interface is as follows: TXD of the 8051 drives SCLK of the DACx551-Q1, whereas RXD drives the serial
data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this
case, port line P3.3 is used. When data are to be transmitted to the DACx551-Q1, P3.3 is taken low. The 8051
transmits data in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left low after the first eight bits are transmitted, then a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken high following the completion of the third write cycle. The 8051 outputs the
serial data in a format that has the LSB first. The DACx551-Q1 requires data with the MSB as the first bit
received. Therefore, the 8051 transmit routine must take this into account, and mirror the data as needed.
80C51 or 80L51(1)
DACx551-Q1(1)
P3.3
SYNC
TXD
SCLK
RXD
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 38. Interface From the DACx551-Q1 to 80C51 or 80L51
8.3.2 Interface From the DACx551-Q1 to Microwire
Figure 39 shows an interface between the DACx551-Q1 and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and is clocked into the DACx551-Q1 on the rising edge of the
SK signal.
MicrowireTM
DACx551-Q1(1)
CS
SYNC
SK
SCLK
SO
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 39. Interface From the DACx551-Q1 to Microwire
8.3.3
Interface From the DACx551-Q1 to 68HC11
Figure 40 shows a serial interface between the DACx551-Q1 and the 68HC11 microcontroller. SCK of the
68HC11 drives SCLK of the DACx551-Q1, whereas the MOSI output drives the serial data line of the DAC. The
SYNC signal is derived from a port line (PC7), similar to the 8051 diagram.
68HC11(1)
DACx551-Q1(1)
PC7
SYNC
SCK
SCLK
MOSI
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 40. Interface From the DACx551-Q1 to 68HC11
The 68HC11 should be configured so that its CPOL bit is 0 and its CPHA bit is 1. This configuration causes data
appearing on the MOSI output to be valid on the falling edge of SCK. When data are being transmitted to the
DAC, the SYNC line is held low (PC7). Serial data from the 68HC11 are transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. (Data are transmitted MSB first.) In order to load data to the
DACx551-Q1, PC7 is left low after the first eight bits are transferred, then a second and third serial write
operation are performed to the DAC. PC7 is taken high at the end of this procedure.
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9 Power Supply Recommendations
The DACx551-Q1 can operate within the specified supply voltage range of 3 V to 5.5 V. The power applied to
VDD should be well-regulated and low-noise. Switching power supplies and dc/dc converters often have highfrequency glitches or spikes riding on the output voltage. In addition, digital components can create similar highfrequency spikes. This noise can easily couple into the DAC output voltage through various paths between the
power connections and analog output. In order to further minimize noise from the power supply, a strong
recommendation is to include a 1-μF to 10-μF capacitor and 0.1-μF bypass capacitor. The current consumption
on the VDD pin, the short-circuit current limit, and the load current for the device is listed in the Electrical
Characteristics table. The power supply must meet the aforementioned current requirements.
10 Layout
10.1 Layout Guidelines
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies.
The DACx551-Q1 offers single-supply operation, and is often used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and
the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output.
Due to the single ground pin of the DACx551-Q1, all return currents, including digital and analog return currents
for the DAC, must flow through a single point. Ideally, GND would be connected directly to an analog ground
plane. This plane would be separate from the ground connection for the digital components until they were
connected at the power-entry point of the system.
As with the GND connection, VDD should be connected to a power-supply plane or trace that is separate from the
connection for digital logic until they are connected at the power-entry point. In addition, a 1 μF to 10 μF
capacitor and 0.1 μF bypass capacitor are strongly recommended. In some situations, additional bypassing may
be required, such as a 100 μF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all
designed to essentially low-pass filter the 5 V supply, removing the high-frequency noise.
10.2 Layout Example
1
2
3
4
8
7
6
5
Figure 41. Layout Diagram
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
2-wire, 4-20mA Transmitter, EMC/EMI Tested Reference Design (TIDUAO7)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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1-Jan-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC6551AQDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D61Q
DAC8551AQDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D81Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jan-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC8551-Q1 :
• Catalog: DAC8551
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC6551AQDGKRQ1
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8551AQDGKRQ1
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC6551AQDGKRQ1
VSSOP
DGK
8
2500
350.0
350.0
43.0
DAC8551AQDGKRQ1
VSSOP
DGK
8
2500
350.0
350.0
43.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Copyright © 2019, Texas Instruments Incorporated
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