Texas Instruments | ADC32RF45 Dual-Channel, 14-Bit, 3.0-GSPS, Analog-to-Digital Converter (Rev. C) | Datasheet | Texas Instruments ADC32RF45 Dual-Channel, 14-Bit, 3.0-GSPS, Analog-to-Digital Converter (Rev. C) Datasheet

Texas Instruments ADC32RF45 Dual-Channel, 14-Bit, 3.0-GSPS, Analog-to-Digital Converter (Rev. C) Datasheet
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ADC32RF45
SBAS747C – MAY 2016 – REVISED DECEMBER 2016
ADC32RF45 Dual-Channel, 14-Bit, 3.0-GSPS, Analog-to-Digital Converter
1 Features
3 Description
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The ADC32RF45 device is a 14-bit, 3.0-GSPS, dualchannel, analog-to-digital converter (ADC) that
supports RF sampling with input frequencies up to
4 GHz and beyond. Designed for high signal-to-noise
ratio (SNR), the ADC32RF45 delivers a noise
spectral density of –155 dBFS/Hz as well as dynamic
range and channel isolation over a large input
frequency range. The buffered analog input with onchip termination provides uniform input impedance
across a wide frequency range and minimizes
sample-and-hold glitch energy.
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14-Bit, Dual-Channel, 3.0-GSPS ADC
Noise Floor: –155 dBFS/Hz
RF Input Supports Up to 4.0 GHz
Aperture Jitter: 90 fS
Channel Isolation: 95 dB at fIN = 1.8 GHz
Spectral Performance (fIN = 900 MHz, –2 dBFS):
– SNR: 60.9 dBFS
– SFDR: 67-dBc HD2, HD3
– SFDR: 77-dBc Worst Spur
Spectral Performance (fIN = 1.78 GHz, –2 dBFS):
– SNR: 58.8 dBFS
– SFDR: 66-dBc HD2, HD3
– SFDR: 75-dBc Worst Spur
On-Chip Digital Down-Converters:
– Up to 4 DDCs (Dual-Band Mode)
– Up to 3 Independent NCOs per DDC
On-Chip Input Clamp for Overvoltage Protection
Programmable On-Chip Power Detectors with
Alarm Pins for AGC Support
On-Chip Dither
On-Chip Input Termination
Input Full-Scale: 1.35 VPP
Support for Multi-Chip Synchronization
JESD204B Interface:
– Subclass 1-Based Deterministic Latency
– 4 Lanes Per Channel at 12.5 Gbps
Power Dissipation: 3.2 W/Ch at 3.0 GSPS
72-Pin VQFN Package (10 mm × 10 mm)
2 Applications
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Multi-Band, Multi-Mode 2G, 3G, 4G Cellular
Receivers
Phased Array Radars
Electronic Warfare
Cable Infrastructure
Broadband Wireless
High-Speed Digitizers
Software-Defined Radios
Communications Test Equipment
Microwave and Millimeter Wave Receivers
Each ADC channel can be connected to a dual-band,
digital down-converter (DDC) with up to three
independent, 16-bit numerically-controlled oscillators
(NCOs) per DDC for phase-coherent frequency
hopping. Additionally, the ADC is equipped with frontend peak and RMS power detectors and alarm
functions to support external automatic gain control
(AGC) algorithms.
The ADC32RF45 supports the JESD204B serial
interface with subclass 1-based deterministic latency
using data rates up to 12.5 Gbps with up to four lanes
per ADC. The device is offered in a 72-pin VQFN
package (10 mm × 10 mm) and supports the
industrial temperature range (–40°C to +85°C).
Device Information(1)
PART NUMBER
ADC32RF45
PACKAGE
BODY SIZE (NOM)
VQFN (72)
10.00 mm × 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
ADC
ADC
ADC
ADC
CM
DA[1:0]P,
DA[1:0]M
Digital Block
Buffer
65
INAP,
INAM
N
Interleave
Correction
Power
Detection
DA[3:2]P,
DA[3:2]M
N
NCO
FOVR
NCO
NCO
CTRL
GPIO[4:1]
CLKINP,
CLKINM
Clock
Divider
PLL
JESD204B
Interface
1
SYNCBP,
SYNCBM
SYSREFP,
SYSREFM
NCO
RESET
SCLK
SDATA
SEN
PDN
SDO
SPI
and
Control
Buffer
INBP,
INBM
65
FOVR
ADC
ADC
ADC
ADC
NCO
Digital Block
N
DB[1:0]P,
DB[1:0]M
Interleave
Correction
Power
Detection
N
DB[3:2]P,
DB[3:2]M
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADC32RF45
SBAS747C – MAY 2016 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
AC Performance Characteristics .............................. 7
Digital Requirements ................................................ 9
Timing Requirements .............................................. 10
Typical Characteristics ............................................ 12
7
Parameter Measurement Information ................ 21
8
Detailed Description ............................................ 22
7.1 Input Clock Diagram ............................................... 21
8.1 Overview ................................................................. 22
8.2 Functional Block Diagram ....................................... 22
8.3 Feature Description................................................. 23
8.4 Device Functional Modes........................................ 50
8.5 Register Maps ......................................................... 64
9
Application and Implementation ...................... 112
9.1 Application Information.......................................... 112
9.2 Typical Application ................................................ 119
10 Power Supply Recommendations ................... 121
11 Layout................................................................. 121
11.1 Layout Guidelines ............................................... 121
11.2 Layout Example .................................................. 121
12 Device and Documentation Support ............... 122
12.1 Documentation Support ......................................
12.2 Receiving Notification of Documentation
Updates..................................................................
12.3 Community Resources........................................
12.4 Trademarks .........................................................
12.5 Electrostatic Discharge Caution ..........................
12.6 Glossary ..............................................................
122
122
122
122
122
122
13 Mechanical, Packaging, and Orderable
Information ......................................................... 122
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2016) to Revision C
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2
Page
Released to production .......................................................................................................................................................... 1
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SBAS747C – MAY 2016 – REVISED DECEMBER 2016
5 Pin Configuration and Functions
DB2P
DB2M
DVDD
DB1P
DB1M
GND
DB0P
DB0M
DVDD
GPIO4
DA0M
DA0P
GND
DA1M
DA1P
DVDD
DA2M
DA2P
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
RMP Package
72-Pin VQFN
Top View
DB3M
1
54
DA3M
DB3P
2
53
DA3P
GND
3
52
GND
DVDD
4
51
DVDD
SDIN
5
50
PDN
SCLK
6
49
GND
SEN
7
48
RESET
DVDD
8
47
DVDD
AVDD
9
Thermal
46
AVDD
AVDD19
10
Pad
45
AVDD19
SDOUT
11
44
AVDD
AVDD
12
43
AVDD
34
35
36
SYNCBP
SYNCBM
32
GND
33
31
AVDD19
SYSREFP
30
SYSREFM
29
GND
28
CLKINM
AVDD
27
GND
CLKINP
AVDD
37
26
38
18
25
17
GND
GND
AVDD
AVDD
AVDD19
24
39
AVDD19
16
23
AVDD19
GND
AVDD
22
40
21
15
CM
AVDD
GPIO3
INAM
20
INAP
41
GPIO2
42
14
19
13
GPIO1
INBP
INBM
Not to scale
Pin Functions
NAME
NO.
I/O
DESCRIPTION
INPUT, REFERENCE
INAM
41
INAP
42
INBM
14
INBP
13
CM
22
I
Differential analog input for channel A
I
Differential analog input for channel B
O
Common-mode voltage for analog inputs, 1.2 V
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Pin Functions (continued)
NAME
NO.
I/O
DESCRIPTION
CLOCK, SYNC
CLKINM
28
CLKINP
27
SYSREFM
34
SYSREFP
33
GPIO1
19
GPIO2
20
GPIO3
21
GPIO4
63
I
Differential clock input for the analog-to-digital converter (ADC).
This pin has an internal differential 100-Ω termination.
I
External sync input. This pin has an internal, differential 100-Ω termination and
requires external biasing.
I/O
GPIO control pin; configured through the SPI. This pin can be configured to be
either a fast overrange output for channel A and B, a fast detect alarm signal from
the peak power detect, or a numerically-controlled oscillator (NCO) control.
GPIO 4 (pin 63) can also be configured as a single-ended SYNCB input.
CONTROL, SERIAL
RESET
48
I
Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor.
SCLK
6
I
Serial interface clock input. This pin has an internal 20-kΩ pulldown resistor.
SDIN
5
I/O
Serial interface data input. This pin has an internal 20-kΩ pulldown resistor. SDIN
can be data input in 4-wire mode, data input and output in 3 wire-mode.
SEN
7
I
Serial interface enable. This pin has an internal 20-kΩ pullup resistor to DVDD.
SDOUT
11
O
Serial interface data output in 4-wire mode
PDN
50
I
Power down; active high. This pin can be configured through an SPI register setting
and can be configured to a fast overrange output channel B through the SPI.
This pin has an internal 20-kΩ pulldown resistor.
O
JESD204B serial data output for channel A
O
JESD204B serial data output for channel B
I
Synchronization input for the JESD204B port. This pin has an LVDS or 1.8-V logic
input, an optional on-chip 100-Ω termination, and is selectable through the SPI.
This pin requires external biasing.
DATA INTERFACE
DA0M
62
DA0P
61
DA1M
59
DA1P
58
DA2M
56
DA2P
55
DA3M
54
DA3P
53
DB0M
65
DB0P
66
DB1M
68
DB1P
69
DB2M
71
DB2P
72
DB3M
1
DB3P
2
SYNCBM
36
SYNCBP
35
POWER SUPPLY
AVDD19
10, 16, 24, 31, 39, 45
I
Analog 1.9-V power supply
AVDD
9, 12, 15, 17, 25, 30,
38, 40, 43, 44, 46
I
Analog 1.15-V power supply
DVDD
4, 8, 47, 51, 57, 64, 70
I
Digital 1.15 V-power supply, including the JESD204B transmitter
3, 18, 23, 26, 29, 32,
37, 49, 52, 60, 67
I
Ground; shorted to thermal pad inside device
GND
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range
Voltage applied to input pins
MIN
MAX
AVDD19
–0.3
2.1
AVDD
–0.3
1.4
DVDD
–0.3
1.4
INAP, INAM and INBP, INBM
–0.3
AVDD19 + 0.3
CLKINP, CLKINM
–0.3
AVDD + 0.6
SYSREFP, SYSREFM, SYNCBP, SYNCBM
–0.3
AVDD + 0.6
SCLK, SEN, SDIN, RESET, PDN, GPIO1, GPIO2,
GPIO3, GPIO4
–0.2
AVDD19 + 0.2
Voltage applied to output pins
Temperature
(1)
–0.3
2.2
Operating free-air, TA
–40
85
Storage, Tstg
–65
150
UNIT
V
V
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage
Temperature
(1)
MIN
NOM
MAX
AVDD19
1.8
1.9
2.0
AVDD
1.1
1.15
1.25
DVDD
1.1
1.15
1.2
Operating free-air, TA
–40
105 (1)
125
UNIT
V
85
Operating junction, TJ
°C
Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.
6.4 Thermal Information
ADC32RF45
THERMAL METRIC
(1)
RMP (VQFN)
UNIT
72 PINS
RθJA
Junction-to-ambient thermal resistance
21.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
4.4
°C/W
RθJB
Junction-to-board thermal resistance
2.0
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
2.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1792
1965
mA
POWER CONSUMPTION (1) (Dual-Channel Operation, Both Channels A and B are Active; DDC Bypass Mode (2))
IAVDD19
1.9-V analog supply current
12-bit, bypass mode, fS = 3.0 GSPS
IAVDD
1.15-V analog supply current
12-bit, bypass mode, fS = 3.0 GSPS
972
1062
mA
IDVDD
1.15-V digital supply current
12-bit, bypass mode, fS = 3.0 GSPS
1748
1892
mA
PD
Power dissipation
12-bit, bypass mode, fS = 3.0 GSPS
6.53
7.01
W
Global power-down power
dissipation
360
mW
14
Bits
1.35
VPP
ANALOG INPUTS
Resolution
Differential input full-scale
VIC
Input common-mode voltage
RIN
Input resistance
Differential resistance at dc
CIN
Input capacitance
Differential capacitance at dc
VCM common-mode voltage output
Analog input bandwidth
(–3-dB point)
ADC driven with 50-Ω source
1.2 (3)
V
65
Ω
2
pF
1.2
V
3200
MHz
ISOLATION
Crosstalk isolation between channel
A and channel B (4)
CLOCK INPUT
fIN = 100 MHz
100
fIN = 900 MHz
99
fIN = 1800 MHz
95
fIN = 2700 MHz
86
fIN = 3500 MHz
85
(5)
Input clock frequency
1.5
3
Differential (peak-to-peak) input
clock amplitude
0.5
1.5
2.5
45%
50%
55%
Input clock duty cycle
(1)
(2)
(3)
(4)
(5)
6
dBc
GHz
VPP
Internal clock biasing
1.0
V
Internal clock termination
(differential)
100
Ω
See the Power Consumption in Different Modes section for more details.
Full-scale signal is applied to the analog inputs of all active channels.
When used in dc-coupling mode, the common-mode voltage at the analog inputs should be kept within VCM ±25 mV for best
performance.
Crosstalk is measured with a –2-dBFS input signal on aggressor channel and no input on the victim channel.
See Figure 59.
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6.6 AC Performance Characteristics
typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER
SNR
Signal-to-noise ratio
TEST CONDITIONS
MIN (1)
62.7
fIN = 900 MHz, AOUT = –2 dBFS
60.9
fIN = 1850 MHz, AOUT = –2 dBFS
55.4
58.2
fIN = 2600 MHz, AOUT = –2 dBFS
56.8
(2)
NF (3)
SINAD
fIN = 2600 MHz, AOUT = –2 dBFS
148.6
fIN = 3500 MHz, AOUT (2) = –3 dBFS with 2-dB gain
146.0
fIN = 1850 MHz, AOUT = –40 dBFS
63.0
dBFS
Input noise figure
fIN = 1850 MHz, AOUT = –40 dBFS
24.7
dB
fIN = 100 MHz, AOUT = –2 dBFS
61.8
fIN = 900 MHz, AOUT = –2 dBFS
60.2
fIN = 1850 MHz, AOUT = –2 dBFS
58.2
fIN = 2100 MHz, AOUT = –2 dBFS
57.5
fIN = 2600 MHz, AOUT = –2 dBFS
56.0
Signal-to-noise and
distortion ratio
Effective number of bits
(2)
= –3 dBFS with 2-dB gain
10.0
fIN = 900 MHz, AOUT = –2 dBFS
9.7
fIN = 1850 MHz, AOUT = –2 dBFS
9.4
fIN = 2100 MHz, AOUT = –2 dBFS
9.3
fIN = 2600 MHz, AOUT = –2 dBFS
9.0
(2)
= –3 dBFS with 2-dB gain
Spurious-free dynamic
range
fIN = 1850 MHz, AOUT = –2 dBFS
8.6
67.0
58
(3)
(4)
66.0
65.0
fIN = 2600 MHz, AOUT = –2 dBFS
57.0
fIN = 3500 MHz, AOUT (2) = –3 dBFS with 2-dB gain
61.0
fIN = 100 MHz, AOUT = –2 dBFS
69.0
fIN = 900 MHz, AOUT = –2 dBFS
Second-order harmonic
distortion
Bits
69.0
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 1850 MHz, AOUT = –2 dBFS
dBFS
53.6
fIN = 100 MHz, AOUT = –2 dBFS
fIN = 900 MHz, AOUT = –2 dBFS
(1)
(2)
dBFS/Hz
Small-signal SNR
fIN = 100 MHz, AOUT = –2 dBFS
HD2 (4)
150.6
150.0
fIN = 3500 MHz, AOUT
SFDR
dBFS
152.7
147.2
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 3500 MHz, AOUT
ENOB
UNIT
154.5
fIN = 900 MHz, AOUT = –2 dBFS
fIN = 1850 MHz, AOUT = –2 dBFS
MAX
54.2
= –3 dBFS with 2-dB gain
fIN = 100 MHz, AOUT = –2 dBFS
NSD
58.8
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 3500 MHz, AOUT
Noise spectral density
averaged across the
Nyquist zone
NOM
fIN = 100 MHz, AOUT = –2 dBFS
dBc
73.0
58
66.0
fIN = 2100 MHz, AOUT = –2 dBFS
65.0
fIN = 2700 MHz, AOUT = –2 dBFS
57.0
fIN = 3500 MHz, AOUT (2) = –3 dBFS with 2-dB gain
61.0
dBc
Minimum values are specified at AOUT = –3 dBFS.
Output amplitude, AOUT, refers to the signal amplitude in the ADC digital output that is same as the analog input amplitude, AIN, except
when the digital gain feature is used. If digital gain is G, then AOUT = G + AIN.
The ADC internal resistance = 65 Ω, the driving source resistance = 50 Ω.
The minimum value of HD2 is specified by bench characterization.
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AC Performance Characteristics (continued)
typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER
HD3
Third-order harmonic
distortion
TEST CONDITIONS
Fourth- and fifth-order
harmonic distortion
72.0
fIN = 900 MHz, AOUT = –2 dBFS
67.0
fIN = 1850 MHz, AOUT = –2 dBFS
61
IL spur
80.0
fIN = 2600 MHz, AOUT = –2 dBFS
79.0
(2)
83.0
fIN = 900 MHz, AOUT = –2 dBFS
81.0
fIN = 1850 MHz, AOUT = –2 dBFS
61
Worst
spur
Interleaving spur for HD2:
fS / 2 – HD2
83.0
fIN = 2600 MHz, AOUT = –2 dBFS
76.0
fIN = 3500 MHz, AOUT (2) = –3 dBFS with 2-dB gain
82.0
fIN = 100 MHz, AOUT = –2 dBFS
89.0
fIN = 2600 MHz, AOUT = –2 dBFS
78.0
fIN = 3500 MHz, AOUT (2) = –3 dBFS with 2-dB gain
78.0
fIN = 100 MHz, AOUT = –2 dBFS
82.0
8
80.0
76.0
fIN = 2600 MHz, AOUT = –2 dBFS
65.0
fIN = 3500 MHz, AOUT (2) = –3 dBFS with 2-dB gain
77.0
fIN = 100 MHz, AOUT = –2 dBFS
81.0
= 900 MHz, AOUT = –2 dBFS
= 1850 MHz, AOUT = –2 dBFS
dBc
dBc
dBc
77.0
64
75.0
= 2100 MHz, AOUT = –2 dBFS
75.0
= 2600 MHz, AOUT = –2 dBFS
74.0
dBc
71.0
fIN1 = 1770 MHz, fIN2 = 1790 MHz,
AOUT = –8 dBFS (each tone)
73
fIN1 = 1800 MHz, fIN2 = 2600 MHz,
AOUT = –8 dBFS (each tone)
65
fIN1 = 3490 MHz, fIN2 = 3510 MHz,
AOUT = –8 dBFS (each tone) with 2-dB gain
75
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dBc
81.0
62
fIN = 2100 MHz, AOUT = –2 dBFS
fIN
Spurious-free dynamic
range (excluding HD2, HD3, fIN
HD4, HD5, and interleaving fIN
spurs IL and HD2 IL)
fIN
Two-tone, third-order
intermodulation distortion
82.0
77.0
fIN = 1850 MHz, AOUT = –2 dBFS
UNIT
79.0
69
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 3500 MHz, AOUT (2) = –3 dBFS with 2-dB gain
IMD3
86.0
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 1850 MHz, AOUT = –2 dBFS
MAX
66.0
= –3 dBFS with 2-dB gain
fIN = 100 MHz, AOUT = –2 dBFS
fIN = 900 MHz, AOUT = –2 dBFS
HD2 IL
70.0
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 900 MHz, AOUT = –2 dBFS
Interleaving spurs:
fS / 2 – fIN,
fS / 4 ± fIN
NOM
fIN = 100 MHz, AOUT = –2 dBFS
fIN = 3500 MHz, AOUT
HD4,
HD5
MIN (1)
dBFS
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6.7 Digital Requirements
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN, GPIO1, GPIO2, GPIO3, GPIO4)
VIH
High-level input voltage
0.8
V
VIL
Low-level input voltage
IIH
High-level input current
50
µA
IIL
Low-level input current
–50
µA
Ci
Input capacitance
4
pF
AVDD19
V
0.4
V
DIGITAL OUTPUTS (SDOUT, GPIO1, GPIO2, GPIO3, GPIO4)
VOH
High-level output voltage
VOL
Low-level output voltage
AVDD19
–0.1
0.1
V
mVPP
DIGITAL INPUTS (SYSREFP and SYSREFM; SYNCBP and SYNCBM; Requires External Biasing)
VID
Differential input voltage
350
450
800
VCM
Input common-mode voltage
1.05
1.2
1.325
V
DIGITAL OUTPUTS (JESD204B Interface: DA[3:0], DB[3:0], Meets JESD204B LV-0IF-11G-SR Standard)
|VOD|
Output differential voltage
700
mVPP
|VOCM|
Output common-mode voltage
450
mV
Transmitter short-circuit current
zos
Single-ended output impedance
Co
Output capacitance
Transmitter pins shorted to any voltage
between –0.25 V and 1.45 V
Output capacitance inside the device, from
either output to ground
–100
100
50
Ω
2
pF
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6.8 Timing Requirements
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
MIN
NOM
MAX
UNIT
750
ps
SAMPLE TIMING
Aperture delay
250
Aperture delay matching between two channels on the same device
±15
ps
±150
ps
90
fS
12-bit bypass mode, LMFS = 82820
461
Input
clock
cycles
14-bit bypass mode, LMFS = 8224
424
Input
clock
cycles
Fast overrange latency, ADC sample to FOVR indication on GPIO pins
70
Aperture delay matching between two devices at the same
temperature and supply voltage
Aperture jitter, clock amplitude = 2 VPP
Latency
(1) (2)
Data latency, ADC sample to
digital output
Propagation delay time: logic gates and output buffer delay
(does not change with fS)
tPD
SYSREF TIMING
tSU_SYSREF SYSREF setup time: referenced to clock rising edge, 3 GSPS
tH_SYSREF
6
ns
140
70
ps
50
20
ps
(3)
SYSREF hold time: referenced to clock rising edge, 3 GSPS
Valid transition window sampling period: tSU_SYSREF – tH_SYSREF, 3 GSPS
143
ps
JESD OUTPUT INTERFACE TIMING
UI
Unit interval: 12.5 Gbps
80
100
400
ps
Serial output data rate
2.5
10.0
12.5
Gbps
Rise, fall times: 1-pF, single-ended load capacitance to ground
Total jitter: BER of 1E-15 and lane rate = 12.5 Gbps
Random jitter: BER of 1E-15 and lane rate = 12.5 Gbps
Deterministic jitter: BER of 1E-15 and lane rate = 12.5 Gbps
(1)
(2)
(3)
10
60
25
ps
%UI
0.99
%UI, rms
9.1
%UI, pkpk
Overall latency = latency + tPD.
Latency increases when the DDC modes are used; see Table 4.
Common-mode voltage for the SYSREF input is kept at 1.2 V.
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SYSREFP, SYNCP, DxP
VID / 4, VOD / 4
VICM, VOCM(1)
VID / 4, VOD / 4
SYSREFM, SYNCM, DxM
SYSREF = SYSREFP-SYNCP,
SYNC = SYNCP-SYNCM,
Dx = DxP-DxM
VID or VOD(1)
0V
GND
(1)
VOCM is not the same as VICM. Similarly, VOD is not the same as VID.
Figure 1. Logic Levels for Digital Inputs and Outputs
Sample N
CLKP
CLKM
tSU_SYSREF
tH_SYSREF
SYSREFP
SYSREFM
Valid Transition Window
Valid Transition Window
Figure 2. SYSREF Timing Diagram
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6.9 Typical Characteristics
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
0
300
600
900
Input Frequency (MHz)
1200
1500
0
SNR = 62.3 dBFS; SFDR = 67 dBc;
HD2 = –70 dBc; HD3 = –67 dBc; non HD2, HD3 = 76 dBc;
IL spur = 82.5 dBc; fIN = 100 MHz
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
1200
1500
D002
Figure 4. FFT for 900-MHz Input Frequency
0
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
0
300
600
900
Input Frequency (MHz)
1200
1500
0
300
D003
SNR = 58.9 dBFS; SFDR = 67 dBc;
HD2 = –68 dBc; HD3 = –67 dBc; non HD2, HD3 = 82 dBc;
IL spur = 80 dBc; fIN = 1780 MHz
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
0
-50
-60
-70
-80
1200
1500
D004
Figure 6. FFT for 2100-MHz Input Frequency
0
-40
600
900
Input Frequency (MHz)
SNR = 57.8 dBFS; SFDR = 70 dBc;
HD2 = –72 dBc; HD3 = –89 dBc; non HD2, HD3 = 70 dBc;
IL spur = 75 dBc; fIN = 2100 MHz
Figure 5. FFT for 1780-MHz Input Frequency
Amplitude (dBFS)
600
900
Input Frequency (MHz)
SNR = 61.4 dBFS; SFDR = 72 dBc;
HD2 = –72 dBc; HD3 = –73 dBc; non HD2, HD3 = 84 dBc;
IL spur = 79 dBc; fIN = 900 MHz
Figure 3. FFT for 100-MHz Input Frequency
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
0
300
600
900
Input Frequency (MHz)
1200
1500
0
300
D005
SNR = 56.8 dBFS; SFDR = 61 dBc;
HD2 = –61 dBc; HD3 = –71 dBc; non HD2, HD3 = 71 dBc;
IL spur = 66 dBc; fIN = 2600 MHz
Figure 7. FFT for 2600-MHz Input Frequency
12
300
D001
600
900
Input Frequency (MHz)
1200
1500
D006
SNR = 53.4 dBFS; SFDR = 56 dBc;
HD2 = –56 dBc; HD3 = –64 dBc; non HD2, HD3 = 67 dBc;
IL spur = 75 dBc; fIN = 3500 MHz, AOUT = –3 dBFS with 2-dB gain
Figure 8. FFT for 3500-MHz Input Frequency
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Typical Characteristics (continued)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
0
300
600
900
Input Frequency (MHz)
1200
1500
0
fIN1 = 0.90 GHz, fIN2 = 0.95 GHz, AOUT = –8 dBFS,
IMD = 78 dBFS
1200
1500
D057
Figure 10. FFT for Two-Tone Input Signal (–36 dBFS)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
600
900
Input Frequency (MHz)
fIN1 = 0.90 GHz, fIN2 = 0.95 GHz, AOUT = –36 dBFS,
IMD = 99 dBFS
Figure 9. FFT for Two-Tone Input Signal (–8 dBFS)
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
0
300
600
900
Input Frequency (MHz)
1200
1500
0
300
D007
600
900
Input Frequency (MHz)
1200
1500
D008
fIN1 = 1.77 GHz, fIN2 = 1.79 GHz, AOUT = –8 dBFS,
IMD = 73 dBFS
fIN1 = 1.77 GHz, fIN2 = 1.79 GHz, AOUT = –36 dBFS,
IMD = 99 dBFS
Figure 11. FFT for Two-Tone Input Signal (–8 dBFS)
Figure 12. FFT for Two-Tone Input Signal (–36 dBFS)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
300
D056
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
0
300
600
900
Input Frequency (MHz)
1200
1500
0
D009
300
600
900
Input Frequency (MHz)
1200
1500
D010
fIN1 = 1.80 GHz, fIN2 = 2.60 GHz, AOUT = –8 dBFS,
IMD = 67 dBFS
fIN1 = 1.80 GHz, fIN2 = 2.60 GHz, AOUT = –36 dBFS,
IMD = 98 dBFS
Figure 13. FFT for Two-Tone Input Signal (–8 dBFS)
Figure 14. FFT for Two-Tone Input Signal (–36 dBFS)
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Typical Characteristics (continued)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
-40
-50
-60
-70
-40
-50
-60
-70
-80
-80
-90
-90
-100
-100
-110
-110
0
300
600
900
Input Frequency (MHz)
1200
0
1500
fIN1 = 3.49 GHz, fIN2 = 3.51 GHz, AOUT = –8 dBFS with 2-dB digital
gain, IMD = 69 dBFS
600
900
Input Frequency (MHz)
1200
1500
D012
fIN1 = 3.49 GHz, fIN2 = 3.51 GHz, AOUT = –36 dBFS with 2-dB
digital gain, IMD = 86 dBFS
Figure 15. FFT for Two-Tone Input Signal (–8 dBFS)
Figure 16. FFT for Two-Tone Input Signal (–36 dBFS)
-70
-65
-75
-70
-75
-80
-80
IMD (dBFS)
IMD (dBFS)
300
D011
-85
-90
-85
-90
-95
-95
-100
-100
-105
-36
-105
-36
-32
-28
-24
-20
-16
Each Tone Amplitude (dBFS)
-12
-8
-32
D013
fIN1 = 1.77 GHz, fIN2 = 1.79 GHz (Excluding fIN1 – fIN2)
Figure 17. Intermodulation Distortion vs Input Amplitude
(1770 MHz and 1790 MHz)
-28
-24
-20
-16
Each Tone Amplitude (dBFS)
-12
-8
D014
fIN1 = 1.80 GHz, fIN2 = 2.60 GHz (Excluding fIN1 – fIN2)
Figure 18. Intermodulation Distortion vs Input Amplitude
(1800 MHz and 2600 MHz)
90
-60
-65
78
-75
SFDR (dBc)
IMD (dBFS)
-70
-80
-85
66
54
-90
42
-95
-100
-36
30
-32
-28
-24
-20
-16
Each Tone Amplitude (dBFS)
-12
-8
fIN1 = 3.49 GHz, fIN2 = 3.51 GHz (Excluding fIN1 – fIN2) with 2-dB
digital gain
Figure 19. Intermodulation Distortion vs Input Amplitude
(3490 MHz and 3510 MHz)
14
0
500
D015
1000
1500 2000 2500 3000
InputFrequency (MHz)
3500
4000
D016
AOUT = –2 dBFS with 0-dB gain for the first and second Nyquist,
AOUT = –3 dBFS with 2-dB gain for the third Nyquist
Figure 20. Spurious-Free Dynamic Range vs
Input Frequency
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Typical Characteristics (continued)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
63
100
fIN + fS/4 (dBc)
fIN - fS/2 (dBc)
fIN - fS/4 (dBc)
61
90
SNR (dBFS)
Interleaving Spurs (dBc)
95
2fIN + fS/4 (dBc)
2fIN - fS/2 (dBc)
2fIN - fS/4 (dBc)
85
80
75
70
59
57
55
65
53
60
0
500
1000
1500 2000 2500 3000
Input Frequency (MHz)
3500
0
4000
AOUT = –2 dBFS with 0-dB gain for the first and second Nyquist,
AOUT = –3 dBFS with 2-dB gain for the third Nyquist
AVDD = 1.1 V
AVDD = 1.15 V
AVDD = 1.2 V
AVDD = 1.25 V
4000
D018
AVDD = 1.1 V
AVDD = 1.15 V
AVDD = 1.2 V
AVDD = 1.25 V
68
SFDR (dBc)
SNR (dBFS)
3500
70
60
59
58
57
66
64
62
-15
10
35
Temperature (°C)
60
60
-40
85
-15
D019
fIN = 1.78 GHz, AOUT = –2 dBFS
10
35
Temperature (°C)
60
85
D020
fIN = 1.78 GHz, AOUT = –2 dBFS
Figure 23. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
Figure 24. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
66
57
AVDD = 1.1 V
AVDD = 1.15 V
AVDD = 1.2 V
AVDD = 1.25 V
AVDD = 1.1 V
AVDD = 1.15 V
AVDD = 1.2 V
AVDD = 1 .25 V
64
SFDR (dBc)
56
SNR (dBFS)
1500 2000 2500 3000
Input Frequency (MHz)
Figure 22. Signal-to-Noise Ratio vs Input Frequency
Figure 21. IL Spur vs Input Frequency
55
54
62
60
58
53
52
-40
1000
AOUT = –2 dBFS with 0-dB gain for the first and second Nyquist,
AOUT = –3 dBFS with 2-dB gain for the third Nyquist
61
56
-40
500
D017
-15
10
35
Temperature (°C)
60
85
56
-40
-15
D021
fIN = 3.5 GHz, AOUT = –3 dBFS with 2-dB digital gain
Figure 25. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
10
35
Temperature (°C)
60
85
D022
fIN = 3.5 GHz, AOUT = –3 dBFS with 2-dB digital gain
Figure 26. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
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Typical Characteristics (continued)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
61
72
DVDD = 1.1 V
DVDD = 1.15 V
DVDD = 1.2 V
70
SFDR (dBc)
SNR (dBFS)
60
59
58
57
56
-40
DVDD = 1.1 V
DVDD = 1.15 V
DVDD = 1.2 V
68
66
64
-15
10
35
Temperature (°C)
60
62
-40
85
-15
D023
fIN = 1.78 GHz, AOUT = –2 dBFS
SFDR (dBc)
SNR (dBFS)
DVDD = 1.1 V
DVDD = 1.15 V
DVDD = 1.2 V
66
55
54
53
64
62
60
-15
10
35
Temperature (°C)
60
58
-40
85
-15
D025
fIN = 3.5 GHz, AOUT = –3 dBFS with 2-dB digital gain
10
35
Temperature (°C)
60
85
D026
fIN = 3.5 GHz, AOUT = –3 dBFS with 2-dB digital gain
Figure 29. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
Figure 30. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
72
61
AVDD19 = 1.8 V
AVDD19 = 1.85 V
AVDD19 = 1.9 V
AVDD19 = 1.8 V
AVDD19 = 1.85 V
AVDD19 = 1.9 V
AVDD19 = 1.95 V
AVDD19 = 2 V
70
SFDR (dBc)
60
SNR (dBFS)
D024
68
DVDD = 1.1 V
DVDD = 1.15 V
DVDD = 1.2 V
56
59
58
AVDD19 = 1.95 V
AVDD19 = 2 V
68
66
64
57
-15
10
35
Temperature (°C)
60
85
62
-40
-15
D027
fIN = 1.78 GHz, AOUT = –2 dBFS
10
35
Temperature (°C)
60
85
D028
fIN = 1.78 GHz, AOUT = –2 dBFS
Figure 31. Signal-to-Noise Ratio vs
AVDD19 Supply and Temperature
16
85
Figure 28. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
57
56
-40
60
fIN = 1.78 GHz, AOUT = –2 dBFS
Figure 27. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
52
-40
10
35
Temperature (°C)
Figure 32. Spurious-Free Dynamic Range vs
AVDD19 Supply and Temperature
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Typical Characteristics (continued)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
57
66
AVDD19 = 1.8 V
AVDD19 = 1.85 V
AVDD19 = 1.9 V
55
54
53
-15
10
35
Temperature (°C)
60
62
60
56
-40
85
-15
10
35
Temperature (°C)
D029
fIN = 3.5 GHz, AOUT = –3 dBFS with 2-dB digital gain
60
85
D030
fIN = 3.5 GHz, AOUT = –3 dBFS with 2-dB digital gain
Figure 33. Signal-to-Noise Ratio vs
AVDD19 Supply and Temperature
Figure 34. Spurious-Free Dynamic Range vs
AVDD19 Supply and Temperature
25
20
D031
HD2 (dBFS)
Figure 36. HD2 Histogram at AVDD19 = 1.9 V
Temp = -40°C
Temp = 25°C
Temp = 85°C
120
SNR (dBFS) 110
SFDR (dBFS)
100
SFDR (dBc)
90
70
68
SNR (dBFS)
66
15
10
5
80
62
70
60
60
58
50
56
40
54
30
52
20
50
10
48
-70
-63
-64
-65
-66
-67
-68
-69
-70
-71
-72
-73
-74
-75
-76
-77
-78
0
64
SFDR (dBc,dBFS)
72
25
-80
-62
fIN = 1.78 GHz, AOUT = –2 dBFS
Figure 35. HD2 Histogram at AVDD19 = 1.8 V
HD2 (dBFS)
-63
D032
HD2 (dBFS)
fIN = 1.78 GHz, AOUT = –2 dBFS
20
-66
-67
-68
-69
-70
-71
-72
-78
-62
-63
-64
-65
-66
-67
-68
-69
-70
-71
-72
-73
-75
-76
0
-77
0
-79
5
-80
5
-73
10
-74
10
15
-75
Count (%)
15
-77
20
Temp = -40°C
Temp = 25°C
Temp = 85°C
-64
Temp = -40°C
Temp = 25°C
Temp = 85°C
-65
25
Count (%)
AVDD19 = 1.95 V
AVDD19 = 2 V
58
52
-40
Count (%)
AVDD19 = 1.8 V
AVDD19 = 1.85 V
AVDD19 = 1.9 V
64
SFDR (dBc)
SNR (dBFS)
56
AVDD19 = 1.95 V
AVDD19 = 2 V
0
-60
D033
-50
-40
-30
Amplitude (dBFS)
-20
-10
0
D034
fIN = 1.78 GHz
fIN = 1.78 GHz, AOUT = –2 dBFS
Figure 37. HD2 Histogram at AVDD19 = 2.0 V
Figure 38. Performance vs Amplitude
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Typical Characteristics (continued)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
80
62
70
60
60
58
50
56
40
54
30
52
20
50
10
-50
-40
-30
Amplitude (dBFS)
-20
-10
59
66
58
65
57
64
56
0.5
0
-60
67
0
Figure 40. Performance vs Clock Amplitude
Figure 39. Performance vs Amplitude
55
65
60
70
54
64
53
63
52
62
51
61
SNR (dBFS)
SNR
SFDR
SFDR (dBc)
SNR (dBFS)
SNR
SFDR
60
2.5
0.9
1.3
1.7
2.1
Differential Clock Amplitude (Vpp)
59
69
58
68
57
67
56
66
55
40
45
D037
Figure 42. Performance vs Clock Duty Cycle
70.5
0
SNR
SFDR
-20
53
66
52
64.5
Amplitude (dBFS)
67.5
SFDR (dBc)
SNR (dBFS)
-10
69
54
D039
D038
fIN = 1.78 GHz
Figure 41. Performance vs Clock Amplitude
56
65
60
50
55
Input Clock Duty Cycle (%)
fIN = 3.5 GHz, AOUT = –3 dBFS with 2-dB digital gain
55
D036
fIN = 1.78 GHz
fIN = 3.5 GHz
50
0.5
63
2.5
0.9
1.3
1.7
2.1
Differential Clock Amplitude (Vpp)
D035
SFDR (dBc)
64
60
SFDR (dBc)
SNR (dBFS)
66
68
SNR
SFDR
SNR (dBFS)
68
48
-70
61
120
SNR (dBFS) 110
SFDR (dBFS)
100
SFDR (dBc)
90
70
SFDR (dBc,dBFS)
72
-30
-40
-50
-60
-70
-80
-90
-100
51
40
45
50
55
Input Clock Duty Cycle (%)
63
60
0
D039
D038
fIN = 3.5 GHz, AOUT = –3 dBFS with 2-dB digital gain
Figure 43. Performance vs Clock Duty Cycle
18
-110
300
600
900
Input Frequency (MHz)
1200
1500
D040
fIN = 1.8 GHz, AOUT = –2 dBFS, fPSRR = 3 MHz,
APSRR = 50 mVPP, AVDD19 = 1.9 V, PSRR = 37 dB
Figure 44. Power-Supply Rejection Ratio FFT for
Test Signal on AVDD19 Supply
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Typical Characteristics (continued)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
0
75
PSRR with 50-mVpp Signal on AVDD
PSRR with 50-mVpp Signal on AVDD19
-20
Amplitude (dBFS)
65
-10
PSRR (dB)
55
45
35
-30
-40
-50
-60
-70
-80
-90
25
-100
-110
0
15
0.02
0.1
1
10
100
Frequency of Signal on Supply (MHz)
300
500
600
900
Input Frequency (MHz)
1200
1500
D042
fCMRR = 10 MHz, ACMRR = 50 mVPP,
no differential input signal, CMRR = 32 dB
D041
fIN = 1.8 GHz, AOUT = –2 dBFS
Figure 46. Common-Mode Rejection Ratio FFT
Figure 45. Power-Supply Rejection Ratio vs
Tone Frequency
45
0
-10
40
-20
-30
Amplitude (dBFS)
CMRR (dB)
35
30
25
20
-40
-50
-60
-70
-80
-90
-100
15
-110
10
0
50
100
150
200
Frequency of Input Common-Mode Signal (MHz)
-120
-375
250
fIN = 1.8 GHz, AOUT = –2 dBFS
0
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
0
-40
-50
-60
-70
-80
375
D045
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-50
50
Input Frequency (MHz)
225
Figure 48. FFT in 4X Decimation (Complex Output)
-10
-150
-75
75
Input Frequency (MHz)
fS = 3 GSPS, fIN = 1.78 GHz,
AOUT = –2 dBFS, SNR = 60.5 dBFS, SFDR = 71.1 dBc
Figure 47. Common-Mode Rejection Ratio vs
Tone Frequency
-120
-250
-225
D043
150
250
-120
-187.5
D045
fS = 3 GSPS, fIN = 1.78 GHz,
AOUT = –2 dBFS, SNR = 61.6 dBFS, SFDR = 74.5 dBc
Figure 49. FFT in 6X Decimation (Complex Output)
-112.5
-37.5
37.5
Input Frequency (MHz)
112.5
187.5
D047
fS = 3 GSPS, fIN = 1.78 GHz,
AOUT = –2 dBFS, SNR = 62.3 dBFS, SFDR = 77.5 dBc
Figure 50. FFT in 8X Decimation (Complex Output)
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Typical Characteristics (continued)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
-40
-50
-60
-70
-80
-70
-80
-90
-100
-110
-110
-99.6
-33.2
33.2
Input Frequency (MHz)
99.6
-120
-150
166
-20
-20
-30
-30
Amplitude (dBFS)
0
-10
-50
-60
-70
-80
-60
-70
-80
-90
-100
-110
-110
75
-120
-93.75
125
-10
-20
-20
-30
-30
Amplitude (dBFS)
0
-10
-40
-50
-60
-70
-80
93.75
D051
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
49.8
56.25
Figure 54. FFT in 16X Decimation (Complex Output)
0
-16.6
16.6
Input Frequency (MHz)
-18.75
18.75
Input Frequency (MHz)
fS = 3 GSPS, fIN = 1.78 GHz,
AOUT = –2 dBFS, SNR = 63.2 dBFS, SFDR = 75.7 dBc
Figure 53. FFT in 12X Decimation (Complex Output)
-49.8
-56.25
D050
fS = 3 GSPS, fIN = 1.78 GHz,
AOUT = –2 dBFS, SNR = 63 dBFS, SFDR = 75 dBc
-120
-83
D048
-50
-100
-25
25
Input Frequency (MHz)
150
-40
-90
-75
90
Figure 52. FFT in 10X Decimation (Complex Output)
-10
-40
-30
30
Input Frequency (MHz)
fS = 3 GSPS, fIN = 1.78 GHz,
AOUT = –2 dBFS, SNR = 62.90 dBFS, SFDR = 80 dBc
0
-120
-125
-90
D048
Figure 51. FFT in 9X Decimation (Complex Output)
Amplitude (dBFS)
-60
-100
fS = 3 GSPS, fIN = 1.78 GHz,
AOUT = –2 dBFS, SNR = 62.5 dBFS, SFDR = 76 dBc
Amplitude (dBFS)
-50
-90
-120
-166
83
-120
-75
D052
fS = 3 GSPS, fIN = 1.78 GHz,
AOUT = –2 dBFS, SNR = 64.1 dBFS, SFDR = 82 dBc
Figure 55. FFT in 18X Decimation (Complex Output)
20
-40
-45
-15
15
Input Frequency (MHz)
45
75
D053
fS = 3 GSPS, fIN = 1.78 GHz,
AOUT = –2 dBFS, SNR = 64.2 dBFS, SFDR = 80.5 dBc
Figure 56. FFT in 20X Decimation (Complex Output)
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Typical Characteristics (continued)
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 3 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
-40
-50
-60
-70
-80
-40
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-62.5
-37.5
-12.5
12.5
Input Frequency (MHz)
37.5
62.5
-120
-46.875
-28.125
D054
fS = 3 GSPS, fIN = 1.78 GHz,
AOUT = –2 dBFS, SNR = 64.36 dBFS, SFDR = 81 dBc
Figure 57. FFT in 24X Decimation (Complex Output)
-9.375
9.375
Input Frequency (MHz)
28.125
46.875
D055
fS = 3 GSPS, fIN = 1.78 GHz,
AOUT = –2 dBFS, SNR = 64.6 dBFS, SFDR = 80 dBc
Figure 58. FFT in 32X Decimation (Complex Output)
7 Parameter Measurement Information
7.1 Input Clock Diagram
Figure 59 shows the input clock diagram.
VCLKIN_DIFF =
VCLKIN+ - VCLKIN-
VCLKIN+
VCLKIN-
Figure 59. Input Clock Diagram
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8 Detailed Description
8.1 Overview
The ADC32RF45 is a dual, 14-bit, 3-GSPS, analog-to-digital converter (ADC) followed by a multi-band digital
down-converter (DDC) that can be bypassed, and a back-end JESD204B digital interface.
The ADCs are preceded by an input buffer and on-chip termination to provide a uniform input impedance over a
large input frequency range. Furthermore, an internal differential clamping circuit provides first-level protection
against overvoltage conditions. Each ADC channel is internally interleaved four times and equipped with
background, analog and digital, and interleaving correction.
The on-chip DDC enables single- or dual-band internal processing to pre-select and filter smaller bands of
interest and also reduces the digital output data traffic. Each DDC is equipped with up to three independent,
16-bit numerically-controlled oscillators (NCOs) for phase coherent frequency hopping; the NCOs can be
controlled through the SPI or GPIO pins. The ADC32RF45 also provides three different power detectors on-chip
with alarm outputs in order to support external automatic gain control (AGC) loops.
The processed data are passed into the JESD204B interface where the data are framed, encoded, serialized,
and output on one to four lanes per channel, depending on the ADC sampling rate and decimation. The CLKIN,
SYSREF, and SYNCB inputs provide the device clock and the SYSREF and SYNCB signals to the JESD204B
interface that are used to derive the internal local frame and local multiframe clocks and establish the serial link.
All features of the ADC32RF45 are configurable through the SPI.
8.2 Functional Block Diagram
ADC
ADC
ADC
ADC
65
INAP,
INAM
CM
DA[1:0]P,
DA[1:0]M
Digital Block
Buffer
N
Interleave
Correction
Power
Detection
DA[3:2]P,
DA[3:2]M
N
NCO
FOVR
NCO
CLKINP,
CLKINM
Clock
Divider
PLL
JESD204B
Interface
NCO
CTRL
GPIO[4:1]
SYNCBP,
SYNCBM
SYSREFP,
SYSREFM
NCO
RESET
SCLK
SDATA
SEN
PDN
SDO
SPI
and
Control
Buffer
INBP,
INBM
FOVR
ADC
ADC
ADC
ADC
65
NCO
Digital Block
N
DB[1:0]P,
DB[1:0]M
Interleave
Correction
Power
Detection
N
DB[3:2]P,
DB[3:2]M
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8.3 Feature Description
8.3.1 Analog Inputs
The ADC32RF45 analog signal inputs are designed to be driven differentially. The analog input pins have
internal analog buffers that drive the sampling circuit. The ADC32RF45 provides on-chip, differential termination
to minimize reflections. The buffer also helps isolate the external driving circuit from the internal switching
currents of the sampling circuit, thus resulting in a more constant SFDR performance across input frequencies.
The common-mode voltage of the signal inputs is internally biased to CM using the 32.5-Ω termination resistors
that allow for ac-coupling of the input drive network. Figure 60 and Figure 61 show SDD11 at the analog inputs
from dc to 5 GHz with a 100-Ω reference impedance.
INxP
TI Device
CIN
RIN
ZIN = RIN || CIN
SDD11 = (ZIN ± 100) / (ZIN + 100)
INxM
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Figure 60. Equivalent Input Impedance
Figure 61. SDD11 Over the Input Frequency Range
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Feature Description (continued)
The input impedance of analog inputs can also be modelled as parallel combination of equivalent resistance and
capacitance. Figure 62 and Figure 63 show how equivalent impedance (CIN and RIN) vary over frequency.
0.07
Differential Shunt Resistance (k Ohm)
Differential Shunt Capacitance (pF)
3
2
1
0
-1
-2
-3
0.06
0.05
0.04
0.03
0.02
0.01
0
500
1000
1500
2000
Input Frequency (MHz)
2500
3000
0
500
D063
Figure 62. Differential Input Capacitance vs
Input Frequency
1000
1500
2000
Input Frequency (MHz)
2500
3000
D064
D001
Figure 63. Differential Input Resistance vs Input Frquency
Each input pin (INP, INM) must swing symmetrically between (CM + 0.3375 V) and (CM – 0.3375 V), resulting in
a 1.35-VPP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to
approximately 3.2 GHz, as shown in Figure 64.
2
1
Transfer Function (dB)
0
-1
-2
-3
-4
-5
-6
-7
-8
100
100 Ohm Source
50 Ohm Source
200
300
500 700 1000
2000 3000
Input Frequency (MHz)
5000
D062
Figure 64. Input Bandwidth with a 100-Ω Source Resistance
24
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Feature Description (continued)
8.3.1.1 Input Clamp Circuit
The ADC32RF45 analog inputs include an internal, differential clamp for overvoltage protection. The clamp
triggers for any input signals at approximately 600 mV above the input common-mode voltage, effectively limiting
the maximum input signal to approximately 2.4 VPP, as shown in Figure 65 and Figure 66.
When the clamp circuit conducts, the maximum differential current flowing through the circuit (via input pins)
must be limited to 20 mA.
ADC32RF45
INxP
+600 mV
To Analog Buffer
+337.5 mV
INP
RDC / 2
IDIFF
Input Vcm
675 mVPP for INP and INM
(1.35 VPP Differentially)
INM
Clamp
Circuit
±337.5 mV
RDC / 2
VCM
±600 mV
To Analog Buffer
INxM
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Figure 65. Clamp Circuit in the ADC32RF45
Figure 66. Clamp Response Timing Diagram
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Feature Description (continued)
8.3.2 Clock Input
The ADC32RF45 sampling clock input includes internal 100-Ω differential termination along with on-chip biasing.
The clock input is recommended to be ac-coupled externally. The input bandwidth of the clock input is
approximately 3 GHz; the clock input impedance is shown with a 100-Ω reference impedance in the smith chart
of Figure 67.
Figure 67. SDD11 of the Clock Input
26
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Feature Description (continued)
The analog-to-digital converter (ADC) aperture jitter is a function of the clock amplitude applied to the pins. The
equivalent aperture jitter for input frequencies at a 1-GHz and a 2-GHz input (fS = 3 GSPS) is shown in
Figure 68. Depending on the clock frequency, a matching circuit can be designed in order to maximize the clock
amplitude.
350
fIN = 1 GHz
fIN = 2 GHz
Aperture Jitter (fS)
300
250
200
150
100
50
0.2
1
Clock Amplitude (vPP)
2
D061
Figure 68. Equivalent Aperture Jitter vs Input Clock Amplitude
8.3.3 SYSREF Input
The SYSREF signal is a periodic signal that is sampled by the ADC32RF45 device clock and is used to align the
boundary of the local multiframe clock inside the data converter. SYSREF is also used to reset critical blocks
[such as the clock divider for the interleaved ADCs, numerically-controlled oscillators (NCOs), decimation filters
and so forth].
The SYSREF input requires external biasing. Furthermore, SYSREF must be established before the SPI
registers are programmed. A programmable delay on the SYSREF input, as shown in Figure 69, is available to
help with skew adjustment when the sampling clock and SYSREF are not provided from the same source.
CLKINP
50
VCM
50
CLKINM
Delay
SYSREFP
SYSREF
Capture
100
SYSREFM
Figure 69. SYSREF Internal Circuit Diagram
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Feature Description (continued)
8.3.3.1 Using SYSREF
The ADC32RF45 uses SYSREF information to reset the clock divider, the NCO phase, and the LMFC counter of
the JESD interface. The device provides flexibility to provide SYSREF information either from dedicated pins or
through SPI register bits. SYSREF is asserted by a low-to-high transition on the SYSREF pins or a 0-to-1 change
in the ASSERT SYSREF REG bit when using SPI registers, as shown in Figure 70.
Input Clock
Divider
(Divide-by-4)
CLKIN
(CLKP-CLKM)
PDN SYSREF
(In Master Page)
DLL
NCO,
JESD Interface
(LMFC Counter)
MASK CLKDIV SYSREF
(In JESD Digital Page)
0
SYSREF
(SYSREFP-SYSREFM)
1
ASSERT SYSREF REG
(In Master Page)
SEL SYSREF REG
(In Master Page)
MASK NCO SYSREF
(In JESD Digital Page)
Figure 70. Using SYSREF to Reset the Clock Divider, the NCO, and the LMFC Counter
The ADC32RF45 samples the SYSREF signal on the input clock rising edge. Required setup and hold time are
listed in the Timing Requirements table. The input clock divider gets reset each time that SYSREF is asserted,
whereas the NCO phase and the LMFC counter of the JESD interface are reset on each SYSREF assertion after
disregarding the first two assertions, as shown in Table 1.
Table 1. Asserting SYSREF
SYSREF ASSERTION INDEX
28
ACTION
INPUT CLOCK DIVIDER
NCO PHASE
LMFC COUNTER
1
Gets reset
Does not get reset
Does not get reset
2
Gets reset
Does not get reset
Does not get reset
3
Gets reset
Gets reset
Gets reset
4 and onwards
Gets reset
Gets reset
Gets reset
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The SESREF use-cases can be classified broadly into two categories:
1. SYSREF is applied as aperiodic multi-shot pulses.
Figure 71 shows a case when only a counted number of pulses are applied as SYSREF to the ADC.
CLKIN
SYSREF
tDLL
(Must be Kept > 40 Ps)
1st SYSREF pulse.
Only the input clock
divider is reset.
2nd SYSREF pulse. If
the MASK CLKDIV bit is
set, the clock divider
ignores this pulse and
any subsequent
SYSREF pulses.
3rd SYSREF pulse.
The NCO phase and
LMFC counter are reset.
4th SYSREF pulse (and
subsequent pulses).
Ignored by the input clock
divider, NCO, and the JESD
interface.
1 (The input clock divider ignores the SYSREF pulses.)
MASK CLKDIV SYSREF Register Bit
0
1 (The NCO and LMFC counter of the JESD interface
ignore the SYSREF pulses.)
MASK NCO SYSREF Register Bit(1)
(1)
0
Alternatively, the SYSREF buffer can be powered down with the PDN SYSREF bit.
Figure 71. SYSREF Used as a Periodic, Finite Number of Pulses
After the first SYSREF pulse is applied, allow the DLL in the clock path to settle by waiting for the tDLL time (>
40 µs) before applying the second pulse. During this time, mask the SYSREF going to the input clock divider
by setting the MASK CLKDIV SYSREF bit so that the divider output phase remains stable. The NCO phase
and LMFC counter are reset on the third SYSREF pulse. After the third SYSREF pulse, the SYSREF going
to the NCO and JESD block can be disabled by setting the MASK NCO SYSREF bit to avoid any unwanted
resets.
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2. SYSREF is applied as a periodic pulse.
Figure 72 shows how SYSREF can be applied as a continuous periodic waveform.
Mask SYSREF to the NCO after
resetting the NCO phase.
The NCO phase is reset here for
the last time.
Then, the NCO mask is set high to
ignore further SYSREF pulses.
CLKIN
SYSREF(1)
Time > tDLL + 2 x tSYSREF
1st SYSREF pulse.
The input clock divider
is reset.
1 (The NCO and LMFC counter of the JESD
interface ignore the SYSREF pulses.)
MASK NCO SYSREF Register Bit(2)
0
(1)
tSYSREF is a period of the SYSREF waveform.
(2)
Alternatively, the SYSREF buffer can be powered down using the PDN SYSREF bit.
Figure 72. SYSREF Used as a Periodic Waveform
After applying the SYSREF signal, DLL must be allowed to lock, and the NCO phase and LMFC counter
must be allowed to reset by waiting for at least the tDLL (40 µs) + 2 × tSYSREF time. Then, the SYSREF going
to the NCO and JESD can be masked by setting the MASK NCO SYSREF register bit.
8.3.3.2 Frequency of the SYSREF Signal
When SYSREF is a periodic signal, its frequency is required to be a sub-harmonic of the internal local multiframe clock (LMFC) frequency, as described in Equation 1. The LMFC frequency is determined by the selected
decimation, frames per multi-frame setting (K), samples per frame (S), and device input clock frequency.
SYSREF = LMFC / N
where
•
N is an integer value (1, 2, 3, and so forth)
(1)
In order for the interleaving correction engine to synchronize properly, the SYSREF frequency must also be a
multiple of fS / 64. Table 2 provides a summary of the valid LMFC clock settings.
Table 2. . SYSREF and LMFC Clock Frequency
OPERATING MODE
LMFS SETTING
LMFC CLOCK FREQUENCY
SYSREF FRQUENCY
Bypass mode
82820
fS (1) / (20 × K)
fS / (N × LCM (2) (64, 20 × K (3)))
Bypass mode
8224
fS/(4 × K)
fS / (N × LCM (64, 4 × K))
Decimation
(1)
(2)
(3)
(4)
(5)
Various
fS / (D × S
(4)
× K)
fS / (N × LCM (64, D (5) × S × K))
fS = sampling (device) clock frequency.
LCM = least-common multiple.
K = number of frames per multi-frame.
S = samples per frame.
D = decimation ratio.
The SYSREF signal is recommended to be a low-frequency signal less than 5 MHz in order to reduce coupling to
the signal path both on the printed circuit board (PCB) as well as internal to the device.
30
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Example 1: fS = 3.0 GSPS, Bypass Mode (LMFS = 82820), K = 16
SYSREF = 3.0 GSPS / LCM (64, 20 × 16) / N = 9.375 MHz / N
Operate SYSREF at 4.6875 MHz (effectively divide-by-640, N = 2)
Example 2: fS = 3.0 GSPS, Divide-by-4 (LMFS = 8411), K = 16
SYSREF = 3.0 GSPS / LCM (4 ,64, 16) = 46.875 MHz / N
Operate SYSREF at 2.929688 MHz (effectively divide-by-1024, N = 16)
For proper device operation, disable the SYSREF signal after the JESD synchronization is established.
8.3.4 DDC Block
The ADC32RF45 provides a sophisticated on-chip, digital down converter (DDC) block that can be controlled
through SPI register settings and the general-purpose input/output (GPIO) pins. The DDC block supports two
basic operating modes: receiver (RX) mode with single- or dual-band DDC and wide-bandwidth observation
receiver mode.
Each ADC channel is followed by two DDC chains consisting of the digital filter along with a complex digital mixer
with a 16-bit numerically-controlled oscillator (NCO), as shown in Figure 73. The NCOs allow accurate frequency
tuning within the Nyquist zone prior to the digital filtering. One DDC chain is intended for supporting a dual-band
DDC configuration in receiver mode and the second DDC chain supports the wide-bandwidth output option for
the observation configuration. At any given time, either the single-band DDC, the dual-band DDC, or the
wideband DDC can be enabled. Furthermore, three different NCO frequencies can be selected on that path and
are quickly switched using the SPI or the GPIO pins to enable wide-bandwidth observation in a multi-band
application.
fOUT / 4
NCO 1,
16 Bits
NCO 2,
16 Bits
NCO 3,
16 Bits
IQ data
Real[ ]
GPIO
3 GSPS
ADC
IQ data, 3 GSPS
LPF
2,3
LPF
2
LPF
N/2
LPF
2
Wideband IQ Output
RX1 IQ Output
Real[ ]
IQ data
Wideband Real Output
RX1 Real Output
JESD204B
fOUT / 4
IQ 3 GSPS
LPF
NCO 4,
16 Bits
N/2
RX2 IQ Output
2
LPF
IQ data
SYSREF
Real[ ]
RX2 Real Output
fOUT / 4
NOTE: Red traces show SYSREF going to the NCO blocks.
Figure 73. DDC Chains Overview (One ADC Channel Shown)
Additionally, the decimation filter block provides the option to convert the complex output back to real format at
twice the decimated, complex output rate. The filter response with a real output is identical to a complex output.
The band is centered in the middle of the Nyquist zone (mixed with fOUT / 4) based on a final output data rate of
fOUT.
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8.3.4.1 Operating Mode: Receiver
In receiver mode, the DDC block can be configured to single- or dual-band operation, as shown in Figure 74.
Both DDC chains use the same decimation filter setting and the available options are discussed in the
Decimation Filters section. The decimation filter setting also directly affects the interface rate and number of
lanes of the JESD204B interface.
fOUT / 4
NCO 1,
16 Bits
NCO 2,
16 Bits
NCO 3,
16 Bits
IQ data
Real[ ]
GPIO
3 GSPS
IQ data, 3 GSPS
ADC
LPF
2,3
LPF
2
LPF
N/2
LPF
2
Wideband IQ Output
RX1 IQ Output
Real[ ]
IQ data
Wideband Real Output
RX1 Real Output
JESD204B
fOUT / 4
IQ 3 GSPS
LPF
NCO 4,
16 Bits
N/2
RX2 IQ Output
2
LPF
IQ data
SYSREF
Real[ ]
RX2 Real Output
fOUT / 4
NOTE: Red traces show SYSREF going to the NCO blocks.
Figure 74. Decimation Filter Option for Single- or Dual-Band Operation
32
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8.3.4.2 Operating Mode: Wide-Bandwidth Observation Receiver
This mode is intended for using a DDC with a wide bandwidth output, but for multiple bands. This mode uses a
single DDC chain where up to three NCOs can be used to perform wide-bandwidth observation in a multi-band
environment, as shown in Figure 75. The three NCOs can be switched dynamically using either the GPIO pins or
an SPI command. All three NCOs operate continuously to ensure phase continuity; however, when the NCO is
switched, the output data are invalid until the decimation filters are completely flushed with data from the new
band.
fOUT / 4
NCO 1,
16 Bits
NCO 2,
16 Bits
NCO 3,
16 Bits
IQ data
Real[ ]
GPIO
3 GSPS
ADC
IQ data, 3 GSPS
LPF
2,3
LPF
2
LPF
N/2
LPF
2
Wideband IQ Output
RX1 IQ Output
Real[ ]
IQ data
Wideband Real Output
RX1 Real Output
JESD204B
fOUT / 4
IQ 3 GSPS
LPF
NCO 4,
16 Bits
N/2
RX2 IQ Output
2
LPF
IQ data
SYSREF
Real[ ]
RX2 Real Output
fOUT / 4
NOTE: Red traces show SYSREF going to the NCO blocks.
Figure 75. Decimation Filter Implementation for Single-Band and Wide-Bandwidth Mode
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8.3.4.3 Decimation Filters
The stop-band rejection of the decimation filters is approximately 90 dB with a pass-band bandwidth of
approximately 80%. Table 3 gives an overview of the pass-band bandwidth depending on decimation filter setting
and ADC sampling rate.
Table 3. Decimation Filter Summary and Maximum Available Output Bandwidth
BANDWIDTH
DECIMATION
SETTING
NO. OF DDCS
AVAILABLE
PER
CHANNEL
NOMINAL
PASSBAND
GAIN
3 dB
(%)
1 dB
(%)
Divide-by-4
complex
1
–0.4 dB
90.9
Divide-by-6
complex
1
–0.65 dB
Divide-by-8
complex
2
Divide-by-9
complex
34
ADC SAMPLE RATE = N MSPS
ADC SAMPLE RATE = 3 GSPS
OUTPUT RATE
(MSPS) PER
BAND
OUTPUT
BANDWIDTH
(MHz) PER
BAND
COMPLEX
OUTPUT RATE
(MSPS) PER
BAND
OUTPUT
BANDWIDTH
(MHz) PER
BAND
86.8
N / 4 complex
0.4 × N / 2
750
600
90.6
86.1
N / 6 complex
0.4 × N / 3
500
400
–0.27 dB
91.0
86.8
N / 8 complex
0.4 × N / 4
375
300
2
–0.45 dB
90.7
86.3
N / 9 complex
0.4 × N / 4.5
333.3
266.6
Divide-by-10
complex
2
–0.58 dB
90.7
86.3
N / 10 complex
0.4 × N / 5
300
240
Divide-by-12
complex
2
–0.55 dB
90.7
86.4
N / 12 complex
0.4 × N / 6
250
200
Divide-by-16
complex
2
–0.42 dB
90.8
86.4
N / 16 complex
0.4 × N / 8
187.5
150
Divide-by-18
complex
2
–0.83 dB
91.2
87.0
N / 18 complex
0.4 × N / 9
166.6
133
Divide-by-20
complex
2
–0.91 dB
91.2
87.0
N / 20 complex
0.4 × N / 10
150
120
Divide-by-24
complex
2
–0.95 db
91.1
86.9
N / 24 complex
0.4 × N / 12
125
100
Divide-by-32
complex
2
–0.78 dB
91.1
86.8
N / 32 complex
0.4 × N / 16
93.75
75
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A dual-band example with a divide-by-8 complex is shown in Figure 76.
NCO 1,
16 Bits
Band 1
Filter
ADC
3 GSPS
IQ 3 GSPS
IQ 3 GSPS
IQ
750 MSPS
8
IQ
750 MSPS
8
IQ Output
Band 1
IQ Output
Band 2
fS/16
Filter
NCO 2,
16 Bits
Band 2
Band 2
fS/4
Band 1
fS/16
NCO 2
NCO 1
fS/2
Figure 76. Dual-Band Example
The decimation filter responses normalized to the ADC sampling clock are illustrated in Figure 76 to Figure 99
and can be interpreted as follows:
Each figure contains the filter pass-band, transition bands, and alias bands, as shown in Figure 77. The x-axis in
Figure 77 shows the offset frequency (after the NCO frequency shift) normalized to the ADC sampling clock
frequency.
For example, in the divide-by-4 complex, the output data rate is an fS / 4 complex with a Nyquist zone of fS / 8 or
0.125 × fS. The transition band is centered around 0.125 × fS and the alias transition band is centered at 0.375 ×
fS. The alias bands that alias on top of the wanted signal band are centered at 0.25 × fS and 0.5 × fS (and are
colored in red).
The decimation filters of the ADC32RF45 provide greater than 90-dB attenuation for the alias bands.
Band That Folds Back On
Top of Transition Band
Filter
Transition
Band
Bands That Aliases On
Top of Signal Band
Figure 77. Interpretation of the Decimation Filter Plots
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8.3.4.3.1 Divide-by-4
Peak-to-peak pass-band ripple: approximately 0.22 dB
0
0
Passband
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-0.2
-40
Attenuation (dB)
Attenuation (dB)
-20
-0.1
-60
-80
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-100
-0.9
-120
-1
0
0.1
0.2
0.3
Frequency
0.4
0.5
0
0.02
0.04
D023
Figure 78. Divide-by-4 Filter Response
0.06
Frequency
0.08
0.1
0.12
D024
Figure 79. Divide-by-4 Filter Response (Zoomed)
8.3.4.3.2 Divide-by-6
Peak-to-peak pass-band ripple: approximately 0.38 dB
0
0
Pass Band
Transition Band
Alias Band
Attn Spec
Pass Band
Transition Band
-0.2
-40
Attenuation (dB)
Attenuation (dB)
-20
-0.1
-60
-80
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-100
-0.9
-120
-1
0
0.1
0.2
0.3
Frequency
0.4
0.5
0
0.01
0.02
0.03
D025
Figure 80. Divide-by-6 Filter Response
0.04 0.05
Frequency
0.06
0.07
0.08
D026
Figure 81. Divide-by-6 Filter Response (Zoomed)
8.3.4.3.3 Divide-by-8
Peak-to-peak pass-band ripple: approximately 0.25 dB
0
0
Pass Band
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-0.2
-40
Attenuation (dB)
Attenuation (dB)
-20
-0.1
-60
-80
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-100
-0.9
-120
-1
0
0.1
0.2
0.3
Frequency
0.4
0.5
Figure 82. Divide-by-8 Filter Response
36
0
D027
0.01
0.02
0.03
Frequency
0.04
0.05
0.06
D028
Figure 83. Divide-by-8 Filter Response (Zoomed)
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8.3.4.3.4 Divide-by-9
Peak-to-peak pass-band ripple: approximately 0.39 dB
0
0
Pass Band
Transition Band
Alias Band
Attn Spec
Attenuation (dB)
-20
Pass Band
Transition Band
-0.1
-0.2
Attenuation (dB)
-40
-60
-80
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-100
-0.9
-120
-1
0
0.1
0.2
0.3
Frequency
0.4
0.5
0
0.01
D029
Figure 84. Divide-by-9 Filter Response
0.02
0.03
Frequency
0.04
0.05
D030
Figure 85. Divide-by-9 Filter Response (Zoomed)
8.3.4.3.5 Divide-by-10
Peak-to-peak pass-band ripple: approximately 0.39 dB
0
0
Pass Band
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-0.2
-40
Attenuation (dB)
Attenuation (dB)
-20
-0.1
-60
-80
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-100
-0.9
-120
-1
0
0.1
0.2
0.3
Frequency
0.4
0.5
0
0.01
D029
Figure 86. Divide-by-10 Filter Response
0.02
0.03
Frequency
0.04
0.05
D032
Figure 87. Divide-by-10 Filter Response (Zoomed)
8.3.4.3.6 Divide-by-12
Peak-to-peak pass-band ripple: approximately 0.36 dB
0
0
Passband
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-0.2
-40
Attenuation (dB)
Attenuation (dB)
-20
-0.1
-60
-80
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-100
-0.9
-120
-1
0
0.1
0.2
0.3
Frequency
0.4
0.5
0
D033
Figure 88. Divide-by-12 Filter Response
0.005
0.01
0.015 0.02 0.025
Frequency
0.03
0.035
0.04
D034
Figure 89. Divide-by-12 Filter Response (Zoomed)
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8.3.4.3.7 Divide-by-16
Peak-to-peak pass-band ripple: approximately 0.29 dB
0
0
Pass Band
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-0.2
-40
Attenuation (dB)
Attenuation (dB)
-20
-0.1
-60
-80
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-100
-0.9
-120
-1
0
0.1
0.2
0.3
Frequency
0.4
0.5
0
0.005
0.01
D035
Figure 90. Divide-by-16 Filter Response
0.015 0.02 0.025
Frequency
0.03
0.035
0.04
D036
Figure 91. Divide-by-16 Filter Response (Zoomed)
8.3.4.3.8 Divide-by-18
Peak-to-peak pass-band ripple: approximately 0.33 dB
0
0
Pass Band
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-0.2
-40
Attenuation (dB)
Attenuation (dB)
-20
-0.1
-60
-80
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-100
-0.9
-120
-1
0
0.1
0.2
0.3
Frequency
0.4
0.5
0
0.005
D037
Figure 92. Divide-by-18 Filter Response
0.01
0.015
Frequency
0.02
0.025
D038
Figure 93. Divide-by-18 Filter Response (Zoomed)
8.3.4.3.9 Divide-by-20
Peak-to-peak pass-band ripple: approximately 0.32 dB
0
0
Pass Band
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-0.2
-40
Attenuation (dB)
Attenuation (dB)
-20
-60
-80
-0.4
-0.6
-0.8
-1
-100
-1.2
-120
-1.4
0
0.1
0.2
0.3
Frequency
0.4
0.5
Figure 94. Divide-by-20 Filter Response
38
0
D039
0.005
0.01
0.015
Frequency
0.02
0.025
D040
Figure 95. Divide-by-20 Filter Response (Zoomed)
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8.3.4.3.10 Divide-by-24
Peak-to-peak pass-band ripple: approximately 0.30 dB
0
0
Pass Band
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-0.2
-40
Attenuation (dB)
Attenuation (dB)
-20
-60
-80
-0.4
-0.6
-0.8
-1
-100
-1.2
-120
-1.4
0
0.1
0.2
0.3
Frequency
0.4
0.5
0
0.005
D041
Figure 96. Divide-by-24 Filter Response
0.01
0.015
Frequency
0.02
0.025
D042
Figure 97. Divide-by-24 Filter Response (Zoomed)
8.3.4.3.11 Divide-by-32
Peak-to-peak pass-band ripple: approximately 0.24 dB
0
0
Pass Band
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-0.2
-40
Attenuation (dB)
Attenuation (dB)
-20
-0.1
-60
-80
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-100
-0.9
-120
-1
0
0.1
0.2
0.3
Frequency
0.4
0.5
0
D043
Figure 98. Divide-by-32 Filter Response
0.005
0.01
Frequency
0.015
0.02
D044
Figure 99. Divide-by-32 Filter Response (Zoomed)
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8.3.4.3.12 Latency with Decimation Options
Device latency in 12-bit bypass mode (with LMFS = 8224) is 424 clock cycles. When the DDC option is used,
latency increases as a result of decimation filters, as described in Table 4.
Table 4. Latency with different Decimation options
DECIMATION OPTION
TOTAL LATENCY, DEVICE CLOCK CYCLES
Divide-by-4
516
Divide-by-6
746
Divide-by-8
621
Divide-by-9
763.5
Divide-by-10
811
Divide-by-12
897
Divide-by-16
1045
Divide-by-18
1164
Divide-by-20
1256
Divide-by-24
1443
Divide-by-32
1773
8.3.4.4 Digital Multiplexer (MUX)
The ADC32RF45 supports a mode where the output data of the ADC channel A can be routed internally to the
digital blocks of both channel A and channel B. The ADC channel B can be powered down as shown in
Figure 100. In this manner, the ADC32RF45 can be configured as a single-channel ADC with up to four
independent DDC chains or two wideband DDC chains. All decimation filters and JESD204B format
configurations are identical to the two ADC channel operation.
N
ADC A
To JESD ChA
N
NCO
NCO
N
ADC B
To JESD ChB
N
NCO
NCO
Figure 100. Digital Multiplexer Option
8.3.4.5 Numerically-Controlled Oscillators (NCOs) and Mixers
The ADC32RF45 is equipped with three independent, complex NCOs per ADC channel. The oscillator generates
a complex exponential sequence, as shown in Equation 2.
x[n] = e–jωn
where
•
40
frequency (ω) is specified as a signed number by the 16-bit register setting
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The complex exponential sequence is multiplied by the real input from the ADC to mix the desired carrier down
to 0 Hz.
Each ADC channel has two DDCs. The first DDC has three NCOs and the second DDC has one NCO. The first
DDC can dynamically select one of the three NCOs based on the GPIO pin or SPI selection. In wide-bandwidth
mode (lower decimation factors, for example, 4 and 6), there can only be one DDC for each ADC channel. The
NCO frequencies can be programmed independently through the DDCx, NCO[4:1], and the MSB and LSB
register settings.
The NCO frequency setting is set by the 16-bit register value given by Equation 3:
DDCxNCOy u fS
fNCO
216
where
•
•
x = 0, 1
y = 1 to 4
(3)
For example:
If fS = 3 GSPS, then the NCO register setting = 38230 (decimal).
Thus, fNCO is defined by Equation 4:
3 GSPS
fNCO 38230 u
1750.03 MHz
216
(4)
Any register setting changes that occur after the JESD204B interface is operational results in a non-deterministic
NCO phase. If a deterministic phase is required, the JESD204B interface must be reinitialized after changing the
register setting.
In bypass mode (when decimation filters are not used), the NCOs are powered down in order to avoid creating
unwanted spurs.
8.3.5 NCO Switching
The first DDC (DDC0) on each ADC channel provides three different NCOs that can be used for phase-coherent
frequency hopping. This feature is available in both single-band and dual-band mode, but only affects DDC0.
The NCOs can be switched through an SPI control or by using the GPIO pins with the register configurations
shown in Table 5 for channel A (50xxh) and channel B (58Xxh). The assignment of which GPIO pin to use for
INSEL0 and INSEL1 is done based on Table 6, using registers 5438h and 5C38h. The NCO selection is done
based on the logic selection on the GPIO pins; see Table 7 and Figure 101.
Table 5. NCO Register Configurations
REGISTER
ADDRESS
DESCRIPTION
NCO CONTROL THROUGH GPIO PINS
NCO SEL pin
500Fh, 580Fh
Selects the NCO control through the SPI (default) or a GPIO pin.
INSEL0, INSEL1
5438h, 5C38h
Selects which two GPIO pins are used to control the NCO.
NCO CONTROL THROUGH SPI CONTROL
NCO SEL pin
500Fh, 580Fh
Selects the NCO control through the SPI (default) or a GPIO pin.
NCO SEL
5010h, 5810h
Selects which NCO to use for DDC0.
Table 6. GPIO Pin Assignment
INSELx[1:0] (Where x = 0 or 1)
GPIO PIN SELECTED
00
GPIO4
01
GPIO1
10
GPIO3
11
GPIO2
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Table 7. NCO Selection
NCO SEL[1]
NCO SEL[0]
NCO SELECTED
0
0
NCO1
0
1
NCO2
1
0
NCO3
1
1
n/a
GPIO4
0
GPIO1
1
GPIO3
2
GPIO2
3
NCO1
0
NCO2
1
NCO3
2
N/A
3
NCO SEL[1:0]
0
1
INSEL1[1:0]
GPIO4
0
GPIO1
1
GPIO3
2
GPIO2
3
NCO for DDC1 of
channel x
NCO SEL PIN
INSEL0[1:0]
Figure 101. NCO Switching from GPIO and SPI
8.3.6 SerDes Transmitter Interface
Each 12.3-Gbps serializer, deserializer (SerDes) LVDS transmitter output requires ac-coupling between the
transmitter and receiver. Terminate the differential pair with 100-Ω resistance (that is, two 50-Ω resistors) as
close to the receiving device as possible to avoid unwanted reflections and signal degradation, as shown in
Figure 102.
0.1 PF
DA[3:0]P,
DB[3:0]P
R t = ZO
Transmission Line,
ZO
VCM
Receiver
R t = ZO
DA[3:0]M,
DB[3:0]M
0.1 PF
Figure 102. External Serial JESD204B Interface Connection
42
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8.3.7 Eye Diagrams
Figure 103 and Figure 104 show the serial output eye diagrams of the ADC32RF45 at 5.0 Gbps and 12 Gbps
against the JESD204B mask.
Figure 103. Data Eye at 5 Gbps
Figure 104. Data Eye at 12 Gbps
8.3.8 Alarm Outputs: Power Detectors for AGC Support
The GPIO pins can be configured as alarm outputs for channels A and B. The ADC32RF45 supports three
different power detectors (an absolute peak power detector, crossing detector, and RMS power detector) as well
as fast overrange from the ADC. The power detectors operate off the full-rate ADC output prior to the decimation
filters.
8.3.8.1 Absolute Peak Power Detector
In this detector mode, the peak is computed over eight samples of the ADC output. Next, the peak for a block of
N samples (N × S`) is computed over a programmable block length and then compared against a threshold to
either set or reset the peak detector output (Figure 105 and Figure 106). There are two sets of thresholds and
each set has two thresholds for hysteresis. The programmable DWELL-time counter is used for clearing the
block detector alarm output.
BLKTHHH,
BLKTHHL,
BLKTHLH,
BLKTHLL
BLKPKDET
N = [1..216]
Output
of ADC
fS
Peak over 8
Samples
S`
fS / 8
Block:
Peak over N
Samples (S`)
fS / (8N)
>THHigh
>THLow
Hysteresis
and DWELL
BLKPKDETH
>TLHigh
>TLLow
Hysteresis
and DWELL
BLKPKDETL
DWELL
Figure 105. Peak Power Detector Implementation
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DWELL Time
THHH
THHL
BLKPKDET
Figure 106. Peak Power Detector Timing Diagram
Table 8 shows the register configurations required to set up the absolute peak power detector. The detector
operates in the fS / 8 clock domain; one peak sample is calculated over eight actual samples.
The automatic gain control (AGC) modes can be configured separately for channel A (54xxh) and channel B
(5Cxxh), although some registers are common in 54xxh (such as the GPIO pin selection).
Table 8. Registers Required for the Peak Power Detector
44
REGISTER
ADDRESS
PKDET EN
5400, 5C00h
BLKPKDET
5401h, 5402h,
5403h, 5C01h,
5C02h, 5C03h
Sets the block length N of number of samples (S`). Number of actual ADC samples is 8X this
value: N is 17 bits: 1 to 216.
BLKTHHH,
BLKTHHL,
BLKTHLH,
BLKTHLL
5407h, 5408h,
5409h, 540Ah,
5C07h, 5C08h,
5C09h, 5C0Ah
Sets the different thresholds for the hysteresis function values from 0 to 256 (where 256 is
equivalent to the peak amplitude).
For example: if BLKTHHH is to –2 dBFS from peak, 10(–2 / 20) × 256 = 203, then set 5407h and
5C07h = CBh.
DWELL
540Bh, 540Ch,
5C0Bh, 5C0Ch
When the computed block peak crosses the upper thresholds BLKTHHH or BLKTHLH, the peak
detector output flags are set. In order to be reset, the computed block peak must remain
continuously lower than the lower threshold (BLKTHHL or BLKTHLL) for the period specified by
the DWELL value. This threshold is 16 bits and is specified in terms of fS / 8 clock cycles.
OUTSEL
GPIO[4:1]
5432h, 5433h,
5434h, 5435h
Connects the BLKPKDETH, BLKPKDETL alarms to the GPIO pins; common register.
IODIR
5437h
RESET AGC
542Bh, 5C2Bh
DESCRIPTION
Enables peak detector
Selects the direction for the four GPIO pins; common register.
After configuration, reset the AGC module to start operation.
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8.3.8.2 Crossing Detector
In this detector mode the peak is computed over eight samples of the ADC output. Next, the peak for a block of
N samples (N × S`) is computed over a programmable block length and then the peak is compared against two
sets of programmable thresholds (with hysteresis). The crossing detector counts how many fS / 8 clock cycles
that the block detector outputs are set high over a programmable time period and compares the counter value
against the programmable thresholds. The alarm outputs are updated at the end of the time period, routed to the
GPIO pins, and held in that state through the next cycle, as shown in Figure 107 and Figure 108. Alternatively, a
2-bit format can be used but (because the ADC32RF45 has four GPIO pins available) this feature uses all four
pins for a single channel.
BLKTHHH,
BLKTHHL,
BLKTHLH,
BLKTHLL
BLKPKDET
N = [1..216]
ADC
Output
fS
Peak Over
8 Samples
S`
fS/8
Block:
Peak Over N
Samples (S`)
>THHigh
>THLow
Hysteresis
fS/(8N) and DWELL
>TLHigh
>TLLow
Hysteresis
and DWELL
FILT0LP
SEL
Time
Constant
1 or 2-Bit
Mode
2-Bit Mode
10: High
00: Mid
01: Low
IIR LPF
>FIL0THH
>FIL0THL
IIR PK DET0
IIR LPF
>FIL1THH
>FIL1THL
IIR PK DET1
Time
Constant
1 or 2-Bit
Mode
1-Bit Mode
With Hysteresis and Dwell
1: High
0: Low
BLKPKDETH
Combine
2-Bit Mode
BLKPKDETHL
BLKPKDETL
DWELL
Figure 107. Crossing Detector Implementation
Crossing Detector Time Period
THHH
THHL
BLKPKDET
Crossing Detector Counter Threshold
Crossing Detector Counter
IIR PK DET
Figure 108. Crossing Detector Timing Diagram
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Table 9 shows the register configurations required to set up the crossing detector. The detector operates in the
fS / 8 clock domain. The AGC modes can be configured separately for channel A (54xxh) and channel B (5Cxxh),
although some registers are common in 54xxh (such as the GPIO pin selection).
Table 9. Registers Required for the Crossing Detector Operation
46
REGISTER
ADDRESS
PKDET EN
5400h, 5C00h
BLKPKDET
5401h, 5402h, 5403h,
5C01h, 5C02h, 5C03h
Sets the block length N of number of samples (S`).
Number of actual ADC samples is 8X this value: N is 17 bits: 1 to 216.
BLKTHHH, BLKTHHL,
BLKTHLH, BLKTHLL
5407h, 5408h, 5409h,
540Ah, 5C07h, 5C08h,
5C09h, 5C0Ah
Sets the different thresholds for the hysteresis function values from 0 to 256
(where 256 is equivalent to the peak amplitude).
For example: if BLKTHHH is to –2 dBFS from peak, 10(–2 / 20) × 256 = 203, then
set 5407h and 5C07h = CBh.
FILT0LPSEL
540Dh, 5C0Dh
Select block detector output or 2-bit output mode as the input to the interrupt
identification register (IIR) filter.
TIMECONST
540Eh, 540Fh,
5C0Eh, 5C0Fh
Sets the crossing detector time period for N = 0 to 15 as 2N × fS / 8 clock cycles.
The maximum time period is 32768 × fS / 8 clock cycles (approximately 87 µs at
3 GSPS).
FIL0THH, FIL0THL,
FIL1THH, FIL1THL
540Fh-5412h, 5C0Fh5C12h, 5416h-5419h,
5C16h-5C19h
Comparison thresholds for the crossing detector counter. These thresholds are 16bit thresholds in 2.14-signed notation. A value of 1 (4000h) corresponds to 100%
crossings, a value of 0.125 (0800h) corresponds to 12.5% crossings.
DWELLIIR
541Dh, 541Eh, 5C1Dh,
5C1Eh
DWELL counter for the IIR filter hysteresis.
IIR0 2BIT EN,
IIR1 2BIT EN
5413h, 54114h,
5C13h, 5C114h
OUTSEL GPIO[4:1]
5432h, 5433h,
5434h, 5435h
IODIR
5437h
RESET AGC
542Bh, 5C2Bh
DESCRIPTION
Enables peak detector
Enables 2-bit output format for the crossing detector.
Connects the IIRPKDET0, IIRPKDET1 alarms to the GPIO pins; common register.
Selects the direction for the four GPIO pins; common register.
After configuration, reset the AGC module to start operation.
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8.3.8.3 RMS Power Detector
In this detector mode the peak power is computed for a block of N samples over a programmable block length
and then compared against two sets of programmable thresholds (with hysteresis).
The RMS power detector circuit provides configuration options, as shown in Figure 109. The RMS power value
(1 or 2 bit) can be output onto the GPIO pins. In 2-bit output mode, two different thresholds are used whereas the
1-bit output provides one threshold together with hysteresis.
M = [1..216]
2-Bit Mode
10: High
00: Mid
01: Low
2-M
Output
of ADC
fS
Randomly
Pick 1 Out of
8 Samples
fS/8
^2
Accumulate
Over 2^M
Inputs
>THHigh
>THLow
Hysteresis
1 or 2-Bit
Mode
PWR DET
1-Bit Mode
With Hysteresis
1: High
0: Low
Figure 109. RMS Power Detector Implementation
Table 10 shows the register configurations required to set up the RMS power detector. The detector operates in
the fS / 8 clock domain. The AGC modes can be configured separately for channel A (54xxh) and channel B
(5Cxxh), although some registers are common in 54xxh (such as the GPIO pin selection).
Table 10. Registers Required for Using the RMS Power Detector Feature
REGISTER
ADDRESS
RMSDET EN
5420h, 5C20h
Enables RMS detector
DESCRIPTION
PWRDETACCU
5421h, 5C21h
Programs the block length to be used for RMS power computation. The block length
is defined in terms of fS / 8 clocks.
The block length can be programmed as 2M with M = 0 to 16.
PWRDETH,
PWRDETL
5422h, 5423h, 5424h,
5425h, 5C22h, 5C23h,
5C24h, 5C25h
RMS2BIT EN
5427h, 5C27h
Enables 2-bit output format for the RMS detector output.
OUTSEL GPIO[4:1]
5432h, 5433h,
5434h, 5435h
Connects the PWRDET alarms to the GPIO pins; common register.
IODIR
5437h
RESET AGC
542Bh, 5C2Bh
The computed average power is compared against these high and low thresholds.
One LSB of the thresholds represents 1 / 216. For example: is PWRDETH is set to
–14 dBFS from peak, [10(–14 / 20)]2 × 216 = 2609, then set 5422h, 5423h, 5C22h,
5C23h = 0A31h.
Selects the direction for the four GPIO pins; common register.
After configuration, reset the AGC module to start operation.
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8.3.8.4 GPIO AGC MUX
The GPIO pins can be used to control the NCO in wideband DDC mode or as alarm outputs for channel A and B.
The GPIO pins can be configured through the SPI control to output the alarm from the peak power (1 bit),
crossing detector (1 or 2 bit), faster overrange, or the RMS power output, as shown in Figure 110.
The programmable output MUX allows connecting any signal (including the NCO control) to any of the four GPIO
pins. These pins can be configured as outputs (AGC alarm) or inputs (NCO control) through SPI programming.
IIR PK DET0 [2]
IIR PK DET1 [2]
BLKPKDETH [1]
To GPIO
AGC Pins
BLKPKDETL [1]
FOVR
PWR DET [2]
OUTSEL GPIO[4:1]
Figure 110. GPIO Output MUX Implementation
8.3.9 Power-Down Mode
The ADC32RF45 provides a lot of configurability for the power-down mode. Power-down can be enabled using
the PDN pin or the SPI register writes.
8.3.10 ADC Test Pattern
The ADC32RF45 provides several different options to output test patterns instead of the actual output data of the
ADC in order to simplify the serial interface and system debug of the JESD204B digital interface link. The output
data path is shown in Figure 111.
Digital Block
ADC Section
ADC
Interleaving
Engine
Transport Layer
DDC
Decimation
Filter Block
Test
Patterns
12-bit
RAMP
Link Layer
PHY Layer
Data Mapping
Frame
Construction
Scrambler
1 + x14 + x15
JESD204B Long
Transport Layer
Test Pattern
8b, 10b
Encoding
Serializer
JESD204B
Link Layer
Test Pattern
Figure 111. Test Pattern Generator Implementation
8.3.10.1 Digital Block
The ADC test pattern replaces the actual output data of the ADC. The test patterns listed in Table 11 are
available when the DDC is enabled and located in register 37h of the decimation filter page. When programmed,
the test patterns are output for each converter (M) stream. The number of converter streams per channel
increases by 2 when complex (I, Q) output or dual-band DDC is selected. The test patterns can be synchronized
for both ADC channels using the SYSREF signal.
Additionally, a 12-bit ramp test pattern is available in DDC bypass mode.
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NOTE
The number of converters increases in dual-band DDC mode and with a complex output.
Table 11. Test Pattern Options (Register 37h)
BIT
7-4
NAME
TEST PATTERN
DEFAULT
DESCRIPTION
0000
Test pattern outputs on channel A and B.
0000 = Normal operation using ADC output data
0001 = Outputs all 0s
0010 = Outputs all 1s
0011 = Outputs toggle pattern: output data are an alternating sequence of
10101010101010 and 01010101010101
0100 = Output digital ramp: output data increment by one LSB every
clock cycle from code 0 to 65535
0110 = Single pattern: output data are a custom pattern 1 (75h and 76h)
0111 Double pattern: output data alternate between custom pattern 1 and
custom pattern 2
1000 = Deskew pattern: output data are AAAAh
1001 = SYNC pattern: output data are FFFFh
8.3.10.2 Transport Layer
The transport layer maps the ADC output data into 8-bit octets and constructs the JESD204B frames using the
LMFS parameters. Tail bits or 0's are added when needed. Alternatively, the JESD204B long transport layer test
pattern can be substituted instead of the ADC data with the JESD frame, as shown in Table 12.
Table 12. Transport Layer Test Mode EN (Register 01h)
BIT
4
NAME
TESTMODE EN
DEFAULT
DESCRIPTION
0
Generates long transport layer test pattern mode according
to section 5.1.6.3 of the JESD204B specification.
0 = Test mode disabled
1 = Test mode disabled
8.3.10.3 Link Layer
The link layer contains the scrambler and the 8b, 10b encoding of any data passed on from the transport layer.
Additionally, the link layer also handles the initial lane alignment sequence that can be manually restarted.
The link layer test patterns are intended for testing the quality of the link (jitter testing and so forth). The test
patterns do not pass through the 8b, 10b encoder and contain the options listed in Table 13.
Table 13. Link Layer Test Mode (Register 03h)
BIT
7-5
NAME
LINK LAYER TESTMODE
DEFAULT
DESCRIPTION
000
Generates a pattern according to section 5.3.3.8.2 of the
JESD204B document.
000 = Normal ADC data
001 = D21.5 (high-frequency jitter pattern)
010 = K28.5 (mixed-frequency jitter pattern)
011 = Repeat the initial lane alignment (generates a K28.5
character and repeats lane alignment sequences
continuously)
100 = 12-octet random pattern (RPAT) jitter pattern
Furthermore, a 215 pseudo-random binary sequence (PRBS) can be enabled by setting up a custom test pattern
(AAAAh) in the ADC section and running AAAAh through the 8b, 10b encoder with scrambling enabled.
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8.4 Device Functional Modes
8.4.1 Device Configuration
The ADC32RF45 can be configured using a serial programming interface, as described in the Serial Interface
section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down modes.
8.4.2 JESD204B Interface
The ADC32RF45 supports device subclass 1 with a maximum output data rate of 12.5 Gbps for each serial
transmitter.
An external SYSREF signal is used to align all internal clock phases and the local multiframe clock to a specific
sampling clock edge. This alignment allows synchronization of multiple devices in a system and minimizes timing
and alignment uncertainty. The SYNCB input is used to control the JESD204B SerDes blocks, as shown in
Figure 112.
Depending on the ADC sampling rate, the JESD204B output interface can be operated with one, two, or four
lanes per ADC channel. The JESD204B setup and configuration of the frame assembly parameters is controlled
through the SPI interface.
SysRef
SYNCB
INA
JESD
204B
JESD204B
D[3:0]
INB
JESD
204B
JESD204B
D[3:0]
Sample Clock
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Figure 112. JESD Signal Overview
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Device Functional Modes (continued)
The JESD204B transmitter block consists of the transport layer, the data scrambler, and the link layer, as shown
in Figure 113. The transport layer maps the ADC output data into the selected JESD204B frame data format and
manages if the ADC output data or test patterns are transmitted. The link layer performs the 8b, 10b data
encoding as well as the synchronization and initial lane alignment using the SYNC input signal. Optionally, data
from the transport layer can be scrambled.
JESD204B Block
Transport Layer
Link Layer
Frame Data
Mapping
Scrambler
1+x14+x15
Test Patterns
8b, 10b
Encoding
Comma Characters
Initial Lane
Alignment
D[3:0]
SYNCB
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Figure 113. JESD Digital Block Implementation
8.4.2.1 JESD204B Initial Lane Alignment (ILA)
The receiving device starts the initial lane alignment process by deasserting the SYNCB signal. The SYNCB
signal can be issued using the SYNCB input pins or by setting the proper SPI bits. When a logic low is detected
on the SYNCB input, the ADC32RF45 starts transmitting comma (K28.5) characters to establish the code group
synchronization, as shown in Figure 114.
When synchronization completes, the receiving device reasserts the SYNCB signal and the ADC32RF45 starts
the initial lane alignment sequence with the next local multiframe clock boundary. The ADC32RF45 transmits
four multiframes, each containing K frames (K is SPI programmable). Each of the multiframes contains the frame
start and end symbols. The second multiframe also contains the JESD204 link configuration data.
SYSREF
LMFC Clock
LMFC Boundary
Multi
Frame
SYNCb
Transmit Data
xxx
K28.5
Code Group
Synchronization
K28.5
ILA
ILA
Initial Lane Alignment
DATA
DATA
Data Transmission
Figure 114. JESD Internal Timing Information
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Device Functional Modes (continued)
8.4.2.2 JESD204B Frame Assembly
The JESD204B standard defines the following parameters:
• F is the number of octets per frame clock period
• L is the number of lanes per link
• M is the number of converters for the device
• S is the number of samples per frame
8.4.2.3 JESD204B Frame Assembly in Bypass Mode
Table 14 lists the available JESD204B formats and valid ranges for the ADC32RF45. The ranges are limited by
the SerDes line rate and the maximum ADC sample frequency. The sample alignment for the bypass modes on
the different lanes is shown in Table 15.
Table 14. JESD Mode Options: Bypass Mode
DECIMATION
SETTING
(Complex)
OUTPUT
RESOLUTION
(Bits)
L
M
F
S
12-BIT
MODE
PLL
MODE
JESD
MODE
0
JESD
MODE
1
JESD
MODE
2
12 (1)
8
2
8
20
3
16X
3
0
14
8
2
2
4
0
20X
1
0
Bypass
(1)
MAX fCLK
(Gsps)
RATIO
[fSerDes / fCLK
(Gbps / GSPS)]
0
3
4
0
2.5
5
In full rate output, the two LSBs are truncated to a 12-bit output.
Table 15. JESD Sample Lane Alignments: Bypass Mode (1)
OUTPUT
LANE
(1)
52
LMFS = 8224
LMFS = 82820
DA0
A0[13:6]
A0[5:0], 00
A0[11:4]
A0[3:0],
A1[11:8]
A1[7:0]
A2[11:4]
A2[3:0],
A3[11:8]
A3[7:0]
A4[11:4]
A4[3:0],
0000
DA1
A1[13:6]
A1[5:0], 00
A5[11:4]
A5[3:0],
A6[11:8]
A6[7:0]
A7[11:4]
A7[3:0],
A8[11:8]
A8[7:0]
A9[11:4]
A9[3:0],
0000
DA2
A2[13:6]
A2[5:0], 00
A10[11:4]
A10[3:0],
A11[11:8]
A11[7:0]
A12[11:4]
A12[3:0],
A13[11:8]
A13[7:0]
A14[11:4]
A14[3:0],
0000
DA3
A3[13:6]
A3[5:0], 00
A15[11:4]
A15[3:0],
A16[11:8]
A16[7:0]
A17[11:4]
A17[3:0],
A18[11:8]
A18[7:0]
A19[11:4]
A19[3:0],
0000
DB0
B0[13:6]
B0[5:0], 00
B0[11:4]
B0[3:0],
B1[11:8]
B1[7:0]
B2[11:4]
B2[3:0],
B3[11:8]
B3[7:0]
B4[11:4]
B4[3:0],
0000
DB1
B1[13:6]
B1[5:0], 00
B5[11:4]
B5[3:0],
B6[11:8]
B6[7:0]
B7[11:4]
B7[3:0],
B8[11:8]
B8[7:0]
B9[11:4]
B9[3:0],
0000
DB2
B2[13:6]
B2[5:0], 00
B10[11:4]
B10[3:0],
B11[11:8]
B11[7:0]
B12[11:4]
B12[3:0],
B13[11:8]
B13[7:0]
B14[11:4]
B14[3:0],
0000
DB3
B3[13:6]
B3[5:0], 00
B15[11:4]
B15[3:0],
B16[11:8]
B16[7:0]
B17[11:4]
B17[3:0],
B18[11:8]
B18[7:0]
B19[11:4]
B19[3:0],
0000
Blue shading indicates channel A and yellow shading indicates channel B.
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8.4.2.4 JESD204B Frame Assembly with Decimation (Single-Band DDC): Complex Output
Table 16 lists the available JESD204B interface formats and valid ranges for the ADC32RF45 with decimation
(single-band DDC) when using a complex output format. The ranges are limited by the SerDes line rate and the
maximum ADC sample frequency. The sample alignment on the different lanes is shown in Table 17.
Table 16. JESD Mode Options: Single-Band Complex Output
DECIMATION
SETTING
(Complex)
Divide-by-4
Divide-by-6
Divide-by-8
Divide-by-9
Divide-by-10
Divide-by-12
Divide-by-16
Divide-by-18
NUMBER OF
ACTIVE DDCS
1 per channel
1 per channel
1 per channel
1 per channel
1 per channel
1 per channel
1 per channel
1 per channel
RATIO
[fSerDes / fCLK
(Gbps / GSPS)]
L
M
F
S
PLL
MODE
JESD
MODE0
JESD
MODE1
JESD
MODE2
8
4
1
1
20X
1
1
0
8
4
2
2
20X
1
0
0
4
4
2
1
40X
0
0
1
4
4
4
2
40X
2
0
0
8
4
1
1
20X
1
1
0
8
4
2
2
20X
1
0
0
4
4
2
1
40X
0
0
1
4
4
4
2
40X
2
0
0
4
4
2
1
20X
1
0
0
2
4
4
1
40X
2
0
0
5
4
4
2
1
20X
1
0
0
2.22
2
4
4
1
40X
2
0
0
4.44
4
4
2
1
20X
1
0
0
2
2
4
4
1
40X
2
0
0
4
4
4
2
1
20X
1
0
0
1.67
2
4
4
1
40X
2
0
0
3.33
4
4
2
1
20X
1
0
0
1.25
2
4
4
1
40X
2
0
0
2.5
4
4
2
1
20X
1
0
0
1.11
2
4
4
1
40X
2
0
0
2.22
4
4
2
1
20X
1
0
0
1
2
4
4
1
40X
2
0
0
2
2.5
5
1.67
3.33
2.5
Divide-by-20
1 per channel
Divide-by-24
1 per channel
4
4
2
1
20X
1
0
0
1.67
Divide-by-32
1 per channel
2
4
4
1
40X
2
0
0
1.25
Table 17. JESD Sample Lane Alignments: Single-Band Complex Output (1)
OUTPUT
LANE
LMFS
= 8411
DA0
AI0
[15:8]
AI0
[15:8]
AI0
[7:0]
AI0
[15:8]
AI0
[7:0]
DA1
AI0
[7:0]
AI1
[15:8]
AI1
[7:0]
AQ0
[15:8]
AQ0
[7:0]
DA2
AQ0
[15:8]
AQ0
[15:8]
AQ0
[7:0]
DA3
AQ0
[7:0]
AQ1
[15:8]
AQ1
[7:0]
DB0
BI0
[15:8]
BI0
[15:8]
BI0
[7:0]
BI0
[15:8]
BI0
[7:0]
DB1
BI0
[7:0]
BI1
[15:8]
BI1
[7:0]
BQ0
[15:8]
BQ0
[7:0]
DB2
BQ0
[15:8]
BQ0
[15:8
BQ0
[7:0]
DB3
BQ0
[7:0]
BQ1
[15:8]
BQ1
[7:0]
(1)
LMFS = 8422
LMFS = 4421
20X
LMFS = 4421
40X
LMFS = 4442
LMFS = 2441
AI0
[15:8]
AI0
[7:0]
AI0
[15:8]
AI0
[7:0]
AI1
[15:8]
AI1
[7:0]
AQ0
[15:8]
AQ0
[7:0]
AQ0
[15:8]
AQ0
[7:0]
AQ1
[15:8]
AQ1
[7:0]
BI0
[15:8]
BI0
[7:0]
BI0
[15:8]
BI0
[7:0]
BI1
[15:8]
BI1
[7:0]
BQ0
[15:8]
BQ0
[7:0]
BQ0
[15:8]
BQ0
[7:0]
BQ1
[15:8]
BQ1
[7:0]
AI0
[15:8]
AI0
[7:0]
AQ0
[15:8]
AQ0
[7:0]
BI0
[15:8]
BI0
[7:0]
BQ0
[15:8]
BQ0
[7:0]
Blue shading indicates channel A and yellow shading indicates channel B.
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8.4.2.5 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
Table 18 lists the available JESD204B formats and valid ranges for the ADC32RF45 with decimation (singleband DDC) when using real output format. The ranges are limited by the SerDes line rate and the maximum
ADC sample frequency. The sample alignment on the different lanes is shown in Table 19.
Table 18. JESD Mode Options: Single-Band Real Output (Wide Bandwidth)
DECIMATION
SETTING
(Complex)
NUMBER OF
ACTIVE DDCS
Divide-by-4
(Divide-by-2 real)
1 per channel
Divide-by-6
(Divide-by-3 real)
1 per channel
L
M
F
S
PLL
MODE
JESD
MODE0
JESD
MODE1
JESD
MODE2
RATIO
[fSerDes / fCLK
(Gbps / GSPS)]
8
2
2
4
20X
1
0
0
2.5
4
2
4
4
40X
2
0
0
4
2
1
1
40X
0
0
1
8
2
2
4
20X
1
0
0
4
2
4
4
40X
2
0
0
4
2
1
1
40X
0
0
1
5
1.67
3.33
Table 19. JESD Sample Lane Alignment: Single-Band Real Output (Wide Bandwidth) (1)
OUTPUT
LANE
(1)
54
LMFS = 8224
LMFS = 4244
LMFS = 4211
DA0
A0[15:8]
A0[7:0]
DA1
A1[15:8]
A1[7:0]
A0[15:8]
A0[7:0]
A1[15:8]
A1[7:0]
A0[15:8]
DA2
A2[15:8]
A2[7:0]
A2[15:8]
A2[7:0]
A3[15:8]
A3[7:0]
A0[7:0]
DA3
A3[15:8]
A3[7:0]
DB0
B0[15:8]
B0[7:0]
DB1
B1[15:8]
B1[7:0]
B0[15:8]
B0[7:0]
B1[15:8]
B1[7:0]
B0[15:8]
DB2
B2[15:8]
B2[7:0]
B0[15:8]
B2[7:0]
B3[15:8]
B3[7:0]
B0[7:0]
DB3
B3[15:8]
B3[7:0]
Blue shading indicates channel A and yellow shading indicates channel B.
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8.4.2.6 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
Table 20 lists the available JESD204B formats and valid ranges for the ADC32RF45 with decimation (dual-band
DDC) when using a complex output format. The sample alignment on the different lanes is shown in Table 21.
Table 20. JESD Mode Options: Single-Band Real Output
DECIMATION
SETTING
(Complex)
NUMBER OF
ACTIVE DDCS
Divide-by-8
(Divide-by-4 real)
1 per channel
Divide-by-9
(Divide-by-4.5 real)
Divide-by-10
(Divide-by-5 real)
1 per channel
1 per channel
Divide-by-12
(Divide-by-6 real)
1 per channel
Divide-by-16
(Divide-by-8 real)
1 per channel
Divide-by-18
(Divide-by-9 real)
1 per channel
Divide-by-20
(Divide-by-10 real)
1 per channel
Divide-by-24
(Divide-by-12 real)
1 per channel
Divide-by-32
(Divide-by-16 real)
1 per channel
L
M
F
S
PLL
MODE
JESD
MODE0
JESD
MODE1
JESD
MODE2
4
2
1
1
20X
1
1
0
4
2
2
2
20X
1
0
0
2
2
2
1
40X
0
0
1
2
2
4
2
40X
2
0
0
4
2
1
1
20X
1
1
0
4
2
2
2
20X
1
0
0
2
2
2
1
40X
0
0
1
2
2
4
2
40X
2
0
0
4
2
1
1
20X
1
1
0
4
2
2
2
20X
1
0
0
2
2
2
1
40X
0
0
1
2
2
4
2
40X
2
0
0
4
2
1
1
20X
1
1
0
4
2
2
2
20X
1
0
0
2
2
2
1
40X
0
0
1
2
2
4
2
40X
2
0
0
4
2
1
1
20X
1
1
0
4
2
2
2
20X
1
0
0
2
2
2
1
40X
0
0
1
2
2
4
2
40X
2
0
0
4
2
1
1
20X
1
1
0
4
2
2
2
20X
1
0
0
2
2
2
1
40X
0
0
1
2
2
4
2
40X
2
0
0
4
2
1
1
20X
1
1
0
4
2
2
2
20X
1
0
0
2
2
2
1
40X
0
0
1
2
2
4
2
40X
2
0
0
2
2
2
1
40X
0
0
1
2
2
4
2
40X
2
0
0
2
2
2
1
40X
0
0
1
2
2
4
2
40X
2
0
0
RATIO
[fSerDes / fCLK
(Gbps / GSPS)]
2.5
5
2.22
4.44
2
4
1.67
3.33
1.25
2.5
1.11
2.22
1
2
1.67
1.25
Table 21. JESD Sample Lane Assignment: Single-Band Real Output (1)
OUTPUT
LANE
LMFS =
4211
DA0
A0[15:8]
A0[15:8]
A0[7:0]
DA1
A0[7:0]
A1[15:8]
A1[7:0]
DB0
B0[15:8]
B0[15:8]
B0[7:0]
DB1
B0[7:0]
B1[15:8]
B1[7:0]
(1)
LMFS = 4222
LMFS = 2221
LMFS = 2242
A0 [15:8]
A0[7:0]
A0[15:8]
A0[7:0]
A1[15:8]
A1[7:0]
B0[15:8]
B0[7:0]
B0[15:8]
B0[7:0]
B1[15:8]
B1[7:0]
Blue shading indicates channel A and yellow shading indicates channel B.
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8.4.2.7 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Complex Output
Table 22 lists the available JESD204B formats and valid ranges for the ADC32RF45 with decimation (dual-band
DDC) when using a complex output format. The ranges are limited by the SerDes line rate and the maximum
ADC sample frequency. The sample alignment on the different lanes is shown in Table 23.
Table 22. JESD Mode Options: Dual-Band Complex Output
DECIMATION
SETTING
(Complex)
NUMBER OF
ACTIVE DDCS
Divide-by-8
2 per channel
Divide-by-9
2 per channel
Divide-by-10
2 per channel
Divide-by-12
2 per channel
Divide-by-16
Divide-by-18
2 per channel
2 per channel
L
M
F
S
PLL
MODE
JESD
MODE0
JESD
MODE1
JESD
MODE2
RATIO
[fSerDes / fCLK
(Gbps / GSPS)]
8
8
2
1
20X
1
0
0
2.5
4
8
4
1
40X
2
0
0
5
8
8
2
1
20X
1
0
0
2.22
4
8
4
1
40X
2
0
0
4.44
8
8
2
1
20X
1
0
0
2
4
8
4
1
40X
2
0
0
4
8
8
2
1
20X
1
0
0
1.67
4
8
4
1
40X
2
0
0
3.33
8
8
2
1
20X
1
0
0
1.25
4
8
4
1
40X
2
0
0
2.5
8
8
2
1
20X
1
0
0
1.11
4
8
4
1
40X
2
0
0
2.22
8
8
2
1
20X
1
0
0
1
4
8
4
1
40X
2
0
0
2
Divide-by-20
2 per channel
Divide-by-24
2 per channel
4
8
4
1
40X
2
0
0
1.67
Divide-by-32
2 per channel
4
8
4
1
40X
2
0
0
1.25
Table 23. JESD Sample Lane Assignment: Dual-Band Complex Output (1)
OUTPUT LANE
(1)
56
LMFS = 8821
LMFS = 4841
DA0
A10[15:8]
A10[7:0]
DA1
A1Q0[15:8]
A1Q0[7:0]
A1I0[15:8]
A1I0[7:0]
A1Q0[15:8]
A1Q0[7:0]
DA2
A2I0[15:8]
A2I0[7:0]
A2I0[15:8]
A2I0[7:0]
A2Q0[15:8]
A2Q0[7:0]
DA3
A2Q0[15:8]
A2Q0[7:0]
DB0
B1I0[15:8]
B1I0[7:0]
DB1
B1Q0[15:8]
B1Q0[7:0]
B1I0[15:8]
B1I0[7:0]
B1Q0[15:8]
B1Q0[7:0]
DB2
B2I0[15:8]
B2I0[7:0]
B2I0[15:8]
B2I0[7:0]
B2Q0[15:8]
B2Q0[7:0]
DB3
B2Q0[15:8]
B2Q0[7:0]
Blue and green shading indicates the two bands for channel A; yellow and orange shading indicates the two bands for channel B.
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8.4.2.8 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Real Output
Table 24 lists the available JESD204B formats and valid ranges for the ADC32RF45 with decimation (dual-band
DDC) when using real output format. The ranges are limited by the SerDes line rate and the maximum ADC
sample frequency. The sample alignment on the different lanes is shown in Table 25.
Table 24. JESD Mode Options: Dual-Band Real Output
DECIMATION
SETTING
(Complex)
NUMBER OF
ACTIVE DDCS
Divide-by-8
(Divide-by-4 real)
2 per channel
Divide-by-9
(Divide-by-4.5 real)
Divide-by-10
(Divide-by-5 real)
2 per channel
2 per channel
Divide-by-12
(Divide-by-6 real)
2 per channel
Divide-by-16
(Divide-by-8 real)
2 per channel
Divide-by-18
(Divide-by-9 real)
2 per channel
Divide-by-20
(Divide-by-10 real)
2 per channel
Divide-by-24
(Divide-by-12 real)
2 per channel
Divide-by-32
(Divide-by-16 real)
2 per channel
L
M
F
S
PLL
MODE
JESD
MODE0
JESD
MODE1
JESD
MODE2
8
4
1
1
20X
1
1
0
8
4
2
2
20X
1
0
0
4
4
2
1
40X
0
0
1
4
4
4
2
40X
2
0
0
8
4
1
1
20X
1
1
0
8
4
2
2
20X
1
0
0
4
4
2
1
40X
0
0
1
4
4
4
2
40X
2
0
0
8
4
1
1
20X
1
1
0
8
4
2
2
20X
1
0
0
4
4
2
1
40X
0
0
1
4
4
4
2
40X
2
0
0
8
4
1
1
20X
1
1
0
8
4
2
2
20X
1
0
0
4
4
2
1
40X
0
0
1
4
4
4
2
40X
2
0
0
8
4
1
1
20X
1
1
0
8
4
2
2
20X
1
0
0
4
4
2
1
40X
0
0
1
4
4
4
2
40X
2
0
0
8
4
1
1
20X
1
1
0
8
4
2
2
20X
1
0
0
4
4
2
1
40X
0
0
1
4
4
4
2
40X
2
0
0
8
4
1
1
20X
1
1
0
8
4
2
2
20X
1
0
0
4
4
2
1
40X
0
0
1
4
4
4
2
40X
2
0
0
4
4
2
1
40X
0
0
1
4
4
4
2
40X
2
0
0
4
4
2
1
40X
0
0
1
4
4
4
2
40X
2
0
0
RATIO
[fSerDes / fCLK
(Gbps / GSPS)]
2.5
5
2.22
4.44
2
4
1.67
3.33
1.25
2.5
1.11
2.22
1
2
1.67
1.25
Table 25. JESD Sample Lane Assignment: Dual-Band Complex Output (1)
(1)
OUTPUT
LANE
LMFS = 8411
DA0
A10[15:8]
A10[15:8]
A10[7:0]
DA1
A10[7:0]
A11[15:8]
A11[7:0]
A10[15:8]
A10[7:0]
A10[15:8]
A10[7:0]
A11[15:8]
A11[7:0]
DA2
A20[15:8]
A20[15:8]
A20[7:0]
A20[15:8]
A20[7:0]
A20[15:8]
A20[7:0]
A21[15:8]
A21[7:0]
DA3
A20[7:0]
A21[15:8]
A21[7:0]
DB0
B10[15:8]
B10[15:8]
B10[7:0]
DB1
B10[7:0]
B11[15:8]
B11[7:0]
B10[15:8]
B10[7:0]
B10[15:8]
B10[7:0]
B11[15:8]
B11[7:0]
DB2
B20[15:8]
B20[15:8]
B20[7:0]
B20[15:8]
B20[7:0]
B20[15:8]
B20[7:0]
B21[15:8]
B21[7:0]
DB3
B20[7:0]
B21[15:8]
B21[7:0]
LMFS = 8422
LMFS = 4421
LMFS = 4442
Blue and green shading indicates the two bands for channel A; yellow and orange shading indicates the two bands for channel B.
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8.4.3 Serial Interface
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins. Serially shifting bits into the
device is enabled when SEN is low. SDIN serial data are latched at every SCLK rising edge when SEN is active
(low), as shown in Figure 115. The interface can function with SCLK frequencies from 20 MHz down to low
speeds (of a few hertz) and also with a non-50% SCLK duty cycle, as shown in Table 26.
The SPI access uses 24 bits consisting of eight register data bits, 12 register address bits, and four special bits
to distinguish between read/write, page and register, and individual channel access, as described in Table 27.
Register Address [11:0]
SDIN
R/W
M
P
CH A11 A10 A9
A8
A7
A6
A5
A4
Register Data [7:0]
A3
A2
A1
A0
D7
D6
tSCLK
D5
D4
D3
D2
D1
D0
tDH
tDSU
SCLK
tSLOADH
tSLOADS
SEN
RESET
Figure 115. SPI Timing Diagram
Table 26. SPI Timing Information
MIN
TYP
UNIT
20
MHz
fSCLK
SCLK frequency (equal to 1 / tSCLK)
tSLOADS
SEN to SCLK setup time
50
ns
tSLOADH
SCLK to SEN hold time
50
ns
tDSU
SDIN setup time
10
ns
tDH
SDIN hold time
10
tSDOUT
Delay between SCLK falling edge to SDOUT
58
1
MAX
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ns
10
ns
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Table 27. SPI Input Description
SPI BIT
DESCRIPTION
OPTIONS
R/W bit
Read/write bit
0 = SPI write
1 = SPI read back
M bit
SPI bank access
0 = Analog SPI bank (master)
1 = All digital SPI banks (main digital, interleaving,
decimation filter, JESD digital, and so forth)
P bit
JESD page selection bit
0 = Page access
1 = Register access
CH bit
SPI access for a specific channel of the JESD SPI
bank
0 = Channel A
1 = Channel B
ADDR[11:0]
SPI address bits
—
DATA[7:0]
SPI data bits
—
Figure 116 shows the SDOUT timing when data are read back from a register. Data are placed on the SDOUT
bus at the SCLK falling edge so that the data can be latched at the SCLK rising edge by the external receiver.
SCLK
tSDOUT
SDOUT
Figure 116. SDOUT Timing
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8.4.3.1 Serial Register Write: Analog Bank
The internal register of the ADC32RF45 analog bank (Figure 117) can be programmed by:
1. Driving the SEN pin low.
2. Initiating a serial interface cycle selecting the page address of the register whose content must be written. To
select the master page: write address 0012h with 04h. To select the ADC page: write address 0011h with
FFh.
3. Writing the register content. When a page is selected, multiple registers located in the same page can be
programmed.
SDIN
0
0
0
R/W
M
P
Register Address [11:0]
0
CH A11 A10 A9
A8
A7
A6
A5
A4
Register Data [7:0]
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
RESET
Figure 117. SPI Write Timing Diagram for the Analog Bank
8.4.3.2 Serial Register Readout: Analog Bank
Contents of the registers located in the two pages of the analog bank (Figure 118) can be readback by:
1. Driving the SEN pin low.
2. Selecting the page address of the register whose content must be read. Master page: write address 0012h
with 04h. ADC page: write address 0011h with FFh.
3. Setting the R/W bit to 1 and writing the address to be read back.
4. Reading back the register content on the SDOUT pin. When a page is selected, the contents of multiple
registers located in same page can be readback.
SDIN
1
0
0
R/W
M
P
Register Address [11:0]
0
CH A11 A10 A9
A8
A7
A6
A5
A4
Register Data [7:0] = XX
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D4
D3
D2
D1
D0
SCLK
SEN
RESET
SDOUT
D7
D6
D5
SDOUT [7:0]
Figure 118. SPI Read Timing Diagram for the Analog Bank
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8.4.3.3 Serial Register Write: Digital Bank
The digital bank contains seven pages (Offset Corrector Page for channel A and B; Digital Gain Page for channel
A and B; Main digital Page for channel A and B; and JESD Digital Page). The timing for the individual page
selection is shown in Figure 119. The registers located in the pages of the digital bank can be programmed by:
1. Driving the SEN pin low.
2. Setting the M bit to 1 and specifying the page with with the desired register. There are seven pages in Digital
Bank. These pages can be selected by appropriately programming register bits DIGITAL BANK PAGE SEL,
located in addresses 002h, 003h, and 004h, using three consecutive SPI cycles. Addressing in a SPI cycle
begins with 4xxx when selecting a page from digital bank because the M bit must be set to 1.
– To select the offset corrector page channel A: write address 4004h with 61h, 4003h with 00h, and 4002h
with 00h.
– To select the offset corrector page channel B: write address 4004h with 61h, 4003h with 01h, and 4002h
with 00h.
– To select the digital gain page channel A: write address 4004h with 61h, 4003h with 00h, and 4002h with
05h.
– To select the digital gain page channel B: write address 4004h with 61h, 4003h with 01h, and 4002h with
05h.
– To select the main digital page channel A: write address 4004h with 68h, 4003h with 00h, and 4002h with
00h.
– To select the main digital page channel B: write address 4004h with 68h, 4003h with 01h, and 4002h with
00h.
– To select the JESD digital page: write address 4004h with 69h, 4003h with 00h, and 4002h with 00h.
SDIN
0
1
0
R/W
M
P
Register Address [11:0]
0
CH A11 A10 A9
A8
A7
A6
A5
A4
Register Data [7:0]
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
RESET
Figure 119. SPI Write Timing Diagram for Digital Bank Page Selection
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3. Writing into the desired register by setting both the M bit and P bit to 1. Write register content. When a page
is selected, multiple writes into the same page can be done. Addressing in an SPI cycle begins with 6xxx
when selecting a page from the digital bank because the M bit must be set to 1, as shown in Figure 120.
Note that the JESD digital page is common for both channels. The CH bit can be used to distinguish
between two channels when programming registers in the JESD digital page. When CH = 0, registers are
programmed for channel B; when CH = 1, registers are programmed for channel A. Thus, an SPI cycle to
program registers for channel B begins with 6xxx and channel A begins with 7xxx.
Register Address [11:0]
SDIN
0
1
1
0
R/W
M
P
CH
A11
A10
A9
A8
A7
A6
A5
A4
Register Data [7:0]
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
RESET
Figure 120. SPI Write Timing Diagram for Digital Bank Register Write
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8.4.3.4 Serial Register Readout: Digital Bank
Readback of the register in one of the digital banks (as shown in Figure 121) can be accomplished by:
1. Driving the SEN pin low.
2. Selecting the page in the digital page: follow step 2 in the Serial Register Write: Digital Bank section.
3. Set the R/W, M, and P bits to 1, select channel A or channel B, and write the address to be read back.
– JESD digital page: use the CH bit to select channel B (CH = 0) or channel A (CH = 1).
4. Read back the register content on the SDOUT pin. When a page is selected, multiple read backs from the
same page can be done.
SDIN
1
1
1
0
R/W
M
P
CH
Register Address [11:0]
A11
A10
A9
A8
A7
A6
A5
Register Data [7:0] = XX
A4
A3
A2
A1
A0
D7
D6
D5
D7
D6
D5
D4
D3
D2
D1
D0
D4
D3
D2
D1
D0
SCLK
SEN
RESET
SDOUT
SDOUT [7:0]
Figure 121. SPI Read Timing Diagram for the Digital Bank
8.4.3.5 Serial Register Write: Decimation Filter and Power Detector Pages
The decimation filter and power detector pages are special pages that accept direct addressing. The sampling
clock and SYSREF signal are required to properly configure the decimation settings. Registers located in these
pages can be programmed in one SPI cycle (Figure 122).
1. Drive the SEN pin low.
2. Directly write to the decimation filter or power detector pages. To program registers in these pages, set M = 1
and CH = 1. Additionally, address bit A[10] selects the decimation filter page (A[10] = 0) or the power
detector page (A[10] = 1). Address bit A[11] selects channel A (A[11] = 0) or channel B (A[11] = 1).
– Decimation filter page: write address 50xxh for channel A or 58xxh for channel B.
– Power detector page: write address 54xxh for channel A or 5Cxxh for channel B.
Example: Writing address 5001h with 02h selects the decimation filter page for channel A and programs
decimation factor of divide-by-8 (complex output).
SDIN
0
1
0
1
R/W
M
P
CH
0/1
0/1
A11 A10
0
0
A9
A8
Register Address [7:0]
A7
A6
A5
A4
A3
A2
A1
Register Data [7:0]
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
RESET
Figure 122. SPI Write Timing Diagram for the Decimation and Power Detector Pages
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8.5 Register Maps
The ADC32RF45 contains two main SPI banks. The analog SPI bank provides access to the ADC core and the digital SPI bank controls the digital blocks
(including the serial JESD interface). Figure 123 and Figure 124 provide a conceptual view of the SPI registers inside the ADC32RF45. The analog SPI
bank contains the master and ADC pages. The digital SPI bank is divided into multiple pages (the main digital, digital gain, decimation filter, JESD digital,
and power detector pages).
Register Address[11:0]
SDIN
R/W
M
P
CH
A11
A10
A9
A8
A7
A6
A5
A4
Register Data[7:0]
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SPI Cycle
SCLK
SEN
Initiate an SPI Cycle(1)
R/W, M, P, CH, Bits Decoder
M=0
Analog Bank(3)
1st SPI Cycle:
Page Selection
General Register
(Address 00h,
Keep M, P = 0)
(Global Reset)
Select Master Page
(Address 12h, value 04h,
Keep M, P = 0)
Value 04h
2nd SPI Cycle:
Page Programing
M=1
Digital Bank
Master Page
(PDN,
DC Coupling,
SYSREF Delay,
JESD Swing,
initialization
Registers)
Keep M, P, R/W =
0 when writing to
this page, and
keep these bits =
1 when reading
from this page
Select ADC Page
(Address 11h, Value FFh,
Keep M, P = 0)
General Register
(Address 05h,
Keep M = 1, P = 0)
Select DIGITAL Bank Page
(Address 04h, Address 03h, and Address 02h bits DIGITAL BANK PAGE SEL[23:0],
Keep M = 1, P = 0)
Value FFh
ADC Page
(Slow Speed
Enable,
Initialization
Registers)
Keep M, P, R/W =
0 when writing to
this page, and
keep these bits =
1 when reading
from this page
Value 610000h
Value 610100h
Offset Corr Page
ChA
(Offset Corr)
Offset Corr Page
ChB
(Offset Corr)
Keep
M, P, CH bits =
(1, 1, 0).
R/W = 0 when
writing to this
page, and = 1
when reading from
this page
Keep
M, P, CH bits =
(1, 1, 0).
R/W = 0 when
writing to this
page, and = 1
when reading from
this page
Value 610005h
Value 610105h
Digital Gain Page
ChA
(Digital Gain)
Digital Gain Page
ChB
(Digital Gain)
Keep
M, P, CH bits =
(1, 1, 0).
R/W = 0 when
writing to this
page, and = 1
when reading from
this page
Keep
M, P, CH bits =
(1, 1, 0).
R/W = 0 when
writing to this
page, and = 1
when reading from
this page
Value 680000h
Value 680100h
Value 690000h
Main
Digital Page for
ChA
Main
Digital Page for
ChB
JESD
Digital Page
(JESD
Configuration)
(Nyquist Zone)
(Nyquist Zone)
Keep
M, P, CH bits =
(1, 1, 0).
R/W = 0 when
writing to this
page, and = 1
when reading
from this page
Keep
M, P, CH bits =
(1, 1, 0).
R/W = 0 when
writing to this
page, and = 1
when reading from
this page
Keep M, P = 1,
CH = 0 for ChB,
CH = 1 for ChA
SPI cycle:
These Pages
are directly
programmed
in one SPI
cycle.
Direct
Addressing
Pages:
DDC and
Power
Detector(2)
Keep R/W = 0
when writing to
this page, and = 1
when reading
from this page
(1)
In general, SPI writes are completed in two steps. The first step is to access the necessary page. The second step is to program the desired register in that page. When
a page is accessed, the registers in that page can be programmed multiple times.
(2)
Registers in the decimation filter page and the power detector page can be directly programmed in one SPI cycle.
(3)
The CH bit is a don't care bit and is recommended to be kept at 0.
Figure 123. SPI Registers, Two-Step Addressing
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Register Maps (continued)
Register Address[11:0]
SDIN
R/W
M
P
CH
A11
A10
A9
A8
A7
A6
A5
A4
Register Data[7:0]
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SPI Cycle
SCLK
SEN
Initiate an SPI Cycle
R/W, M, P, CH, Bits Decoder
M=0
Analog Bank
1st SPI Cycle:
Page Selection
Direct Addressing Pages
M=1
Digital Bank
M=1,P=0, CH=1,
A11=1, A10=0
M=1,P=0, CH=1,
A11=0, A10=0
SPI cycle(1):
These pages
are directly
programmed
in one SPI
cycle.
Addr
00h(3)
Program
Decimation
Filter Page for
ChA(2)
(DDC modes)
nd
2 SPI Cycle:
Page Programing
Addr
3Ah
Addr
00h(3)
Addr
00h(3)
Program
Decimation
Filter Page for
ChB(2)
(DDC modes)
Addr
3Ah
M=1,P=0, CH=1,
A11=1, A10=1
M=1,P=0, CH=1,
A11=0, A10=1
Addr
00h(3)
Program
Power
Detector Page
for ChA(3)
Addr
25h
Program
Power
Detector Page
for ChB(3)
Addr
25h
(1)
Registers in the decimation filter page and the power detector page can be directly programmed in one SPI cycle.
(2)
To program registers in the decimation filter page, aet M = 1, CH = 1, A[10] = 0, and A[11] = 0 or 1 for channel A or B. Addressing begins at 50xx for channel A and
58xx for channel B.
(3)
To program registers in power detector page, set M = 1, CH = 1, A[10] = 1, and A[11] = 0 or 1 for channel A or B. Addressing begins at 54xx for channel A and 5Cxx for
channel B.
Figure 124. SPI Registers: Direct Addressing
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Register Maps (continued)
Table 28 lists the register map for the ADC32RF45.
Table 28. Register Map
REGISTER
ADDRESS
A[11:0] (Hex)
REGISTER DATA
7
6
5
RESET
0
0
4
3
2
1
0
0
0
0
0
RESET
0
0
0
3 or 4 WIRE
GENERAL REGISTERS
000
002
DIGITAL BANK PAGE SEL[7:0]
003
DIGITAL BANK PAGE SEL[15:8]
004
DIGITAL BANK PAGE SEL[23:16]
010
0
0
0
0
011
ADC PAGE SEL
0
0
0
0
0
MASTER PAGE
SEL
0
0
020
0
0
0
PDN SYSREF
0
0
0
GLOBAL PDN
032
0
0
INCR CM
IMPEDANCE
0
0
0
0
0
039
0
ALWAYS WRITE 1
0
ALWAYS WRITE 1
0
0
0
SYNC TERM DIS
03C
0
SYSREF DEL EN
0
0
0
0
03D
0
0
0
0
0
012
MASTER PAGE (M = 0)
05A
SYSREF DEL[2:0]
SYSREF DEL[4:3]
JESD OUTPUT SWING
0
0
0
0
0
0
0
0
057
0
0
0
SEL SYSREF REG
ASSERT SYSREF
REG
058
0
0
SYNCB POL
0
0
0
0
0
03F
0
0
0
0
0
SLOW SP EN1
0
0
042
0
0
0
SLOW SP EN2
0
0
0
0
0
ALWAYS WRITE 1
0
0
DIS OFFSET
CORR
ALWAYS WRITE 1
0
0
ALWAYS WRITE 1
0
0
DIS OFFSET
CORR
ALWAYS WRITE 1
0
0
0
0
ADC PAGE (FFh, M = 0)
Offset Corr Page Channel A (610000h, M = 1)
68
FREEZE OFFSET
CORR
Offset Corr Page Channel B (610100h, M = 1)
68
FREEZE OFFSET
CORR
Digital Gain Page Channel A (610005, M = 1)
0A6
66
0
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Register Maps (continued)
Table 28. Register Map (continued)
REGISTER
ADDRESS
A[11:0] (Hex)
REGISTER DATA
7
6
5
4
0
0
0
3
2
1
0
0
DIG CORE RESET
GBL
Digital Gain Page Channel B (610105, M = 1)
0A6
0
DIGITAL GAIN
Main Digital Page Channel A (680000h, M = 1)
000
0
0
0
0
0
0
0A2
0
0
0
0
NQ ZONE EN
NYQUIST ZONE
Main Digital Page Channel B (680001h, M = 1)
000
0
0
0
0
0
0A2
0
0
0
0
NQ ZONE EN
0
0
0
0
NYQUIST ZONE
JESD DIGITAL PAGE (690000h, M = 1)
001
CTRL K
0
0
TESTMODE EN
002
SYNC REG
SYNC REG EN
0
0
003
LINK LAYER TESTMODE
LANE ALIGN
LINK LAY RPAT
LMFC MASK
RESET
JESD MODE1
0
0
0
0
0
0
006
SCRAMBLE EN
0
0
0
0
0
007
0
0
016
0
0
0
0
TX LINK DIS
JESD MODE0
004
017
FRAME ALIGN
12BIT MODE
JESD MODE2
RAMP 12BIT
REL ILA SEQ
0
0
FRAMES PER MULTIFRAME (K)
40X MODE
0
0
0
0
0
LANE0
POL
LANE1
POL
LANE2
POL
LANE3
POL
0
032
SEL EMP LANE 0
0
0
033
SEL EMP LANE 1
0
0
034
SEL EMP LANE 2
0
0
0
0
035
SEL EMP LANE 3
036
0
CMOS SYNCB
0
0
0
0
037
0
0
0
0
0
0
03E
0
MASK CLKDIV
SYSREF
MASK NCO
SYSREF
0
0
0
0
0
PLL MODE
0
0
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Register Maps (continued)
Table 28. Register Map (continued)
REGISTER
ADDRESS
A[11:0] (Hex)
REGISTER DATA
7
6
5
4
3
2
1
0
0
0
0
DDC EN
DECIMATION FILTER PAGE (Direct Addressing, 16-Bit Address, 5000h for Channel A and 5800h for Channel B)
68
000
0
0
0
0
001
0
0
0
0
002
0
0
0
0
0
0
0
DUAL BAND EN
005
0
0
0
0
0
0
0
REAL OUT EN
006
0
0
0
0
0
0
0
DDC MUX
0
NCO SEL PIN
DECIM FACTOR
007
DDC0 NCO1 LSB
008
DDC0 NCO1 MSB
009
DDC0 NCO2 LSB
00A
DDC0 NCO2 MSB
00B
DDC0 NCO3 LSB
00C
DDC0 NCO3 MSB
00D
DDC1 NCO4 LSB
00E
DDC1 NCO4 MSB
00F
0
0
0
0
0
0
010
0
0
0
0
0
0
NCO SEL
011
0
0
0
0
0
0
LMFC RESET MODE
014
0
0
0
0
0
0
0
DDC0 6DB GAIN
016
0
0
0
0
0
0
0
DDC1 6DB GAIN
01E
0
0
0
0
0
01F
0
0
0
0
WBF 6DB GAIN
DDC DET LAT
0
0
0
033
CUSTOM PATTERN1[7:0]
034
CUSTOM PATTERN1[15:8]
035
CUSTOM PATTERN2[7:0]
036
CUSTOM PATTERN2[15:8]
037
0
0
0
0
03A
0
0
0
0
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TEST PATTERN SEL
0
0
TEST PAT RES
TP RES EN
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Register Maps (continued)
Table 28. Register Map (continued)
REGISTER
ADDRESS
A[11:0] (Hex)
REGISTER DATA
7
6
5
4
3
2
1
0
0
0
0
PKDET EN
0
0
0
BLKPKDET [16]
0
0
0
FILT0LPSEL
POWER DETECTOR PAGE (Direct Addressing, 16-Bit Address, 5400h for Channel A and 5C00h for Channel B)
000
0
0
0
0
001
BLKPKDET [7:0]
002
BLKPKDET [15:8]
003
0
0
0
0
007
BLKTHHH
008
BLKTHHL
009
BLKTHLH
00A
BLKTHLL
00B
DWELL[7:0]
00C
DWELL[15:8]
00D
0
0
0
0
00E
0
0
0
0
TIMECONST
00F
FIL0THH[7:0]
010
FIL0THH[15:8]
011
FIL0THL[7:0]
012
FIL0THL[15:8]
013
0
0
0
0
016
FIL1THH[7:0]
017
FIL1THH[15:8]
018
FIL1THL[7:0]
019
FIL1THL[15:8]
01A
0
0
0
0
01D
DWELLIIR[7:0]
01E
DWELLIIR[15:8]
020
0
0
0
021
0
0
0
0
0
0
0
IIR0 2BIT EN
0
0
0
IIR1 2BIT EN
0
0
IIR0 2BIT EN
0
PWRDETACCU
022
PWRDETH[7:0]
023
PWRDETH[15:8]
024
PWRDETL[7:0]
025
PWRDETL[15:8]
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Register Maps (continued)
Table 28. Register Map (continued)
REGISTER
ADDRESS
A[11:0] (Hex)
REGISTER DATA
7
6
5
4
3
2
1
0
0
0
0
RMS 2BIT EN
0
0
0
0
IODIR GPIO4
IODIR GPIO3
IODIR GPIO2
0
0
POWER DETECTOR PAGE (continued)
027
0
0
0
0
02B
0
0
0
RESET AGC
032
OUTSEL GPIO1
033
OUTSEL GPIO2
034
OUTSEL GPIO3
035
70
OUTSEL GPIO4
037
0
0
038
0
0
0
0
INSEL1
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IODIR GPIO1
INSEL0
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8.5.1 Example Register Writes
This section provides three different example register writes. Table 29 describes a global power-down register
write, Table 30 describes the register writes when the scrambler is enabled, and Table 31 describes the register
writes for 8X decimation for channels A and B (complex output, 1 DDC mode) with the NCO set to 1.8 GHz (fS =
3 GSPS) and the JESD format configured to LMFS = 4421.
Table 29. Global Power-Down
ADDRESS
DATA
12h
04h
Set the master page
COMMENT
20h
01h
Set the global power-down
Table 30. Scrambler Enable
ADDRESS
DATA
4004h
69h
COMMENT
4003h
00h
6006h
80h
Scrambler enable, channel A
7006h
80h
Scrambler enable, channel B
Select the digital JESD page
Table 31. 8X Decimation for Channel A and B
ADDRESS
DATA
COMMENT
4004h
68h
4003h
00h
6000h
01h
Issue a digital reset for channel A
6000h
00h
Clear the digital for reset channel A
4003h
01h
Select the main digital page for channel B
6000h
01h
Issue a digital reset for channel B
6000h
00h
Clear the digital reset for channel B
4004h
69h
4003h
00h
6002h
01h
Set JESD MODE0 = 1, channel A
7002h
01h
Set JESD MODE0 = 1, channel B
5000h
01h
Enable the DDC, channel A
5001h
02h
Set decimation to 8X complex
5007h
9Ah
Set the LSB of DDC0, NCO1 to 9Ah (fNCO = 1.8 GHz, fS = 3 GSPS)
5008h
99h
Set the MSB of DDC0, NCO1 to 99h (fNCO = 1.8 GHz, fS = 3 GSPS)
5014h
01h
Enable the 6-dB digital gain of DDC0
5801h
02h
Set decimation to 8X complex
5807h
9Ah
Set the LSB of DDC0, NCO1 to 9Ah (fNCO = 1.8 GHz, fS = 3 GSPS)
5808h
99h
Set the MSB of DDC0, NCO1 to 99h (fNCO = 1.8 GHz, fS = 3 GSPS)
5814h
01h
Enable the 6-dB digital gain of DDC0
Select the main digital page for channel A
Select the digital JESD page
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8.5.2 Register Descriptions
8.5.2.1 General Registers
8.5.2.1.1 Register 000h (address = 000h), General Registers
Figure 125. Register 000h
7
RESET
R/W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
RESET
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 32. Register 000h Field Descriptions
Bit
7
6-1
0
(1)
Field
Type
Reset
Description
RESET
R/W
0h
0 = Normal operation
1 = Internal software reset, clears back to 0
0
W
0h
Must write 0
RESET
R/W
0h
0 = Normal operation (1)
1 = Internal software reset, clears back to 0
Both bits (7, 0) must be set simultaneously to perform a reset.
8.5.2.1.2 Register 002h (address = 002h), General Registers
Figure 126. Register 002h
7
6
5
4
3
DIGITAL BANK PAGE SEL[7:0]
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 33. Register 002h Field Descriptions
72
Bit
Field
Type
Reset
Description
7-0
DIGITAL BANK PAGE SEL[7:0]
R/W
0h
Program the JESD BANK PAGE SEL[23:0] bits to access the
desired page in the JESD bank.
680000h = Main digital page CHA selected
680100h = Main digital page CHB selected
610000h = Digital function page CHA selected
610100h = Digital function page CHB selected
690000h = JESD digital page selected
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8.5.2.1.3 Register 003h (address = 003h), General Registers
Figure 127. Register 003h
7
6
5
4
3
DIGITAL BANK PAGE SEL[15:8]
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 34. Register 003h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DIGITAL BANK PAGE SEL[15:8]
R/W
0h
Program the JESD BANK PAGE SEL[23:0] bits to access the
desired page in the JESD bank.
680000h = Main digital page CHA selected
680100h = Main digital page CHB selected
610000h = Digital function page CHA selected
610100h = Digital function page CHB selected
690000h = JESD digital page selected
8.5.2.1.4 Register 004h (address = 004h), General Registers
Figure 128. Register 004h
7
6
5
4
3
DIGITAL BANK PAGE SEL[23:16]
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 35. Register 004h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DIGITAL BANK PAGE SEL[23:16]
R/W
0h
Program the JESD BANK PAGE SEL[23:0] bits to access the
desired page in the JESD bank.
680000h = Main digital page CHA selected
680100h = Main digital page CHB selected
610000h = Digital function page CHA selected
610100h = Digital function page CHB selected
690000h = JESD digital page selected
8.5.2.1.5 Register 010h (address = 010h), General Registers
Figure 129. Register 010h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
3 or 4 WIRE
R/W-0h
LEGEND: R/W = Read/Write; W = Write; -n = value after reset
Table 36. Register 010h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
3 or 4 WIRE
R/W
0h
0 = 4-wire SPI (default)
1 = 3-wire SPI where SDIN become input or output
0
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8.5.2.1.6 Register 011h (address = 011h), General Registers
Figure 130. Register 011h
7
6
5
4
3
ADC PAGE SEL
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 37. Register 011h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
ADC PAGE SEL
R/W
0h
00000000 = Normal operation, ADC page is not selected
11111111 = ADC page is selected; MASTER PAGE SEL must
be set to 0
8.5.2.1.7 Register 012h (address = 012h), General Registers
Figure 131. Register 012h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
MASTER PAGE SEL
R/W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 38. Register 012h Field Descriptions
Bit
Field
Type
Reset
Description
7-3
0
W
0h
Must write 0
MASTER PAGE SEL
R/W
0h
0 = Normal operation
1 = Selects the master page address; ADC PAGE must be set
to 0
0
W
0h
Must write 0
2
1-0
74
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8.5.3 Master Page (M = 0)
8.5.3.1 Register 020h (address = 020h), Master Page
Figure 132. Register 020h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
PDN SYSREF
R/W-0h
3
0
W-0h
2
0
R/W-0h
1
PDN CHB
R/W-0h
0
GLOBAL PDN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 39. Register 020h Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
W
0h
Must write 0
PDN SYSREF
R/W
0h
This bit powers down the SYSREF input buffer.
0 = Normal operation
1 = SYSREF input capture buffer is powered down and further
SYSREF input pulses are ignored
4
3-2
0
W
0h
Must write 0
1
PDN CHB
R/W
0h
This bit powers down channel B.
0 = Normal operation
1 = Channel B is powered down
0
GLOBAL PDN
R/W
0h
This bit enables the global power-down.
0 = Normal operation
1 = Global power-down enabled
8.5.3.2 Register 032h (address = 032h), Master Page
Figure 133. Register 032h
7
6
0
0
W-0h
W-0h
5
INCR CM
IMPEDANCE
R/W-0h
4
3
2
1
0
0
0
0
0
0
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 40. Register 032h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
W
0h
Must write 0
INCR CM IMPEDANCE
R/W
0h
Only use this bit when analog inputs are dc-coupled to the
driver.
0 = VCM buffer directly drives the common point of biasing
resistors.
1 = VCM buffer drives the common point of biasing resistors with
> 5 kΩ
0
W
0h
Must write 0
5
4-0
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8.5.3.3 Register 039h (address = 039h), Master Page
Figure 134. Register 039h
7
6
ALWAYS
WRITE 1
W-0h
0
W-0h
5
0
W-0h
4
ALWAYS
WRITE 1
W-0h
3
2
1
0
0
0
PDN CHB EN
SYNC TERM DIS
W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 41. Register 039h Field Descriptions
Bit
Field
Type
Reset
Description
7
0
W
0h
Must write 0
6
ALWAYS WRITE 1
W
0h
Always set this bit to 1
5
0
W
0h
Must write 0
4
ALWAYS WRITE 1
W
0h
Always set this bit to 1
3-2
0
W
0h
Must write 0
1
PDN CHB EN
R/W
0h
This bit enables the power-down control of channel B through
the SPI in register 20h.
0 = PDN control disabled
1 = PDN control enabled
0
SYNC TERM DIS
R/W
0h
This bit disables the on-chip, 100-Ω termination resistors on the
SYNCB input.
0 = On-chip, 100-Ω termination enabled
1 = On-chip, 100-Ω termination disabled
8.5.3.4 Register 03Ch (address = 03Ch), Master Page
Figure 135. Register 03Ch
7
0
W-0h
6
SYSREF DEL EN
R/W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
SYSREF DEL[4:3]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 42. Register 03Ch Field Descriptions
Bit
76
Field
Type
Reset
Description
7
0
W
0h
Must write 0
6
SYSREF DEL EN
R/W
0h
This bit allows an internal delay to be added to the SYSREF
input.
0 = SYSREF delay disabled
1 = SYSREF delay enabled through register settings [3Ch (bits
1-0), 5Ah (bits 7-5)]
5-2
0
W
0h
Must write 0
1-0
SYSREF DEL[4:3]
R/W
0h
When the SYSREF delay feature is enabled (3Ch, bit 6) the
delay can be adjusted in 25-ps steps; the first step is 175 ps.
The PVT variation of each 25-ps step is ±10 ps. The 175-ps step
is ±50 ps; see Table 44.
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8.5.3.5 Register 05Ah (address = 05Ah), Master Page
Figure 136. Register 05Ah
7
6
SYSREF DEL[2:0]
R/W-0h
W-0h
5
4
0
W-0h
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 43. Register 05Ah Field Descriptions
Bit
Field
Type
Reset
Description
7
SYSREF DEL2
W
0h
6
SYSREF DEL1
R/W
5
SYSREF DEL0
W
When the SYSREF delay feature is enabled (3Ch, bit 6) the
delay can be adjusted in 25-ps steps; the first step is 175 ps.
The PVT variation of each 25-ps step is ±10 ps. The 175-ps step
is ±50 ps; see Table 44.
0
W
0h
Must write 0
4-0
Table 44. SYSREF DEL[2:0] Bit Settings
STEP
SETTING
STEP (NOM)
TOTAL DELAY (NOM)
1
01000
175 ps
175 ps
2
00111
25 ps
200 ps
3
00110
25 ps
225 ps
4
00101
25 ps
250 ps
5
00100
25 ps
275 ps
6
00011
25 ps
300 ps
8.5.3.6 Register 03Dh (address = 3Dh), Master Page
Figure 137. Register 03Dh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
1
JESD OUTPUT SWING
R/W-0h
0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 45. Register 03Dh Field Descriptions
Bit
Field
Type
Reset
Description
7-3
0
W
0h
Must write 0
2-0
JESD OUTPUT SWING
R/W
0h
These bits select the output amplitude, VOD (mVPP), of the JESD
transmitter for all lanes.
0 = 860 mVPP
1= 810 mVPP
2 = 770 mVPP
3 = 745 mVPP
4 = 960 mVPP
5 = 930 mVPP
6 = 905 mVPP
7 = 880 mVPP
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8.5.3.7 Register 057h (address = 057h), Master Page
Figure 138. Register 057h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
SEL SYSREF REG
R/W-0h
3
ASSERT SYSREF REG
R/W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 46. Register 057h Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
W
0h
Must write 0
4
SEL SYSREF REG
R/W
0h
SYSREF can be asserted using this bit. Ensure that the SEL
SYSREF REG register bit is set high before using this bit; see
Using SYSREF .
0 = SYSREF is logic low
1 = SYSREF is logic high
3
ASSERT SYSREF REG
R/W
0h
Set this bit to use the SPI register to assert SYSREF.
0 = SYSREF is asserted by device pins
1 = SYSREF can be asserted by the ASSERT SYSREF REG
register bit
Other bits = 0
0
W
0h
Must write 0
2-0
8.5.3.8 Register 058h (address = 058h), Master Page
Figure 139. Register 058h
7
0
W-0h
6
0
W-0h
5
SYNCB POL
R/W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 47. Register 058h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
W
0h
Must write 0
SYNCB POL
R/W
0h
This bit inverts the SYNCB polarity.
0 = Polarity is not inverted; this setting matches the timing
diagrams in this document and is the proper setting to use
1 = Polarity is inverted
0
W
0h
Must write 0
5
4-0
78
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8.5.4 ADC Page (FFh, M = 0)
8.5.4.1 Register 03Fh (address = 03Fh), ADC Page
Figure 140. Register 03Fh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
SLOW SP EN1
R/W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 48. Register 03Fh Field Descriptions
Bit
Field
Type
Reset
Description
7-3
0
W
0h
Must write 0
SLOW SP EN1
R/W
0h
This bit must be enabled for clock rates below 2.5 GSPS.
0 = ADC sampling rates are faster than 2.5 GSPS
1 = ADC sampling rates are slower than 2.5 GSPS
0
W
0h
Must write 0
2
1-0
8.5.4.2 Register 042h (address = 042h), ADC Page
Figure 141. Register 042h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
SLOW SP EN2
R/W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 49. Register 042h Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
W
0h
Must write 0
SLOW SP EN2
R/W
0h
This bit must be enabled for clock rates below 2.5 GSPS.
0 = ADC sampling rates are faster than 2.5 GSPS
1 = ADC sampling rates are slower than 2.5 GSPS
0
W
0h
Must write 0
4
3-0
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8.5.5 Digital Function Page (610000h, M = 1 for Channel A and 610100h, M = 1 for Channel B)
8.5.5.1 Register A6h (address = 0A6h), Digital Function Page
Figure 142. Register 0A6h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
2
1
0
DIG GAIN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 50. Register 0A6h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
3-0
DIG GAIN
R/W
0h
These bits set the digital gain of the ADC output data prior to
decimation up to 11 dB; see Table 51.
Table 51. DIG GAIN Bit Settings
SETTING
DIGITAL GAIN
0000
0 dB
0001
1 dB
0010
2 dB
…
…
1010
10 dB
1011
11 dB
8.5.6 Offset Corr Page Channel A (610000h, M = 1)
8.5.6.1 Register 034h (address = 034h), Offset Corr Page Channel A
Figure 143. Register 034h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
SEL EXT EST
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 52. Register 034h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
SEL EXT EST
R/W
0h
This bit selects the external estimate for the offset correction
block; see the Using DC Coupling in the ADC32RF45 section.
0
80
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8.5.6.2 Register 068h (address = 068h), Offset Corr Page Channel A
Figure 144. Register 068h
7
6
5
4
3
FREEZE OFFSET
CORR
0
ALWAYS WRITE 1
0
0
R/W-0h
W-0h
R/W-0h
W-0h
W-0h
2
DIS
OFFSET
CORR
R/W-0h
1
0
ALWAYS WRITE 1
0
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 53. Register 068h Field Descriptions
Bit
Field
Type
Reset
Description
7
FREEZE OFFSET CORR
R/W
0h
Use this bit and bits 5 and 1 to freeze the offset estimation
process of the offset corrector; see the Using DC Coupling in
the ADC32RF45 section.
011 = Apply this setting after powering up the device
111 = Offset corrector is frozen, does not estimate offset
anymore, and applies the last computed value.
Others = Do not use
6
0
W
0h
Must write 0
5
ALWAYS WRITE 1
R/W
0h
Always write this bit as 1 for the offset correction block to work
properly.
0
W
0h
Must write 0
2
DIS OFFSET CORR
R/W
0h
0 = Offset correction block works and removes fS/8, fS/4, 3fS/8,
and fS/2 spurs
1 = Offset correction block is disabled
1
ALWAYS WRITE 1
R/W
0h
Always write this bit as 1 for the offset correction block to work
properly.
0
0
W
0h
Must write 0
4-3
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8.5.7 Offset Corr Page Channel B (610000h, M = 1)
8.5.7.1 Register 068h (address = 068h), Offset Corr Page Channel B
Figure 145. Register 068h
7
6
5
4
3
FREEZE OFFSET
CORR
0
ALWAYS WRITE 1
0
0
R/W-0h
W-0h
R/W-0h
W-0h
W-0h
2
DIS
OFFSET
CORR
R/W-0h
1
0
ALWAYS WRITE 1
0
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 54. Register 068h Field Descriptions
Bit
Field
Type
Reset
Description
FREEZE OFFSET CORR
R/W
0h
Use this bit and bits 5 and 1 to freeze the offset estimation
process of the offset corrector; see the Using DC Coupling in
the ADC32RF45 section.
011 = Apply this setting after powering up the device
111 = Offset corrector is frozen, does not estimate offset
anymore, and applies the last computed value.
Others = Do not use
6
0
W
0h
Must write 0
5
ALWAYS WRITE 1
R/W
0h
Always write this bit as 1 for the offset correction block to work
properly.
7,5,1
4-3
82
0
W
0h
Must write 0
2
DIS OFFSET CORR
R/W
0h
0 = Offset correction block works and removes fS/8, fS/4, 3fS/8,
and fS/2 spurs
1 = Offset correction block is disabled
1
ALWAYS WRITE 1
R/W
0h
Always write this bit as 1 for the offset correction block to work
properly.
0
0
W
0h
Must write 0
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8.5.8 Digital Gain Page (610005h, M = 1 for Channel A and 610105h, M = 1 for Channel B)
8.5.8.1 Register 0A6h (address = 0A6h), Digital Gain Page
Figure 146. Register 0A6h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
2
1
0
DIGITAL GAIN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 55. Register 0A6h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
3-0
DIGITAL GAIN
R/W
0h
These bits apply a digital gain to the ADC data (before the DDC)
up to 11 dB.
0000 = Default
0001 = 1 dB
1011 = 11 dB
Others = Do not use
8.5.9 Main Digital Page Channel A (680000h, M = 1)
8.5.9.1 Register 000h (address = 000h), Main Digital Page Channel A
Figure 147. Register 000h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
DIG CORE RESET GBL
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 56. Register 000h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
DIG CORE RESET GBL
R/W
0h
Pulse this bit (0 →1 →0) to reset the digital core (applies to both
channel A and B).
All Nyquist zone settings take effect when this bit is pulsed.
0
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8.5.9.2 Register 0A2h (address = 0A2h), Main Digital Page Channel A
Figure 148. Register 0A2h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
NQ ZONE EN
R/W-0h
2
1
NYQUIST ZONE
R/W-0h
0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 57. Register 0A2h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
NQ ZONE EN
R/W
0h
This bit allows for specification of the operating Nyquist zone.
0 = Nyquist zone specification disabled
1 = Nyquist zone specification enabled
NYQUIST ZONE
R/W
0h
These bits specify the operating Nyquist zone for the analog
correction loop.
Set the NQ ZONE EN bit before programming these bits.
For example, at s 3-GSPS chip clock, the first Nyquist zone is
from dc to 1.5 GHz, the second Nyquist zone is from 1.5 GHz to
3 GHz, and so on.
000 = First Nyquist zone (dc – fS / 2)
001 = Second Nyquist zone (fS / 2 – fS)
010 = Third Nyquist zone
011 = Fourth Nyquist zone
3
2-0
8.5.10 Main Digital Page Channel B (680001h, M = 1)
8.5.10.1 Register 000h (address = 000h), Main Digital Page Channel B
Figure 149. Register 000h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
DIG CORE RESET GBL
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 58. Register 000h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
DIG CORE RESET GBL
R/W
0h
Pulse this bit (0 →1 →0) to reset the digital core (applies to both
channel A and B).
All Nyquist zone settings take effect when this bit is pulsed.
0
84
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8.5.10.2 Register 0A2h (address = 0A2h), Main Digital Page Channel B
Figure 150. Register 0A2h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
NQ ZONE EN
R/W-0h
2
1
NYQUIST ZONE
R/W-0h
0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 59. Register 0A2h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
NQ ZONE EN
R/W
0h
This bit allows for specification of the operating Nyquist zone.
0 = Nyquist zone specification disabled
1 = Nyquist zone specification enabled
NYQUIST ZONE
R/W
0h
These bits specify the operating Nyquist zone for the analog
correction loop.
Set the NQ ZONE EN bit before programming these bits.
For example, at a 3-GSPS chip clock, first Nyquist zone is from
dc to 1.5 GHz, the second Nyquist zone is from 1.5 GHz to 3
GHz, and so on.
000 = First Nyquist zone (dc – fS / 2)
001 = Second Nyquist zone (fS / 2 – fS)
010 = Third Nyquist zone
011 = Fourth Nyquist zone
3
2-0
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8.5.11 JESD Digital Page (6900h, M = 1)
8.5.11.1 Register 001h (address = 001h), JESD Digital Page
Figure 151. Register 001h
7
CTRL K
R/W-0h
6
0
W-0h
5
0
W-0h
4
TESTMODE EN
R/W-0h
3
0
W-0h
2
LANE ALIGN
R/W-0h
1
FRAME ALIGN
R/W-0h
0
TX LINK DIS
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 60. Register 001h Field Descriptions
Bit
7
6-5
86
Field
Type
Reset
Description
CTRL K
R/W
0h
This bit is the enable bit for the number of frames per
multiframe.
0 = Default is five frames per multiframe
1 = Frames per multiframe can be set in register 06h
0
R/W
0h
Must write 0
0
This bit generates a long transport layer test pattern mode
according to section 5.1.6.3 of the JESD204B specification.
0 = Test mode disabled
1 = Test mode enabled
4
TESTMODE EN
3
0
W
0h
Must write 0
2
LANE ALIGN
R/W
0h
This bit inserts a lane alignment character (K28.3) for the
receiver to align to the lane boundary per section 5.3.3.5 of the
JESD204B specification.
0 = Normal operation
1 = Inserts lane alignment characters
1
FRAME ALIGN
R/W
0h
This bit inserts a frame alignment character (K28.7) for the
receiver to align to the frame boundary per section 5.3.35 of the
JESD204B specification.
0 = Normal operation
1 = Inserts frame alignment characters
0
TX LINK DIS
R/W
0h
This bit disables sending the initial link alignment (ILA) sequence
when SYNC is deasserted.
0 = Normal operation
1 = ILA disabled
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8.5.11.2 Register 002h (address = 002h ), JESD Digital Page
Figure 152. Register 002h
7
SYNC REG
R/W-0h
6
SYNC REG EN
R/W-0h
5
0
W-0h
4
0
W-0h
3
2
12BIT MODE
R/W-0h
1
0
JESD MODE0
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 61. Register 002h Field Descriptions
Bit
Field
Type
Reset
Description
7
SYNC REG
R/W
0h
This bit provides SYNC control through the SPI.
0 = Normal operation
1 = ADC output data are replaced with K28.5 characters
6
SYNC REG EN
R/W
0h
This bit is the enable bit for SYNC control through the SPI.
0 = Normal operation
1 = SYNC control through the SPI is enabled (ignores the
SYNCB input pins)
5-4
0
W
0h
Must write 0
3-2
12BIT MODE
R/W
0h
This bit enables the 12-bit output mode for more efficient data
packing.
00 = Normal operation, 14-bit output
01, 10 = Unused
11 = High-efficient data packing enabled
1-0
JESD MODE0
R/W
0h
These bits select the configuration register to configure the
correct LMFS frame assemblies for different decimation settings;
see the JESD frame assembly tables in the JESD204B Frame
Assembly section.
00 = 0
01 = 1
10 = 2
11 = 3
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8.5.11.3 Register 003h (address = 003h), JESD Digital Page
Figure 153. Register 003h
7
6
5
4
LINK LAYER TESTMODE
LINK LAY RPAT
R/W-0h
R/W-0h
3
LMFC MASK
RESET
R/W-0h
2
1
0
JESD MODE1
JESD MODE2
RAMP 12BIT
R/W-1h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 62. Register 003h Field Descriptions
Bit
Field
Type
Reset
Description
7-5
LINK LAYER TESTMODE
R/W
0h
These bits generate a pattern according to section 5.3.3.8.2 of
the JESD204B document.
000 = Normal ADC data
001 = D21.5 (high-frequency jitter pattern)
010 = K28.5 (mixed-frequency jitter pattern)
011 = Repeat initial lane alignment (generates a K28.5 character
and repeats lane alignment sequences continuously)
100 = 12-octet RPAT jitter pattern
4
LINK LAY RPAT
R/W
0h
This bit changes the running disparity in a modified RPAT
pattern test mode (only when link layer test mode = 100).
0 = Normal operation
1 = Changes disparity
3
LMFC MASK RESET
R/W
0h
0 = Normal operation
2
JESD MODE1
R/W
1h
These bits select the configuration register to configure the
correct LMFS frame assemblies for different decimation settings;
see the JESD frame assembly tables in the JESD204B Frame
Assembly section
1
JESD MODE2
R/W
0h
These bits select the configuration register to configure the
correct LMFS frame assemblies for different decimation settings;
see the JESD frame assembly tables in the JESD204B Frame
Assembly section
0
RAMP 12BIT
R/W
0h
This bit enables the RAMP test pattern for 12-bit mode only
(LMFS = 82820).
0 = Normal data output
1 = Digital output is the RAMP pattern
8.5.11.4 Register 004h (address = 004h), JESD Digital Page
Figure 154. Register 004h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
REL ILA SEQ
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 63. Register 004h Field Descriptions
88
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
1-0
REL ILA SEQ
R/W
0h
These bits delay the generation of the lane alignment sequence
by 0, 1, 2, or 3 multiframes after the code group synchronization.
00 = 0 multiframe delays
01 = 1 multiframe delay
10 = 2 multiframe delays
11 = 3 multiframe delays
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8.5.11.5 Register 006h (address = 006h), JESD Digital Page
Figure 155. Register 006h
7
SCRAMBLE EN
R/W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 64. Register 006h Field Descriptions
Bit
7
6-0
Field
Type
Reset
Description
SCRAMBLE EN
R/W
0h
This bit is the scramble enable bit in the JESD204B interface.
0 = Scrambling disabled
1 = Scrambling enabled
0
W
0h
Must write 0
8.5.11.6 Register 007h (address = 007h), JESD Digital Page
Figure 156. Register 007h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
3
2
1
FRAMES PER MULTIFRAME (K)
R/W-0h
0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 65. Register 007h Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
W
0h
Must write 0
4-0
FRAMES PER MULTIFRAME (K)
R/W
0h
These bits set the number of multiframes.
Actual K is the value in hex + 1 (that is, 0Fh is K = 16).
8.5.11.7 Register 016h (address = 016h), JESD Digital Page
Figure 157. Register 016h
7
0
W-0h
6
5
40x MODE
R/W-0h
4
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 66. Register 016h Field Descriptions
Bit
Field
Type
Reset
Description
0
W
0h
Must write 0
6-4
40x MODE
R/W
0h
This register must be set for 40X mode operation.
000 = Register is set for 20X and 80X mode
111 = Register must be set for 40X mode
3-0
0
W
0h
Must write 0
7
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8.5.11.8 Register 017h (address = 017h), JESD Digital Page
Figure 158. Register 017h
7
6
5
4
0
0
0
0
W-0h
R/W-0h
R/W-0h
R/W-0h
3
Lane0
POL
W-0h
2
Lane1
POL
W-0h
1
Lane2
POL
W-0h
0
Lane3
POL
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 67. Register 017h Field Descriptions
Bit
Field
Type
Reset
Description
7
0
W
0h
Must write 0
6-4
0
R/W
0h
Must write 0
3-0
Lane[3:0] POL
W
0h
These bits set the polarity of the individual JESD output lanes.
0 = Polarity as given in the pinout (noninverted)
1 = Inverts polarity (positive, P, or negative, M)
8.5.11.9 Register 032h-035h (address = 032h-035h), JESD Digital Page
Figure 159. Register 032h
7
6
5
4
SEL EMP LANE 0
R/W-0h
3
2
1
0
W-0h
0
0
W-0h
2
1
0
W-0h
0
0
W-0h
2
1
0
W-0h
0
0
W-0h
2
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 160. Register 033h
7
6
5
4
SEL EMP LANE 1
R/W-0h
3
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 161. Register 034h
7
6
5
4
SEL EMP LANE 2
R/W-0h
3
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 162. Register 035h
7
6
5
4
SEL EMP LANE 3
R/W-0h
3
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
90
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Table 68. Register 032h-035h Field Descriptions
Bit
Field
Type
Reset
Description
7-2
SEL EMP LANE
R/W
0h
These bits select the amount of de-emphasis for the JESD
output transmitter. The de-emphasis value in dB is measured as
the ratio between the peak value after the signal transition to the
settled value of the voltage in one bit period.
0 = 0 dB
1 = –1 dB
3 = –2 dB
7 = –4.1 dB
15 = –6.2 dB
31 = –8.2 dB
63 = –11.5 dB
1-0
0
W
0h
Must write 0
8.5.11.10 Register 036h (address = 036h), JESD Digital Page
Figure 163. Register 036h
7
0
W-0h
6
CMOS SYNCB
R/W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 69. Register 036h Field Descriptions
Bit
Field
Type
Reset
Description
7
0
W
0h
Must write 0
6
CMOS SYNCB
R/W
0h
This bit enables single-ended control of SYNCB using the
GPIO4 pin (pin 63). The differential SYNCB input is ignored.
0 = Differential SYNCB input
1 = Single-ended SYNCB input using pin 63
0
W
0h
Must write 0
5-0
8.5.11.11 Register 037h (address = 037h), JESD Digital Page
Figure 164. Register 037h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
PLL MODE
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 70. Register 037h Field Descriptions
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
1-0
PLL MODE
R/W
0h
These bits select the PLL multiplication factor; see the JESD
tables in the JESD204B Frame Assembly section for settings.
00 = 20X mode
01 = 16X mode
10 = 40x mode (the 40x MODE bit in register 16h must also be
set)
11 = 80x mode
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8.5.11.12 Register 03Eh (address = 03Eh), JESD Digital Page
Figure 165. Register 03Eh
7
0
W-0h
6
MASK CLKDIV SYSREF
R/W-0h
5
MASK NCO SYSREF
R/W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 71. Register 03Eh Field Descriptions
Bit
Field
Type
Reset
Description
7
0
W
0h
Must write 0
6
MASK CLKDIV SYSREF
R/W
0h
Use this bit to mask the SYSREF going to the input clock
divider.
0 = Input clock divider is reset when SYSREF is asserted (that
is, when SYSREF transitions from low to high)
1 = Input clock divider ignores SYSREF assertions
5
MASK NCO SYSREF
R/W
0h
Use this bit to mask the SYSREF going to the NCO in the DDC
block and LMFC counter of the JESD interface.
0 = NCO phase and LMFC counter are reset when SYSREF is
asserted (that is, when SYSREF transitions from low to high)
1 = NCO and LMFC counter ignore SYSREF assertions
0
W
0h
Must write 0
4-0
8.5.12 Decimation Filter Page
Direct Addressing, 16-Bit Address, 5000h for Channel A, 5800h for Channel B
8.5.12.1 Register 000h (address = 000h), Decimation Filter Page
Figure 166. Register 000h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
DDC EN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 72. Register 000h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
DDC EN
R/W
0h
This bit enables the decimation filter and disables the bypass
mode.
0 = Bypass mode (DDC disabled)
1 = Decimation filter enabled
0
92
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8.5.12.2 Register 001h (address = 001h), Decimation Filter Page
Figure 167. Register 001h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
2
1
DECIM FACTOR
R/W-0h
0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 73. Register 001h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
3-0
DECIM FACTOR
R/W
0h
These bits configure the decimation filter setting.
0000 = Divide-by-4 complex
0001 = Divide-by-6 complex
0010 = Divide-by-8 complex
0011 = Divide-by-9 complex
0100 = Divide-by-10 complex
0101 = Divide-by-12 complex
0110 = Not used
0111 = Divide-by-16 complex
1000 = Divide-by-18 complex
1001 = Divide-by-20 complex
1010 = Divide-by-24 complex
1011 = Not used
1100 = Divide-by-32 complex
8.5.12.3 Register 002h (address = 2h), Decimation Filter Page
Figure 168. Register 002h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
DUAL BAND EN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 74. Register 002h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
DUAL BAND EN
R/W
0h
This bit enables the dual-band DDC filter for the corresponding
channel.
0 = Single-band DDC
1 = Dual-band DDC
0
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8.5.12.4 Register 005h (address = 005h), Decimation Filter Page
Figure 169. Register 005h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
REAL OUT EN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 75. Register 005h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
REAL OUT EN
R/W
0h
This bit converts the complex output to real output at 2x the
output rate.
0 = Complex output format
1 = Real output format
0
8.5.12.5 Register 006h (address = 006h), Decimation Filter Page
Figure 170. Register 006h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
DDC MUX
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 76. Register 006h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
DDC MUX
R/W
0h
This bit connects the DDC to the alternate channel ADC to
enable up to four DDCs with one ADC and completely turn off
the other ADC channel.
0 = Normal operation
1 = DDC block takes input from the alternate ADC
0
8.5.12.6 Register 007h (address = 007h), Decimation Filter Page
Figure 171. Register 007h
7
6
5
4
3
DDC0 NCO1 LSB
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 77. Register 007h Field Descriptions
94
Bit
Field
Type
Reset
Description
7-0
DDC0 NCO1 LSB
R/W
0h
These bits are the LSB of the NCO frequency word for NCO1 of
DDC0 (band 1).
The LSB represents fS / (216), where fS is the ADC sampling
frequency.
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8.5.12.7 Register 008h (address = 008h), Decimation Filter Page
Figure 172. Register 008h
7
6
5
4
3
DDC0 NCO1 MSB
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 78. Register 008h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DDC0 NCO1 MSB
R/W
0h
These bits are the MSB of the NCO frequency word for NCO1 of
DDC0 (band 1).
The LSB represents fS / (216), where fS is the ADC sampling
frequency.
8.5.12.8 Register 009h (address = 009h), Decimation Filter Page
Figure 173. Register 009h
7
6
5
4
3
DDC0 NCO2 LSB
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 79. Register 009h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DDC0 NCO2 MSB
R/W
0h
These bits are the LSB of the NCO frequency word for NCO2 of
DDC0 (band 1).
The LSB represents fS / (216), where fS is the ADC sampling
frequency.
8.5.12.9 Register 00Ah (address = 00Ah), Decimation Filter Page
Figure 174. Register 00Ah
7
6
5
4
3
DDC0 NCO2 MSB
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 80. Register 00Ah Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DDC0 NCO2 MSB
R/W
0h
These bits are the MSB of the NCO frequency word for NCO2 of
DDC0 (band 1).
The LSB represents fS / (216), where fS is the ADC sampling
frequency.
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8.5.12.10 Register 00Bh (address = 00Bh), Decimation Filter Page
Figure 175. Register 00Bh
7
6
5
4
3
DDC0 NCO3 LSB
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 81. Register 00Bh Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DDC0 NCO3 LSB
R/W
0h
These bits are the LSB of the NCO frequency word for NCO3 of
DDC0 (band 1).
The LSB represents fS / (216), where fS is the ADC sampling
frequency.
8.5.12.11 Register 00Ch (address = 00Ch), Decimation Filter Page
Figure 176. Register 00Ch
7
6
5
4
3
DDC0 NCO3 MSB
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 82. Register 00Ch Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DDC0 NCO3 MSB
R/W
0h
These bits are the MSB of the NCO frequency word for NCO3 of
DDC0 (band 1).
The LSB represents fS / (216), where fS is the ADC sampling
frequency.
8.5.12.12 Register 00Dh (address = 00Dh), Decimation Filter Page
Figure 177. Register 00Dh
7
6
5
4
3
DDC1 NCO4 LSB
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 83. Register 00Dh Field Descriptions
96
Bit
Field
Type
Reset
Description
7-0
DDC1 NCO4 LSB
R/W
0h
These bits are the LSB of the NCO frequency word for NCO4 of
DDC1 (band 2, only when dual-band mode is enabled).
The LSB represents fS / (216), where fS is the ADC sampling
frequency.
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8.5.12.13 Register 00Eh (address = 00Eh), Decimation Filter Page
Figure 178. Register 00Eh
7
6
5
4
3
DDC1 NCO4 MSB
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 84. Register 00Eh Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DDC1 NCO4 MSB
R/W
0h
These bits are the MSB of the NCO frequency word for NCO4 of
DDC1 (band 2, only when dual-band mode is enabled).
The LSB represents fS / (216), where fS is the ADC sampling
frequency.
8.5.12.14 Register 00Fh (address = 00Fh), Decimation Filter Page
Figure 179. Register 00Fh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
NCO SEL PIN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 85. Register 00Fh Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
NCO SEL PIN
R/W
0h
This bit enables NCO selection through the GPIO pins.
0 = NCO selection through SPI (see address 0h10)
1 = NCO selection through GPIO pins
0
8.5.12.15 Register 010h (address = 010h), Decimation Filter Page
Figure 180. Register 010h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
NCO SEL
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 86. Register 010h Field Descriptions
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
1-0
NCO SEL
R/W
0h
These bits enable NCO selection through register setting.
00 = NCO1 selected for DDC 1
01 = NCO2 selected for DDC 1
10 = NCO3 selected for DDC 1
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8.5.12.16 Register 011h (address = 011h), Decimation Filter Page
Figure 181. Register 011h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
LMFC RESET MODE
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 87. Register 011h Field Descriptions
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
1-0
LMFC RESET MODE
R/W
0h
These bits reset the configuration for all DDCs and NCOs.
00 = All DDCs and NCOs are reset with every LMFC RESET
01 = Reset with first LMFC RESET after DDC start. Afterwards,
reset only when analog clock dividers are resynchronized.
10 = Reset with first LMFC RESET after DDC start. Afterwards,
whenever analog clock dividers are resynchronized, use two
LMFC resets.
11 = Do not use an LMFC reset at all. Reset the DDCs only
when a DDC start is asserted and afterwards continue normal
operation. Deterministic latency is not ensured.
8.5.12.17 Register 014h (address = 014h), Decimation Filter Page
Figure 182. Register 014h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
DDC0 6DB GAIN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 88. Register 014h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
DDC0 6DB GAIN
R/W
0h
This bit scales the output of DDC0 by 2 (6 dB) to compensate
for real-to-complex conversion and image suppression. This
scaling does not apply to the high-bandwidth filter path (divideby-4 and -6); see register 1Fh.
0 = Normal operation
1 = 6-dB digital gain is added
0
98
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8.5.12.18 Register 016h (address = 016h), Decimation Filter Page
Figure 183. Register 016h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
DDC1 6DB GAIN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 89. Register 016h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
DDC1 6DB GAIN
R/W
0h
This bit scales the output of DDC0 by 2 (6 dB) to compensate
for real-to-complex conversion and image suppression. This
scaling does not apply to the high-bandwidth filter path (divideby-4 and -6); see register 1Fh.
0 = Normal operation
1 = 6-dB digital gain is added
0
8.5.12.19 Register 01Eh (address = 01Eh), Decimation Filter Page
Figure 184. Register 01Eh
7
0
W-0h
6
5
DDC DET LAT
R/W-0h
4
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 90. Register 01Eh Field Descriptions
Bit
Field
Type
Reset
Description
0
W
0h
Must write 0
6-4
DDC DET LAT
R/W
0h
These bits ensure deterministic latency depending on the decimation setting
used; see Table 91.
3-0
0
W
0h
Must write 0
7
Table 91. DDC DET LAT Bit Settings
SETTING
COMPLEX DECIMATION SETTING
10h
Divide-by-24, -32 complex
20h
Divide-by-16, -18, -20 complex
40h
Divide-by-by 6, -12 complex
50h
Divide-by-4, -8, -9, -10 complex
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8.5.12.20 Register 01Fh (address = 01Fh), Decimation Filter Page
Figure 185. Register 01Fh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
WBF 6DB GAIN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 92. Register 01Fh Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
WBF 6DB GAIN
R/W
0h
This bit scales the output of the wide bandwidth DDC filter by 2
(6 dB) to compensate for real-to-complex conversion and image
suppression. This setting only applies to the high-bandwidth filter
path (divide-by-4 and -6).
0 = Normal operation
1 = 6-dB digital gain is added
0
8.5.12.21 Register 033h-036h (address = 033h-036h), Decimation Filter Page
Figure 186. Register 033h
7
6
5
4
3
CUSTOM PATTERN1[7:0]
R/W-0h
2
1
0
2
1
0
2
1
0
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 187. Register 034h
7
6
5
4
3
CUSTOM PATTERN1[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 188. Register 035h
7
6
5
4
3
CUSTOM PATTERN2[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 189. Register 036h
7
6
5
4
3
CUSTOM PATTERN2[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 93. Register 033h-036h Field Descriptions
100
Bit
Field
Type
Reset
Description
7-0
CUSTOM PATTERN
R/W
0h
These bits set the custom test pattern in address 33h, 34h, 35h,
or 36h.
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8.5.12.22 Register 037h (address = 037h), Decimation Filter Page
Figure 190. Register 037h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
2
1
TEST PATTERN SEL
R/W-0h
0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 94. Register 037h Field Descriptions
Bit
Field
Type
Reset
Description
7-3
0
W
0h
Must write 0
3-0
TEST PATTERN SEL
R/W
0h
These bits select the test pattern output on the channel.
0000 = Normal operation using ADC output data
0001 = Outputs all 0s
0010 = Outputs all 1s
0011 = Outputs toggle pattern: output data are an alternating
sequence of 10101010101010 and 01010101010101
0100 = Output digital ramp: output data increment by one LSB
every clock cycle from code 0 to 16384
0110 = Single pattern: output data are custom pattern 1 (75h
and 76h)
0111 = Double pattern: output data alternate between custom
pattern 1 and custom pattern 2
1000 = Deskew pattern: output data are AAAAh
1001 = SYNC pattern: output data are FFFFh
8.5.12.23 Register 03Ah (address = 03Ah), Decimation Filter Page
Figure 191. Register 03Ah
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
TEST PAT RES
R/W-0h
0
TP RES EN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 95. Register 03Ah Field Descriptions
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
1
TEST PAT RES
R/W
0h
Pulsing this bit resets the test pattern. The test pattern reset
must be enabled first (bit D0).
0 = Normal operation
1 = Reset the test pattern
0
TP RES EN
R/W
0h
This bit enables the test pattern reset.
0 = Reset disabled
1 = Reset enabled
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8.5.13 Power Detector Page
8.5.13.1 Register 000h (address = 000h), Power Detector Page
Figure 192. Register 000h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
PKDET EN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 96. Register 000h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
PKDET EN
R/W
0h
This bit enables the peak power and crossing detector.
0 = Power detector disabled
1 = Power detector enabled
0
8.5.13.2 Register 001h-002h (address = 001h-002h), Power Detector Page
Figure 193. Register 001h
7
6
5
4
3
BLKPKDET [7:0]
R/W-0h
2
1
0
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 194. Register 002h
7
6
5
4
3
BLKPKDET [15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 97. Register 001h-002h Field Descriptions
102
Bit
Field
Type
Reset
Description
7-0
BLKPKDET
R/W
0h
This register specifies the block length in terms of number of
samples (S`) used for peak power computation. Each sample S`
is a peak of 8 actual ADC samples. This parameter is a 17-bit
value directly in linear scale. In decimation mode, the block
length must be a multiple of a divide-by-4 or -6 complex: length
= 5 × decimation factor.
The divide-by-8 to -32 complex: length = 10 × decimation factor.
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8.5.13.3 Register 003h (address = 003h), Power Detector Page
Figure 195. Register 003h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
BLKPKDET[16]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 98. Register 003h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
BLKPKDET[16]
R/W
0h
This register specifies the block length in terms of number of
samples (S`) used for peak power computation. Each sample S`
is a peak of 8 actual ADC samples. This parameter is a 17-bit
value directly in linear scale. In decimation mode, the block
length must be a multiple of a divide-by-4 or -6 complex: length
= 5 × decimation factor.
The divide-by-8 to -32 complex: length = 10 × decimation factor.
0
8.5.13.4 Register 007h-00Ah (address = 007h-00Ah), Power Detector Page
Figure 196. Register 007h
7
6
5
4
3
2
1
0
2
1
0
2
1
0
2
1
0
BLKTHHH
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 197. Register 008h
7
6
5
4
3
BLKTHHL
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 198. Register 009h
7
6
5
4
3
BLKTHLH
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 199. Register 00Ah
7
6
5
4
3
BLKTHLL
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 99. Register 007h-00Ah Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BLKTHHH
BLKTHHL
BLKTHLH
BLKTHLL
R/W
0h
These registers set the four different thresholds for the
hysteresis function threshold values from 0 to 256 (2TH), where
256 is equivalent to the peak amplitude.
Example: BLKTHHH is set to –2 dBFS from peak: 10(-2 / 20) × 256
= 203, then set 5407h, 5C07h = CBh.
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8.5.13.5 Register 00Bh-00Ch (address = 00Bh-00Ch), Power Detector Page
Figure 200. Register 00Bh
7
6
5
4
3
2
1
0
2
1
0
DWELL[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 201. Register 00Ch
7
6
5
4
3
DWELL[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 100. Register 00Bh-00Ch Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DWELL
R/W
0h
DWELL time counter.
When the computed block peak crosses the upper thresholds
BLKTHHH or BLKTHLH, the peak detector output flags are set.
In order to be reset, the computed block peak must remain
continuously lower than the lower threshold (BLKTHHL or
BLKTHLL) for the period specified by the DWELL value. This
threshold is 16 bits, is specified in terms of fS / 8 clock cycles,
and must be set to 0 for the crossing detector. Example: if fS = 3
GSPS, fS / 8 = 375 MHz, and DWELL = 0100h then the DWELL
time = 29 / 375 MHz = 1.36 µs.
8.5.13.6 Register 00Dh (address = 00Dh), Power Detector Page
Figure 202. Register 00Dh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
FILT0LPSEL
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 101. Register 00Dh Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
FILT0LPSEL
R/W
0h
This bit selects either the block detector output or 2-bit output as
the input to the IIR filter.
0 = Use the output of the high comparators (HH and HL) as the
input of the IIR filter
1 = Combine the output of the high (HH and HL) and low (LH
and LL) comparators to generate a 3-level input to the IIR filter
(–1, 0, 1)
0
104
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8.5.13.7 Register 00Eh (address = 00Eh), Power Detector Page
Figure 203. Register 00Eh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
2
1
0
TIMECONST
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 102. Register 00Eh Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
3-0
TIMECONST
R/W
0h
These bits set the crossing detector time period for N = 0 to 15
as 2N × fS / 8 clock cycles. The maximum time period is 32768 ×
fS / 8 clock cycles (approximately 87 µs at 3 GSPS).
8.5.13.8 Register 00Fh, 010h-012h, and 016h-019h (address = 00Fh, 010h-012h, and 016h-019h), Power
Detector Page
Figure 204. Register 00Fh
7
6
5
4
3
2
1
0
2
1
0
2
1
0
2
1
0
2
1
0
FIL0THH[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 205. Register 010h
7
6
5
4
3
FIL0THH[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 206. Register 011h
7
6
5
4
3
FIL0THL[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 207. Register 012h
7
6
5
4
3
FIL0THL[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 208. Register 016h
7
6
5
4
3
FIL1THH[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
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Figure 209. Register 017h
7
6
5
4
3
2
1
0
2
1
0
2
1
0
FIL1THH[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 210. Register 018h
7
6
5
4
3
FIL1THL[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 211. Register 019h
7
6
5
4
3
FIL1THL[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 103. Register 00Fh, 010h, 011h, 012h, 016h, 017h, 018h, and 019h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
FIL0THH
FIL0THL
FIL1THH
FIL1THL
R/W
0h
Comparison thresholds for the crossing detector counter. This
threshold is 16 bits in 2.14 signed notation. A value of 1 (4000h)
corresponds to 100% crossings, a value of 0.125 (0800h)
corresponds to 12.5% crossings.
8.5.13.9 Register 013h-01Ah (address = 013h-01Ah), Power Detector Page
Figure 212. Register 013h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
IIR0 2BIT EN
R/W-0h
2
0
W-0h
1
0
W-0h
0
IIR1 2BIT EN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 213. Register 01Ah
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 104. Register 013h and 01Ah Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
IIR0 2BIT EN
IIR1 2BIT EN
R/W
0h
This bit enables 2-bit output format of the IIR0 and IIR1 output
comparators.
0 = Selects 1-bit output format
1 = Selects 2-bit output format
0
106
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8.5.13.10 Register 01Dh-01Eh (address = 01Dh-01Eh), Power Detector Page
Figure 214. Register 01Dh
7
6
5
4
3
2
1
0
2
1
0
DWELLIIR[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 215. Register 01Eh
7
6
5
4
3
DWELLIIR[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 105. Register 01Dh-01Eh Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DWELLIIR
R/W
0h
DWELL time counter for the IIR output comparators. When the
IIR filter output crosses the upper thresholds FIL0THH or
FIL1THH, the IIR peak detector output flags are set. In order to
be reset, the output of the IIR filter must remain continuously
lower than the lower threshold (FIL0THL or FIL1THL) for the
period specified by the DWELLIIR value. This threshold is 16
bits and is specified in terms of fS / 8 clock cycles.
Example: if fS = 3 GSPS, fS / 8 = 375 MHz, and DWELLIIR =
0100h, then the DWELL time = 29 / 375 MHz = 1.36 µs.
8.5.13.11 Register 020h (address = 020h), Power Detector Page
Figure 216. Register 020h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
RMSDET EN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 106. Register 020h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
RMSDET EN
R/W
0h
This bit enables the RMS power detector.
0 = Power detector disabled
1 = Power detector enabled
0
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8.5.13.12 Register 021h (address = 021h), Power Detector Page
Figure 217. Register 021h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
3
2
PWRDETACCU
R/W-0h
1
0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 107. Register 021h Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
W
0h
Must write 0
4-0
PWRDETACCU
R/W
0h
These bits program the block length to be used for RMS power
computation.
The block length is defined in terms of fS / 8 clocks and can be
programmed as 2M, where M = 0 to 16.
8.5.13.13 Register 022h-025h (address = 022h-025h), Power Detector Page
Figure 218. Register 022h
7
6
5
4
3
2
1
0
2
1
0
2
1
0
2
1
0
PWRDETH[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 219. Register 023h
7
6
5
4
3
PWRDETH[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 220. Register 024h
7
6
5
4
3
PWRDETL[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 221. Register 025h
7
6
5
4
3
PWRDETL[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 108. Register 022h-025h Field Descriptions
108
Bit
Field
Type
Reset
Description
7-0
PWRDETH[15:0]
PWRDETL[15:0]
R/W
0h
The computed average power is compared against these high and low
thresholds. One LSB of the thresholds represents 1 / 216.
Example: if PWRDETH is set to –14 dBFS from peak, (10(–14 / 20))2 × 216 = 2609,
then set 5422h, 5423h, 5C22h, 5C23h = 0A31h.
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8.5.13.14 Register 027h (address = 027h), Power Detector Page
Figure 222. Register 027h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
RMS 2BIT EN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 109. Register 027h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
RMS 2BIT EN
R/W
0h
This bit enables 2-bit output format on the RMS output
comparators.
0 = Selects 1-bit output format
1 = Selects 2-bit output format
0
8.5.13.15 Register 02Bh (address = 02Bh), Power Detector Page
Figure 223. Register 02Bh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
RESET AGC
R/W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 110. Register 02Bh Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
W
0h
Must write 0
RESET AGC
R/W
0h
After configuration, the AGC module must be reset and then
brought out of reset to start operation.
0 = Clear AGC reset
1 = Set AGC reset
Example: set 542Bh to 10h and then to 00h.
0
W
0h
Must write 0
4
3-0
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8.5.13.16 Register 032h-035h (address = 032h-035h), Power Detector Page
Figure 224. Register 032h
7
6
5
4
3
OUTSEL GPIO1
R/W-0h
2
1
0
2
1
0
2
1
0
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 225. Register 033h
7
6
5
4
3
OUTSEL GPIO2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 226. Register 034h
7
6
5
4
3
OUTSEL GPIO3
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 227. Register 035h
7
6
5
4
3
OUTSEL GPIO4
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 111. Register 032h-035h Field Descriptions
110
Bit
Field
7-0
OUTSEL
OUTSEL
OUTSEL
OUTSEL
GPIO1
GPIO2
GPIO3
GPIO4
Type
Reset
Description
R/W
0h
These bits set the function or signal for each GPIO pin.
0 = IIR PK DET0[0] of channel A
1 = IIR PK DET0[1] of channel A (2-bit mode)
2 = IIR PK DET1[0] of channel A
3 = IIR PK DET1[1] of channel A (2-bit mode)
4 = BLKPKDETH of channel A
5 = BLKPKDETL of channel A
6 = PWR Det[0] of channel A
7 = PWR Det[1] of channel A (2-bit mode)
8 = FOVR of channel A
9-17 = Repeat outputs 0-8 but for channel B instead
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8.5.13.17 Register 037h (address = 037h), Power Detector Page
Figure 228. Register 037h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
IODIR GPIO4
R/W-0h
2
IODIR GPIO3
R/W-0h
1
IODIR GPIO2
R/W-0h
0
IODIR GPIO1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 112. Register 037h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
3-0
IODIRGPIO[4:1]
R/W
0h
These bits select the output direction for the GPIO[4:1] pins.
0 = Input (for the NCO control)
1 = Output (for the AGC alarm function)
8.5.13.18 Register 038h (address = 038h), Power Detector Page
Figure 229. Register 038h
7
0
W-0h
6
0
W-0h
5
4
3
0
R/W-0h
INSEL1
R/W-0h
2
0
R/W-0h
1
0
INSEL0
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 113. Register 038h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
W
0h
Must write 0
5-4
INSEL1
R/W
0h
These bits select which GPIO pin is used for the INSEL1 bit.
00 = GPIO4
01 = GPIO1
10 = GPIO3
11 = GPIO2
Table 114 lists the NCO selection, based on the bit settings of
the INSEL pins.
3-2
0
W
0h
Must write 0
1-0
INSEL0
R/W
0h
These bits select which GPIO pin is used for the INSEL0 bit.
00 = GPIO4
01 = GPIO1
10 = GPIO3
11 = GPIO2
Table 114 lists the NCO selection, based on the bit settings of
the INSEL pins.
Table 114. INSEL Bit Settings
INSEL1
INSEL2
NCO SELECTED
0
0
NCO1
0
1
NCO2
1
0
NCO3
1
1
n/a
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Start-Up Sequence
The steps in Table 115 are recommended as the power-up sequence when the ADC32RF45 is in bypass mode
with a 12-bit output (LMFS = 82820).
Table 115. Initialization Sequence
STEP
DESCRIPTION
PAGE, REGISTER
ADDRESS AND DATA
COMMENT
1
Supply all supply voltages. There is no required
power-supply sequence for the 1.15 V, 1.2 V,
and 1.9 V supplies, and can be supplied in any
order.
—
—
2
Provide the SYSREF signal.
—
—
3
Pulse a hardware reset (low-to-high-to-low) on
pins 33 and 34.
—
—
4
Write the register addresses described in the
PowerUpConfig file.
See the files located in
SBAA226
The Power-up config file contains analog
trim registers that are required for best
performance of the ADC. Write these
registers every time after power up.
5
Write the register addresses mentioned in the
ILConfigNyqX_ChA file, where X is the Nyquist
zone.
See the files located in
SBAA226
Based on the signal band of interest, provide
the Nyquist zone information to the device.
6
Write the register addresses mentioned in the
ILConfigNyqX_ChB file, where X is the Nyquist
zone.
See the files located in
SBAA226
This step optimizes device’ performance by
reducing interleaving mismatch errors.
6.1
—
—
7
Depending upon the Nyquist band of operation,
choose and write the registers from the
appropriate file, NLConfigNyqX_ChA, where X
is the Nyquist zone.
See the files located in
SBAA226
Third-order nonlinearity of the device is
optimized by this step for channel A.
7.1
Depending upon the Nyquist band of operation,
choose and write the registers from the
appropriate file, NLConfigNyqX_ChB, where X
is the Nyquist zone.
See the files located in
SBAA226
Third-order nonlinearity of the device is
optimized by this step for channel B.
Configure the JESD interface and DDC block
by writing the registers mentioned in the DDC
Config file.
See the files located in
SBAA226
Determine the DDC and JESD interface
LMFS options. Program these options in this
step.
8
112
Wait for 50 ms for the device to estimate the
interleaving errors.
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9.1.2 Hardware Reset
Timing information for the hardware reset is shown in Figure 230 and Table 116.
Power Supplies
t1
RESET
t2
t3
SEN
Figure 230. Hardware Reset Timing Diagram
Table 116. Hardware Reset Timing Information
MIN
TYP
MAX
UNIT
t1
Power-on delay from power-up to active high RESET pulse
1
ms
t2
Reset pulse duration: active high RESET pulse duration
1
µs
t3
Register write delay from RESET disable to SEN active
100
ns
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9.1.3 SNR and Clock Jitter
The signal-to-noise ratio (SNR) of the ADC is limited by three different factors: quantization noise, thermal noise,
and jitter, as shown in Equation 5. The quantization noise is typically not noticeable in pipeline converters and is
84 dB for a 14-bit ADC. The thermal noise limits the SNR at low input frequencies and the clock jitter sets the
SNR for higher input frequencies.
SNRADC ¬ªdBc ¼º
§
20log ¨ 10
¨
©
SNRQuantization Noise
20
·
¸
¸
¹
2
§
¨ 10
¨
©
SNRThermal Noise
20
·
¸
¸
¹
2
§
¨10
¨
©
SNRJitter
20
·
¸
¸
¹
2
(5)
The SNR limitation resulting from sample clock jitter can be calculated by Equation 6:
20log 2S u fIN u t Jitter
SNRJitter ª¬dBc º¼
(6)
The total clock jitter (TJitter) has two components: the internal aperture jitter (90 fS) is set by the noise of the clock
input buffer and the external clock jitter. TJitter can be calculated by Equation 7:
t Jitter
t Jitter ,
2
Ext _ Clock _ Input
t Aperture_ ADC
2
(7)
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass
filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter.
The ADC32RF45 has a thermal noise of approximately 63 dBFS and an internal aperture jitter of 90 fS. The
SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 231.
63
62
61
SNR (dBFS)
60
59
58
57
56
55
54
35 fs
50 fs
100 fs
150 fs
200 fs
53
52
10
100
1000
Input Frequency (MHz)
5000
D048
Figure 231. ADC SNR vs Input Frequency and External Clock Jitter
114
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9.1.3.1 External Clock Phase Noise Consideration
External clock jitter can be calculated by integrating the phase noise of the clock source out to approximately two
times of the ADC sampling rate (2 × fS), as shown in Figure 232. In order to maximize the ADC SNR, an external
band-pass filter is recommended to be used on the clock input. This filter reduces the jitter contribution from the
broadband clock phase noise floor by effectively reducing the integration bandwidth to the pass band of the
band-pass filter. This method is suitable when estimating the overall ADC SNR resulting from clock jitter at a
certain input frequency.
Clock Phase Noise
Integration Bandwidth
Frequency Offset
fmin
2 u fS
Figure 232. Integration Bandwidth for Extracting Jitter from Clock Phase Noise
However, when estimating the affect of a nearby blocker (such as a strong in-band interferer to the sensitivity,
the phase noise information can be used directly to estimate the noise budget contribution at a certain offset
frequency, as shown in Figure 233.
Inband Blocker
Clock Phase Noise
Modulated Onto the Blocker
ADC Noise Floor
Wanted Signal
Figure 233. Small Wanted Signal in Presence of Interferer
At the sampling instant, the phase noise profile of the clock source convolves with the input signal (for example,
the small wanted signal and the strong interferer merge together). If the power of the clock phase noise in the
signal band of interest is too large, the wanted signal cannot not be recovered.
The resulting equivalent phase noise at the ADC input is also dependent on the sampling rate of the ADC and
frequency of the input signal. The ADC sampling rate scales the clock phase noise, as shown in Equation 8.
ADCNSD dBc / Hz
PNCLK dBc / Hz
§f ·
20 u log ¨ S ¸
© fIN ¹
(8)
Using this information, the noise contribution resulting from the phase noise profile of the ADC sampling clock
can be calculated.
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9.1.4 Power Consumption in Different Modes
The ADC32RF45 consumes approximately 6.6 W of power when both channels are active with a 12-bit, 3-GSPS
output and a DDC option is not used (bypass mode). When different DDC options are used, the power
consumption on the DVDD supply changes by a small amount but remains unaffected on other supplies. In the
applications requiring just one channel to be active, channel A must be chosen as the active channel and
channel B can be powered down. Power consumption reduces to approximately 4 W in single-channel operation
with a 12-bit, 3-GSPS output (bypass mode).
Table 117 shows power consumption in different DDC modes for dual-channel and single-channel operation.
Table 117. Power Consumption in Different DDC Modes (Sampling Clock Frequency, f S = 3 GSPS)
DECIMATION
OPTION
ACTIVE
CHANNEL
ACTIVE DDC
AVDD19 (mA)
AVDD (mA)
DVDD (mA)
TOTAL POWER
(mW)
Bypass mode
Divide-by-4
Channels A, B
NA
1792
972
1748
6533
Channels A, B
Single
1777
970
1785
6545
Divide-by-8
Divide-by-8
Channels A, B
Dual
1777
973
1960
6749
Channels A, B
Single
1777
973
1730
6485
Divide-by-16
Channels A, B
Dual
1777
972
1971
6761
Divide-by-16
Channels A, B
Single
1777
972
1705
6455
Divide-by-24
Channels A, B
Dual
1771
975
1938
6715
Divide-by-24
Channels A, B
Single
1771
972
1667
6400
Divide-by-32
Channels A, B
Dual
1768
972
1835
6587
Divide-by-32
Channels A, B
Single
1768
970
1574
6285
Bypass mode
Channel A
NA
968
793
1133
4054
Divide-by-4
Channel A
Single
961
796
1096
4002
Divide-by-8
Channel A
Dual
961
790
1168
4078
Divide-by-8
Channel A
Single
961
786
1047
3934
Divide-by-16
Channel A
Dual
961
789
1172
4081
Divide-by-16
Channel A
Single
961
786
1045
3932
Divide-by-24
Channel A
Dual
958
785
1155
4051
Divide-by-24
Channel A
Single
958
787
1016
3894
Divide-by-32
Channel A
Dual
956
788
1104
3992
Divide-by-32
Channel A
Single
956
786
978
3845
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9.1.5 Using DC Coupling in the ADC32RF45
The ADC32RF45 can be used in dc-coupling applications. However, the following points must be considered
when designing the system:
1. Ensure that the correct common-mode voltage is used at the ADC analog inputs.
The analog inputs are internally self-biased to VCM through approximately a 33-Ω resistor. The internal
biasing resistors also function as a termination resistor. However, if a different termination is required, the
external resistor RTERM can be differentially placed between the analog inputs, as shown in Figure 234. The
amplifier VOCM pin is recommended to be driven from the CM pin of the ADC to help the amplifier output
common-mode voltage track the required common-mode voltage of the ADC.
ADC32RF45
ADC
Digital
INxP
OUTP
RS / 2
RDC/2(2)
Low-Pass
Filter
Driving Amp
RTERM
RDC / 2
RCM(1)
VCM
Offset
Corrector
Interleaving
Engine
DDC
Block
JESD
204B
Interface
Digital
Ouput
RS / 2
OUTM
INxM
VOCM
CM
Copyright © 2016, Texas Instruments Incorporated
(1)
Set the INCR CM IMPEDANCE bit to increase the RCM from 0 Ω to > 5000 Ω.
(2)
RDC is approximately 65 Ω.
Figure 234. The ADC32RF45 in a DC-Coupling Application
2. Ensure that the correct SPI settings are written to the ADC.
As shown in Figure 235, the ADC32RF45 has a digital block that estimates and corrects the offset mismatch
among four interleaving ADC cores for a given channel.
Offset Corrector
+
Data In
Freeze
Correction
Data Out
+
±
Disable
Correction
Estimator
Figure 235. Offset Corrector in the ADC32RF45
The offset corrector block nullifies dc, fS / 8, fS / 4, 3 fS / 8, and fS / 2. The resulting spectrum becomes free
from static spurs at these frequencies. The corrector continuously processes the data coming from the
interleaving ADC cores and cannot distinguish if the tone at these frequencies is part of signal or if the tone
originated from a mismatch among the interleaving ADC cores. Thus, in applications where the signal is
present at these frequencies, the offset corrector block can be bypassed.
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9.1.5.1 Bypassing the Offset Corrector Block
When the offset corrector is bypassed, offset mismatch among interleaving ADC cores appears in the ADC
output spectrum. To correct the effects of mismatch, place the ADC in an idle channel state (no signal at the
ADC inputs) and the corrector must be allowed to run for some time to estimate the mismatch, then the corrector
is frozen so that the last estimated value is held. Required register writes are provided in Table 118.
Table 118. Freezing and Bypassing the Offset Corrector Block
STEP
REGISTER WRITE
COMMENT
STEPS FOR FREEZING THE CORRECTOR BLOCK
1
—
Signal source is turned off. The device detects an idle channel at its input.
2
—
Wait for at least 0.4 ms for the corrector to estimate the internal offset
Address 4001h, value 00h
Address 4002h, value 00h
Address 4003h, value 00h
3
Select Offset Corr Page Channel A
Address 4004h, value 61h
4
Address 6068h, value C2h
Freeze the corrector for channel A
Address 4003h, value 01h
Select Offset Corr Page Channel B
Address 6068h, value C2h
Freeze the corrector for channel B
—
Signal source can now be turned on
STEPS FOR BYPASSING THE CORRECTOR BLOCK
Address 4001h, value 00h
Address 4002h, value 00h
—
Address 4003h, value 00h
1
Address 4004h, value 61h
Select Offset Corr Page Channel A
Address 6068h, value 46h
Disable the corrector for channel A
Address 4003h, value 01h
Select Offset Corr Page Channel B
Address 6068h, value 46h
Disable the corrector for channel B
9.1.5.1.1 Effect of Temperature
Figure 236 and Figure 237 show the behavior of nfS / 8 tones with respect to temperature when the offset
corrector block is frozen or disabled.
-40
-20
Average of fS/8
Average of 3fS/8
Average of fS/4
-50
Average of fS/4
Average of fS/8
Average of 3fS/8
-30
Spurs (dBFS)
Spurs (dBFS)
-40
-60
-70
-80
-50
-60
-70
-80
-90
-100
-40
-90
-15
10
35
Temperature (°C)
60
85
Figure 236. Offset Corrector Block Frozen at Room
Temperature
118
-100
-40
-15
10
35
Temperature (°C)
60
85
Figure 237. Offset Corrector Block Disabled
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ADC32RF45
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9.2 Typical Application
The ADC32RF45 is designed for wideband receiver applications demanding high dynamic range over a large
input frequency range. A typical schematic for an ac-coupled receiver is shown in Figure 238.
Decoupling capacitors with low ESL are recommended to be placed as close as possible at the pins indicated in
Figure 238. Additional capacitors can be placed on the remaining power pins.
DVDD
Matching Network
10 k
0.1 F
Driver
SPI Master
GND
0.1 F
0.1 F
GND
SYSREFP
SYSREFM
SYNCBP
SYNCBM
2
100-
10 nF
72
20
71
21
70
22
69
23
68
24
67
25
66
26
65
27
64
ADC32RF45
28
63
GND PAD (backside)
29
62
30
61
31
60
32
59
33
58
34
57
35
56
36
55
38
39
40
42
43
44
45
46
47
48
49
50
51
52
53
DB2P
DB2M
DVDD
DB1P
DVDD
10 nF
GND
10 nF
DB1M
GND
10 nF
DB0P
DB0M
DVDD
GPIO4
DVDD
0.1 F
GND
DA0M
DA0P
GND
10 nF
DA1M
FPGA
DA1P
DVDD
DA2M
DVDD
10 nF
10 nF
GND
DA2P
10 nF
54
DA3M
DA3P
GND
DVDD
PDN
GND
RESET
DVDD
AVDD
AVDD19
AVDD
AVDD
INAP
INAM
AVDD
AVDD19
AVDD
GND
AVDD19
AVDD
41
Differential
1
19
37
100-
Differential
10 nF
DVDD
AVDD
AVDD19
0.1 F
0.1 F
GND
Driver
3
DB3M
AVDD19
4
DB3P
AVDD19
0.1 F
AVDD
5
GND
0.1 F
Low Jitter Clock
Generator
6
DVDD
GND
7
SDIN
10 nF
8
SCLK
CLKINM
9
SEN
CLKINP
DVDD
GND
10
AVDD
AVDD
0.1 F
AVDD
11
DVDD
AVDD19
Matching
Network
AVDD19
12
SDOUT
0.1 F
AVDD19
13
AVDD
GND
14
INBP
0.1 F
15
INBM
VCM
16
AVDD
GPIO3
AVDD19
GND
GPIO2
AVDD
GPIO1
17
10 nF
0.1 F
AVDD
AVDD19
18
DVDD
0.1 F
AVDD19
AVDD
0.1 F
DVDD
0.1 F
Matching Network
Copyright © 2016, Texas Instruments Incorporated
Figure 238. Typical Application Implementation Diagram
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Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Transformer-Coupled Circuits
Typical applications involving transformer-coupled circuits are discussed in this section. To ensure good
amplitude and phase balance at the analog inputs, transformers (such as TC1-1-13 and TC1-1-43) can be used
from the dc to 1000-MHz range and from the 1000-MHz to 4-GHz range of input frequencies, respectively. When
designing the driving circuits, the ADC input impedance (or SDD11) must be considered.
By using the simple drive circuit of Figure 239, uniform performance can be obtained over a wide frequency
range. The buffers present at the analog inputs of the device help isolate the external drive source from the
switching currents of the sampling circuit.
0.1 F
T2
T1
5
(Optional)
0.1 F
CHx_INP
RIN
5
(Optional)
0.1 F
1:1
CIN
CHx_INM
1:1
TI Device
Copyright © 2016, Texas Instruments Incorporated
Figure 239. Input Drive Circuit
9.2.2 Detailed Design Procedure
For optimum performance, the analog inputs must be driven differentially. This architecture improves commonmode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input
pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 239.
9.2.3 Application Curves
0
0
-10
-10
-20
-20
-30
-30
Amplitude (dBFS)
Amplitude (dBFS)
Figure 240 and Figure 241 show the typical performance at 100 MHz and 1780 MHz, respectively.
-40
-50
-60
-70
-80
-50
-60
-70
-80
-90
-90
-100
-100
-110
-110
0
120
-40
300
600
900
Input Frequency (MHz)
1200
1500
0
D001
300
600
900
Input Frequency (MHz)
1200
1500
D003
SNR = 61.8 dBFS, SINAD = 61.2 dBFS,
HD2 = 71 dBc, HD3 = 75 dBc, SFDR = 71 dBc,
THD = 68 dBc, IL spur = 77 dBc, worst spur = 73 dBc
SNR = 57.9 dBFS, SINAD = 57.1 dBFS,
HD2 = 63 dBc, HD3 = 66 dBc, SFDR = 63 dBc,
THD = 60 dBc, IL spur = 79 dBc, worst spur = 77 dBc
Figure 240. FFT for 100-MHz Input Frequency
Figure 241. FFT for 1780-MHz Input Frequency
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SBAS747C – MAY 2016 – REVISED DECEMBER 2016
10 Power Supply Recommendations
The device requires a 1.15-V nominal supply for DVDD, a 1.15-V nominal supply for AVDD, and a 1.9-V nominal
supply for AVDD19. There is no specific sequence for power-supply requirements during device power-up.
AVDD, DVDD, and AVDD19 can power-up in any order.
11 Layout
11.1 Layout Guidelines
The device evaluation module (EVM) layout can be used as a reference layout to obtain the best performance. A
layout diagram of the EVM top layer is provided in Figure 242. The ADC32RF45/RF80 EVM Quick Startup Guide
provides a complete layout of the EVM. Some important points to remember during board layout are:
• Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package
level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as shown
in the reference layout of Figure 242 as much as possible.
• In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to
minimize coupling. This configuration is also maintained on the reference layout of Figure 242 as much as
possible.
• Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output
traces must not be kept parallel to the analog input traces because this configuration can result in coupling
from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver
[such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs)] must be
matched in length to avoid skew among outputs.
• At each power-supply pin (AVDD, DVDD, or AVDD19), keep a 0.1-µF decoupling capacitor close to the
device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF
capacitors can be kept close to the supply source.
11.2 Layout Example
Figure 242. ADC32RF45EVM Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• ADC32RF45/RF80 EVM Quick Startup Guide (SLAU620)
• Configuration Files for the ADC32RF45 (SBAA226)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
122
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADC32RF45IRMP
ACTIVE
VQFN
RMP
72
168
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ32RF45
ADC32RF45IRMPT
ACTIVE
VQFN
RMP
72
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ32RF45
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Aug-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADC32RF45IRMPT
Package Package Pins
Type Drawing
VQFN
RMP
72
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
24.4
Pack Materials-Page 1
10.25
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.25
2.25
16.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADC32RF45IRMPT
VQFN
RMP
72
250
213.0
191.0
55.0
Pack Materials-Page 2
PACKAGE OUTLINE
RMP0072A
VQFN - 0.9 mm max height
SCALE 1.700
VQFN
10.1
9.9
B
A
PIN 1 ID
10.1
9.9
0.9 MAX
0.05
0.00
C
0.08 C
(0.2)
SEATING PLANE
4X (45 X0.42)
19
36
18
4X
8.5
37
SYMM
8.5 0.1
PIN 1 ID
(R0.2)
1
68X 0.5
54
55
72
SYMM
72X
0.5
0.3
72X
0.30
0.18
0.1
0.05
C B
C
A
4221047/B 02/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RMP0072A
VQFN - 0.9 mm max height
VQFN
(
8.5)
SYMM
72X (0.6)
SEE DETAILS
55
72
1
54
72X (0.24)
(0.25) TYP
(9.8)
SYMM
(1.315) TYP
68X (0.5)
( 0.2) TYP
VIA
37
18
19
36
(1.315) TYP
(9.8)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221047/B 02/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB application report
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RMP0072A
VQFN - 0.9 mm max height
VQFN
(9.8)
72X (0.6)
(1.315) TYP
72
55
1
54
72X (0.24)
(1.315)
TYP
(0.25) TYP
SYMM
(1.315)
TYP
(9.8)
68X (0.5)
METAL
TYP
37
18
( 0.2) TYP
VIA
19
36
36X ( 1.115)
(1.315) TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
62% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
4221047/B 02/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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