Texas Instruments | DAC121S101QML-SP Radiation Hardened 12-Bit Micro Power Digital-to-Analog Converter With Rail-to-Rail Output (Rev. F) | Datasheet | Texas Instruments DAC121S101QML-SP Radiation Hardened 12-Bit Micro Power Digital-to-Analog Converter With Rail-to-Rail Output (Rev. F) Datasheet

Texas Instruments DAC121S101QML-SP Radiation Hardened 12-Bit Micro Power Digital-to-Analog Converter With Rail-to-Rail Output (Rev. F) Datasheet
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DAC121S101QML-SP
SNAS410F – MAY 2008 – REVISED JULY 2016
DAC121S101QML-SP Radiation Hardened 12-Bit Micro Power Digital-to-Analog Converter
With Rail-to-Rail Output
1 Features
3 Description
•
The DAC121S101QML-SP device is a full-featured,
general-purpose, 12-bit voltage-output digital-toanalog converter (DAC) that can operate from a
single 2.7-V to 5.5-V supply and consumes just
177 µA of current at 3.6 V. The on-chip output
amplifier allows rail-to-rail output swing and the threewire serial interface operates at clock rates up to
20 MHz over the specified supply voltage range and
is compatible with standard SPI, QSPI, MICROWIRE,
and DSP interfaces.
1
•
•
•
•
•
•
•
•
•
5962R07726
– Total Ionizing Dose 100 krad(Si)
– Single Event Latch-up Immune
120 MeV-cm2/mg
– Single Event Functional Interrupt Immune
120 MeV-cm2/mg (See Radiation Report)
Ensured Monotonicity
Low Power Operation
Rail-to-Rail Voltage Output
Power-On Reset to Zero Volts Output
SYNC Interrupt Facility
Wide Power Supply Range (2.7 V to 5.5 V)
Small Packages
Power-Down Feature
Key Specifications
– Resolution: 12 Bits
– DNL: +0.21, –0.10 LSB (Typical)
– Output Settling Time: 12.5 µs (Typical)
– Zero Code Error: 2.1 mV (Typical)
– Full-Scale Error: −0.04% FS (Typical)
– Power Dissipation
– Normal Mode: 0.52 mW (3.6 V) and 1.19
mW (5.5 V) Typical
– Power-Down Mode: 0.014 µW (3.6 V) and
0.033 µW (5.5 V) Typical
2 Applications
•
•
Satellites
– Altitude and Orbit Control
– Precision Sensors
– Motor Control
High Temperatures
The supply voltage for the DAC121S101QML-SP
serves as its voltage reference, providing the widest
possible output dynamic range. A power-on reset
circuit ensures that the DAC output powers up to zero
volts and remains there until there is a valid write to
the device. A power-down feature reduces power
consumption to less than a microWatt.
The low power consumption and small packages of
the DAC121S101QML-SP make it an excellent
choice for use in battery-operated equipment.
Device Information(1)
PART NUMBER
GRADE
PACKAGE
DAC121S101WGRQV
5962R0722601VZA 100 krad
10-lead ceramic
SOIC
DAC121S101WGRLV
5962R0722602VZA 100 krad
ELDRS-Free
10-lead ceramic
SOIC
DAC121S101-MDR
5962R0722601V9A 100 krad
Die
DAC121S101WGMPR
Pre-Flight Engineering
Prototype
10-lead ceramic
SOIC
DAC121S101CVAL
Ceramic Evaluation Board
10-lead ceramic
SOIC
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
VA
GND
POWER-ON
RESET
DAC121S101
REF(+) REF(-)
DAC
REGISTER
12
12-BIT DAC
BUFFER
VOUT
12
POWER-DOWN
CONTROL
LOGIC
INPUT
CONTROL
LOGIC
SYNC
SCLK
DIN
5k
100k
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC121S101QML-SP
SNAS410F – MAY 2008 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
DAC121S101QML-SP Electrical Characteristics DC
Parameters................................................................. 5
DAC121S101QML-SP Electrical Characteristics AC
and Timing Characteristics ........................................ 7
DAC121S101QML Electrical Characteristics
Radiation Electrical Characteristics ........................... 7
DAC121S101QML-SP Electrical Characteristics
Operating Life Test Delta Parameters
TA at 25°C .................................................................. 8
Typical Characteristics ............................................ 10
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 16
7.5 Programming........................................................... 17
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 21
9
Power Supply Recommendations...................... 22
9.1 Using References as Power Supplies..................... 22
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
27
27
27
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
12.1 Engineering Samples ............................................ 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2013) to Revision F
Page
•
Changed data sheet title DAC121S101QML 12-Bit Micro Power Digital-to-Analog Converter With Rail-to-Rail Output
to DAC121S101QML-SP Radiation Hardened 12-Bit Micro Power Digital-to-Analog Converter With Rail-to-Rail Output.... 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision D (March 2013) to Revision E
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 20
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Product Folder Links: DAC121S101QML-SP
DAC121S101QML-SP
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SNAS410F – MAY 2008 – REVISED JULY 2016
5 Pin Configuration and Functions
NAC Package
10-Pin CFP
Top View
VA
1
10
GND
N/C
2
9
DIN
N/C
3
8
SCLK
VOUT
4
7
SYNC
N/C
5
6
N/C
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
VA
—
Power supply and reference input; must be decoupled to GND
2
N/C
—
No connect; pin not internally connected to die
3
N/C
—
No connect; pin not internally connected to die
4
VOUT
Output
5
N/C
—
No connect; pin not internally connected to die
6
N/C
—
No connect; pin not internally connected to die
DAC analog output voltage
7
SYNC
Input
Frame synchronization input for the data input. When this pin goes low, it enables the input
shift register and data is transferred on the falling edges of SCLK. The DAC is updated on
the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
8
SCLK
Input
Serial clock input; data is clocked into the input shift register on the falling edges of this pin.
9
DIN
Input
Serial data input; data is clocked into the 16-bit shift register on the falling edges of SCLK
after the fall of SYNC.
10
GND
—
Ground reference for all on-chip circuitry
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: DAC121S101QML-SP
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DAC121S101QML-SP
SNAS410F – MAY 2008 – REVISED JULY 2016
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6 Specifications
6.1 Absolute Maximum Ratings (1) (2)
MIN
Supply voltage, VA
−0.3
Voltage on any input pin
MAX
UNIT
6.5
V
(VA + 0.3)
V
Input current at any pin (3)
10
mA
Maximum output current (4)
10
mA
VOUT pin in power-down mode
1
mA
Package input current (3)
20
mA
175
°C
260
°C
220
mg
150
°C
Power dissipation at TA = 25°C
See
Maximum junction temperature
Lead temperature
CFP package
(Soldering 10 Seconds)
Package weight (typical)
CFP package
−65
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
(5)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are measured with respect to GND = 0 V, unless otherwise specified.
When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than VA), the current at that pin should
be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power
supplies with an input current of 10 mA to two.
Maximum output current may not exceed 10 mA. At VDD = 5.5 V the minimum external resistive load can be no less than 550 Ω
(360 Ω at VDD = 3.6 V).
The absolute maximum junction temperature (TJmax) for this device is 175°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (RθJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA) / RθJA. The values for maximum power dissipation will be reached only when the device is operated in a severe
fault condition (for example, when input or output pins are driven beyond the power supply voltages, or the power supply polarity is
reversed). Obviously, such conditions must be avoided.
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2)
VALUE
UNIT
±5000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Human body model is 100-pF capacitor discharged through a 1.5-kΩ resistor. Machine model is 220 pF discharged through 0 Ω.
6.3 Recommended Operating Conditions
MIN
MAX
UNIT
−55
125
°C
Supply voltage, VA
2.7
5.5
V
Any input voltage (1)
−0.1
(VA + 0.1)
V
0
1500
pF
Operating temperature
Output load
SCLK frequency
(1)
20
MHz
The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not
damage this device. However, errors in the conversion result can occur if any input goes above VA or below GND by more than 100 mV.
For example, if VA is 2.7-V DC , ensure that –100 mV ≤ input voltages ≤ 2.8-V DC to ensure accurate conversions.
I/O
TO INTERNAL
CIRCUITRY
GND
4
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SNAS410F – MAY 2008 – REVISED JULY 2016
6.4 Thermal Information
THERMAL METRIC
DAC121S101QML
-SP
(1) (2)
UNIT
NAC (CFP)
10 PINS
RθJA
Junction-to-ambient thermal resistance
214
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
25.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
10-pin CFP Package on 2-layer, 1-oz. PCB
(2)
6.5 DAC121S101QML-SP Electrical Characteristics DC Parameters
The following specifications apply for VA = 2.7 V to 5.5 V, RL = ∞, CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48
to 4047. All limits TA = 25°C, unless otherwise specified.
PARAMETER
TEST CONDITIONS
NOTES
SUBGROUPS
MIN
TYP (1) MAX
UNIT
STATIC PERFORMANCE
Resolution
TMIN ≤ TA ≤ TMAX
See (2)
12
Bits
Monotonicity
TMIN ≤ TA ≤ TMAX
See (2)
12
Bits
Integral non-linearity
Over Decimal codes 48 to 4047
DNL
Differential non-linearity
VA = 2.7 V to
5.5 V
ZE
Zero code error
IOUT = 0
[1, 2, 3]
2.12
15
mV
FSE
Full-scale error
IOUT = 0
[1, 2, 3]
−0.04
−1
%FSR
GE
Gain error
All ones Loaded to DAC register
[1, 2, 3]
−0.11
±1
%FSR
ZCED
Zero code error drift
TC GE
Gain error tempco
INL
[1, 2, 3]
DNL MAX
[1, 2, 3]
DNL MIN
−8
−0.7
See (2)
VA = 3 V
VA = 5 V
±2.75
8
0.21
1
LSB
LSB
−0.1
−20
µV/°C
−0.7
See (2)
ppm/°C
−1
OUTPUT CHARACTERISTICS
IPD
SINK
Vout pin in power-down
mode
Output voltage range
ZCO
FSO
Zero code output
Full-scale output
Maximum load
capacitance
All PD Modes, TMIN ≤ TA ≤ TMAX
TMIN ≤ TA ≤ TMAX
See (2)
See
1
(2)
0
VA
VA = 3 V, IOUT = 10 µA
[1, 2, 3]
2
6
VA = 3 V, IOUT = 100 µA
[1, 2, 3]
4
10
VA = 5 V, IOUT = 10 µA
[1, 2, 3]
2
8
VA = 5 V, IOUT = 100 µA
[1, 2, 3]
4
9
VA = 3 V, IOUT = 10 µA
[1, 2, 3]
2.99
2.997
VA = 3 V, IOUT = 100 µA
[1, 2, 3]
2.985
2.991
VA = 5 V, IOUT = 10 µA
[1, 2, 3]
4.985
4.994
VA = 5 V, IOUT = 100 µA
[1, 2, 3]
4.985
4.992
RL = ∞
RL = 2 kΩ
DC output impedance
mV
pF
1500
[1, 2, 3]
V
V
1500
See (2)
mA
8
16
Ω
6
200
nA
LOGIC INPUT
IIN
Input current
VIL
Input low voltage
VIH
Input high voltage
(1)
(2)
[1, 2, 3]
−200
VA = 5 V, TMIN ≤ TA ≤ TMAX
[1, 2, 3]
0.8
VA = 3 V, TMIN ≤ TA ≤ TMAX
[1, 2, 3]
0.5
VA = 5 V, TMIN ≤ TA ≤ TMAX
[1, 2, 3]
2.4
VA = 3 V, TMIN ≤ TA ≤ TMAX
[1, 2, 3]
2.1
V
V
Typical figures are at TJ = 25°C, and represent most likely parametric norms.
This parameter is ensured by design and/or characterization and is not tested in production.
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DAC121S101QML-SP Electrical Characteristics DC Parameters (continued)
The following specifications apply for VA = 2.7 V to 5.5 V, RL = ∞, CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48
to 4047. All limits TA = 25°C, unless otherwise specified.
PARAMETER
CIN
TEST CONDITIONS
NOTES
SUBGROUPS
See (2)
Input capacitance
MIN
TYP (1) MAX
5
UNIT
pF
POWER REQUIREMENTS
IA
PC
IOUT
IA
6
Supply current (output
unloaded)
Power consumption
(output unloaded)
Power efficiency
Submit Documentation Feedback
Normal Mode 5.5 V
fSCLK = 20 MHz
[1, 2, 3]
216
270
Normal Mode 3.6 V
fSCLK = 20 MHz
[1, 2, 3]
145
200
Normal Mode 5.5 V
fSCLK = 10 MHz
[1, 2, 3]
185
230
Normal Mode 3.6 V
fSCLK = 10 MHz
[1, 2, 3]
132
175
Normal Mode 5.5 V
fSCLK = 0
[1, 2, 3]
150
190
Normal Mode 3.6 V
fSCLK = 0
[1, 2, 3]
115
160
All PD Modes, 5.5 V
fSCLK = 20 MHz
[1, 2, 3]
22
60
All PD Modes, 3.6 V
fSCLK = 20 MHz
[1, 2, 3]
12
30
All PD Modes, 5.5 V
fSCLK = 10 MHz
[1, 2, 3]
12
40
All PD Modes, 3.6 V
fSCLK = 10 MHz
[1, 2, 3]
6
20
All PD Modes, 5.5 V
fSCLK = 0
[1, 2, 3]
0.006
1
All PD Modes, 3.6 V
fSCLK = 0
[1, 2, 3]
0.004
1
Normal Mode, 5.5 V
fSCLK = 20 MHz
[1, 2, 3]
1.19
1.49
Normal Mode 3.6 V
fSCLK = 20 MHz
[1, 2, 3]
0.52
0.72
Normal Mode, 5.5 V
fSCLK = 10 MHz
[1, 2, 3]
1.02
1.27
Normal Mode 3.6 V
fSCLK = 10 MHz
[1, 2, 3]
0.47
0.63
Normal Mode, 5.5 V
fSCLK = 0
[1, 2, 3]
0.82
1.05
Normal Mode 3.6 V
fSCLK = 0
[1, 2, 3]
0.41
0.58
All PD Modes, 5.5 V
fSCLK = 20 MHz
[1, 2, 3]
0.12
0.33
All PD Modes, 3.6 V
fSCLK = 20 MHz
[1, 2, 3]
0.07
0.11
All PD Modes, 5.5 V
fSCLK = 10 MHz
[1, 2, 3]
0.04
0.22
All PD Modes, 3.6 V
fSCLK = 10 MHz
[1, 2, 3]
0.02
0.08
All PD Modes, 5.5 V
fSCLK = 0
[1, 2, 3]
0.033
5.5
All PD Modes, 3.6 V
fSCLK = 0
[1, 2, 3]
0.014
3.6
ILOAD = 2 mA
µA
mW
91%
See (2)
94%
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6.6 DAC121S101QML-SP Electrical Characteristics AC and Timing Characteristics
The following specifications apply for VA = 2.7 V to 5.5 V, RL = ∞, CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48
to 4047. All limits TA = 25°C, unless otherwise specified.
PARAMETER
fSCLK
SCLK frequency
Output voltage
settling time
ts
SR
TEST CONDITIONS
SUBGROUPS
(See Figure 31)
MIN
TYP (1) MAX
UNIT
20
MHz
[9,10,11]
FF0 to 00F code
change, RL = ∞
CL ≤ 200 pF
[9,10,11]
12.5
15
CL = 500 pF
[9,10,11]
12.5
15
00Fh to FF0h code
change, RL = ∞
CL ≤ 200 pF
[9,10,11]
12.5
15
[9,10,11]
12.5
15
CL = 500 pF
Output slew rate
Glitch impulse
NOTES
Code change from 800h to 7FFh
See (2)
1
V/µs
See (2)
12
nV-sec
0.5
nV-sec
See (2)
Digital feedthrough
VA = 5 V
µs
0.65
See (2)
tWU
Wake-Up Time
1/fSCLK
SCLK cycle time
(See Figure 31)
[9,10,11]
50
ns
tH
SCLK high time
(See Figure 31)
[9,10,11]
20
ns
tL
SCLK low time
(See Figure 31)
[9,10,11]
20
ns
tSUCL
Setup time SYNC to
(See Figure 31)
SCLK rising edge
[9,10,11]
0
ns
tSUD
Data setup time
(See Figure 31)
[9,10,11]
6
ns
tDHD
Data hold time
(See Figure 31)
[9,10,11]
4.5
ns
tCS
SCLK fall to rise of
SYNC
VA = 5.5 V (See Figure 31)
[9,10,11]
10
VA = 2.7 V (See Figure 31)
[9,10,11]
18
tSYNC
SYNC high time
VA = 5.5 V (See Figure 31)
[9,10,11]
37
VA = 2.7 V (See Figure 31)
[9,10,11]
36
(1)
(2)
VA = 3 V
µs
1.1
ns
ns
Typical figures are at TJ = 25°C, and represent most likely parametric norms.
This parameter is ensured by design and/or characterization and is not tested in production.
6.7 DAC121S101QML Electrical Characteristics Radiation Electrical Characteristics (1)
The following specifications apply for VA = 2.7 V to 5.5 V, RL = ∞, CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48
to 4047.
PARAMETER
SUBGROUPS
TEST CONDITIONS
MIN
MAX
UNIT
POWER REQUIREMENTS
IA
(1)
Supply current (output
unloaded)
Normal Mode
fSCLK = 20 MHz
5.5 V
[1]
325
3.6 V
[1]
250
Normal Mode
fSCLK = 10 MHz
5.5 V
[1]
300
3.6 V
[1]
225
Normal Mode
fSCLK = 0
5.5 V
[1]
275
3.6 V
[1]
200
All PD Modes,
fSCLK = 20 MHz
5.5 V
[1]
125
3.6 V
[1]
100
All PD Modes,
fSCLK = 10 MHz
5.5 V
[1]
115
3.6 V
[1]
95
All PD Modes,
fSCLK = 0
5.5 V
[1]
100
3.6 V
[1]
100
µA
Pre- and post-irradiation limits are identical to those listed in the DAC121S101QML-SP Electrical Characteristics DC Parameters and
DAC121S101QML-SP Electrical Characteristics AC and Timing Characteristics tables, except as listed in the Radiation Electrical
Characteristics table. When performing post irradiation electrical measurements for any RHA level, TA = 25°C. See Radiation
Environments for dose rate and test conditions.
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6.8 DAC121S101QML-SP Electrical Characteristics Operating Life Test Delta Parameters
TA at 25°C (1)
PARAMETER
TEST CONDITIONS
SUB-GROUPS
MIN
MAX
UNIT
INL
Integral non-linearity
[1]
±2
LBS
ts
Output voltage settling time
[1]
±5
µA
Normal Mode, VA = 5.5 V, fSCLK = 20 MHz
[1]
±10
Normal Mode, VA = 3.6 V, fSCLK = 20 MHz
[1]
±6
Normal Mode, VA = 5.5 V, fSCLK = 10 MHz
[1]
±10
Normal Mode, VA = 3.6 V, fSCLK = 10 MHz
[1]
±6
Normal Mode, VA = 5.5 V, fSCLK = 0
[1]
±8
Normal Mode, VA = 3.6 V, fSCLK = 0
[1]
±6
All PD Modes, VA = 5.5 V, fSCLK = 20 MHz
[1]
±2
All PD Modes, VA = 3.6 V, fSCLK = 20 MHz
[1]
±1
All PD Modes, VA = 5.5 V, fSCLK = 10 MHz
[1]
±1
All PD Modes, VA = 3.6 V, fSCLK = 10 MHz
[1]
±1
All PD Modes, VA = 5.5 V, fSCLK = 0
[1]
±0.1
All PD Modes, VA = 3.6 V, fSCLK = 0
[1]
±0.1
IA
(1)
Supply current (output
unloaded)
µA
These parameters are worse case drift. Deltas are performed at room temperature Post OP Life. All other parameters no Deltas are
required.
The DAC121S101QML-SP operates over the extended temperature range of –55°C to +125°C.
See Radiation Environments for dose rate environment information.
Table 1. Quality Conformance Inspection (1)
(1)
8
SUB-GROUP
DESCRIPTION
1
Static tests at
TEMP (°C)
+25
2
Static tests at
+125
3
Static tests at
–55
4
Dynamic tests at
+25
5
Dynamic tests at
+125
6
Dynamic tests at
–55
7
Functional tests at
+25
8A
Functional tests at
+125
8B
Functional tests at
–55
9
Switching tests at
+25
10
Switching tests at
+125
11
Switching tests at
–55
12
Setting time at
+25
13
Setting time at
+125
14
Setting time at
–55
MIL-STD-883, Method 5005 - Group A
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FSE
4095 x VA
4096
GE = FSE - ZE
FSE = GE + ZE
OUTPUT
VOLTAGE
ZE
0
0
4095
DIGITAL INPUT CODE
Figure 1. Input / Output Transfer Characteristic
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6.9 Typical Characteristics
fSCLK = 20 MHz, TA = 25°C, Input Code Range 48 to 4047, unless otherwise stated
10
Figure 2. DNL at VA = 2.7 V
Figure 3. DNL at VA = 5.5 V
Figure 4. INL at VA = 2.7 V
Figure 5. INL at VA = 5.5 V
Figure 6. DNL vs VA
Figure 7. INL vs VA
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Typical Characteristics (continued)
fSCLK = 20 MHz, TA = 25°C, Input Code Range 48 to 4047, unless otherwise stated
Figure 8. 2.7-V DNL vs fSCLK
Figure 9. 5.5-V DNL vs fSCLK
Figure 10. 2.7-V DNL vs Clock Duty Cycle
Figure 11. 5.5-V DNL vs Clock Duty Cycle
Figure 12. 2.7-V DNL vs Temperature
Figure 13. 5.5-V DNL vs Temperature
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Typical Characteristics (continued)
fSCLK = 20 MHz, TA = 25°C, Input Code Range 48 to 4047, unless otherwise stated
12
Figure 14. 2.7-V INL vs fSCLK
Figure 15. 5.5-V INL vs fSCLK
Figure 16. 2.7-V INL vs Clock Duty Cycle
Figure 17. 5.5-V INL vs Clock Duty Cycle
Figure 18. 2.7-V INL vs Temperature
Figure 19. 5.5-V INL vs Temperature
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Typical Characteristics (continued)
fSCLK = 20 MHz, TA = 25°C, Input Code Range 48 to 4047, unless otherwise stated
Figure 20. Zero Code Error vs fSCLK
Figure 21. Zero Code Error vs Temperature
Figure 22. Full-Scale Error vs fSCLK
Figure 23. Full-Scale Error vs Temperature
Figure 24. Supply Current vs VA
Figure 25. Supply Current vs Temperature
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Typical Characteristics (continued)
fSCLK = 20 MHz, TA = 25°C, Input Code Range 48 to 4047, unless otherwise stated
14
Figure 26. 5-V Glitch Response
Figure 27. Power-On Reset
Figure 28. 3-V Wake-Up Time
Figure 29. 5-V Wake-Up Time
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7 Detailed Description
7.1 Overview
The DAC121S101QML-SP device is a full-featured, general purpose 12-bit voltage-output digital-to-analog
converter (DAC). Control of the output of the DAC is achieved over a 3-wire SPI interface. Once the DAC output
has been set, additional communication with the DAC is not required unless the output condition needs to be
changed. Likewise, the DAC121S101QML-SP power-on state is 0 V. The DAC output will remain at 0 V until a
valid write sequence is made.
7.2 Functional Block Diagram
VA
GND
POWER-ON
RESET
DAC121S101
REF(+) REF(-)
DAC
REGISTER
12
12-BIT DAC
BUFFER
VOUT
12
POWER-DOWN
CONTROL
LOGIC
INPUT
CONTROL
LOGIC
SYNC
SCLK
DIN
5k
100k
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7.3 Feature Description
7.3.1 DAC Section
The DAC121S101QML-SP is fabricated on a CMOS process with an architecture that consists of switches and a
resistor string that are followed by an output buffer. The power supply serves as the reference voltage. The input
coding is straight binary with an ideal output voltage of:
VOUT = VA × (D / 4096)
where
•
D is the decimal equivalent of the binary code that is loaded into the DAC register and can take on any value
between 0 and 4095.
(1)
7.3.2 Resistor String
Figure 30 shows the simplified resistor string. Conceptually, this string consists of 4096 equal valued resistors
with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register
determines which switch is closed, connecting the proper node to the amplifier. This configuration ensures that
the DAC is monotonic.
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Feature Description (continued)
VA
R
R
R
To Output Amplifier
R
R
Figure 30. DAC Resistor String
7.3.3 Output Amplifier
The output buffer amplifier is a rail-to-rail type, providing an output voltage range of 0 V to VA. All amplifiers, even
rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0 V and VA, in this case). For
this reason, linearity is specified over less than the full output range of the DAC. The output capabilities of the
amplifier are described in the electrical tables in Specifications.
7.3.4 Power-On Reset
The power-on reset circuit controls the output voltage during power-up. Upon application of power, the DAC
register is filled with zeros and the output voltage is 0 V and remains there until a valid write sequence is made to
the DAC.
7.4 Device Functional Modes
7.4.1 Power-Down Modes
The DAC121S101QML-SP has four modes of operation. These modes are set with two bits (DB13 and DB12) in
the control register.
Table 2. Modes of Operation
16
DB13
DB12
0
0
Normal Operation
0
1
Power Down with 5 kΩ to GND
1
0
Power Down with 100 kΩ to GND
1
1
Power Down with Hi-Z
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When both DB13 and DB12 are 0, the device operates normally. For the other three possible combinations of
these bits the supply current drops to its power-down level and the output is pulled down with either a 5-kΩ or a
100-kΩ resistor, or is in a high impedance state, as described in Table 2.
The bias generator, output amplifier, the resistor string, and other linear circuitry are all shut down in any of the
power-down modes. Minimum power consumption is achieved in the power-down mode with SCLK disabled and
SYNC and DIN idled low.
7.5 Programming
7.5.1 Serial Interface
The three-wire interface is compatible with SPI, QSPI, and MICROWIRE, as well as most DSPs. See Figure 31
for information on a write sequence.
A write sequence begins by bringing the SYNC line low. When SYNC is low, the data on the DIN line is clocked
into the 16-bit serial input register on the falling edges of SCLK. On the 16th falling clock edge, the last data bit is
clocked in and the programmed function (a change in the mode of operation or a change in the DAC register
contents) is executed. At this point the SYNC line may be kept low or brought high. In either case, it must be
brought high for the minimum specified time before the next write sequence as a falling edge of SYNC can
initiate the next write cycle.
Because the SYNC and DIN buffers draw more current when they are high, they must be idled low between write
sequences to minimize power consumption.
SCLK
1
2
13
14
15
16
tL
tSUCL
tH
tCS
|
tSYNC
|
|
1 / fSCLK
|
SYNC
DB15
|
DIN
| |
tDHD
DB0
tSUD
Figure 31. DAC121S101QML-SP Timing
7.5.2 Input Shift Register
The input shift register, Figure 32, has 16 bits. The first two bits are don't cares and are followed by two bits that
determine the mode of operation (normal mode or one of three power-down modes). The contents of the serial
input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See the timing diagram,
Figure 31.
DB15 (MSB)
X
DB0 (LSB)
X PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
0
0
1
1
0 Normal Operation
1 5 k: to GND
0 100 k: to GND
1 High Impedance
Power-Down Modes
Figure 32. Input Register Contents
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Programming (continued)
Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th
SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the shift register is reset and
the write sequence is invalid. The DAC register is not updated and there is no change in the mode of operation
or in the output voltage.
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The simplicity of the DAC121S101QML-SP implies ease of use. However, it is important to recognize that any
data converter that uses its supply voltage as its reference voltage will have essentially zero PSRR (Power
Supply Rejection Ratio). Therefore, it is necessary to provide a noise-free supply voltage to the device.
8.1.1 Bipolar Operation
The DAC121S101QML-SP is designed for single-supply operation and thus has a unipolar output. However, a
bipolar output may be obtained with the circuit in Figure 33. This circuit will provide an output voltage range of
±5 V. A rail-to-rail amplifier must be used if the amplifier supplies are limited to ±5 V.
10 pF
R2
+5V
+5V
10 PF
+
R1
-
0.1 PF
±5V
+
DAC121S101
-5V
SYNC
VOUT
DIN
SCLK
Copyright © 2016, Texas Instruments Incorporated
Figure 33. Bipolar Operation
The output voltage of this circuit for any code is found to be:
VO = (VA × (D / 4096) x ((R1 + R2) / R1) – VA × R2 / R1)
where
•
D is the input code in decimal form
(2)
With VA = 5 V and R1 = R2,
VO = (10 × D / 4096) – 5 V
(3)
8.1.2 DSP and Microprocessor Interfacing
Interfacing the DAC121S101QML-SP to microprocessors and DSPs is quite simple. The following guidelines are
offered to hasten the design process.
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Application Information (continued)
8.1.2.1 ADSP-2101/ADSP2103 Interfacing
Figure 34 shows a serial interface between the DAC121S101QML-SP and the ADSP-2101/ADSP2103. The DSP
must be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT
control register and should be configured for Internal Clock Operation, Active Low Framing and 16-bit Word
Length. Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.
ADSP-2101/
ADSP2103
TFS
DT
SCLK
DAC121S101
SYNC
DIN
SCLK
Figure 34. ADSP-2101/2103 Interface
8.1.2.2 80C51/80L51 Interface
Figure 35 shows a serial interface between the DAC121S101QML-SP and the 80C51/80L51 microcontroller. The
SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line
P3.3. This line is taken low when data is to transmitted to the DAC121S101QML-SP. Because the 80C51/80L51
transmits 8-bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the
P3.3 line must be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the
second byte of data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize
that the 80C51/80L51 transmits data with the LSB first while the DAC121S101QML-SP requires data with the
MSB first.
80C51/80L51
P3.3
DAC121S101
SYNC
TXD
SCLK
RXD
DIN
Figure 35. 80C51/80L51 Interface
8.1.2.3 68HC11 Interface
Figure 36 shows a serial interface between the DAC121S101QML-SP and the 68HC11 microcontroller. The
SYNC line of the DAC121S101QML-SP is driven from a port line (PC7 in the figure), similar to the 80C51/80L51.
The 68HC11 must be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration
causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the
DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB
first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the
second byte of data to the DAC, after which PC7 must be raised to end the write sequence.
68HC11
DAC121S101
PC7
SCK
MOSI
SYNC
SCLK
DIN
Figure 36. 68HC11 Interface
8.1.2.4 Microwire Interface
Figure 37 shows an interface between a Microwire-compatible device and the DAC121S101QML-SP. Data is
clocked out on the rising edges of the SCLK signal.
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Application Information (continued)
MICROWIRE
DEVICE
DAC121S101
CS
SYNC
SK
SCLK
SO
DIN
Figure 37. Microwire Interface
8.1.3 Radiation Environments
Carefully consider the environmental conditions when using a product in a radiation environment. Radiation on
test reports are available on TI.com/radiation.
8.1.3.1 Total Ionizing Dose
The products with the radiation hardness assurance (RHA) levels listed in the are qualified for low dose rate
environments only.
8.1.3.1.1 DAC121S101WGRQV 5962R0722601VZA
This product is tested and qualified per MIL-STD-883 Test Method 1019, Condition A and the extended room
temperature anneal test where a high-dose irradiation followed by a room temperature anneal is used to simulate
a dose rate of 0.027 rad(Si)/s and is qualified for environments with radiation levels of 0.027 rad(Si)/s or lower.
8.1.3.1.2 DAC121S101WGRLV 5962R0722602VZA
This product is tested and qualified per MIL-STD-883 Test Method 1019, Condition D at a dose rate of 0.01
rad(Si)/s and are qualified for environments with radiation levels of 0.01 rad(Si)/s or lower.
8.1.3.2 Single Event Latch-Up and Functional Interrupt
One-time single event latch-up (SEL) and single event functional interrupt (SEFI) testing was preformed
according to EIA/JEDEC Standard, EIA/JEDEC57. The linear energy transfer threshold (LETth) shown in
Features is the maximum LET tested. A test report is available upon request.
8.1.3.3 Single Event Upset
A report on single event upset (SEU) is available at TI.com/radiation.
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8.2 Typical Application
3
VA
1
VOUT
+5
120pF
+5
3
+
/SYNC
5
SCLK
4
DIN
8
SCLK
7
DOUT
6
/CS
2
1uF
5
1
A2
4
LM4132-3.3
4
5
3
2 .1uF
DAC121S101
6
-
.2uF
2
180
+5
+3.3
10
VA
9
VIO
100K
2
470pF
+IN
1
VREF
ADC161S626
AV = 100
2.02K
3
-IN
4,5
+5
.2uF
100K
3
-
5
1
A1
Pressure
Sensor
0.2mV/Volt/PSI
4
+
180
470pF
2
A1 and A2 = LMP7701
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Figure 38. Pressure Sensor Gain Adjust
8.2.1 Design Requirements
The DAC121S101QML-SP is a positive supply-only data acquisition system capable of digitizing a pressure
sensor output. In addition to digitizing the pressure sensor output, the system designer can use the DAC121S101
to correct for gain errors in the pressure sensor output by adjusting the bias voltage to the bridge pressure
sensor.
8.2.2 Detailed Design Procedure
As shown in Equation 4, the output of the pressure sensor is relative to the imbalance of the resistive bridge
times the output of the DAC121S101, thus providing the desired gain correction.
Pressure Sensor Output = (DAC_Output × [(R2 / (R1 + R2) – (R4 / (R3 + R4)]
(4)
Likewise for the ADC161S626, Equation 5 shows that the ADC output is function of the Pressure Sensor Output
times relative to the ratio of the ADC input divided by the DAC121S101 output voltage.
ADC161S626 Output = (Pressure Sensor Output × 100 / (2 × VREF)) × 216
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(5)
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Typical Application (continued)
8.2.3 Application Curve
Figure 39. Total Unadjusted Error vs Output Code
9 Power Supply Recommendations
9.1 Using References as Power Supplies
Recall the need for a quiet supply source for devices that use their power supply voltage as a reference voltage.
Because the DAC121S101QML-SP consumes very little power, a reference source may be used as the supply
voltage. The advantages of using a reference source over a voltage regulator are accuracy and stability. Some
low-noise regulators can also be used for the power supply of the DAC121S101QML-SP. The following sections
describe a few power supply options for the DAC121S101QML-SP.
9.1.1 LM4050QML-SP
The LM4050QML-SP is a space-grade, radiation-qualified shunt reference within an accuracy of ±0.1% at room
temperature and a temperature coefficient of 23 ppm/°C.
Input
Voltage
R
VZ
0.47 PF
LM4050-5.0
DAC121S101
SYNC
VOUT = 0V to 5V
DIN
SCLK
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Figure 40. The LM4050 as a Power Supply
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Using References as Power Supplies (continued)
The minimum resistor value in the circuit of Figure 40 must be chosen such that the maximum current through
the LM4050 does not exceed its 15-mA rating. The conditions for maximum current include the input voltage at
its maximum, the LM4050 voltage at its minimum, the resistor value at its minimum due to tolerance, and the
DAC121S101QML-SP draws zero current. The maximum resistor value must allow the LM4050 to draw more
than its minimum current for regulation plus the maximum DAC121S101QML-SP current in full operation. The
conditions for minimum current include the input voltage at its minimum, the LM4050 voltage at its maximum, the
resistor value at its maximum due to tolerance, and the DAC121S101QML-SP draws its maximum current.
These conditions can be summarized as:
R(min) = ( VIN(max) − VZ(min) / (IA(min) + IZ(max))
(6)
and
R(max) = ( VIN(min) − VZ(max) / (IA(max) + IZ(min))
where
•
•
•
•
•
VZ(min) and VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over
temperature
IZ(max) is the maximum allowable current through the LM4050
IZ(min) is the minimum current required by the LM4050 for proper regulation
IA(max) is the maximum DAC121S101QML-SP supply current
IA(min) is the minimum DAC121S101QML-SP supply current
(7)
9.1.2 LP3985
The LP3985 is a low-noise, ultra-low dropout voltage regulator with a 3% accuracy over temperature. It is a good
choice for applications that do not require a precision reference for the DAC121S101QML-SP. It comes in 3-V,
3.3-V, and 5-V versions, among others, and sports a low 30-µV noise specification at low frequencies. Because
low frequency noise is relatively difficult to filter, this specification could be important for some applications. The
LP3985 comes in a space-saving 5-pin SOT-23 and 5-bump DSBGA packages.
Input
Voltage
LP3985
1 PF
0.1 PF
0.01 PF
DAC121S101
SYNC
VOUT = 0V to 5V
DIN
SCLK
Copyright © 2016, Texas Instruments Incorporated
Figure 41. Using the LP3985 Regulator
An input capacitance of 1 µF without any ESR requirement is required at the LP3985 input, while a 1-µF ceramic
capacitor with an ESR requirement of 5 mΩ to 500 mΩ is required at the output. Careful interpretation and
understanding of the capacitor specification is required to ensure correct device operation.
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Using References as Power Supplies (continued)
9.1.3 LP2980-N
The LP2980-N is an ultra-low dropout regulator with a 0.5% or 1% accuracy over temperature, depending upon
grade. It is available in 3-V, 3.3-V, and 5-V versions, among others.
Input
Voltage
VIN
ON / OFF
LP2980
VOUT
1 PF
DAC121S101
SYNC
VOUT = 0V to 5V
DIN
SCLK
Copyright © 2016, Texas Instruments Incorporated
Figure 42. Using the LP2980-N Regulator
Like any low-dropout regulator, the LP2980-N requires an output capacitor for loop stability. This output capacitor
must be at least 1 µF over temperature, but values of 2.2 µF or more will provide even better performance. The
ESR of this capacitor must be within the range specified in the LP2980-N data sheet. Surface-mount solid
tantalum capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to
their small size but generally have ESR values that are too low for use with the LP2980-N. Aluminum electrolytic
capacitors are typically not a good choice due to their large size and have ESR values that may be too high at
low temperatures.
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10 Layout
10.1 Layout Guidelines
For best accuracy and minimum noise, the printed-circuit board containing the DAC121S101QML-SP must have
separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes.
Both of these planes should be located in the same board layer. There must be a single ground plane. A single
ground plane is preferred if digital return current does not flow through the analog ground area. Frequently a
single ground plane design will use a fencing technique to prevent the mixing of analog and digital ground
current. Separate ground planes must only be used when the fencing technique is inadequate. The separate
ground planes must be connected in one place, preferably near the DAC121S101QML-SP. Take special care to
ensure that digital signals with fast edge rates do not pass over split ground planes. They must always have a
continuous return path below their traces.
The DAC121S101QML-SP power supply must be bypassed with a 10-µF and a 0.1-µF capacitor as close as
possible to the device with the 0.1 µF right at the device supply pin. The 10-µF capacitor must be a tantalum type
and the 0.1-µF capacitor should be a low ESL, low ESR type. The power supply for the DAC121S101QML-SP
must only be used for analog circuits.
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the
board. The clock and data lines must have controlled impedances.
10.2 Layout Example
VDD 5 V
C4 .1 µf
94
GND
74 75
DAC121S101WG
C5
.01 µf
1
VA
GND
NC
DIN
2
3
VOUT
4
78 79
5
C1
200 pf
1
NC
SCLK
VOUT
SYNC
NC
NC
10
DIN
3
77
9
2
8
7
SCLK
83 84
6
R1
2 kW
SYNC
81 82
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Note: N/C pins can be left floating or connected to ground
Figure 43. DAC121S101 Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For development support, see the following:
• 5962R07726
• Radiation Data for Space
11.1.2 Device Nomenclature
11.1.2.1 Specification Definitions
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB, which is VREF / 4096 = VA / 4096.
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital
inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus.
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded
into the DAC and the value of VA x 4095 / 4096.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and
Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error.
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register
changes. It is specified as the area of the glitch in nanovolt-seconds.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line
through the input to output transfer function. The deviation of any given code from this straight line is measured
from the center of that code value. The end point method is used. INL for this product is specified over a limited
range, per the Electrical Tables.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is
LSB = VREF / 2n
(8)
where VREF is the supply voltage for this product, and n is the DAC resolution in bits, which is 12 for the
DAC121S101QML-SP.
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output
stability maintained.
MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when
the input code increases.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is
1/2 of VA.
POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from
the power supply. The difference between the supply and output currents is the power consumed by the device
without a load.
SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is
updated.
WAKE-UP TIME is the time for the output to exit power-down mode. This is the time measured from the falling
edge of 16th SCLK pulse to when the output voltage deviates from the power-down voltage of 0 V.
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been
entered.
26
Submit Documentation Feedback
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: DAC121S101QML-SP
DAC121S101QML-SP
www.ti.com
SNAS410F – MAY 2008 – REVISED JULY 2016
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
LP2980-N Micropower 50-mA Ultra Low-Dropout Regulator in SOT-23 Package, SNOS733
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12.1 Engineering Samples
Engineering samples are available for order and are identified by the "MPR" in the orderable device name (see
Packaging Information in the Addendum). Engineering (MPR) samples meet the performance specifications of
the datasheet at room temperature only and have not received the full space production flow or testing.
Engineering samples may be QCI rejects that failed tests that would not impact the performance at room
temperature, such as radiation or reliability testing.
Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: DAC121S101QML-SP
Submit Documentation Feedback
27
PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962R0722601VZA
ACTIVE
CFP
NAC
10
54
TBD
Call TI
Call TI
-55 to 125
DAC121S101
WGRQMLV Q
5962R07226
01VZA ACO
01VZA >T
5962R0722602VZA
ACTIVE
CFP
NAC
10
54
TBD
Call TI
Call TI
-55 to 125
DAC121S101
WGRLV Q
5962R07226
02VZA ACO
02VZA >T
DAC121S101 MDR
ACTIVE
DIESALE
Y
0
10
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NA-UNLIM
-55 to 125
DAC121S101WGMPR
ACTIVE
CFP
NAC
10
54
TBD
Call TI
Call TI
25 to 25
DAC121S101
WGMPR ES
ACO
>T
DAC121S101WGRLV
ACTIVE
CFP
NAC
10
54
TBD
Call TI
Call TI
-55 to 125
DAC121S101
WGRLV Q
5962R07226
02VZA ACO
02VZA >T
DAC121S101WGRQV
ACTIVE
CFP
NAC
10
54
TBD
Call TI
Call TI
-55 to 125
DAC121S101
WGRQMLV Q
5962R07226
01VZA ACO
01VZA >T
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2019
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
NAC0010A
WG10A (Rev H)
www.ti.com
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