Texas Instruments | DAC088S085 8-Bit Micro Power OCTAL Digital-to-Analog Converter With Rail-to-Rail Outputs (Rev. D) | Datasheet | Texas Instruments DAC088S085 8-Bit Micro Power OCTAL Digital-to-Analog Converter With Rail-to-Rail Outputs (Rev. D) Datasheet

Texas Instruments DAC088S085 8-Bit Micro Power OCTAL Digital-to-Analog Converter With Rail-to-Rail Outputs (Rev. D) Datasheet
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DAC088S085
SNAS424D – AUGUST 2007 – REVISED APRIL 2016
DAC088S085 8-Bit Micro Power OCTAL Digital-to-Analog Converter With Rail-to-Rail
Outputs
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The DAC088S085 is a full-featured, general-purpose,
OCTAL, 8-bit, voltage-output, digital-to-analog
converter (DAC) that can operate from a single 2.7 V
to 5.5 V supply and consumes 1.95 mW at 3 V and
4.85 mW at 5 V. The DAC088S085 is packaged in a
16-pin WQFN package and a 16-pin TSSOP
package. The WQFN package makes the
DAC088S085 the smallest OCTAL DAC in its class.
The on-chip output amplifiers allow rail-to-rail output
swing and the three-wire serial interface operates at
clock rates up to 40 MHz over the entire supply
voltage range. Competitive devices are limited to
25‑MHz clock rates at supply voltages in the range of
2.7 V to 3.6 V. The serial interface is compatible with
standard SPI™, QSPI, MICROWIRE, and DSP
interfaces. The DAC088S085 also offers daisy chain
operation where an unlimited number of devices can
be updated simultaneously using a single serial
interface.
1
•
•
•
Ensured Monotonicity
Low Power Operation
Rail-to-Rail Voltage Output
Daisy Chain Capability
Power-On Reset to 0 V
Simultaneous Output Updating
Individual Channel Power Down Capability
Wide Power Supply Range (2.7 V to 5.5 V)
Dual Reference Voltages With Range of 0.5 V to
VA
Operating Temperature Range of –40°C to 125°C
Industry's Smallest Package
Key Specifications
– Resolution: 8 Bits
– INL: ±0.5 LSB (Maximum)
– DNL: 0.15 / –0.1 LSB (Maximum)
– Settling Time: 4.5 µs (Maximum)
– Zero Code Error: 15 mV (Maximum)
– Full-Scale Error: –0.75 %FSR (Maximum)
– Supply Power :
– Normal: 1.95 mW (3 V) / 4.85 mW (5 V)
Typical
– Power Down: 0.3 µW (3 V) / 1 µW (5 V)
Typical
Device Information(1)
PART NUMBER
DAC088S085
PACKAGE
BODY SIZE (NOM)
TSSOP (16)
5.00 mm × 4.40 mm
WQFN (16)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
DNL vs Code
2 Applications
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•
•
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•
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Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Voltage Reference for ADCs
Sensor Supply Voltage
Range Detectors
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC088S085
SNAS424D – AUGUST 2007 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
6
6
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
AC and Timing Requirements...................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 16
8.5 Programming........................................................... 17
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Applications ................................................ 25
9.3 Do's and Don'ts ....................................................... 27
10 Power Supply Recommendations ..................... 27
10.1 Using References as Power Supplies................... 27
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 30
12 Device and Documentation Support ................. 31
12.1
12.2
12.3
12.4
12.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
32
32
32
32
13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2013) to Revision D
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision B (March 2013) to Revision C
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 29
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5 Description (continued)
There are two references for the DAC088S085. One reference input serves channels A through D, while the
other reference serves channels E through H. Each reference can be set independently between 0.5 V and VA,
providing the widest possible output dynamic range. The DAC088S085 has a 16-bit input shift register that
controls the mode of operation, the power-down condition, and the DAC channels' register and output value. All
eight DAC outputs can be updated simultaneously or individually.
A power-on reset circuit ensures that the DAC outputs power up to 0 V and remain there until there is a valid
write to the device. The power-down feature of the DAC088S085 allows each DAC to be independently powered
with three different termination options. With all the DAC channels powered down, power consumption reduces
to less than 0.3 µW at 3 V and less than 1 µW at 5 V. The low power consumption and small packages of the
DAC088S085 make it an excellent choice for use in battery-operated equipment.
The DAC088S085 is one of a family of pin-compatible DACs, including the 10-bit DAC108S085 and the 12-bit
DAC128S085. All three parts are offered with the same pinout, allowing system designers to select a resolution
appropriate for their application without redesigning their printed-circuit board. The DAC088S085 operates over
the extended industrial temperature range of –40°C to 125°C.
6 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
SYNC
SCLK
D !
IN
!
D
OUT
RGH Package
16-Pin WQFN
Top View
13
12
V
11
V
PAD
!
3
10
V
!
4
9
V
OUTC
OUTD
14
2
5
V
!
D
OUTE
OUTF
V
!
V
!
!
OUTG
OUTH
!
V
V
16
SCLK
2
15
SYNC
3
14
V
4
13
V
!
5
12
V
!
6
11
V
7
10
GND
8
9
!
!
!
OUTC
OUTD
V !
A
!
V
OUTF
!
!
!
OUTG
OUTH
REF2
!
!
GND
REF2
!
REF1
OUTE
V
!
REF1
V
1
OUT
OUTB
V
V !
A
!
IN
OUTA
8
V
OUTB
1
7
V
!
OUTA
6
V
15
16
D
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Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
WQFN
TSSOP
DIN
15
1
Digital Input
DOUT
16
2
Digital Output
GND
8
10
Ground
SCLK
14
16
Digital Input
Serial Clock Input. Data is clocked into the input shift register on the falling edges of
this pin.
Digital Input
Frame Synchronization Input. When this pin goes low, data is written into the DAC's
input shift register on the falling edges of SCLK. After the 16th falling edge of SCLK, a
rising edge of SYNC causes the DAC to be updated. If SYNC is brought high before
the 15th falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the
write sequence is ignored by the DAC.
Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of
SCLK after the fall of SYNC.
Serial Data Output. DOUT is used in daisy chain operation and is connected directly to a
DIN pin on another DAC088S085. Data is not available at DOUT unless SYNC remains
low for more than 16 SCLK cycles.
Ground reference for all on-chip circuitry.
SYNC
13
15
VA
5
7
Supply
VOUTA
1
3
Analog Output
Channel A Analog Output Voltage.
VOUTB
2
4
Analog Output
Channel B Analog Output Voltage.
VOUTC
3
5
Analog Output
Channel C Analog Output Voltage.
VOUTD
4
6
Analog Output
Channel D Analog Output Voltage.
VOUTE
12
14
Analog Output
Channel E Analog Output Voltage.
VOUTF
11
13
Analog Output
Channel F Analog Output Voltage.
VOUTG
10
12
Analog Output
Channel G Analog Output Voltage.
VOUTH
9
11
Analog Output
Channel H Analog Output Voltage.
VREF1
6
8
Analog Input
Unbuffered reference voltage shared by Channels A, B, C, and D. Must be decoupled
to GND.
VREF2
7
9
Analog Input
Unbuffered reference voltage shared by Channels E, F, G, and H. Must be decoupled
to GND.
PAD (1)
—
—
Ground
Exposed die attach pad can be connected to ground or left floating. Soldering the pad
to the PCB offers optimal thermal performance and enhances package self-alignment
during reflow.
(1)
4
Power supply input. Must be decoupled to GND.
WQFN only
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
Supply voltage, VA
Voltage on any input pin
–0.3
Input current at any pin (4)
Package input current (4)
Power Consumption at TA = 25°C
See
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
–65
MAX
UNIT
6.5
V
6.5
V
10
mA
30
mA
150
°C
150
°C
(5)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are measured with respect to GND = 0 V, unless otherwise specified.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin must be limited to 10 mA. The 30-mA
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10
mA to three.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (RθJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax – TA) / RθJA. The values for maximum power dissipation is reached only when the device is operated in a severe fault
condition (for example, when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).
Such conditions must always be avoided.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model (MM)
±250
UNIT
V
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Operating temperature, TA
–40
125
°C
Supply voltage, VA
2.7
5.5
V
Reference voltage, VREF1,2
V
0.5
VA
Digital input voltage (2)
0
5.5
V
Output load
0
1500
pF
SCLK frequency
(1)
(2)
40
MHz
All voltages are measured with respect to GND = 0 V, unless otherwise specified.
The inputs are protected as shown below. Input voltage magnitudes up to 5.5 V, regardless of VA, does not cause errors in the
conversion result. For example, if VA is 3 V, the digital input pins can be driven with a 5 V logic device.
I/O
TO INTERNAL
CIRCUITRY
GND
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7.4 Thermal Information
DAC088S085
THERMAL METRIC (1) (2)
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
ψJB
RθJC(bot)
(1)
(2)
PW (TSSOP)
RGH (WQFN)
16 PINS
16 PINS
UNIT
130
38
°C/W
32
21
°C/W
44.2
9.8
°C/W
2
0.2
°C/W
Junction-to-board characterization parameter
43.5
9.8
°C/W
Junction-to-case (bottom) thermal resistance
—
2.4
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Soldering process must comply with Texas Instruments' Reflow Temperature Profile specifications. See http://www.ti.com/packaging.
Reflow temperature profiles are different for lead-free packages.
7.5 Electrical Characteristics
The following specifications apply for VA = 2.7 V to 5.5 V, VREF1 = VREF2 = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input
code range 3 to 252. Typical values apply for TA = 25°C; minimum and maximum limits apply for TA = –40°C to 125°C, unless
otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
Resolution
8
Monotonicity
8
Bits
Bits
INL
Integral non‑linearity
DNL
Differential non‑linearity
ZE
Zero code error
IOUT = 0
5
15
FSE
Full-scale error
IOUT = 0
–0.1
–0.75
%FSR
GE
Gain error
–0.2
–1
%FSR
ZCED
Zero code error drift
–20
µV/°C
TC GE
Gain error tempco
–1
ppm/°C
–0.1
±0.12
±0.5
0.03
0.15
–0.02
LSB
LSB
mV
OUTPUT CHARACTERISTICS
Output voltage range
0
High-impedance output
leakage current (1)
IOZ
ZCO
Zero code output
VA = 3 V, IOUT = 200 µA
10
VA = 3 V, IOUT = 1 mA
45
VA = 5 V, IOUT = 200 µA
Full scale output
V
±1
µA
mV
8
VA = 5 V, IOUT = 1 mA
FSO
VREF1,2
34
VA = 3 V, IOUT = 200 µA
2.984
VA = 3 V, IOUT = 1 mA
2.933
VA = 5 V, IOUT = 200 µA
4.987
VA = 5 V, IOUT = 1 mA
4.955
IOS
Output short circuit current
(source)
VA = 3 V, VOUT = 0 V, Input Code = FFh
VA = 5 V, VOUT = 0 V, Input Code = FFh
–60
IOS
Output short circuit current
(sink)
VA = 3 V, VOUT = 3 V, Input Code = 00h
50
VA = 5 V, VOUT = 5 V, Input Code = 00h
70
IO
Continuous output current
per channel (1)
TA = 105°C
10
TA = 125°C
6.5
(1)
6
–50
V
mA
mA
mA
This parameter is specified by design or characterization and is not tested in production.
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Electrical Characteristics (continued)
The following specifications apply for VA = 2.7 V to 5.5 V, VREF1 = VREF2 = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input
code range 3 to 252. Typical values apply for TA = 25°C; minimum and maximum limits apply for TA = –40°C to 125°C, unless
otherwise specified.
PARAMETER
CL
Maximum load capacitance
ZOUT
DC output impedance
TEST CONDITIONS
MIN
TYP
RL = ∞
1500
RL = 2 kΩ
1500
MAX
UNIT
pF
Ω
8
REFERENCE INPUT CHARACTERISTICS
VREF1,2
input range
2.7
Input impedance
0.5
VA
30
V
kΩ
LOGIC INPUT CHARACTERISTICS
IIN
Input Current (1)
VIL
Input low voltage
VIH
Input high voltage
CIN
Input Capacitance (1)
±1
VA = 2.7 V to 3.6 V
1
0.6
VA = 4.5 V to 5.5 V
1.1
0.8
VA = 2.7 V to 3.6 V
2.1
1.4
VA = 4.5 V to 5.5 V
2.4
2
µA
V
V
3
pF
5.5
V
POWER REQUIREMENTS
VA
Supply voltage
Normal supply current for
supply pin VA
2.7
VA = 2.7 V to 3.6 V
460
575
VA = 4.5 V to 5.5 V
650
840
VA = 2.7 V to 3.6 V
95
135
VA = 4.5 V to 5.5 V
160
225
VA = 2.7 V to 3.6 V
370
VA = 4.5 V to 5.5 V
440
VA = 2.7 V to 3.6 V
95
VA = 4.5 V to 5.5 V
160
fSCLK = 30 MHz, SYNC = VA, and
DIN = 0 V after PD mode loaded
VA = 2.7 V to 3.6 V
0.2
1.5
VA = 4.5 V to 5.5 V
0.5
3
fSCLK = 0, SYNC = VA, and
DIN = 0 V after PD mode loaded
VA = 2.7 V to 3.6 V
0.1
1
VA = 4.5 V to 5.5 V
0.2
2
VA = 2.7 V to 3.6 V
1.95
3
VA = 4.5 V to 5.5 V
4.85
7.1
VA = 2.7 V to 3.6 V
1.68
VA = 4.5 V to 5.5 V
3.8
fSCLK = 30 MHz, SYNC = VA, and
DIN = 0 V after PD mode loaded
VA = 2.7 V to 3.6 V
0.6
5.4
VA = 4.5 V to 5.5 V
2.5
16.5
fSCLK = 0, SYNC = VA, and
DIN = 0 V after PD mode loaded
VA = 2.7 V to 3.6 V
0.3
3.6
VA = 4.5 V to 5.5 V
1
11
fSCLK = 30 MHz, output unloaded
IN
Normal supply current for
VREF1 or VREF2
Static supply current for
supply pin VA
fSCLK = 30 MHz, output unloaded
fSCLK = 0, output unloaded
IST
Static supply current for
VREF1 or VREF2
IPD
Total power down supply
current for all PD Modes (1)
fSCLK = 0, output unloaded
fSCLK = 30 MHz, output unloaded
PN
Total power consumption
(output unloaded)
fSCLK = 0, output unloaded
PPD
Total power consumption in
all PD Modes (1)
µA
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µA
µA
mW
µW
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7.6 AC and Timing Requirements
Test limits are specified to AOQL (Average Outgoing Quality Level). Typical values apply for TA = 25°C; minimum and
maximum limits apply for TA = –40°C to 125°C, unless otherwise noted.
MIN
NOM
MAX
UNIT
40
30
MHz
3
4.5
µs
fSCLK
SCLK frequency
ts
Output voltage settling time (1)
SR
Output Slew Rate
GI
Glitch Impulse
DF
DC
CROSS
DAC-to-DAC crosstalk
MBW
Multiplying bandwidth
VREF1,2 = 2.5 V ± 2 VPP
360
kHz
ONSD
Output noise spectral density
DAC Code = 80h, 10 kHz
40
nV/√(Hz)
ON
Output noise
BW = 30 kHz
14
µV
tWU
Wake-up time
1/fSCLK
SCLK cycle time
33
25
ns
tCH
SCLK high time
10
7
ns
tCL
SCLK low time
10
7
ns
40h to C0h code change,
RL = 2 kΩ, CL = 200 pF
1
V/µs
40
nV-sec
Digital Feedthrough
0.5
nV-sec
Digital Crosstalk
0.5
nV-sec
1
nV-sec
Code change from 80h to 7Fh
VA = 3 V
3
VA = 5 V
20
TA = 25°C
3 1/fSCLK – 3
µs
tSS
SYNC set-up time before SCLK falling edge
tDS
Data set-up time before SCLK falling edge
2.5
1
ns
tDH
Data hold time after SCLK falling edge
2.5
1
ns
tSH
SYNC hold time after the 16th
falling edge of SCLK
tSYNC
SYNC high time
(1)
TA = –40°C to 125°C
10
TA = 25°C
0 1/fSCLK – 3
TA = –40°C to 125°C
3
15
5
ns
ns
ns
This parameter is specified by design or characterization and is not tested in production.
|
1 / fSCLK
SCLK
1
2
13
tSS
tSYNC
tCL
14
15
16
tCH
tSH
|
SYNC
DIN
| |
tDH
DB15
DB0
tDS
Figure 1. Serial Timing Diagram
8
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7.7 Typical Characteristics
VA = 2.7 V to 5.5 V, VREF1,2 = VA, fSCLK = 30 MHz, TA = 25°C, unless otherwise stated
FSE
255 x VA
256
GE = FSE - ZE
FSE = GE + ZE
OUTPUT
VOLTAGE
ZE
0
0
255
DIGITAL INPUT CODE
Figure 2. I/O Transfer Characteristic
Figure 3. INL vs Code
Figure 4. DNL vs Code
Figure 5. INL and DNL vs VREF
Figure 6. INL and DNL vs fSCLK
Figure 7. INL and DNL vs VA
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Typical Characteristics (continued)
VA = 2.7 V to 5.5 V, VREF1,2 = VA, fSCLK = 30 MHz, TA = 25°C, unless otherwise stated
10
Figure 8. INL and DNL vs Temperature
Figure 9. Zero Code Error vs VA
Figure 10. Zero Code Error vs VREF
Figure 11. Zero Code Error vs fSCLK
Figure 12. Zero Code Error vs Temperature
Figure 13. Full-Scale Error vs VA
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Typical Characteristics (continued)
VA = 2.7 V to 5.5 V, VREF1,2 = VA, fSCLK = 30 MHz, TA = 25°C, unless otherwise stated
Figure 14. Full-Scale Error vs VREF
Figure 15. Full-Scale Error vs fSCLK
Figure 16. Full-Scale Error vs Temperature
Figure 17. IVA vs VA
Figure 18. IVA vs Temperature
Figure 19. IVREF vs VREF
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Typical Characteristics (continued)
VA = 2.7 V to 5.5 V, VREF1,2 = VA, fSCLK = 30 MHz, TA = 25°C, unless otherwise stated
12
Figure 20. IVREF vs Temperature
Figure 21. Settling Time
Figure 22. Glitch Response
Figure 23. Wake-Up Time
Figure 24. DAC-to-DAC Crosstalk
Figure 25. Power-On Reset
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Typical Characteristics (continued)
VA = 2.7 V to 5.5 V, VREF1,2 = VA, fSCLK = 30 MHz, TA = 25°C, unless otherwise stated
Figure 26. Multiplying Bandwidth
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8 Detailed Description
8.1 Overview
The DAC085S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor
strings that are followed by an output buffer.
8.2 Functional Block Diagram
VREF1
DAC088S085
REF
8 BIT DAC
VOUTA
BUFFER
8
2.5k
100k
REF
8 BIT DAC
VOUTB
BUFFER
8
POWER-ON
RESET
2.5k
100k
REF
8 BIT DAC
VOUTC
BUFFER
8
2.5k
100k
REF
8 BIT DAC
VOUTD
BUFFER
8
2.5k
100k
REF
8 BIT DAC
DAC
REGISTER
VOUTE
BUFFER
8
2.5k
100k
REF
8 BIT DAC
VOUTF
BUFFER
8
2.5k
100k
REF
8 BIT DAC
VOUTG
BUFFER
8
2.5k
100k
8
REF
8 BIT DAC
VOUTH
BUFFER
8
2.5k
DOUT
14
SYNC
SCLK
100k
POWER-DOWN
CONTROL
LOGIC
INPUT
CONTROL
LOGIC
DIN
VREF2
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8.3 Feature Description
8.3.1 DAC Architecture
The DAC088S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor
strings that are followed by an output buffer. The reference voltages are externally applied at VREF1 for DAC
channels A through D and VREF2 for DAC channels E through H.
For simplicity, a single resistor string is shown in Figure 27. This string consists of 256 equal valued resistors
with a switch at each junction of two resistors, plus a switch-to-ground. The code loaded into the DAC register
determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight
binary with an ideal output voltage of:
VOUTA,B,C,D = VREF1 × (D / 256)
VOUTE,F,G,H = VREF2 × (D / 256)
(1)
where
•
D is the decimal equivalent of the binary code that is loaded into the DAC register.
(2)
D can take on any value between 0 and 255. This configuration ensures that the DAC is monotonic.
VREF
R
S2 n
R
S2 n-1
R
VOUT
S2 n-2
S2
R
S1
R
S0
Figure 27. DAC Resistor String
Because all eight DAC channels of the DAC088S085 can be controlled independently, each channel consists of
a DAC register and a 8-bit DAC. Figure 28 is a simple block diagram of an individual channel in the
DAC088S085. Depending on the mode of operation, data written into a DAC register causes the 8-bit DAC
output to be updated or an additional command is required to update the DAC output. Further description of the
modes of operation can be found in Serial Interface.
VREF
REF
DAC
REGISTER
8 BIT DAC
BUFFER
8
VOUT
Figure 28. Single-Channel Block Diagram
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Feature Description (continued)
8.3.2 Output Amplifiers
The output amplifiers are rail-to-rail, providing an output voltage range of 0 V to VA when the reference is VA. All
amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0 V and VA,
in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the
reference is less than VA, there is only a loss in linearity in the lowest codes.
The output amplifiers are capable of driving a load of 2 kΩ in parallel with 1500 pF to ground or to VA. The zerocode and full-scale outputs for given load currents are available in Electrical Characteristics.
8.3.3 Reference Voltage
The DAC088S085 uses dual external references, VREF1 and VREF2, that are shared by channels A, B, C, D and
channels E, F, G, H respectively. The reference pins are not buffered and have an input impedance of 30 kΩ. TI
recommends that VREF1 and VREF2 be driven by voltage sources with low output impedance. The reference
voltage range is 0.5 V to VA, providing the widest possible output dynamic range.
8.4 Device Functional Modes
8.4.1 Power-On Reset
The power-on reset circuit controls the output voltages of the eight DACs during power up. Upon application of
power, the DAC registers are filled with zeros and the output voltages are set to 0 V. The outputs remain at 0 V
until a valid write sequence is made.
8.4.2 Power-Down Modes
The DAC088S085 has three power-down modes where different output terminations can be selected (see
Table 1). With all channels powered down, the supply current drops to 0.1 µA at 3 V and 0.2 µA at 5 V. By
selecting the channels to be powered down in DB[7:0] with a 1, individual channels can be powered down
separately or multiple channels can be powered down simultaneously. The three different output terminations
include high output impedance, 100 kΩ to GND, and 2.5 kΩ to GND.
The output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the power-down
modes. The bias generator, however, is only shut down if all the channels are placed in power down mode. The
contents of the DAC registers are unaffected when in power down. Therefore, each DAC register maintains its
value before the DAC088S085 being powered down unless it is changed during the write sequence which
instructed it to recover from power down. Minimum power consumption is achieved in the power-down mode with
SYNC idled high, DIN idled low, and SCLK disabled. The time to exit power-down (Wake-Up Time) is typically 3
µs at 3 V and 20 µs at 5 V.
Table 1. Power-Down Modes
16
DB[15:12]
DB[11:8]
7
6
5
4
3
2
1
0
1101
XXXX
H
G
F
E
D
C
B
A
High-Z outputs
1110
XXXX
H
G
F
E
D
C
B
A
100-kΩ outputs
1111
XXXX
H
G
F
E
D
C
B
A
2.5-kΩ outputs
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8.5 Programming
8.5.1 Serial Interface
The three-wire interface is compatible with SPI, QSPI, and MICROWIRE, as well as most DSPs and operates at
clock rates up to 40 MHz. A valid serial frame contains 16 falling edges of SCLK. See Figure 1 for information on
a write sequence.
A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked
into the 16-bit serial input register on the falling edges of SCLK. To avoid mis-clocking data into the shift register,
it is critical that SYNC not be brought low on a falling edge of SCLK (see minimum and maximum setup times for
SYNC in Figure 1 and Figure 29). On the 16th falling edge of SCLK, the last data bit is clocked into the register.
The write sequence is concluded by bringing the SYNC line high. Once SYNC is high, the programmed function
(a change in the DAC channel address, mode of operation or register contents) is executed. To avoid misclocking data into the shift register, it is critical that SYNC be brought high between the 16th and 17th falling
edges of SCLK (see minimum and maximum hold times for SYNC in Figure 1 and Figure 29).
SCLK
1
15
17
16
tSS
tSH
SYNC
Figure 29. CS Setup and Hold Times
If SYNC is brought high before the 15th falling edge of SCLK, the write sequence is aborted and the data that
has been shifted into the input register is discarded. If SYNC is held low beyond the 17th falling edge of SCLK,
the serial data presented at DIN begins to be output on DOUT. More information on this mode of operation can be
found in Daisy Chain Operation. In either case, SYNC must be brought high for the minimum specified time
before the next write sequence is initiated with a falling edge of SYNC.
Because the DIN buffer draws more current when it is high, it must be idled low between write sequences to
minimize power consumption. On the other hand, SYNC must be idled high to avoid the activation of daisy chain
operation where DOUT is active.
8.5.2 Daisy Chain Operation
Daisy chain operation allows communication with any number of DAC088S085s using a single serial interface.
As long as the correct number of data bits are input in a write sequence (multiple of sixteen bits), a rising edge of
SYNC properly updates all DACs in the system.
To support multiple devices in a daisy chain configuration, SCLK and SYNC are shared across all DAC088S085s
and DOUT of the first DAC in the chain is connected to DIN of the second. Figure 30 shows three DAC088S085s
connected in daisy chain fashion. Similar to a single-channel write sequence, the conversion for a daisy chain
operation begins on a falling edge of SYNC and ends on a rising edge of SYNC. A valid write sequence for n
devices in a chain requires n times 16 falling edges to shift the entire input data stream through the chain. Daisy
chain operation is specified for a maximum SCLK speed of 30 MHz.
SYNC
SCLK
DIN
SYNC
SCLK
SYNC
SCLK
SYNC
SCLK
DIN DOUT
DIN DOUT
DIN DOUT
DAC 1
DAC 2
DAC 3
Figure 30. Daisy Chain Configuration
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Programming (continued)
The serial data output pin, DOUT, is available on the DAC088S085 to allow daisy-chaining of multiple
DAC088S085 devices in a system. In a write sequence, DOUT remains low for the first fourteen falling edges of
SCLK before going high on the fifteenth falling edge. Subsequently, the next sixteen falling edges of SCLK
outputs the first sixteen data bits entered into DIN. Figure 31 shows the timing of three DAC088S085s in
Figure 30. In this instance, It takes forty-eight falling edges of SCLK followed by a rising edge of SYNC to load all
three DAC088S085s with the appropriate register data. On the rising edge of SYNC, the programmed function is
executed in each DAC088S085 simultaneously.
48 SCLK Cycles (16 X 3)
SYNC
DIN1
DAC 3
DIN2/DOUT1
15th SCLK Cycle
DAC 2
DAC 1
DAC 3
DAC 2
31st SCLK Cycle
DIN3/DOUT2
DAC 3
Data Loaded into the DACs
Figure 31. Daisy Chain Timing Diagram
8.5.3 Serial Input Register
The DAC088S085 has two modes of operation plus a few special command operations. The two modes of
operation are Write Register Mode (WRM) and Write Through Mode (WTM). For the rest of this document, these
modes is referred to as WRM and WTM. The special command operations are separate from WRM and WTM
because they can be called upon regardless of the current mode of operation. The mode of operation is
controlled by the first four bits of the control register, DB15 through DB12. See Table 2 for a detailed summary.
Table 2. Write Register and Write Through Modes
DB[15:12]
DB[11:0]
DESCRIPTION OF MODE
1000
XXXXXXXXXXXX
WRM: The registers of each DAC Channel can be written to without causing
their outputs to change.
1001
XXXXXXXXXXXX
WTM: Writing data to a channel's register causes the DAC output to change.
When the DAC088S085 first powers up, the DAC is in WRM. In WRM, the registers of each individual DAC
channel can be written to without causing the DAC outputs to be updated. This is accomplished by setting DB15
to 0, specifying the DAC register to be written to in DB[14:12], and entering the new DAC register setting in
DB[11:0] (see Table 3).The DAC088S085 remains in WRM until the mode of operation is changed to WTM. The
mode of operation is changed from WRM to WTM by setting DB[15:12] to 1001. Once in WTM, writing data to a
DAC channel's register causes the DAC's output to be updated as well. Changing a DAC channel's register in
WTM is accomplished in the same manner as it is done in WRM. However, in WTM the DAC's register and
output are updated at the completion of the command (see Table 3). Similarly, the DAC088S085 remains in
WTM until the mode of operation is changed to WRM by setting DB[15:12] to 1000.
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Table 3. Commands Impacted by WRM and WTM
DB15
DB[14:12]
DB[11:0]
DESCRIPTION OF MODE
0
000
D11 D10 ... D4 X X X X
WRM: D[11:0] written to ChA's data register only
WTM: ChA's output is updated by data in D[11:0]
0
001
D11 D10 ... D4 X X X X
WRM: D[11:0] written to ChB's data register only
WTM: ChB's output is updated by data in D[11:0]
0
010
D11 D10 ... D4 X X X X
WRM: D[11:0] written to ChC's data register only
WTM: ChC's output is updated by data in D[11:0]
0
011
D11 D10 ... D4 X X X X
WRM: D[11:0] written to ChD's data register only
WTM: ChD's output is updated by data in D[11:0]
0
100
D11 D10 ... D4 X X X X
WRM: D[11:0] written to ChE's data register only
WTM: ChE's output is updated by data in D[11:0]
0
101
D11 D10 ... D4 X X X X
WRM: D[11:0] written to ChF's data register only
WTM: ChF's output is updated by data in D[11:0]
0
110
D11 D10 ... D4 X X X X
WRM: D[11:0] written to ChG's data register only
WTM: ChG's output is updated by data in D[11:0]
0
111
D11 D10 ... D4 X X X X
WRM: D[11:0] written to ChH's data register only
WTM: ChH's output is updated by data in D[11:0]
As mentioned previously, the special command operations can be exercised at any time regardless of the mode
of operation. There are three special command operations. The first command is exercised by setting data bits
DB[15:12] to 1010. This allows a user to update multiple DAC outputs simultaneously to the values currently
loaded in their respective control registers. This command is valuable if the user wants each DAC output to be at
a different output voltage but still have all the DAC outputs change to their appropriate values simultaneously
(see Table 4).
The second special command allows the user to alter the DAC output of channel A with a single write frame.
This command is exercised by setting data bits DB[15:12] to 1011 and data bits DB[11:0] to the desired control
register value. It also has the added benefit of causing the DAC outputs of the other channels to update to their
current control register values as well. A user may choose to exercise this command to save a write sequence.
For example, the user may wish to update several DAC outputs simultaneously, including channel A. To
accomplish this task in the minimum number of write frames, the user would alter the control register values of all
the DAC channels except channel A while operating in WRM. The last write frame would be used to exercise the
special command Channel A Write Mode. In addition to updating channel A's control register and output to a new
value, all of the other channels would be updated as well. At the end of this sequence of write frames, the
DAC088S085 would still be operating in WRM (see Table 4).
The third special command allows the user to set all the DAC control registers and outputs to the same level.
This command is commonly referred to as broadcast mode because the same data bits are being broadcast to
all of the channels simultaneously. This command is exercised by setting data bits DB[15:12] to 1100 and data
bits DB[7:0] to the value that the user wishes to broadcast to all the DAC control registers. Once the command is
exercised, each DAC output is updated by the new control register value. This command is frequently used to set
all the DAC outputs to some known voltage such as 0 V, VREF / 2, or Full Scale. A summary of the commands
can be found in Table 4.
Table 4. Special Command Operations
DB[15:12]
DB[11:0]
DESCRIPTION OF MODE
1010
XXXXHGFEDCBA
Update Select: The DAC outputs of the channels selected with a 1 in DB[7:0]
are updated simultaneously to the values in their respective control registers.
1011
D11 D10 ... D4 X X X X
Channel A Write: the control register of Channel A and DAC output are
updated to the data in DB[11:0]. The outputs of the other seven channels are
also updated according to their respective control register values.
1100
D11 D10 ... D4 X X X X
Broadcast: The data in DB[11:0] is written to all channels' control register and
DAC output simultaneously.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Examples Programming the DAC088S085
This section presents the step-by-step instructions for programming the serial input register.
9.1.1.1 Updating DAC Outputs Simultaneously
When the DAC088S085 is first powered on, the DAC is operating in Write Register Mode (WRM). Operating in
WRM allows the user to program the registers of multiple DAC channels without causing the DAC outputs to be
updated. As an example, here are the steps for setting Channel A to a full scale output, Channel B to threequarters full scale, Channel C to half-scale, Channel D to one-quarter full scale and having all the DAC outputs
update simultaneously.
As stated previously, the DAC088S085 powers up in WRM. If the device was previously operating in Write
Through Mode (WTM), an extra step to set the DAC into WRM would be required. First, the DAC registers need
to be programmed to the desired values. To set Channel A to an output of full scale, write 0FF0 to the control
register. This updates the data register for Channel A without updating the output of Channel A. Second, set
Channel B to an output of three-quarters full scale by writing 1C00 to the control register. This updates the data
register for Channel B. Once again, the output of Channel B and Channel A is not updated because the DAC is
operating in WRM. Third, set Channel C to half scale by writing 2800 to the control register. Fourth, set Channel
D to one-quarter full scale by writing 3400 to the control register. Finally, update all four DAC channels
simultaneously by writing A00F to the control register. This procedure allows the user to update four channels
simultaneously with five steps.
Because Channel A was one of the DACs to be updated, one command step could have been saved by writing
to Channel A last. This is accomplished by writing to Channel B, C, and D first and using the special command
Channel A Write to update the DAC register and output of Channel A. This special command has the added
benefit of updating all DAC outputs while updating Channel A. With this sequence of commands, the user was
able to update four channels simultaneously with four steps. A summary of this command can be found in
Table 4.
9.1.1.2 Updating DAC Outputs Independently
If the DAC088S085 is currently operating in WRM, change the mode of operation to WTM by writing 9XXX to the
control register. Once the DAC is operating in WTM, any DAC channel can be updated in one step. For example,
if a design required Channel G to be set to half scale, the user can write 6800 to the control register and the data
register of Channel G and DAC output is updated. Similarly, if the output of Channel F needed to be set to full
scale, 5FF0 would need to be written to the control register. Channel A is the only channel that has a special
command that allows its DAC output to be updated in one command regardless of the mode of operation. Setting
the DAC output of Channel A to full scale could be accomplished in one step by writing BFFF to the control
register.
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Application Information (continued)
9.1.2 Bipolar Operation
The DAC088S085 is designed for single-supply operation and thus has a unipolar output. However, a bipolar
output may be achieved with the circuit in Figure 32. This circuit provides an output voltage range of ±5 V. A railto-rail amplifier must be used if the amplifier supplies are limited to ±5 V.
10 pF
R2
+5V
R1
+5V
10 PF
+
-
0.1 PF
±5V
+
VA / VREF1,2
-5V
DAC088S085
VOUT
SYNC
DIN
SCLK
Figure 32. Bipolar Operation
The output voltage of this circuit for any code is found to be
VO = VA × (D / 256) × ( (R1 + R2) / R1) – VA × R2 / R1
where
•
D is the input code in decimal form.
(3)
With VA = 5 V and R1 = R2,
VO = (10 × D / 256) – 5 V
(4)
A list of rail-to-rail amplifiers suitable for this application are indicated in Table 5.
Table 5. Some Rail-to-Rail Amplifiers
AMP
PKGS
TYP VOS
TYP ISUPPLY
LMP7701
SOT-23
±37 µV
0.79 mA
LMV841
SOT-23
–17 µV
1.11 mA
LMC7111
SOT-23
900 µV
25 µA
LM7301
SOT-23
30 µV
620 µA
LM8261
SOT-23
700 µV
1 mA
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9.1.3 Variable Current Source Output
The DAC088S085 is a voltage output DAC but can be easily converted to a current output with the addition of an
operational amplifier. In Figure 33, one of the channels of the DAC088S085 is converted to a variable current
source capable of sourcing up to 40 mA.
R1
R2
LMV710
+5V
10 PF
+
-
0.1 PF
+
VREF
RB
R3 (= R1)
SYNC
VOUT
DIN
IO
RA
SCLK
Load
DAC088S085
Figure 33. Variable Current Source
The output current of this circuit (IO) for any DAC code is found to be
IO = (VREF × (D / 256) × (R2) ) / (R1 × RB)
where
•
•
D is the input code in decimal form
R2 = RA + RB
(5)
9.1.4 DSP and Microprocessor Interfacing
Interfacing the DAC088S085 to microprocessors and DSPs is quite simple. The following guidelines are offered
to hasten the design process.
9.1.4.1 ADSP-2101 and ADSP2103 Interfacing
Figure 34 shows a serial interface between the DAC088S085 and the ADSP-2101 or ADSP2103. The DSP must
be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control
register and must be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length.
Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.
ADSP-2101/
ADSP2103
TFS
DT
SCLK
DAC088S085
SYNC
DIN
SCLK
Figure 34. ADSP-2101 and ADSP-2103 Interface
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9.1.4.2 80C51 and 80L51 Interface
A serial interface between the DAC088S085 and the 80C51 or 80L51 microcontroller is shown in Figure 35. The
SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line
P3.3. This line is taken low when data is transmitted to the DAC088S085. Because the 80x51 transmits 8-bit
bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must be
left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of
data, after which port line P3.3 is brought high. The 80x51 transmit routine must recognize that the 80x51
transmits data with the LSB first while the DAC088S085 requires data with the MSB first.
80C51/80L51
DAC088S085
P3.3
SYNC
TXD
SCLK
RXD
DIN
Figure 35. 80C51 and 80L51 Interface
9.1.4.3 68HC11 Interface
A serial interface between the DAC088S085 and the 68HC11 microcontroller is shown in Figure 36. The SYNC
line of the DAC088S085 is driven from a port line (PC7 in the figure), similar to the 80C51 and 80L51.
The 68HC11 must be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration
causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the
DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB
first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the
second byte of data to the DAC, after which PC7 must be raised to end the write sequence.
68HC11
DAC088S085
PC7
SYNC
SCK
SCLK
MOSI
DIN
Figure 36. 68HC11 Interface
9.1.4.4 Microwire Interface
Figure 37 shows an interface between a Microwire compatible device and the DAC088S085. Data is clocked out
on the rising edges of the SK signal. As a result, the SK of the Microwire device must be inverted before driving
the SCLK of the DAC088S085.
MICROWIRE
DEVICE
CS
SYNC
SK
SCLK
SO
DIN
DAC088S085
Figure 37. Microwire Interface
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9.1.5 Industrial Application
Figure 38 shows the DAC088S085 controlling several different circuits in an industrial setting. Channel A is
shown providing the reference voltage to the ADC081S625, one of Texas Instruments' general-purpose Analogto-Digital Converters (ADCs). The reference for the ADC121S625 may be set to any voltage from 0.2 V to 5.5 V,
providing the widest dynamic range possible. Typically, the ADC121S625 is monitoring a sensor and would
benefit from the reference voltage of ADC being adjustable. Channel B is providing the drive or supply voltage for
a sensor. By having the sensor supply voltage adjustable, the output of the sensor can be optimized to the input
level of the ADC monitoring it. Channel C is defined to adjust the offset or gain of an amplifier stage in the
system. Channel D is configured with an operational amplifier to provide an adjustable current source. Being able
to convert one of the eight channels of the DAC088S085 to a current output eliminates the need for a separate
current output DAC to be added to the circuit. Channel E, in conjunction with an operational amplifier, provides a
bipolar output swing for devices requiring control voltages that are centered around ground. Channel F and G are
used to set the upper and lower limits for a range detector. Channel H is reserved for providing voltage control or
acting as a voltage setpoint.
ADC121S625
Sensor
Signal
Set ADC Reference
VREF
VOUTA
Setting Sensor Drive or Supply
(Add buffer for sensor with low
input impedance)
VOUTB
Set offset and gain
VOUTC
Programmable ISOURCE
VOUTD
SCLK
SYNC
DIN
+V
VOUTE
-V
+
-
Control (Valve, Damper, Robotics,
Process Ctrl) or Voltage Setpoint
(Battery Ctrl, Signal Trigger)
VOUTF
VIN
+
-
Output to Another
DAC (Daisy Chain)
DAC088S085
Bipolar Output Swing
Set Limits for Range Detector
DOUT
VREF1
(Ch A - Ch D)
3V or 5V Reference
VREF2
(Ch E - Ch H)
3V or 5V Reference
VOUTG
VOUTH
Figure 38. Industrial Application
24
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9.2 Typical Applications
The following figures are examples of the DAC088S085 in typical application circuits. These circuits are basic
and generally requires modification for specific circumstances.
9.2.1 ADC Reference
Figure 39 shows Channel A of the DAC088S085 providing the drive or supply voltage for a bridge sensor. By
having the sensor supply voltage adjustable, the output of the sensor can be optimized to the input level of the
ADC monitoring it.
+5V
Channel A
REF
SYNCB
DIN
Controller
+
-
+5V
RF
Bridge
Sensor
RI
REF
ADC121S705
RF
+
REF
Channel B
LMP7702
Av = 1 + 2
DAC088S085
SCLK
DOUT
CSB
SCLK
RF
RI
Figure 39. Driving an ADC Reference
9.2.1.1 Design Requirements
For this design example, use these requirements:
• Provide drive for a bridge sensor that is adjustable through SPI from an MCU.
• Provide reference voltage for an ADC that is adjustable through SPI from an MCU.
• Use a single 5 V supply.
• Use ratiometric design for the bridge and ADC reference.
9.2.1.2 Detailed Design Procedure
The output of the sensor is amplified by a fixed gain amplifier stage with a differential gain of 1 + 2 × (RF / RI).
The advantage of this amplifier configuration is the high input impedance seen by the output of the bridge
sensor. The disadvantage is the poor common-mode rejection ratio (CMRR). The common-mode voltage (VCM)
of the bridge sensor is half of the DAC output of Channel A. The VCM is amplified by a gain of 1 V/V by the
amplifier stage and thus becomes the bias voltage for the input of the ADC121S705. Channel B of the
DAC088S085 is providing the reference voltage to the ADC121S705. The reference for the ADC121S705 may
be set to any voltage from 1 V to 5 V, providing the widest dynamic range possible.
The reference voltage for Channel A and B is powered by an external 5 V power supply. Because the 5 V supply
is common to the sensor supply voltage and the reference voltage of the ADC, fluctuations in the value of the
5‑V supply has a minimal effect on the digital output code of the ADC. This type of configuration is often referred
to as a Ratio-metric design. For example, an increase of 5% to the 5 V supply causes the sensor supply voltage
to increase by 5%. This causes the gain or sensitivity of the sensor to increase by 5%. The gain of the amplifier
stage is unaffected by the change in supply voltage. The ADC121S705 on the other hand, also experiences a
5% increase to its reference voltage. This causes the size of the least significant bit (LSB) of the ADC to increase
by 5%. As a result of the sensor's gain increasing by 5% and the LSB size of the ADC increasing by the same
5%, there is no net effect on the circuit's performance. It is assumed that the amplifier gain is set low enough to
allow for a 5% increase in the sensor output. Otherwise, the increase in the sensor output level may cause the
output of the amplifiers to clip.
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Typical Applications (continued)
9.2.1.3 Application Curve
FSE
255 x VA
256
GE = FSE - ZE
FSE = GE + ZE
OUTPUT
VOLTAGE
ZE
0
0
255
DIGITAL INPUT CODE
Figure 40. I/O Transfer Characteristic
9.2.2 Programmable Attenuator
Figure 41 shows one of the channels of the DAC088S085 being used as a single-quadrant multiplier.
4.7 PF
20 k:
20 k:
+5V
VBIAS
+5V
Controller
+
LMP7731
VA REF
DAC088S085
Figure 41. Programmable Attenuator Diagram
9.2.2.1 Design Requirements
For this design example, use these requirements:
• Use a single 5 V supply.
• Use the SPI interface to control the amount of attenuation of a signal.
• Do not add any noise to the signal.
9.2.2.2 Detailed Design Procedure
In this configuration, an AC or DC signal can be driven into one of the reference pins. The SPI interface of the
DAC can be used to digitally attenuate the signal to any level from 0 dB (full scale) to 0 V. This is accomplished
without adding any noticeable level of noise to the signal. An amplifier stage is shown in Figure 41 as a reference
for applications where the input signal requires amplification. Notice how the AC signal in this application is ACcoupled to the amplifier before being amplified. A separate bias voltage is used to set the common-mode voltage
for the DAC088S085's reference input to VA / 2, allowing the largest possible input swing. The multiplying
bandwidth of VREF1,2 is 360 kHz with a VCM of 2.5 V and a peak-to-peak signal swing of 2 V.
26
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Typical Applications (continued)
9.2.2.3 Application Curve
Figure 42. Multiplying Bandwidth
9.3 Do's and Don'ts
•
•
•
Install bypass capacitors next to the VA, VREF1, and VREF2 pins.
The reference inputs must be kept stable and noise free. Besides installing bypass capacitors close to the
pins, the traces that have the reference voltages must kept away from noisy traces.
Keep analog and digital traces away from each other. If they need to cross, have the traces cross at a 90°
angle.
10 Power Supply Recommendations
10.1 Using References as Power Supplies
While the simplicity of the DAC088S085 implies ease of use, it is important to recognize that the path from the
reference input (VREF1,2) to the DAC outputs has zero Power Supply Rejection Ratio (PSRR). Therefore, it is
necessary to provide a noise-free supply voltage to VREF1,2. To use the full dynamic range of the DAC088S085,
the supply pin (VA) and VREF1,2 can be connected together and share the same supply voltage. Because the
DAC088S085 consumes very little power, a reference source may be used as the reference input or the supply
voltage. The advantages of using a reference source over a voltage regulator are accuracy and stability. Some
low noise regulators can also be used. Listed below are a few reference and power supply options for the
DAC088S085.
10.1.1 LM4132
The LM4132, with its ±0.05% accuracy over temperature, is a good choice as a reference source for the
DAC088S085. The 4.096 V version is useful if a 0 V to 4.09 V output range is desirable. Bypassing the LM4132
voltage input pin with a 4.7-µF capacitor and the voltage output pin with a 4.7-µF capacitor improves stability and
reduce output noise. The LM4132 comes in a space-saving, 5-pin SOT-23 package.
Input
Voltage
LM4132-4.1
C1 +
4.7 PF
C3
0.1 PF
+ C2
4.7 PF
VA VREF1,2
DAC088S085
SYNC
DIN
VOUT = 0V
to 4.095V
SCLK
Figure 43. The LM4132 as a Power Supply
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Using References as Power Supplies (continued)
10.1.2 LM4050
Available with accuracy of ±0.1%, the LM4050 shunt reference is also a good choice as a reference for the
DAC088S085. It is available in 4.096 V and 5 V versions and comes in a space-saving, 3-pin SOT-23 package.
Input
Voltage
R
IDAC
VZ
IZ
0.1 PF
1 PF
LM4050-4.1
or
LM4050-5.0
VA VREF1,2
DAC088S085
SYNC
VOUT = 0V
to 5V
DIN
SCLK
Figure 44. The LM4050 as a Power Supply
The minimum resistor value in the circuit of Figure 44 must be chosen such that the maximum current through
the LM4050 does not exceed its 15-mA rating. The conditions for maximum current include the input voltage at
its maximum, the LM4050 voltage at its minimum, and the DAC088S085 drawing zero current. The maximum
resistor value must allow the LM4050 to draw more than its minimum current for regulation plus the maximum
DAC088S085 current in full operation. The conditions for minimum current include the input voltage at its
minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the
DAC088S085 draws its maximum current. These conditions can be summarized as:
R(min) = ( VIN(max) – VZ(min) ) / IZ(max)
(6)
and
R(max) = ( VIN(min) – VZ(max) ) / (IDAC(max) + IZ(min) )
where
•
•
•
VZ(min) and VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over
temperature
IZ(max) is the maximum allowable current through the LM4050, IZ(min) is the minimum current required by the
LM4050 for proper regulation
IDAC(max) is the maximum DAC088S085 supply current.
(7)
10.1.3 LP3985
The LP3985 is a low-noise, ultra-low dropout voltage regulator with a ±3% accuracy over temperature. It is a
good choice for applications that do not require a precision reference for the DAC088S085. It comes in 3 V, 3.3
V, and 5 V versions, among others, and sports a low 30-µV noise specification at low frequencies. Because low
frequency noise is relatively difficult to filter, this specification could be important for some applications. The
LP3985 comes in a space-saving, 5-pin SOT-23 and 5-bump DSBGA packages.
Input
Voltage
VIN
LP2980
ON /OFF
VOUT
+
4.7 PF
0.1 PF
VA VREF1,2
DAC088S085
SYNC
DIN
VOUT = 0V
to 5V
SCLK
Figure 45. Using the LP3985 Regulator
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Using References as Power Supplies (continued)
An input capacitance of 1 µF without any ESR requirement is required at the LP3985 input, while a 1-µF ceramic
capacitor with an ESR requirement of 5 mΩ to 500 mΩ is required at the output. Careful interpretation and
understanding of the capacitor specification is required to ensure correct device operation.
10.1.4 LP2980
The LP2980 is an ultra-low dropout regulator with a ±0.5% or ±1% accuracy over temperature, depending upon
grade. It is available in 3 V, 3.3 V, and 5 V versions, among others.
VIN
Input
Voltage
LP2980
ON /OFF
VOUT
+
4.7 PF
0.1 PF
VA VREF1,2
DAC088S085
SYNC
DIN
VOUT = 0V
to 5V
SCLK
Figure 46. Using the LP2980 Regulator
Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor
must be at least 1 µF over temperature, but values of 2.2 µF or more provides even better performance. The
ESR of this capacitor must be within the range specified in the LP2980 data sheet. Surface-mount solid tantalum
capacitors offer a good combination of small size and low ESR. Ceramic capacitors are attractive due to their
small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic
capacitors are typically not a good choice due to their large size and high ESR values at low temperatures.
11 Layout
11.1 Layout Guidelines
For best accuracy and minimum noise, the printed-circuit board containing the DAC088S085 must have separate
analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of
these planes must be located in the same board layer. A single ground plane is preferred if digital return current
does not flow through the analog ground area. Frequently a single ground plane design uses a fencing technique
to prevent the mixing of analog and digital ground current. Separate ground planes must only be used when the
fencing technique is inadequate. The separate ground planes must be connected in one place, preferably near
the DAC088S085. Take special care to ensure that digital signals with fast edge rates do not pass over split
ground planes. They must always have a continuous return path below their traces.
For best performance, the DAC088S085 power supply must be bypassed with at least a 1-µF and a 0.1-µF
capacitor. The 0.1-µF capacitor must be placed right at the device supply pin. The 1-µF or larger valued
capacitor can be a tantalum capacitor while the 0.1-µF capacitor must be a ceramic capacitor with low ESL and
low ESR. If a ceramic capacitor with low ESL and low ESR is used for the 1-µF value and it can be placed right
at the supply pin, the 0.1-µF capacitor can be eliminated. Capacitors of this nature typically span the same
frequency spectrum as the 0.1-µF capacitor and thus eliminate the need for the extra capacitor. The power
supply for the DAC088S085 must only be used for analog circuits.
It is also advisable to avoid the crossover of analog and digital signals. This helps minimize the amount of noise
from the transitions of the digital signals from coupling onto the sensitive analog signals such as the reference
pins and the DAC outputs.
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11.2 Layout Example
Figure 47. Typical Layout
30
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
12.1.1.1 Specification Definitions
DIFFERENTIAL NON-LINEARITY (DNL) The measure of the maximum deviation from the ideal step size of 1
LSB, which is VREF / 256 = VA / 256.
DAC-to-DAC CROSSTALK The glitch impulse transferred to a DAC output in response to a full-scale change in
the output of another DAC.
DIGITAL CROSSTALK The glitch impulse transferred to a DAC output at mid-scale in response to a full-scale
change in the input register of another DAC.
DIGITAL FEEDTHROUGH A measure of the energy injected into the analog output of the DAC from the digital
inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the
data bus.
FULL-SCALE ERROR The difference between the actual output voltage with a full scale code (FFh) loaded into
the DAC and the value of VA x 255 / 256.
GAIN ERROR The deviation from the ideal slope of the transfer function. It can be calculated from Zero and FullScale Errors as GE = FSE – ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero
Error.
GLITCH IMPULSE The energy injected into the analog output when the input code to the DAC register changes.
It is specified as the area of the glitch in nanovolt-seconds.
INTEGRAL NON-LINEARITY (INL) A measure of the deviation of each individual code from a straight line
through the input to output transfer function. The deviation of any given code from this straight line
is measured from the center of that code value. The end point method is used. INL for this product
is specified over a limited range, per Electrical Characteristics.
LEAST SIGNIFICANT BIT (LSB) The bit that has the smallest value or weight of all bits in a word. This value is:
LSB = VREF / 2n
where
•
•
VREF is the supply voltage for this product
n is the DAC resolution in bits, which is 8 for the DAC088S085
(8)
MAXIMUM LOAD CAPACITANCE The maximum capacitance that can be driven by the DAC with output
stability maintained.
MONOTONICITY The condition of being monotonic, where the DAC has an output that never decreases when
the input code increases.
MOST SIGNIFICANT BIT (MSB) The bit that has the largest value or weight of all bits in a word. Its value is 1/2
of VA.
MULTIPLYING BANDWIDTH The frequency at which the output amplitude falls 3 dB below the input sine wave
on VREF1,2 with the DAC code at full-scale.
NOISE SPECTRAL DENSITY The internally generated random noise. It is measured by loading the DAC to midscale and measuring the noise at the output.
POWER EFFICIENCY The ratio of the output current to the total supply current. The output current comes from
the power supply. The difference between the supply and output currents is the power consumed
by the device without a load.
SETTLING TIME The time for the output to settle to within 1/2 LSB of the final value after the input code is
updated.
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Device Support (continued)
TOTAL HARMONIC DISTORTION PLUS NOISE (THD+N) The ratio of the harmonics plus the noise present at
the output of the DACs to the rms level of an ideal sine wave applied to VREF1,2 with the DAC code
at mid-scale.
WAKE-UP TIME The time for the output to exit power-down mode. This is the time from the rising edge of SYNC
to when the output voltage deviates from the power-down voltage of 0 V.
ZERO CODE ERROR The output error, or voltage, present at the DAC output after a code of 00h has been
entered.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
SPI is a trademark of Motorola, Inc..
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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19-Jan-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC088S085CIMT/NOPB
ACTIVE
TSSOP
PW
16
92
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
X82C
DAC088S085CIMTX/NOPB
ACTIVE
TSSOP
PW
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
X82C
DAC088S085CISQ/NOPB
ACTIVE
WQFN
RGH
16
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
088S085
DAC088S085CISQX/NOPB
ACTIVE
WQFN
RGH
16
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
088S085
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jan-2016
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jan-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DAC088S085CIMTX/NOP
B
Package Package Pins
Type Drawing
TSSOP
DAC088S085CISQ/NOPB WQFN
DAC088S085CISQX/NOP
B
WQFN
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
PW
16
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
RGH
16
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
RGH
16
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jan-2016
*All dimensions are nominal
Device
DAC088S085CIMTX/NOP
B
DAC088S085CISQ/NOPB
DAC088S085CISQX/NOP
B
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TSSOP
PW
16
2500
367.0
367.0
35.0
WQFN
RGH
16
1000
210.0
185.0
35.0
WQFN
RGH
16
4500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RGH0016A
WQFN - 0.8 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
0.5
0.3
PIN 1 INDEX AREA
0.3
0.2
4.1
3.9
DETAIL
OPTIONAL TERMINAL
TYPICAL
DIM A
OPT 1 OPT 1
(0.1)
(0.2)
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08
2.6 0.1
5
SEE TERMINAL
DETAIL
(A) TYP
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
17
4X
1.5
SYMM
1
12
16X
PIN 1 ID
(OPTIONAL)
16
SYMM
13
16X
0.3
0.2
0.1
0.05
C A B
0.5
0.3
4214978/B 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGH0016A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 2.6)
SYMM
16
13
16X (0.6)
(R0.05)
TYP
1
12
16X (0.25)
SYMM
17
(3.8)
(1)
12X (0.5)
9
4
( 0.2) TYP
VIA
8
5
(1)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214978/B 01/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGH0016A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.15)
(0.675) TYP
16
13
17
16X (0.6)
1
12
(0.675)
TYP
16X (0.25)
SYMM
(3.8)
12X (0.5)
9
4
EXPOSED METAL
TYP
8
5
(R0.05)
TYP
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4214978/B 01/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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