Texas Instruments | ADS54J42 Dual-Channel, 14-Bit, 625-MSPS, Analog-to-Digital Converter (Rev. A) | Datasheet | Texas Instruments ADS54J42 Dual-Channel, 14-Bit, 625-MSPS, Analog-to-Digital Converter (Rev. A) Datasheet

Texas Instruments ADS54J42 Dual-Channel, 14-Bit, 625-MSPS, Analog-to-Digital Converter (Rev. A) Datasheet
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ADS54J42
SBAS756A – FEBRUARY 2016 – REVISED MARCH 2016
ADS54J42
Dual-Channel, 14-Bit, 625-MSPS, Analog-to-Digital Converter
1 Features
3 Description
•
•
•
The ADS54J42 is a low-power, wide-bandwidth, 14bit, 625-MSPS, dual-channel, analog-to-digital
converter (ADC). Designed for high signal-to-noise
ratio (SNR), the device delivers a noise floor of
–157 dBFS/Hz for applications aiming for highest
dynamic range over a wide instantaneous bandwidth.
The device supports the JESD204B serial interface
with data rates up to 6.25 Gbps. The buffered analog
input provides uniform input impedance across a wide
frequency range and minimizes sample-and-hold
glitch energy. Each ADC channel optionally can be
connected to a wideband digital down-converter
(DDC) block. The ADS54J42 provides excellent
spurious-free dynamic range (SFDR) over a large
input frequency range with very low power
consumption.
1
•
•
•
•
•
•
•
•
•
14-Bit Resolution, Dual-Chanel, 625-MSPS ADC
Noise Floor: –157 dBFS/Hz
Spectral Performance (fIN = 170 MHz at –1 dBFS):
– SNR: 71.0 dBFS
– NSD: –155.9 dBFS/Hz
– SFDR: 85 dBc
– SFDR: 93 dBc (Except HD2, HD3, and
Interleaving Tones)
Spectral Performance (fIN = 350 MHz at –1 dBFS):
– SNR: 69 dBFS
– NSD: –153.9 dBFS/Hz
– SFDR: 76 dBc
– SFDR: 90 dBc (Except HD2, HD3, and
Interleaving Tones)
Channel Isolation: 100 dBc at fIN = 170 MHz
Input Full-Scale: 1.9 VPP
Input Bandwidth (3 dB): 1.2 GHz
On-Chip Dither
Integrated Wideband DDC Block
JESD204B Interface with Subclass 1 Support:
– 2 Lanes per ADC at 6.25 Gbps
– 4 Lanes per ADC at 3.125 Gbps
– Support for Multi-Chip Synchronization
Power Dissipation: 970 mW/Ch at 625 MSPS
Package: 72-Pin VQFNP (10 mm × 10 mm)
The JESD204B interface reduces the number of
interface lines, allowing high system integration
density. An internal phase-locked loop (PLL)
multiplies the ADC sampling clock to derive the bit
clock that is used to serialize the 14-bit data from
each channel.
Device Information
PART NUMBER
ADS54J42
FFT for 170-MHz Input Signal
0
SNR = 71 dBFS
SFDR = 85 dBc
-20 Non HD2,HD3 Spur = 93 dBc
Amplitude (dBFS)
Radar and Antenna Arrays
Broadband Wireless
Cable CMTS, DOCSIS 3.1 Receivers
Communications Test Equipment
Microwave Receivers
Software Defined Radio (SDR)
Digitizers
Medical Imaging and Diagnostics
BODY SIZE (NOM)
10.00 mm × 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
•
•
•
PACKAGE
VQFNP (72)
-40
-60
-80
-100
-120
0
62.5
125
187.5
Input Frequency (MHz)
250
312.5
D101
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS54J42
SBAS756A – FEBRUARY 2016 – REVISED MARCH 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
AC Characteristics .................................................... 8
Digital Characteristics ............................................. 11
Timing Characteristics............................................. 12
Typical Characteristics ............................................ 14
Typical Characteristics: Contour ........................... 23
Detailed Description ............................................ 25
8.1 Overview ................................................................. 25
8.2
8.3
8.4
8.5
9
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Register Maps .........................................................
25
26
33
43
Application and Implementation ........................ 66
9.1 Application Information............................................ 66
9.2 Typical Application .................................................. 71
10 Power Supply Recommendations ..................... 73
11 Layout................................................................... 73
11.1 Layout Guidelines ................................................. 73
11.2 Layout Example .................................................... 74
12 Device and Documentation Support ................. 75
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
75
75
75
75
75
13 Mechanical, Packaging, and Orderable
Information ........................................................... 75
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2016) to Revision A
Page
•
Changed front-page figure...................................................................................................................................................... 1
•
Changed AC Characteristics table: changes made throughout table..................................................................................... 8
•
Changed conditions of Typical Characteristics section ........................................................................................................ 14
•
Changed Figure 9................................................................................................................................................................. 15
•
Changed Figure 19 and Figure 20 ...................................................................................................................................... 16
•
Changed Figure 21 .............................................................................................................................................................. 17
•
Added note to Figure 45 and Figure 46 .............................................................................................................................. 21
•
Added Typical Characteristics: Contour section................................................................................................................... 23
•
Changed description of Eye Diagrams section for clarification ............................................................................................ 42
•
Changed steps 4 and 5 in Table 66 ..................................................................................................................................... 68
•
Changed Figure 132............................................................................................................................................................. 70
2
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5 Device Comparison Table
PART NUMBER
SPEED GRADE (MSPS)
RESOLUTION (Bits)
CHANNEL
ADS54J42
625
14
2
ADS54J60
1000
16
2
ADS54J40
1000
14
2
ADS54J66
500
14
4
ADS54J69
500
16
2
6 Pin Configuration and Functions
DB2P
DB2M
IOVDD
DB1P
DB1M
DGND
DB0P
DB0M
IOVDD
SYNC
DA0M
DA0P
DGND
DA1M
DA1P
IOVDD
DA2M
DA2P
RMP Package
72-Pin VQFNP
Top View
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DB3M
1
54
DA3M
DB3P
2
53
DA3P
DGND
3
52
DGND
IOVDD
4
51
IOVDD
SDIN
5
50
PDN
SCLK
6
49
RES
SEN
7
48
RESET
DVDD
8
47
DVDD
AVDD
9
46
AVDD
AVDD3V
10
45
AVDD3V
SDOUT
11
44
AVDD
AVDD
12
43
AVDD
INBP
13
42
INAP
INBM
14
41
INAM
AVDD
15
40
AVDD
AVDD3V
16
39
AVDD3V
AVDD
17
38
AVDD
AGND
18
37
AGND
22
23
24
25
26
27
28
29
30
31
32
33
NC
NC
VCM
AGND
AVDD3V
AVDD
AGND
CLKINP
CLKINM
AGND
AVDD
AVDD3V
AGND
SYSREFP
34
35
36
AGND
21
AVDD
20
SYSREFM
19
NC
GND Pad
(Back Side)
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Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CLOCK, SYSREF
CLKINM
28
I
Negative differential clock input for the ADC
CLKINP
27
I
Positive differential clock input for the ADC
SYSREFM
34
I
Negative external SYSREF input
SYSREFP
33
I
Positive external SYSREF input
PDN
50
I/O
RESET
48
I
Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor.
SCLK
6
I
Serial interface clock input
SDIN
5
I
Serial interface data input
SDOUT
11
O
Serial interface data output.
Can be configured to fast overrange output for channel B via the SPI.
SEN
7
I
Serial interface enable
O
JESD204B serial data negative outputs for channel A
O
JESD204B serial data positive outputs for channel A
O
JESD204B serial data negative outputs for channel B
O
JESD204B serial data positive outputs for channel B
CONTROL, SERIAL
Power-down. Can be configured via an SPI register setting.
Can be configured to fast overrange output for channel A via the SPI.
DATA INTERFACE
DA0M
62
DA1M
59
DA2M
56
DA3M
54
DA0P
61
DA1P
58
DA2P
55
DA3P
53
DB0M
65
DB1M
68
DB2M
71
DB3M
1
DB0P
66
DB1P
69
DB2P
72
DB3P
2
SYNC
63
I
Synchronization input for the JESD204B port
INAM
41
I
Differential analog negative input for channel A
INAP
42
I
Differential analog positive input for channel A
INBM
14
I
Differential analog negative input for channel B
INBP
13
I
Differential analog positive input for channel B
VCM
22
O
Common-mode voltage, 2.1 V.
Note that analog inputs are internally biased to this pin through 600 Ω (effective), no external
connection from the VCM pin to the INxP or INxM pin is required.
AGND
18, 23, 26, 29, 32, 36, 37
I
Analog ground
AVDD
9, 12, 15, 17, 25, 30, 35, 38,
40, 43, 44, 46
I
Analog 1.9-V power supply
INPUT, COMMON MODE
POWER SUPPLY
AVDD3V
10, 16, 24, 31, 39, 45
I
Analog 3.0-V power supply for the analog buffer
DGND
3, 52, 60, 67
I
Digital ground
DVDD
8, 47
I
Digital 1.9-V power supply
IOVDD
4, 51, 57, 64, 70
I
Digital 1.15-V power supply for the JESD204B transmitter
19-21
—
49
I
NC, RES
NC
RES
4
Unused pins, do not connect
Reserved pin. Connect to DGND.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range
MIN
MAX
AVDD3V
–0.3
3.6
AVDD
–0.3
2.1
DVDD
–0.3
2.1
IOVDD
–0.2
1.4
Voltage between AGND and DGND
Voltage applied to input pins
–0.3
0.3
INAP, INBP, INAM, INBM
–0.3
3
CLKINP, CLKINM
–0.3
AVDD + 0.3
SYSREFP, SYSREFM
–0.3
AVDD + 0.3
SCLK, SEN, SDIN, RESET, SYNC, PDN
–0.2
2.1
–65
150
Storage temperature, Tstg
(1)
UNIT
V
V
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V HBM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2)
AVDD3V
Supply voltage range
Analog inputs
NOM
MAX
2.85
3.0
3.6
AVDD
1.8
1.9
2.0
DVDD
1.7
1.9
2.0
IOVDD
1.1
1.15
1.2
1.9
VPP
2.0
V
Maximum analog input frequency for a 1.9-VPP input
amplitude (3) (4)
400
MHz
Input clock amplitude differential
(VCLKP – VCLKM)
LVPECL, ac-coupled
300 (5)
Operating free-air, TA
625
0.75
1.5
0.8
1.6
45%
50%
LVDS, ac-coupled
Input device clock duty cycle
(1)
(2)
(3)
(4)
(5)
(6)
V
Input common-mode voltage
Sine wave, ac-coupled
Temperature
UNIT
Differential input voltage range
Input clock frequency, device clock frequency
Clock inputs
MIN
VPP
0.7
–40
Operating junction, TJ
MHz
55%
85
105
(6)
125
ºC
SYSREF must be applied for the device to initialize; see the SYSREF Signal section for details.
After power-up, always use a hardware reset to reset the device for the first time; see Table 66 for details.
Operating 0.5 dB below the maximum-supported amplitude is recommended to accommodate gain mismatch in interleaving ADCs.
At high frequencies, the maximum supported input amplitude reduces; see Figure 36 for details.
See Table 9.
Prolonged use above the nominal junction temperature can increase the device failure-in-time (FIT) rate.
7.4 Thermal Information
ADS54J42
THERMAL METRIC (1)
RMP (VQFNP)
UNIT
72 PINS
RθJA
Junction-to-ambient thermal resistance
22.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
5.1
°C/W
RθJB
Junction-to-board thermal resistance
2.4
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
2.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.4
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
625
MSPS
GENERAL
ADC sampling rate
Resolution
14
Bits
POWER SUPPLIES
AVDD3V
3.0-V analog supply
2.85
3.0
3.6
V
AVDD
1.9-V analog supply
1.8
1.9
2.0
V
DVDD
1.9-V digital supply
1.7
1.9
2.0
V
IOVDD
1.15-V SERDES supply
1.1
1.15
1.2
V
IAVDD3V
3.0-V analog supply current
VIN = full-scale on both channels
247
310
mA
IAVDD
1.9-V analog supply current
VIN = full-scale on both channels
260
410
mA
IDVDD
1.9-V digital supply current
Eight lanes active
(LMFS = 8224)
137
210
mA
IIOVDD
1.15-V SERDES supply current
Eight lanes active
(LMFS = 8224)
382
720
mA
Pdis
Total power dissipation
Eight lanes active
(LMFS = 8224)
1.94
2.68
W
IDVDD
1.9-V digital supply current
Four lanes active (LMFS = 4222),
2X decimation
130
mA
IIOVDD
1.15-V SERDES supply current
Four lanes active (LMFS = 4222),
2X decimation
404
mA
Pdis
Total power dissipation
Four lanes active (LMFS = 4222),
2X decimation
1.95
W
IDVDD
1.9-V digital supply current
Two lanes active (LMFS = 2221),
4X decimation
129
mA
IIOVDD
1.15-V SERDES supply current
Two lanes active (LMFS = 2221),
4X decimation
400
mA
Pdis (1)
Total power dissipation
Two lanes active (LMFS = 2221),
4X decimation
1.94
W
Global power-down power dissipation
285
315
mW
ANALOG INPUTS (INAP, INAM, INBP, INBM)
Differential input full-scale voltage
1.9
VIC
Common-mode input voltage
2.0
VPP
V
RIN
Differential input resistance
At 170-MHz input frequency
0.6
kΩ
CIN
Differential input capacitance
At 170-MHz input frequency
4.7
pF
Analog input bandwidth (3 dB)
50-Ω source driving ADC inputs
terminated with 50 Ω
1.2
GHz
1.15
V
CLOCK INPUT (CLKINP, CLKINM)
Internal clock biasing
(1)
CLKINP and CLKINM are
connected to internal biasing
voltage through 400 Ω
See the Power-Down Mode section for details.
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7.6 AC Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input amplitude, and
0-dB digital gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Signal-to-noise ratio
fIN = 100 MHz, AIN = –1 dBFS
71.5
fIN = 270 MHz, AIN = –1 dBFS
69.9
fIN = 300 MHz, AIN = –1 dBFS
69.5
fIN = 370 MHz, AIN = –1 dBFS
68.7
fIN = 470 MHz, AIN = –3 dBFS
68.7
AIN = –6 dBFS
AIN = –6 dBFS, gain = 5 dB
SINAD
Signal-to-noise and distortion
ratio
fIN = 100 MHz, AIN = –1 dBFS
156.4
Spurious-free dynamic range
(excluding IL spurs)
155.2
154.8
fIN = 300 MHz, AIN = –1 dBFS
154.4
fIN = 370 MHz, AIN = –1 dBFS
153.6
fIN = 470 MHz, AIN = –3 dBFS
153.6
AIN = –6 dBFS
152.8
AIN = –6 dBFS, gain = 5 dB
147.6
fIN = 10 MHz, AIN = –1 dBFS
71.7
fIN = 100 MHz, AIN = –1 dBFS
71.4
67
69.8
fIN = 270 MHz, AIN = –1 dBFS
69.7
fIN = 300 MHz, AIN = –1 dBFS
69.1
fIN = 370 MHz, AIN = –1 dBFS
67.4
fIN = 470 MHz, AIN = –3 dBFS
66.4
AIN = –6 dBFS
dBFS
65.8
AIN = –6 dBFS, gain = 5 dB
61
fIN = 10 MHz, AIN = –1 dBFS
90
fIN = 100 MHz, AIN = –1 dBFS
85
76
85
fIN = 230 MHz, AIN = –1 dBFS
80
fIN = 270 MHz, AIN = –1 dBFS
84
fIN = 300 MHz, AIN = –1 dBFS
81
fIN = 370 MHz, AIN = –1 dBFS
73
fIN = 470 MHz, AIN = –3 dBFS
69
AIN = –6 dBFS
64
AIN = –6 dBFS, gain = 5 dB
65
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dBFS/Hz
70.8
fIN = 230 MHz, AIN = –1 dBFS
fIN = 720 MHz
8
155.9
fIN = 270 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
SFDR
154.2
fIN = 230 MHz, AIN = –1 dBFS
fIN = 720 MHz
dBFS
62.7
156.7
fIN = 170 MHz, AIN = –1 dBFS
UNIT
67.9
fIN = 10 MHz, AIN = –1 dBFS
fIN = 720 MHz
MAX
71
70.3
fIN = 170 MHz, AIN = –1 dBFS
Noise spectral density
67.2
fIN = 230 MHz, AIN = –1 dBFS
fIN = 720 MHz
NSD
TYP
71.8
fIN = 170 MHz, AIN = –1 dBFS
SNR
MIN
fIN = 10 MHz, AIN = –1 dBFS
dBc
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AC Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input amplitude, and
0-dB digital gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Second-order harmonic
distortion
fIN = 100 MHz, AIN = –1 dBFS
98
88
85
fIN = 300 MHz, AIN = –1 dBFS
81
fIN = 370 MHz, AIN = –1 dBFS
73
fIN = 470 MHz, AIN = –3 dBFS
70
AIN = –6 dBFS
64
AIN = –6 dBFS, gain = 5 dB
65
fIN = 10 MHz, AIN = –1 dBFS
98
fIN = 100 MHz, AIN = –1 dBFS
85
80
fIN = 270 MHz, AIN = –1 dBFS
84
fIN = 300 MHz, AIN = –1 dBFS
84
fIN = 370 MHz, AIN = –1 dBFS
80
fIN = 470 MHz, AIN = –3 dBFS
69
AIN = –6 dBFS
75
AIN = –6 dBFS, gain = 5 dB
77
fIN = 10 MHz, AIN = –1 dBFS
96
fIN = 100 MHz, AIN = –1 dBFS
97
fIN = 170 MHz, AIN = –1 dBFS
Spurious-free dynamic range
(excluding HD2, HD3, and IL
spur)
94
fIN = 270 MHz, AIN = –1 dBFS
94
fIN = 300 MHz, AIN = –1 dBFS
93
fIN = 370 MHz, AIN = –1 dBFS
88
fIN = 470 MHz, AIN = –3 dBFS
90
AIN = –6 dBFS
Effective number of bits
11.6
fIN = 100 MHz, AIN = –1 dBFS
11.6
10.8
11.5
fIN = 230 MHz, AIN = –1 dBFS
11.3
fIN = 270 MHz, AIN = –1 dBFS
11.3
fIN = 300 MHz, AIN = –1 dBFS
11.2
fIN = 370 MHz, AIN = –1 dBFS
11.0
fIN = 470 MHz, AIN = –3 dBFS
10.7
AIN = –6 dBFS
AIN = –6 dBFS, gain = 5 dB
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10.6
9.8
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dBFS
83
fIN = 10 MHz, AIN = –1 dBFS
fIN = 720 MHz
dBc
82
AIN = –6 dBFS, gain = 5 dB
fIN = 170 MHz, AIN = –1 dBFS
dBc
96
fIN = 230 MHz, AIN = –1 dBFS
fIN = 720 MHz
ENOB
79
UNIT
85
fIN = 230 MHz, AIN = –1 dBFS
fIN = 720 MHz
Non
HD2,
HD3
76
MAX
95
fIN = 270 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
Third-order harmonic
distortion
76
fIN = 230 MHz, AIN = –1 dBFS
fIN = 720 MHz
HD3
TYP
90
fIN = 170 MHz, AIN = –1 dBFS
HD2
MIN
fIN = 10 MHz, AIN = –1 dBFS
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AC Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input amplitude, and
0-dB digital gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Total harmonic distortion
fIN = 100 MHz, AIN = –1 dBFS
84
79
81
fIN = 300 MHz, AIN = –1 dBFS
79
fIN = 370 MHz, AIN = –1 dBFS
72
fIN = 470 MHz, AIN = –3 dBFS
67
AIN = –6 dBFS
63
AIN = –6 dBFS, gain = 5 dB
64
fIN = 10 MHz, AIN = –1 dBFS
91
fIN = 100 MHz, AIN = –1 dBFS
89.
Crosstalk isolation between
channel A and B
85
fIN = 270 MHz, AIN = –1 dBFS
85
fIN = 300 MHz, AIN = –1 dBFS
83
fIN = 370 MHz, AIN = –1 dBFS
84
fIN = 470 MHz, AIN = –3 dBFS
86
10
AIN = –6 dBFS
82
AIN = –6 dBFS, gain = 5 dB
83
fIN1 = 185 MHz, fIN2 = 190 MHz,
AIN = –7 dBFS
93
fIN1 = 365 MHz, fIN2 = 370 MHz,
AIN = –7 dBFS
78
fIN1 = 465 MHz, fIN2 = 470 MHz,
AIN = –7 dBFS
71
Full-scale, 170-MHz signal on aggressor, idle
channel is victim
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UNIT
dBc
86.
fIN = 230 MHz, AIN = –1 dBFS
fIN = 720 MHz
Two-tone, third-order
intermodulation distortion
69
MAX
84
fIN = 270 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
IMD3
73
fIN = 230 MHz, AIN = –1 dBFS
fIN = 720 MHz
SFDR_IL Interleaving spur
TYP
89
fIN = 170 MHz, AIN = –1 dBFS
THD
MIN
fIN = 10 MHz, AIN = –1 dBFS
100
dBc
dBFS
dB
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7.7 Digital Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless
otherwise noted)
PARAMETER
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, SYNC, PDN)
TEST CONDITIONS
MIN
0.8
VIH
High-level input voltage
All digital inputs support 1.2-V and 1.8-V logic levels
VIL
Low-level input voltage
All digital inputs support 1.2-V and 1.8-V logic levels
IIH
High-level input current
IIL
Low-level input current
TYP
MAX
UNITS
(1)
V
0.4
SEN
0
RESET, SCLK, SDIN, PDN, SYNC
50
SEN
50
RESET, SCLK, SDIN, PDN, SYNC
V
µA
µA
0
DIGITAL INPUTS (SYSREFP, SYSREFM)
VD
Differential input voltage
V(CM_DIG)
Common-mode voltage for SYSREF (2)
0.35
0.45
1.4
V
1.3
V
DVDD
V
DIGITAL OUTPUTS (SDOUT, PDN (2))
VOH
High-level output voltage
VOL
Low-level output voltage
DVDD –
0.1
0.1
V
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM) (3)
VOD
Output differential voltage
VOC
Output common-mode voltage
Transmitter short-circuit current
zos
(2)
(3)
Transmitter pins shorted to any voltage between
–0.25 V and 1.45 V
Single-ended output impedance
Output capacitance
(1)
With default swing setting
Output capacitance inside the device,
from either output to ground
700
mVPP
450
mV
–100
100
mA
50
Ω
2
pF
The RESET, SCLK, SDIN, and PDN pins have a 20-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 20-kΩ
(typical) pullup resistor to IOVDD.
When functioning as an OVR pin for channel B.
100-Ω differential termination.
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7.8 Timing Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless
otherwise noted)
MIN
TYP
MAX
UNITS
SAMPLE TIMING
Aperture delay
0.75
Aperture delay matching between two channels on the same device
1.6
±70
Aperture delay matching between two devices at the same temperature and supply voltage
ns
ps
±270
ps
120
fS rms
Wake-up time to valid data after coming out of global power-down
150
µs
Data latency (1): ADC sample to digital output
134
Input
clock
cycles
62
Input
clock
cycles
4
ns
Aperture jitter
WAKE-UP TIMING
LATENCY
OVR latency: ADC sample to OVR bit
tPD
Propagation delay: logic gates and output buffers delay (does not change with fS)
SYSREF TIMING
tSU_SYSREF
Setup time for SYSREF, referenced to the input clock falling edge
300
tH_SYSREF
Hold time for SYSREF, referenced to the input clock falling edge
100
900
ps
ps
JESD OUTPUT INTERFACE TIMING CHARACTERISTICS
Unit interval
160
400
ps
Serial output data rate
2.5
6.25
Gbps
Total jitter for BER of 1E-15 and lane rate = 6.25 Gbps
26
Random jitter for BER of 1E-15 and lane rate = 6.25 Gbps
tR, tF
(1)
0.75
ps
ps rms
Deterministic jitter for BER of 1E-15 and lane rate = 6.25 Gbps
12
ps, pk-pk
Data rise time, data fall time: rise and fall times are measured from 20% to 80%,
differential output waveform, 2.5 Gbps ≤ bit rate ≤ 6.25 Gbps
35
ps
Overall ADC latency = data latency + tPDI.
Sample N
ts_min
ts_max
CLKIN
625 MSPS
SYSREF
Figure 1. SYSREF Timing
12
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N+1
N+2
N
N+3
Sample
tPD
Data Latency: 134 Clock Cycles
CLKINM
CLKINP
DA0P, DA0M,
DB0P, DB0M
D
20
Sample N-1
DA1P, DA1M,
DB1P, DB1M
Sample N-1
D
11
D
20
Sample N
D
10
D
11
D
20
Sample N+1
D
1
D
10
Sample N
Sample N+2
D
1
Sample N+1
D
10
Sample N+2
Figure 2. Sample Timing Requirements
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7.9 Typical Characteristics
0
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
-40
-60
-80
-40
-60
-80
-100
-100
-120
-120
0
62.5
125
187.5
Input Frequency (MHz)
250
0
312.5
SNR = 71.9 dBFS, SINAD = 71.86 dBFS,
THD = 93 dBc, IL spur = 94 dBc, SFDR = 94 dBc,
non HD2, HD3 spur = 94 dBc
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
250
312.5
D102
Figure 4. FFT for 140-MHz Input Signal
0
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
0
62.5
125
187.5
Input Frequency (MHz)
250
312.5
0
62.5
D103
SNR = 71 dBFS, SINAD = 70.9 dBFS,
SFDR = 85 dBc, THD = 84 dBc, IL spur = 87 dBc,
non HD2, HD3 spur = 93 dBc
-20
-20
Amplitude (dBFS)
0
-60
-80
-100
250
312.5
D104
Figure 6. FFT for 230-MHz Input Signal
0
-40
125
187.5
Input Frequency (MHz)
SNR = 70.4 dBFS, SINAD = 69.9 dBFS,
IL spur = 89 dBc, SFDR = 80 dBc, THD = 79 dBc,
non HD2, HD3 spur = 91 dBc
Figure 5. FFT for 170-MHz Input Signal
Amplitude (dBFS)
125
187.5
Input Frequency (MHz)
SNR = 71.3 dBFS, SINAD = 71.1 dBFS,
SFDR = 86 dBc, THD = 85 dBc, IL spur = 87 dBc,
non HD2, HD3 spur = 95 dBc
Figure 3. FFT for 10-MHz Input Signal
-40
-60
-80
-100
-120
-120
0
62.5
125
187.5
Input Frequency (MHz)
250
312.5
0
D105
SNR = 69.5 dBFS, SINAD = 69.1 dBFS,
IL spur = 81 dBc, SFDR = 80 dBc, THD = 79 dBc,
non HD2, HD3 spur = 90 dBc
62.5
125
187.5
Input Frequency (MHz)
250
312.5
D106
SNR = 68.8 dBFS, SINAD = 67.3 dBFS,
SFDR = 73 dBc, THD = 72 dBc,
IL spur = 81 dBc, non HD2, HD3 spur = 89 dBc
Figure 7. FFT for 300-MHz Input Signal
14
62.5
D101
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Figure 8. FFT for 370-MHz Input Signal
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Typical Characteristics (continued)
0
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
-40
-60
-80
-100
-80
-120
0
62.5
125
187.5
Input Frequency (MHz)
250
312.5
0
62.5
D107
Fundamental amplitude = –3 dBFS, SNR = 68.4 dBFS,
SINAD = 66.1 dBFS, SFDR = 68 dBc, THD = 67 dBc,
IL spur = 89 dBc, non HD2, HD3 spur = 85 dBc
125
187.5
Input Frequency (MHz)
250
312.5
D108
fIN1 = 185 MHz, fIN2 = 190 MHz, each tone at –7 dBFS,
IMD = 89 dBFS
Figure 9. FFT for 470-MHz Input Signal
Figure 10. FFT for Two-Tone Input Signal (–7 dBFS)
0
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
-60
-100
-120
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
0
62.5
125
187.5
Input Frequency (MHz)
250
312.5
0
62.5
D109
fIN1 = 185 MHz, fIN2 = 190 MHz, each tone at –36 dBFS,
IMD = 107 dBFS
-20
-20
Amplitude (dBFS)
0
-60
-80
-100
250
312.5
D110
Figure 12. FFT for Two-Tone Input Signal (–7 dBFS)
0
-40
125
187.5
Input Frequency (MHz)
fIN1 = 370 MHz, fIN2 = 365 MHz, each tone at –7 dBFS,
IMD = 78 dBFS
Figure 11. FFT for Two-Tone Input Signal (–36 dBFS)
Amplitude (dBFS)
-40
-40
-60
-80
-100
-120
0
62.5
125
187.5
Input Frequency (MHz)
250
312.5
-120
0
D111
fIN1 = 370 MHz, fIN2 = 365 MHz, each tone at –36 dBFS,
IMD = 109 dBFS
Figure 13. FFT for Two-Tone Input Signal (–36 dBFS)
62.5
125
187.5
Input Frequency (MHz)
250
312.5
D112
fIN1 = 470 MHz, fIN2 = 465 MHz, each tone at –7 dBFS,
IMD = 71 dBFS
Figure 14. FFT for Two-Tone Input Signal (–7 dBFS)
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Typical Characteristics (continued)
0
-82
-20
-86
-90
-40
IMD (dBFS)
Amplitude (dBFS)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
-60
-94
-98
-80
-102
-100
-106
-120
0
62.5
125
187.5
Input Frequency (MHz)
250
312.5
-110
-35
-31
fIN1 = 470 MHz, fIN2 = 465 MHz, each tone at –36 dBFS,
IMD = 107 dBFS
Figure 15. FFT for Two-Tone Input Signal
(–36 dBFS)
-70
-80
-74
D114
-78
-82
-88
IMD (dBFS)
IMD (dBFS)
-7
Figure 16. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
-84
-92
-96
-86
-90
-94
-100
-98
-104
-102
-31
-27
-23
-19
-15
Each Tone Amplitude (dBFS)
-11
-106
-35
-7
-31
D115
fIN1 = 365 MHz, fIN2 = 370 MHz
-27
-23
-19
-15
Each Tone Amplitude (dBFS)
-11
-7
D116
fIN1 = 465 MHz, fIN2 = 470 MHz
Figure 17. Intermodulation Distortion vs Input Amplitude
(365 MHz and 370 MHz)
Figure 18. Intermodulation Distortion vs Input Amplitude
(465 MHz and 470 MHz)
95
95
AIN = -1 dBFS
AIN = -3 dBFS
AIN = -6 dBFS
90
91
Interleaving Spur (dBc)
85
SFDR (dBc)
-11
fIN1 = 185 MHz, fIN2 = 190 MHz
-76
-108
-35
-27
-23
-19
-15
Each Tone Amplitude (dBFS)
D113
80
75
70
65
87
83
79
60
75
55
0
100
200
300
400
500
Input Frequency (MHz)
600
700
Figure 19. Spurious-Free Dynamic Range vs
Input Frequency
16
0
D017
50
100
150 200 250 300 350
Input Frequency (MHz)
400
450
500
D018
Figure 20. Interleaving Spur vs Input Frequency
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
72.5
73
AIN = -1 dBFS
AIN = -3 dBFS
AIN = -6 dBFS
71
70
71
70.5
68
70
69.5
-40
67
100
200
300
400
500
Input Frequency (MHz)
600
700
AVDD = 1.95 V
AVDD = 2 V
71.5
69
0
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
72
SNR (dBFS)
SNR (dBFS)
72
-15
D019
10
35
Temperature (°C)
60
85
D120
fIN = 170 MHz
Figure 21. Signal-to-Noise Ratio vs Input Frequency
Figure 22. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
73
96
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
94
AVDD = 1.95 V
AVDD = 2 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
72
AVDD = 1.95 V
AVDD = 2 V
90
SNR (dBFS)
SFDR (dBc)
92
88
86
71
70
69
84
68
82
80
-40
-15
10
35
Temperature (°C)
60
67
-40
85
-15
D121
fIN = 170 MHz
60
85
D122
fIN = 350 MHz
Figure 23. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
Figure 24. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
80
72
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
79
AVDD = 1.95 V
AVDD = 2 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
71.6
78
SNR (dBFS)
SFDR (dBc)
10
35
Temperature (°C)
77
DVDD = 1.9 V
DVDD = 1.95 V
DVDD = 2 V
2
71.2
70.8
76
70.4
75
74
-40
-15
10
35
Temperature (°C)
60
85
70
-40
D123
fIN = 350 MHz
-15
10
35
Temperature (°C)
60
85
D124
fIN = 170 MHz
Figure 25. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
Figure 26. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
94
72
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
92
DVDD = 1.9 V
DVDD = 1.95 V
DVDD = 2 V
2
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.95 V
DVDD = 2 V
SNR (dBFS)
SFDR (dBc)
71
90
88
70
69
86
84
-40
-15
10
35
Temperature (°C)
60
68
-40
85
-15
D125
fIN = 170 MHz
D126
72.2
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.95 V
DVDD = 2 V
AVDD3V = 2.85 V
AVDD3V = 3 V
AVDD3V = 3.1 V
AVDD3V = 3.2 V
71.8
SNR (dBFS)
80
SFDR (dBc)
85
Figure 28. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
82
78
76
AVDD3V = 3.3 V
AVDD3V = 3.4 V
AVDD3V = 3.5 V
AVDD3V = 3.6 V
71.4
71
70.6
74
-15
10
35
Temperature (°C)
60
70.2
-40
85
-15
D127
fIN = 350 MHz
10
35
Temperature (°C)
60
85
D128
fIN = 170 MHz
Figure 29. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
Figure 30. Signal-to-Noise Ratio vs
AVDD3V Supply and Temperature
73
94
AVDD3V = 2.85 V
AVDD3V = 3 V
AVDD3V = 3.1 V
AVDD3V = 3.2 V
AVDD3V = 3.3 V
AVDD3V = 3.4 V
AVDD3V = 3.5 V
AVDD3V = 3.6 V
AVDD3V = 2.85 V
AVDD3V = 3 V
AVDD3V = 3.1 V
AVDD3V = 3.2 V
72
SNR (dBFS)
92
SFDR (dBc)
60
fIN = 350 MHz
Figure 27. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
72
-40
10
35
Temperature (°C)
90
88
AVDD3V = 3.3 V
AVDD3V = 3.4 V
AVDD3V = 3.5 V
AVDD3V = 3.6 V
71
70
69
86
84
-40
68
-15
10
35
Temperature (°C)
60
85
67
-40
D129
fIN = 170 MHz
10
35
Temperature (°C)
60
85
D130
fIN = 350 MHz
Figure 31. Spurious-Free Dynamic Range vs
AVDD3V Supply and Temperature
18
-15
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Figure 32. Signal-to-Noise Ratio vs
AVDD3V Supply and Temperature
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Typical Characteristics (continued)
75
84
AVDD3V = 2.85 V
AVDD3V = 3 V
AVDD3V = 3.1 V
AVDD3V = 3.2 V
SNR (dBFS)
80
78
76
-15
10
35
Temperature (°C)
60
71
100
69
75
67
50
65
-70
85
25
-60
-50
D031
fIN = 350 MHz
72
120
70.5
90
69
60
67.5
30
-40
-30
Amplitude (dBFS)
-20
-10
110
74
100
72
90
70
80
68
70
66
0.2
0
D134
fIN = 170 MHz
Figure 35. Performance vs Amplitude
Figure 36. Performance vs Differential Clock Amplitude
125
73
95
SNR
SFDR
74
75
71
50
68
25
0
2.2
SNR (dBFS)
100
SFDR (dBc)
SNR
SFDR
77
0.6
1
1.4
1.8
Differential Clock Amplitude (Vpp)
60
2.2
0.6
1
1.4
1.8
Differential Clock Amplitude (Vpp)
D133
80
SNR (dBFS)
D132
SNR
SFDR
fIN = 350 MHz
65
0.2
0
76
0
-50
-10
Figure 34. Performance vs Amplitude
SNR (dBFS)
73.5
180
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS) 150
SFDR (dBc,dBFS)
SNR (dBFS)
75
-60
-20
fIN = 170 MHz
Figure 33. Spurious-Free Dynamic Range vs
AVDD3V Supply and Temperature
66
-70
-40
-30
Amplitude (dBFS)
SFDR (dBc)
74
-40
73
150
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS) 125
72
90
71
85
70
80
69
75
68
30
D135
fIN = 350 MHz
35
40
45
50
55
60
Input Clock Duty Cycle (%)
65
SFDR (dBc)
SFDR (dBc)
82
AVDD3V = 3.3 V
AVDD3V = 3.4 V
AVDD3V = 3.5 V
AVDD3V = 3.6 V
SFDR (dBc,dBFS)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
70
70
D136
fIN = 170 MHz
Figure 37. Performance vs Differential Clock Amplitude
Figure 38. Performance vs Input Clock Duty Cycle
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
72
71
90
SNR
SFDR 87
70
84
69
81
68
78
67
75
66
72
-10
PSRR with 50-mVPP Signal on AVDD
PSRR with 50-mVPP Signal on AVDD3V
-15
-25
PSRR (dB)
SFDR (dBc)
SNR (dBFS)
-20
-30
-35
-40
-45
-50
65
30
35
40
45
50
55
60
Input Clock Duty Cycle (%)
65
-55
-60
69
70
0
50
D137
100
150
200
250
Frequency of Signal on Supply (MHz)
300
D138
fIN = 350 MHz
Figure 39. Performance vs Input Clock Duty Cycle
Figure 40. Power-Supply Rejection Ratio vs
Test Signal on AVDD
-20
0
-25
-20
Amplitude (dBFS)
-30
CMRR (dB)
-40
-60
-80
-35
-40
-45
-50
-100
-55
-60
-120
0
62.5
125
187.5
Input Frequency (MHz)
250
0
312.5
50
100
150
200
250
Frequency of Input Common-Mode Signal (MHz)
D139
300
D140
fIN = 170 MHz, AIN = –1 dBFS,
fPSRR = 5 MHz, APSRR= 50 mVPP, PSRR (AVDD supply) = 51 dB
Figure 41. Power-Supply Rejection Ratio FFT
for Test Signal on the AVDD Supply
Figure 42. Common-Mode Rejection Ratio vs
Common-Mode Signal
2
Fundamental Amplitude (dBFS)
0
Amplitude (dBFS)
-20
-40
-60
-80
-100
0
-2
-4
-6
-8
-10
-120
0
62.5
125
187.5
Input Frequency (MHz)
250
312.5
0
100
D141
200
300 400 500 600 700
Input Frequency (MHz)
800
900 1000
D046
fIN = 170 MHz, AIN = –1 dBFS,
fCMRR = 5 MHz, ACMRR= 50 mVPP, CMRR = 40 dB
Figure 43. Common-Mode Rejection Ratio FFT
20
Figure 44. Maximum-Supported Amplitude vs
Input Frequency
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
110
85
Gain = 0 dB
Gain = 2 dB
Gain = 4 dB
Gain = 12 dB
Gain = 0 dB
Gain = 2 dB
Gain = 4 dB
105
100
Gain = 6 dB
Gain = 8 dB
Gain = 10 dB
Gain = 12 dB
95
75
SFDR (dBc)
SNR (dBFS)
80
Gain = 6 dB
Gain = 8 dB
Gain = 10 dB
70
65
90
85
80
75
70
60
65
60
55
0
80
160
240
320
Input Frequency (MHz)
400
0
480
D043
NOTE: ADC output amplitude is –1 dBFS, input amplitude is
scaled down by the amount of programmed digital gain.
160
240
320
Input Frequency (MHz)
400
480
D044
NOTE: ADC output amplitude is –1 dBFS, input amplitude is
scaled down by the amount of programmed digital gain.
Figure 46. Spurious-Free Dynamic Range vs
Gain and Input Frequency
Figure 45. Signal-to-Noise Ratio vs
Gain and Input Frequency
3
0
AVDD
DVDD
AVDD3V
IOVDD
TOTAL POWER
-20
Amplitude (dBFS)
2.5
Power Consumption (W)
80
2
1.5
1
0.5
-40
-60
-80
-100
0
275
-120
325
375
425
475
525
Sampling Speed (MSPS)
575
625
0
31.25
D045
62.5
93.75
Input Frequency (MHz)
125
156.25
D146
SNR = 74.1 dBFS, SINAD = 74.09 dBFS,
SFDR = 98 dBc, THD = 93 dBc, non HD2, HD3 spur = 99 dBc
Figure 48. FFT for 185-MHz Input Signal in
Decimate-by-2 Mode
0
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
Figure 47. Power Consumption vs Sampling Speed
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
0
31.25
62.5
93.75
Input Frequency (MHz)
125
156.25
0
D146
SNR = 72 dBFS, SINAD = 71.8 dBFS,
SFDR = 84 dBc, THD = 83 dBc, non HD2, HD3 spur = 98 dBc
15.625
31.25
46.875
Input Frequency (MHz)
62.5
78.125
D148
SNR = 77.6 dBFS, SINAD = 77.5 dBFS,
SFDR = 93 dBc, THD = 92 dBc, non HD2, HD3 spur = 106 dBc
Figure 49. FFT for 350-MHz Input Signal in
Decimate-by-2 Mode
Figure 50. FFT for 10-MHz Input Signal in
Decimate-by-4 Mode
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Typical Characteristics (continued)
0
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
0
15.625
31.25
46.875
Input Frequency (MHz)
62.5
78.125
0
15.625
D149
SNR = 77.4 dBFS, SINAD = 77.3 dBFS,
SFDR = 105 dBc, THD = 102 dBc, non HD2, HD3 spur = 105 dBc
31.25
46.875
Input Frequency (MHz)
62.5
78.125
D150
SNR = 76.7 dBFS, SINAD = 76.6 dBFS,
SFDR = 96 dBc, THD = 98 dBc, non HD2, HD3 spur = 96 dBc
Figure 51. FFT for 70-MHz Input Signal in
Decimate-by-4 Mode
Figure 52. FFT for 170-MHz Input Signal in
Decimate-by-4 Mode
0
Amplitude (dBFS)
-20
-40
-60
-80
-100
-120
0
15.625
31.25
46.875
Input Frequency (MHz)
62.5
78.125
D151
SNR = 74.9 dBFS, SINAD = 74.8 dBFS,
SFDR = 93 dBc, THD = 92 dBc,
non HD2, HD3 spur = 93 dBc
Figure 53. FFT for 270-MHz Input Signal in
Decimate-by-4 Mode
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7.10 Typical Characteristics: Contour
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
600
70.8
Sampling Frequency, MSPS
71.2
70.4
70
69.6
69.2
68.8
69.6
69.2
68.8
68.4
68
550
500
71.2
450
70.8
70.4
70
68.4
68
400
350
71.2
300
50
70.8
100
68
150
68.5
70.4
68.8
70 69.6 69.2
200
250
300
Input Frequency, MHz
69
69.5
68.4
68
350
70
400
70.5
450
71
Figure 54. Signal-to-Noise-Ratio with 0-dB Digital Gain
600
Sampling Frequency, MSPS
65.4
64.6
65
63.8
64.2
63.4
550
63
500
65.4
450
64.6
65
64.2 63.8
63.4
400
350
65.4
300
100
63
64.6
65
200
63.5
64.2 63.8
300
400
500
Input Frequency, MHz
64
63.4
600
64.5
63
700
65
Figure 55. Signal-to-Noise-Ratio with
6-dB Digital Gain
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Typical Characteristics: Contour (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 625 MSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
80
600
Sampling Frequency, MSPS
85
80
80
70
75
550
500
450
90
85
80
80
70
75
400
80
350
300
80
80
90
85
50
100
150
70
75
200
250
300
Input Frequency, MHz
75
350
80
70
400
85
450
90
Figure 56. Spurious-Free-Dynamic-Range with
0-dB Digital Gain
600
Sampling Frequency, MSPS
88
84
80
76
72
68
550
500
450
88
84
80
88
84
80
76
72
400
350
300
100
65
200
70
76
72
300
400
500
Input Frequency, MHz
75
80
600
700
85
Figure 57. Spurious-Free-Dynamic-Range with
6-dB Digital Gain
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8 Detailed Description
8.1 Overview
The ADS54J42 is a low-power, wide-bandwidth, 14-bit, 625-MSPS, dual-channel, analog-to-digital converter
(ADC). The ADS54J42 employs four interleaving ADCs for each channel to achieve a noise floor of
–157 dBFS/Hz. The ADS54J42 uses TI's proprietary interleaving and dither algorithms to achieve a clean
spectrum with a high spurious-free dynamic range (SFDR). The device also offers various programmable
decimation filtering options for systems requiring higher signal-to-noise ratio (SNR) and SFDR over a wide range
of frequencies.
Analog input buffers isolate the ADC driver from glitch energy generated from sampling process, thereby simplify
the driving network on-board. The JESD204B interface reduces the number of interface lines with two-lane and
four-lane options, allowing a high system integration density. The JESD204B interface operates in subclass 1,
enabling multi-chip synchronization with the SYSREF input.
8.2 Functional Block Diagram
ADC
ADC
ADC
ADC
INAP, INAM
Interleaving
Correction
DA2P, DA2M,
DA3P, DA3M
PLL:
x20
x40
Divideby-4
CLKINP,
CLKINM
SYSREFP,
SYSREFM
Buffer
INBP, INBM
DDC Block:
2X, 4X Decimation
Mixer: fS / 16, fS / 4
Digital Block
ADC
ADC
ADC
ADC
DA0P, DA0M,
DA1P, DA1M
DDC Block:
2X, 4X Decimation
Mixer: fS / 16, fS / 4
Digital Block
Interleaving
Correction
JESD204B
Interface
Buffer
SYNC
DB0P, DB0M,
DB1P, DB1M
DB2P, DB2M,
DB3P, DB3M
FOVR
SCLK
SEN
SDIN
RESET
PDN
Control and SPI
Common
Mode
SDOUT
VCM
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8.3 Feature Description
8.3.1 Analog Inputs
The ADS54J42 analog signal inputs are designed to be driven differentially. The analog input pins have internal
analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high
impedance input across a very wide frequency range to the external driving source that enables great flexibility in
the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps
isolate the external driving circuit from the internal switching currents of the sampling circuit, resulting in a more
constant SFDR performance across input frequencies.
The common-mode voltage of the signal inputs is internally biased to VCM using 600-Ω resistors, allowing for accoupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM +
0.475 V) and (VCM – 0.475 V), resulting in a 1.9-VPP (default) differential input swing. The input sampling circuit
has a 3-dB bandwidth that extends up to 1.2 GHz. An equivalent analog input network diagram is shown in
Figure 58.
0.77 :
2 nH
0.6 :
500 fF
150 fF
150 fF
1:
200 fF
3.3 :
3 pF
375 fF
INP
40 :
0.77 :
1:
150 fF
200 fF
3.3 :
600 :
3 pF
375 fF
VCM
40 :
600 :
0.77 :
150 fF
2 nH
0.6 :
500 fF
150 fF
1:
200 fF
3.3 :
3 pF
375 fF
INM
40 :
0.77 :
1:
150 fF
200 fF
3.3 :
3 pF
375 fF
40 :
Figure 58. Analog Input Network
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Feature Description (continued)
The input bandwidth shown in Figure 59 is measured with respect to a 50-Ω differential input termination at the
ADC input pins.
Output Power/Input Power (dB)
0
-3
-6
-9
-12
-15
-18
0
200
400
600 800 1000 1200 1400 1600 1800 2000
Input Frequency (MHz)
D056
Figure 59. Transfer Function versus Frequency
8.3.2 DDC Block
The ADS54J42 has an optional DDC block that can be enabled via an SPI register write. Each ADC channel is
followed by a DDC block consisting of three different decimate-by-2 and decimate-by-4 finite impulse response
(FIR) half-band filter options. The different decimation filter options can be selected via SPI programming.
Figure 60 shows the signal processing done inside the DDC block of the ADS54J42.
Default 14-Bit Data (At 625 MSPS)
Decimate-by-2 Data (At 312.5 MSPS)
LPF
2
BPF
4
Decimate-by-4 Data (At 156.25 MSPS)
Interleaving
Engine,
Digital
Features
Ch X
625 MSPS
Data, x(n)
To JESD
Encoder
4
LPF
Decimate-by-4, I-Data (At 156.25 MSPS)
cos(2 n Πfmix / fS)(1)
sin(2 n Πfmix / fS)(1)
LPF
Decimate-by-4 Q-Data (At 156.25 MSPS)
4
Mode Selection Using
DECFIL MODE[3:0]
Register Bits
(1)
In IQ decimate-by-4 mode, the mixer frequency is fixed at fmix = fS / 4. For fS = 625 MSPS and fmix = 156.25 MHz.
Figure 60. DDC Block
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Feature Description (continued)
8.3.2.1 Decimate-by-2 Filter
This decimation filter has 41 taps. The stop-band attenuation is approximately 90 dB and the pass-band flatness
is ±0.05 dB. Table 1 shows corner frequencies for the low-pass and high-pass filter options.
Table 1. Corner Frequencies for the Decimate-by-2 Filter
CORNERS (dB)
LOW PASS
HIGH PASS
–0.1
0.202 × fS
0.298 × fS
–0.5
0.210 × fS
0.290 × fS
–1
0.215 × fS
0.285 × fS
–3
0.227 × fS
0.273 × fS
Figure 61 and Figure 62 show the frequency response of the decimate-by-2 filter from dc to fS / 2.
5
0.5
0
-20
Magnitude (dB)
Magnitude (dB)
-0.5
-45
-70
-1
-1.5
-2
-95
-2.5
-120
-3
0
0.05
0.1
0.15 0.2 0.25 0.3 0.35
Frequency Response
0.4
0.45
0.5
Figure 61. Decimate-by-2 Filter Response
28
0
D013
0.05
0.1
0.15
Frequency Response
0.2
0.25
D014
Figure 62. Decimate-by-2 Filter Response (Zoomed)
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8.3.2.2 Decimate-by-4 Filter Using a Digital Mixer
This band-pass decimation filter consists of a digital mixer and three concatenated FIR filters with a combined
latency of approximately 28 output clock cycles. The alias band attenuation is approximately 55 dB and the passband flatness is ±0.1 dB. By default after reset, the band-pass filter is centered at fS / 16. Using the SPI, the
center frequency can be programmed at N × fS / 16 (where N = 1, 3, 5, or 7). Table 2 shows corner frequencies
for two extreme options.
Table 2. Corner frequencies for the Decimate-by-4 Filter
CORNERS (dB)
CORNER FREQUENCY AT LOWER SIDE
(Center Frequency fS / 16)
CORNER FREQUENCY AT HIGHER SIDE
(Center Frequency fS / 16)
–0.1
0.011 × fS
0.114 × fS
–0.5
0.010 × fS
0.116 × fS
–1
0.008 × fS
0.117 × fS
–3
0.006 × fS
0.120 × fS
Figure 63 and Figure 64 show the frequency response of the decimate-by-4 filter for center frequencies fS / 16
and 3 × fS / 16 (N = 1 and N = 3, respectively).
10
0.2
0.1
0
0
-0.1
-20
Magnitude (dB)
Magnitude (dB)
-10
-30
-40
-50
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-60
-0.8
-70
-0.9
-80
-1
0
0.05
0.1
0.15 0.2 0.25 0.3 0.35
Frequency Response
0.4
0.45
0.5
0
D015
Figure 63. Decimate-by-4 Filter Response
0.05
0.1
0.15
Frequency Response
0.2
0.25
D016
Figure 64. Decimate-by-4 Filter Response (Zoomed)
8.3.2.3 Decimate-by-4 Filter with IQ Outputs
In this configuration, the DDC block includes a fixed digital fS / 4 mixer. Thus, the IQ pass band is approximately
±0.11 fS, centered at fS / 4. This decimation filter has 41 taps with a latency of approximately ten output clock
cycles. The stop-band attenuation is approximately 90 dB and the pass-band flatness is ±0.05 dB. Table 3 shows
the corner frequencies for a low-pass, decimate-by-4 IQ filter.
Table 3. Corner Frequencies for a Decimate-by-4 IQ Output Filter
CORNERS (dB)
LOW PASS
–0.1
0.107 × fS
–0.5
0.112 × fS
–1
0.115 × fS
–3
0.120 × fS
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Figure 65 and Figure 66 show the frequency response of a decimate-by-4 IQ output filter from dc to fS / 2.
5
0.5
0
-20
Magnitude (dB)
Magnitude (dB)
-0.5
-45
-70
-1
-1.5
-2
-95
-2.5
-120
-3
0
0.05
0.1
0.15 0.2 0.25 0.3 0.35
Frequency Response
0.4
0.45
0.5
0
0.025
D011
Figure 65. Decimate-by-4 IQ Output Filter Response
0.05
0.075
Frequency Response
0.1
0.125
D012
Figure 66. Decimate-by-4 IQ Output Filter Response
(Zoomed)
8.3.3 SYSREF Signal
The SYSREF signal is a periodic signal that is sampled by the ADS54J42 device clock and used to align the
boundary of the local multi-frame clock inside the data converter. SYSREF is required to be a sub-harmonic of
the local multiframe clock (LMFC) internal timing. To meet this requirement, the timing of SYSREF is dependent
on the device clock frequency and the LMFC frequency, as determined by the selected DDC decimation and
frames per multi-frame settings. The SYSREF signal is recommended to be a low-frequency signal in the range
of 1 MHz to 5 MHz to reduce coupling to the signal path both on the printed circuit board (PCB) as well as
internal to the device.
The external SYSREF signal must be a sub-harmonic of the internal LMFC clock, as shown in Equation 1 and
Table 4.
SYSREF = LMFC / 2N
where
•
N = 0, 1, 2, and so forth
(1)
Table 4. LMFSC Clock Frequency
(1)
(2)
LMFS CONFIGURATION
DECIMATION
LMFC CLOCK (1) (2)
4211
—
fS / K
4244
—
(fS / 4) / K
8224
—
(fS / 4) / K
4222
2X
(fS / 4) / K
2242
2X
(fS / 4) / K
2221
4X
(fS / 4) / K
2441
4X (IQ)
(fS / 4) / K
4421
4X (IQ)
(fS / 4) / K
1241
4X
(fS / 4) / K
K = Number of frames per multi-frame (JESD digital page 6900h, address 06h, bits 4-0).
fS = sampling (device) clock frequency.
For example, if LMFS = 8224, the default value of K is 8 + 1 = 9 (the actual value for K = the value set in the SPI
register + 1). If the device clock frequency is fS = 625 MSPS, then the local multi-frame clock frequency becomes
(625 / 4) / 9 = 17.361111 MHz. The SYSREF signal frequency can be chosen as LMFC frequency / 8 =
2.1701389 MHz.
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8.3.4 Overrange Indication
The ADS54J42 provides a fast overrange indication that can be presented in the digital output data stream via
SPI configuration. Alternatively, if not used, the SDOUT (pin 11) and PDN (pin 50) pins can be configured via the
SPI to output the fast OVR indicator.
The JESD 8b, 10b encoder receives 16-bit data that is formed by 14-bit ADC data padded with two 0s as LSBs.
When the FOVR indication is embedded in the output data stream, the LSB of the 16-bit data stream going to the
8b, 10b encoder is replaced, as shown in Figure 67.
16-Bit Data Output (14-Bit ADC Data Padded with Two 0s)
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0,
OVR
16-Bit Data Going to the 8b, 10b Encoder
Figure 67. Overrange Indication in a Data Stream
8.3.4.1 Fast OVR
The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented
after only seven clock cycles, thus enabling a quicker reaction to an overrange event.
The input voltage level that the overload is detected at is referred to as the threshold. The threshold is
programmable using the FOVR THRESHOLD bits, as shown in Figure 68. The FOVR is triggered seven output
clock cycles after the overload condition occurs.
0
FOVR Threshold (dBFS)
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
0
32
64
96
128
160
192
Threshold Decimal Value
224
255
D055
Figure 68. Programming Fast OVR Thresholds
The input voltage level that the fast OVR is triggered at is defined by Equation 2:
Full-Scale × [Decimal Value of the FOVR Threshold Bits] / 255)
(2)
The default threshold is E3h (227d), corresponding to a threshold of –1 dBFS.
In terms of full-scale input, the fast OVR threshold can be calculated as Equation 3:
20log (FOVR Threshold / 255)
(3)
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8.3.5 Power-Down Mode
The ADS54J42 provides a highly-configurable power-down mode. Power-down can be enabled using the PDN
pin or SPI register writes.
A power-down mask can be configured that allows a trade-off between wake-up time and power consumption in
power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2, as shown in
Table 5. See the master page registers in Table 14 for further details.
Table 5. Register Addresses for Power-Down Modes
REGISTER
ADDRESS
REGISTER DATA
COMMENT
A[7:0] (Hex)
7
6
5
4
3
2
0
0
1
0
MASTER PAGE (80h)
20
MASK 1
21
23
MASK 2
24
PDN ADC CHA
PDN BUFFER CHB
PDN ADC CHA
PDN BUFFER CHB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PDN MASK
0
0
0
0
OVERRIDE
PDN PIN
PDN MASK
SEL
53
0
MASK
SYSREF
55
0
0
CONFIG
0
PDN ADC CHB
PDN BUFFER CHA
GLOBAL
PDN
26
PDN ADC CHB
PDN BUFFER CHA
To save power, the device can be put in complete power-down by using the GLOBAL PDN register bit. However,
when JESD is required to remain active when putting the device in power-down, the ADC and analog buffer can
be powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN
MASK register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 6
shows the power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF
CHx register bits.
Table 6. Power Consumption in Different Power-Down Settings
REGISTER BIT
COMMENT
IAVDD3V
(mA)
IAVDD
(mA)
IDVDD
(mA)
IIOVDD
(mA)
TOTAL
POWER
(W)
Default
After reset, with a full-scale input signal to both
channels
247
260
137
382
1.94
GBL PDN = 1
The device is in a complete power-down state
3
6
23
192
0.28
GBL PDN = 0,
PDN ADC CHx = 1
(x = A or B)
The ADC of one channel is powered down
206
166
97
367
1.54
GBL PDN = 0,
PDN BUFF CHx = 1
(x = A or B)
The input buffer of one channel is powered down
195
258
137
381
1.78
GBL PDN = 0,
PDN ADC CHx = 1,
PDN BUFF CHx = 1
(x = A or B)
The ADC and input buffer of one channel are
powered down
152
166
97
363
1.37
GBL PDN = 0,
PDN ADC CHx = 1,
PDN BUFF CHx = 1
(x = A and B)
The ADC and input buffer of both channels are
powered down
55
70
56
356
0.81
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8.4 Device Functional Modes
8.4.1 Device Configuration
The ADS54J42 can be configured by using a serial programming interface, as described in the Serial Interface
section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down mode.
The ADS54J42 supports a 24-bit (16-bit address, 8-bit data) SPI operation and uses paging (see the Register
Maps section) to access all register bits.
8.4.1.1 Serial Interface
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins, as shown in Figure 69. SPI
bits in Figure 69 are explained in Table 7. Serially shifting bits into the device is enabled when SEN is low. Serial
data on SDIN are latched at every SCLK rising edge when SEN is active (low). The interface can function with
SCLK frequencies from 2 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty
cycle.
Register Address[11:0]
SDIN
R/W
M
P
CH
A11
A10
A9
A8
A7
A6
A5
A4
Register Data[7:0]
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
tDH
tSCLK
tDSU
SCLK
tSLOADS
tSLOADH
SEN
RESET
Figure 69. SPI Timing Diagram
Table 7. SPI Timing Diagram Legend
SPI BITS
DESCRIPTION
BIT SETTINGS
Read/write bit
0 = SPI write
1 = SPI read back
M
SPI bank access
0 = Analog SPI bank (master and ADC pages)
1 = JESD SPI bank (main digital, JESD analog, and
JESD digital pages)
P
JESD page selection bit
0 = Page access
1 = Register access
SPI access for a specific channel of the JESD SPI
bank
0 = Channel A
1 = Channel B
By default, both channels are being addressed.
A[11:0]
SPI address bits
—
D[7:0]
SPI data bits
—
R/W
CH
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Table 8 shows the timing requirements for the serial interface signals in Figure 69.
Table 8. SPI Timing Requirements
MIN
TYP
MAX
UNIT
2
MHz
fSCLK
SCLK frequency (equal to 1 / tSCLK)
> dc
tSLOADS
SEN to SCLK setup time
100
ns
tSLOADH
SCLK to SEN hold time
100
ns
tDSU
SDIN setup time
100
ns
tDH
SDIN hold time
100
ns
8.4.1.2 Serial Register Write: Analog Bank
The analog SPI bank contains two pages (the master and ADC pages). The internal register of the ADS54J42
analog SPI bank can be programmed by:
1. Driving the SEN pin low.
2. Initiating a serial interface cycle specifying the page address of the register whose content must be written.
– Master page: write address 0011h with 80h.
– ADC page: write address 0011h with 0Fh.
3. Writing the register content as shown in Figure 70. When a page is selected, multiple writes into the same
page can be done.
SDIN
0
0
0
0
R/W
M
P
CH
Register Address[11:0]
A11
A10
A9
A8
A7
A6
A5
A4
Register Data[7:0]
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
RESET
Figure 70. Serial Register Write Timing Diagram
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8.4.1.3 Serial Register Readout: Analog Bank
The content from one of the two analog banks can be read out by:
1. Driving the SEN pin low.
2. Selecting the page address of the register whose content must be read.
– Master page: write address 0011h with 80h.
– ADC page: write address 0011h with 0Fh.
3. Setting the R/W bit to 1 and writing the address to be read back.
4. Reading back the register content on the SDOUT pin, as shown in Figure 71. When a page is selected,
multiple read backs from the same page can be done.
SDIN
1
0
0
0
R/W
M
P
CH
Register Address[11:0]
A11
A10
A9
A8
A7
A6
A5
A4
Register Data[7:0] = XX
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
RESET
SDOUT
SDOUT[7:0]
Figure 71. Serial Register Read Timing Diagram
8.4.1.4 JESD Bank SPI Page Selection
The JESD SPI bank contains four pages (main digital, JESD digital, and JESD analog pages). The individual
pages can be selected by:
1. Driving the SEN pin low.
2. Setting the M bit to 1 and specifying the page with two register writes. Note that the P bit must be set to 0, as
shown in Figure 72.
– Write address 4003h with 00h (LSB byte of the page address).
– Write address 4004h with the MSB byte of the page address.
– For the main digital page: write address 4004h with 68h.
– For the JESD digital page: write address 4004h with 69h.
– For the JESD analog page: write address 4004h with 6Ah.
SDIN
0
1
0
0
R/W
M
P
CH
Register Address[11:0]
A11
A10
A9
A8
A7
A6
A5
A4
Register Data[7:0]
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
RESET
Figure 72. SPI Page Selection
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8.4.1.5 Serial Register Write: JESD Bank
The ADS54J42 is a dual-channel device and the JESD204B portion is configured individually for each channel by
using the CH bit. Note that the P bit must be set to 1 for register writes.
1. Drive the SEN pin low.
2. Select the JESD bank page. Note that the M bit = 1 and the P bit = 0.
– Write address 4003h with 00h.
– Write address 4005h with 01h to enable separate control for both channels.
– For the main digital page: write address 4004h with 68h.
– For the JESD digital page: write address 4004h with 69h.
– For the JESD analog page: write address 4004h with 6Ah.
3. Set the M and P bits to 1, select channel A (CH = 0) or channel B (CH = 1), and write the register content as
shown in Figure 73. When a page is selected, multiple writes into the same page can be done.
SDIN
0
1
1
0
R/W
M
P
CH
Register Address[11:0]
A11
A10
A9
A8
A7
A6
A5
A4
Register Data[7:0]
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
RESET
Figure 73. JESD Serial Register Write Timing Diagram
8.4.1.5.1 Individual Channel Programming
By default, register writes are applied to both channels. To enable individual channel writes, write address 4005h
with 01h (default is 00h).
8.4.1.6 Serial Register Readout: JESD Bank
The content from one of the pages of the JESD bank can be read out by:
1. Driving the SEN pin low.
2. Selecting the JESD bank page. Note that the M bit = 1 and the P bit = 0.
– Write address 4003h with 00h.
– Write address 4005h with 01h to enable separate control for both channels.
– For the main digital page: write address 4004h with 68h.
– For the JESD digital page: write address 4004h with 69h.
– For the JESD analog page: write address 4004h with 6Ah.
3. Setting the R/W, M, and P bits to 1, selecting channel A or channel B, and writing the address to be read
back.
4. Reading back the register content on the SDOUT pin; see Figure 74. When a page is selected, multiple read
backs from the same page can be done.
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1
1
1
0
R/W
M
P
CH
Register Address[11:0]
A11
A10
A9
A8
A7
A6
A5
A4
Register Data[7:0] = XX
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
RESET
SDOUT
SDOUT[7:0]
Figure 74. JESD Serial Register Read Timing Diagram
8.4.2 JESD204B Interface
The ADS54J42 supports device subclass 1 with a maximum output data rate of 6.25 Gbps for each serial
transmitter.
An external SYSREF signal is used to align all internal clock phases and the local multi-frame clock to a specific
sampling clock edge, allowing synchronization of multiple devices in a system and minimizing timing and
alignment uncertainty. The SYNC input is used to control the JESD204B SERDES blocks.
Depending on the ADC output data rate, the JESD204B output interface can be operated with either two or four
lanes per single ADC, as shown in Figure 75. The JESD204B setup and configuration of the frame assembly
parameters is controlled via the SPI interface.
SYSREF
SYNC
INA
JESD204B
JESD204B
DA[3:0]
INB
JESD204B
JESD204B
DB[3:0]
Sample Clock
Figure 75. ADS54J42 Block Diagram
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The JESD204B transmitter block shown in Figure 76 consists of the transport layer, the data scrambler, and the
link layer. The transport layer maps the ADC output data into the selected JESD204B frame data format. The link
layer performs the 8b, 10b data encoding as well as the synchronization and initial lane alignment using the
SYNC input signal. Optionally, data from the transport layer can be scrambled.
JESD204B Block
Transport Layer
Link Layer
8b, 10b
Encoding
Frame Data
Mapping
Scrambler
1 + x14 + x15
D[3:0]
Comma Characters,
Initial Lane Alignment
SYNC
Figure 76. JESD204B Transmitter Block
8.4.2.1 JESD204B Initial Lane Alignment (ILA)
The initial lane alignment process is started when the receiving device de-asserts the SYNC signal, as shown in
Figure 77. When a logic low is detected on the SYNC input pin, the ADS54J42 starts transmitting comma (K28.5)
characters to establish a code group synchronization.
When synchronization is complete, the receiving device asserts the SYNC signal and the ADS54J42 starts the
initial lane alignment sequence with the next local multi-frame clock boundary. The ADS54J42 transmits four
multi-frames, each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame
start and end symbols and the second multi-frame also contains the JESD204 link configuration data.
SYSREF
LMFC Clock
LMFC Boundary
Multi
Frame
SYNC
Transmit Data
xxx
K28.5
Code Group
Synchronization
K28.5
ILA
Initial Lane
Alignment
ILA
DATA
DATA
Data Transmission
Figure 77. Lane Alignment Sequence
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8.4.2.2 JESD204B Test Patterns
There are three different test patterns available in the transport layer of the JESD204B interface. The ADS54J42
supports a clock output, encoded, and a PRBS (215 – 1) pattern. These test patterns can be enabled via an SPI
register write and are located in the JESD digital page of the JESD bank.
8.4.2.3 JESD204B Frame
The JESD204B standard defines the following parameters:
• L is the number of lanes per link.
• M is the number of converters per device.
• F is the number of octets per frame clock period, per lane.
• S is the number of samples per frame per converter.
8.4.2.4 JESD204B Frame
Table 9 lists the available JESD204B formats and valid ranges for the ADS54J42 when the decimation filter is
not used. The ranges are limited by the SERDES lane rate and the maximum ADC sample frequency.
NOTE
The 16-bit data going to the JESD 8b, 10b encoder is formed by padding two 0s as LSBs
into the 14-bit ADC data.
Table 9. Default Interface Rates
MINIMUM RATES
MAXIMUM RATES
L
M
F
S
DECIMATION
SAMPLING
RATE (MSPS)
SERDES BIT
RATE (Gbps)
SAMPLING
RATE (MSPS)
SERDES BIT
RATE (Gbps)
4
2
1
1
Not used
250
2.5
625
6.25
4
2
4
4
Not used
250
2.5
625
6.25
8
2
2
4
Not used
500
2.5
625
3.125
NOTE
In the LMFS = 8224 row of Table 9, the sample order in lane DA2 and DA3 are swapped.
The detailed frame assembly is shown in Table 10.
Table 10. Default Frame Assembly
PIN
LMFS = 4211
LMFS = 4244
LMFS = 8224
DA0
A3[15:8]
A3[7:0]
DA1
A0[7:0]
A2[15:8]
A2[7:0]
A3[15:8]
A3[7:0]
A2[15:8]
A2[7:0]
DA2
A0[15:8]
A0[15:8]
A0[7:0]
A1[15:8]
A1[7:0]
A0[15:8]
A0[7:0]
DA3
A1[15:8]
A1[7:0]
DB0
B3[15:8]
B3[7:0]
DB1
B0[7:0]
B2[15:8]
B2[7:0]
B3[15:8]
B3[7:0]
B2[15:8]
B2[7:0]
DB2
B0[15:8]
B0[15:8]
B0[7:0]
B1[15:8]
B1[7:0]
B0[15:8]
B0[7:0]
B1[15:8]
B1[7:0]
DB3
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8.4.2.5 JESD204B Frame Assembly with Decimation
Table 11 lists the available JESD204B formats and valid ranges for the ADS54J42 when enabling the decimation
filter. The ranges are limited by the SERDES lane rate (2.5 Gbps to 6.25 Gbps) and the ADC sample frequency
(300 MSPS to 625 MSPS).
Table 11. Interface Rates with Decimation Filter
MINIMUM RATES
DEVICE
CLOCK
FREQUENCY
(MSPS)
OUTPUT
SAMPLE
RATE (MSPS)
MAXIMUM RATES
SERDES BIT
RATE (Gbps)
DEVICE
CLOCK
FREQUENCY
(MSPS)
OUTPUT
SAMPLE
RATE (MSPS)
SERDES BIT
RATE (Gbps)
L
M
F
S
DECIMATION
4
4
2
1
4X (IQ)
500
125
2.5
625
156.25
3.125
4
2
2
2
2X
500
250
2.5
625
312.5
3.125
2
2
4
2
2X
300
150
3
625
312.5
6.25
2
2
2
1
4X
500
125
2.5
625
156.25
3.125
2
4
4
1
4X (IQ)
300
75
3
625
156.25
6.25
1
2
4
1
4X
300
75
3
625
156.25
6.25
Table 12 lists the detailed frame assembly with different decimation options.
Table 12. Frame Assembly with Decimation Filter
PIN
LMFS = 4222, 2X
DECIMATION
DA0
A1
[15:8]
A1
[7:0]
DA1
A0
[15:8]
A0
[7:0]
DB0
B1
[15:8]
B1
[7:0]
DB1
B0
[15:8]
B0
[7:0]
LMFS = 2242, 2X
DECIMATION
A0
[15:8]
A0
[7:0]
A1
[15:8]
LMFS = 2221, 4X
DECIMATION
A1
[7:0]
A0
[15:8]
A0
[7:0]
LMFS = 2441, 4X
DECIMATION (IQ)
AI0
[15:8]
AI0
[7:0]
AQ0
[15:8]
AQ0
[7:0]
LMFS = 4421, 4X
DECIMATION (IQ)
AQ0
[15:8]
AQ0
[7:0]
AI0
[15:8]
AI0
[7:0]
BQ0
[15:8]
BQ0
[7:0]
BI0
[15:8]
BI0
[7:0]
LMFS = 1241, 4X
DECIMATION
A0
[15:8]
A0
[7:0]
B0
[15:8]
B0
[7:0]
DA2
DA3
B0
[15:8]
B0
[7:0]
B1
[15:8]
B1
[7:0]
B0
[15:8]
B0
[7:0]
BI0
[15:8]
BI0
[7:0]
BQ0
[15:8]
BQ0
[7:0]
DB2
DB3
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Appropriate register bits must be programmed to enable different options when the decimation filter is enabled. Table 13 summarizes all the decimation
filter options available in the DDC block, the corresponding JESD link parameters (L, M, F, and S), and the register bits required to be programmed for
each option.
Table 13. Program Summary of DDC Modes and JESD Link Configuration (1) (2)
LMFS OPTIONS
DDC MODES PROGRAMMING
DEC MODE EN,
DECFIL EN (3)
JESD LINK (LMFS) PROGRAMMING
L
M
F
S
DECIMATION
OPTIONS
4
2
1
1
No decimation
00
00
000
100
10
0
00h
00h
0
0
4
2
4
4
No decimation
00
00
000
010
10
0
00h
00h
0
0
00
00
000
001
00
0
00h
00h
0
0
DECFIL MODE[3:0]
(4)
JESD FILTER
(5)
JESD MODE
(6)
JESD PLL
MODE (7)
LANE SHARE (8)
DA_BUS_
REORDER (9)
DB_BUS_
REORDER (10)
BUS_REORDER
EN1 (11)
BUS_REORDER
EN2 (12)
8
2
2
4
No decimation
(Default after
reset)
4
4
2
1
4X (IQ)
11
0011 (LPF with fS / 4 mixer)
111
001
00
0
0Ah
0Ah
1
1
4
2
2
2
2X
11
0010 (LPF) or 0110 (HPF)
110
001
00
0
0Ah
0Ah
1
1
2
2
4
2
2X
11
0010 (LPF) or 0110 (HPF)
110
010
10
0
0Ah
0Ah
1
1
100
001
00
0
0Ah
0Ah
1
1
2
2
2
1
4X
11
0000, 0100, 1000, or 1100
(all BPFs with different
center frequencies).
2
4
4
1
4X (IQ)
11
0011 (LPF with an fS / 4
mixer)
111
010
10
0
0Ah
0Ah
1
1
1
2
4
1
4X
11
0000, 0100, 1000, or 1100
(all BPFs with different
center frequencies)
100
010
10
1
0Ah
0Ah
1
1
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
Keeping the same LMFS settings for both channels is recommended.
The PULSE RESET register bit must be pulsed after the registers in the main digital page are programmed.
The DEC MODE EN and DECFIL EN register bits are located in the main digital page, register 04Dh (bit 3) and register 041h (bit 4).
The DECFIL MODE[3:0] register bits are located in the main digital page, register 041h (bits 5 and 2-0).
The JESD FILTER register bits are located in the JESD digital page, register 001h (bits 5-3).
The JESD MODE register bits are located in the JESD digital page, register 001h (bits 2:0).
The JESD PLL MODE register bits are located in the JESD analog page, register 016h (bits 1-0).
The LANE SHARE register bit is located in the JESD digital page, register 016h (bit 4).
The DA_BUS_REORDER register bits are located in the JESD digital page, register 031h (bits 7-0).
The DB_BUS_REORDER register bits are located in the JESD digital page, register 032h (bits 7-0).
The BUS_REORDER EN1 register bit is located in the main digital page, register 052h (bit 7).
The BUS_REORDER EN2 register bit is located in the main digital page, register 072h (bit 3).
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8.4.2.5.1 JESD Transmitter Interface
Each of the 6.25-Gbps SERDES JESD transmitter outputs requires ac-coupling between the transmitter and
receiver. The differential pair must be terminated with 100-Ω resistors as close to the receiving device as
possible to avoid unwanted reflections and signal degradation, as shown in Figure 78.
0.1 PF
DA[3:0]P,
DB[3:0]P
R t = ZO
Transmission Line, Zo
VCM
Receiver
R t = ZO
DA[3:0]M,
DB[3:0]M
0.1 PF
Figure 78. Output Connection to Receiver
8.4.2.5.2 Eye Diagrams
Figure 79 and Figure 80 show the serial output eye diagrams of the ADS54J42 at 6.25 Gbps and 2.5 Gbps
(respectively) with default output voltage swings against the JESD204B mask.
Figure 79. Eye Diagram at 6.25-Gbps Bit Rate with
Default Output Swing
42
Figure 80. Eye Diagram at 2.5-Gbps Bit Rate with
Default Output Swing
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8.5 Register Maps
Figure 81 shows a conceptual diagram of the serial registers.
Initiate an SPI Cycle
R/W, M, P, CH, Bits Decoder
M=0
M=1
Analog Bank
JESD Bank
General Register
(Address 00h,
Keep M = 0, P = 0)
Analog Bank Page Selection
(Address 011h, Keep M = 0, P = 0)
Value 80h
Addr 20h
Keep
M = 0, P = 0
Addr 59h
Value 6800h
Value 0Fh
Addr 0h
Addr 5Fh
Master Page
(PDN, OVR,
DC Coupling)
JESD Bank Page Selection
(Address 003h and Address 004h,
Keep M = 1, P = 0)
General Register
(Address 005h,
Keep M = 1, P = 0)
Keep
M = 0, P = 0
Addr F7h
Value 6A00h
Value 6900h
Addr 0h
Main
Digital Page
ADC Page
(Fast OVR)
Unused Registers
(Address 01h, Address 02h.
Keep M = 1, P = 0)
Addr 12h
(Nyquist Zone,
Gain,
OVR, Filter)
(JESD
Configuration)
JESD
Analog Page
(PLL Configuration,
Output Swing,
Pre-Emphasis)
Keep M = 1,
P=1
Keep M = 1,
P=1
Keep M = 1,
P=1
JESD
Digital Page
Addr 32h
Addr 1Bh
Figure 81. Serial Interface Registers
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8.5.1 Detailed Register Info
The ADS54J42 contains two main SPI banks. The analog SPI bank provides access to the ADC analog blocks
and the digital SPI bank controls the interleaving engine and anything related to the JESD204B serial interface.
The analog SPI bank is divided into two pages (master and ADC) and the digital SPI bank is divided into three
pages (main digital, JESD digital, and JESD analog). Table 14 lists a register map for the ADS54J42.
Table 14. Register Map
REGISTER
ADDRESS
REGISTER DATA
A[11:0] (Hex)
7
6
5
RESET
0
0
4
3
2
1
0
0
0
0
0
RESET
0
0
DISABLE
BROADCAST
0
0
GENERAL REGISTERS
0
3
JESD BANK PAGE SEL[7:0]
4
JESD BANK PAGE SEL[15:8]
5
0
0
0
11
0
0
ANALOG BANK PAGE SEL
MASTER PAGE (80h)
20
21
PDN ADC CHA
PDN BUFFER CHB
23
24
PDN ADC CHB
PDN BUFFER CHA
0
0
PDN ADC CHA
PDN BUFFER CHB
PDN ADC CHB
PDN BUFFER CHA
PDN MASK
SEL
0
0
0
0
0
0
0
0
0
0
26
GLOBAL PDN
OVERRIDE
PDN PIN
39
HIGH FREQ 1
HIGH FREQ 0
0
0
0
0
0
3A
0
HIGH FREQ 2
0
0
0
0
0
0
4F
0
0
0
0
0
0
0
EN INPUT DC
COUPLING
53
0
MASK SYSREF
0
0
0
0
EN SYSREF
DC COUPLING
0
55
0
0
0
PDN MASK
0
0
0
0
56
0
0
0
0
0
HIGH FREQ 3
0
0
0
ALWAYS
WRITE 1
0
0
0
0
0
0
0
PULSE RESET
59
FOVR CHB
ADC PAGE (0Fh)
5F
FOVR THRESHOLD PROG
MAIN DIGITAL PAGE (6800h)
0
44
0
0
0
0
0
DECFIL EN
0
41
0
0
DECFIL
MODE[3]
42
0
0
0
0
0
43
0
0
0
0
0
44
0
DECFIL MODE[2:0]
NYQUIST ZONE
0
0
FORMAT SEL
DIGITAL GAIN
4B
0
0
FORMAT EN
0
0
0
0
0
4D
0
0
0
0
DEC MODE EN
0
0
0
4E
CTRL
NYQUIST
0
0
0
0
0
0
0
52
BUS_
REORDER
EN1
0
0
0
0
0
0
DIG GAIN EN
72
0
0
0
0
BUS_
REORDER
EN2
0
0
0
0
AB
0
0
0
0
0
0
AD
0
0
0
0
0
0
F7
0
0
0
0
0
0
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LSB SEL EN
LSB SELECT
0
DIG RESET
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Table 14. Register Map (continued)
REGISTER
ADDRESS
A[11:0] (Hex)
REGISTER DATA
7
6
5
4
3
2
1
0
0
TESTMODE
EN
FLIP ADC
DATA
LANE ALIGN
FRAME ALIGN
TX LINK DIS
JESD DIGITAL PAGE (6900h)
0
CTRL K
0
1
SYNC REG
SYNC REG EN
JESD FILTER
LINK LAYER TESTMODE
LINK LAYER
RPAT
2
3
FORCE LMFC
COUNT
5
SCRAMBLE
EN
0
0
6
0
0
0
7
0
0
16
1
0
JESD MODE
LMFC MASK
RESET
0
LMFC COUNT INIT
0
0
RELEASE ILANE SEQ
0
0
0
0
0
SUBCLASS
0
LANE SHARE
0
0
0
0
0
0
0
0
0
FRAMES PER MULTI FRAME (K)
31
DA_BUS_REORDER[7:0]
32
DB_BUS_REORDER[7:0]
JESD ANALOG PAGE (6A00h)
12
SEL EMP LANE 1
0
0
13
SEL EMP LANE 0
0
0
14
SEL EMP LANE 2
0
0
15
SEL EMP LANE 3
0
0
16
0
0
0
0
0
0
17
0
PLL RESET
0
0
0
0
0
0
1A
0
0
0
0
0
0
FOVR CHA
0
0
FOVR CHA EN
0
0
0
1B
JESD SWING
JESD PLL MODE
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8.5.2 Example Register Writes
This section provides three different example register writes. Table 15 describes a global power-down register
write, Table 16 describes the register writes when the default lane setting (eight active lanes per device) is
changed to four active lanes (LMFS = 4211), and Table 17 describes the register writes for 2X decimation with
four active lanes (LMFS = 4222).
Table 15. Global Power Down
ADDRESS (Hex)
DATA (Hex)
0-011h
80h
Set the master page
COMMENT
0-026h
C0h
Set the global power-down
Table 16. Two Lanes per Channel Mode (LMFS = 4211)
ADDRESS (Hex)
DATA (Hex)
4-004h
69h
Select the JESD digital page
COMMENT
4-003h
00h
Select the JESD digital page
6-001h
02h
Select the digital to 40X mode
4-004h
6Ah
Select the JESD analog page
6-016h
02h
Set the SERDES PLL to 40X mode
Table 17. 2X Decimation (LPF for Both Channels) with Four Active Lanes (LMFS = 4222)
ADDRESS (Hex)
DATA (Hex)
4-004h
68h
Select the main digital page (6800h)
4-003h
00h
Select the main digital page (6800h)
6-041h
12h
Set decimate-by-2 (low-pass filter)
6-04Dh
08h
Enable decimation filter control
6-072h
08h
BUS_REORDER EN2
6-052h
80h
BUS_REORDER EN1
6-000h
01h
6-000h
00h
4-004h
69h
Select the JESD digital page (6900h)
4-003h
00h
Select the JESD digital page (6900h)
6-031h
0Ah
Output bus reorder for channel A
6-032h
0Ah
Output bus reorder for channel B
6-001h
31h
Program the JESD MODE and JESD FILTER register bits for LMFS = 4222.
46
COMMENT
Pulse the PULSE RESET bit (so that register writes to the main digital page go into effect).
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8.5.3 Register Descriptions
8.5.3.1 General Registers
8.5.3.1.1 Register 0h (address = 0h)
Figure 82. Register 0h
7
RESET
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
RESET
W-0h
LEGEND: W = Write only; -n = value after reset
Table 18. Register 0h Field Descriptions
Bit
7
6-1
0
Field
Type
Reset
Description
RESET
W
0h
0 = Normal operation
1 = Internal software reset, clears back to 0
0
W
0h
Must write 0
RESET
W
0h
0 = Normal operation
1 = Internal software reset, clears back to 0
8.5.3.1.2 Register 3h (address = 3h)
Figure 83. Register 3h
7
6
5
4
3
JESD BANK PAGE SEL[7:0]
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 19. Register 3h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
JESD BANK PAGE SEL[7:0]
R/W
0h
Program these bits to access the desired page in the JESD bank.
6800h = Main digital page selected
6900h = JESD digital page selected
6A00h = JESD analog page selected
8.5.3.1.3 Register 4h (address = 4h)
Figure 84. Register 4h
7
6
5
4
3
JESD BANK PAGE SEL[15:8]
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 20. Register 4h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
JESD BANK PAGE SEL[15:8]
R/W
0h
Program these bits to access the desired page in the JESD bank.
6800h = Main digital page selected
6900h = JESD digital page selected
6A00h = JESD analog page selected
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8.5.3.1.4 Register 5h (address = 5h)
Figure 85. Register 5h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
DISABLE BROADCAST
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 21. Register 5h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
DISABLE BROADCAST
R/W
0h
0 = Normal operation; channel A and B are programmed as a pair
1 = Channel A and B can be individually programmed based on the
CH bit
0
8.5.3.1.5 Register 11h (address = 11h)
Figure 86. Register 11h
7
6
5
4
3
ANALOG PAGE SELECTION
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 22. Register 11h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
ANALOG BANK PAGE SEL
R/W
0h
Program these bits to access the desired page in the analog bank.
Master page = 80h
ADC page = 0Fh
8.5.3.2 Master Page (080h) Registers
8.5.3.2.1 Register 20h (address = 20h), Master Page (080h)
Figure 87. Register 20h
7
6
5
4
3
PDN ADC CHA
R/W-0h
2
1
0
PDN ADC CHB
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 23. Registers 20h Field Descriptions
48
Bit
Field
Type
Reset
Description
7-4
PDN ADC CHA
R/W
0h
3-0
PDN ADC CHB
R/W
0h
There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. The power-down mask 1
or mask 2 are selected via register bit 5 in address 26h.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
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8.5.3.2.2 Register 21h (address = 21h), Master Page (080h)
Figure 88. Register 21h
7
6
PDN BUFFER CHB
R/W-0h
5
4
PDN BUFFER CHA
R/W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 24. Register 21h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
PDN BUFFER CHB
R/W
0h
5-4
PDN BUFFER CHA
R/W
0h
There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. The power-down mask 1
or mask 2 are selected via register address 26h, bit 5.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
3-0
0
W
0h
Must write 0.
8.5.3.2.3 Register 23h (address = 23h), Master Page (080h)
Figure 89. Register 23h
7
6
5
4
3
2
PDN ADC CHA
R/W-0h
1
0
PDN ADC CHB
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 25. Register 23h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
PDN ADC CHA
R/W
0h
3-0
PDN ADC CHB
R/W
0h
There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. The power-down mask 1
or mask 2 are selected via register address 26h, bit 5.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
8.5.3.2.4 Register 24h (address = 24h), Master Page (080h)
Figure 90. Register 24h
7
6
PDN BUFFER CHB
R/W-0h
5
4
PDN BUFFER CHA
R/W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 26. Register 24h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
PDN BUFFER CHB
R/W
0h
5-4
PDN BUFFER CHA
R/W
0h
There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. The power-down mask 1
or mask 2 are selected via register address 26h, bit 5.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
3-0
0
W
0h
Must write 0.
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8.5.3.2.5 Register 26h (address = 26h), Master Page (080h)
Figure 91. Register 26h
7
GLOBAL PDN
R/W-0h
6
OVERRIDE
PDN PIN
R/W-0h
5
PDN MASK
SEL
R/W-0h
4
3
2
1
0
0
0
0
0
0
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 27. Register 26h Field Descriptions
Bit
Field
Type
Reset
Description
7
GLOBAL PDN
R/W
0h
Bit 6 (OVERRIDE PDN PIN) must be set before this bit can be
programmed.
0 = Normal operation
1 = Global power-down via the SPI
6
OVERRIDE PDN PIN
R/W
0h
This bit ignores the power-down pin control.
0 = Normal operation
1 = Ignores inputs on the power-down pin
5
PDN MASK SEL
R/W
0h
This bit selects power-down mask 1 or mask 2.
0 = Power-down mask 1
1 = Power-down mask 2
0
W
0h
Must write 0
4-0
8.5.3.2.6 Register 39h (address = 39h), Master Page (080h)
Figure 92. Register 39h
7
HIGH FREQ 1
R/W-0h
6
HIGH FREQ 0
R/W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 28. Register 39h Field Descriptions
Bit
Field
Type
Reset
Description
7
HIGH FREQ 1
R/W
0h
6
HIGH FREQ 0
R/W
0h
Set these bits (and the HIGH FREQ[3:2] bits) high when the
input frequency > 400 MHz.
0
W
0h
5-0
Must write 0
8.5.3.2.7 Register 3Ah (address = 3Ah), Master Page (080h)
Figure 93. Register 3Ah
7
0
W-0h
6
HIGH FREQ 2
R/W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 29. Register 3Ah Field Descriptions
Bit
Field
Type
Reset
Description
7
0
W
0h
Must write 0
6
HIGH FREQ 2
R/W
0h
Set this bit (and the HIGH FREQ 3 and HIGH FREQ[1:0] bits)
high when the input frequency > 400 MHz.
0
W
0h
Must write 0
5-0
50
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8.5.3.2.8 Register 4Fh (address = 4Fh), Master Page (080h)
Figure 94. Register 4Fh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
EN INPUT DC COUPLING
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 30. Register 4Fh Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
EN INPUT DC COUPLING
R/W
0h
This bit enables dc-coupling between the analog inputs and the
driver by changing the internal biasing resistor between the
analog inputs and VCM from 600 Ω to 5 kΩ.
0 = The dc-coupling support is disabled
1 = The dc-coupling support is enabled
0
8.5.3.2.9 Register 53h (address = 53h), Master Page (080h)
Figure 95. Register 53h
7
6
MASK
SYSREF
R/W-0h
0
W-0h
5
4
3
2
0
0
0
0
W-0h
W-0h
W-0h
W-0h
1
EN SYSREF
DC COUPLING
R/W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 31. Register 53h Field Descriptions
Bit
Field
Type
Reset
Description
7
0
W
0h
Must write 0
6
MASK SYSREF
R/W
0h
0 = Normal operation
1 = Ignores the SYSREF input
5-2
0
W
0h
Must write 0
1
EN SYSREF DC COUPLING
R/W
0h
This bit enables a higher common-mode voltage input on the
SYSREF signal (up to 1.6 V).
0 = Normal operation
1 = Enables a higher SYSREF common-mode voltage support
0
0
W
0h
Must write 0
8.5.3.2.10 Register 55h (address = 55h), Master Page (080h)
Figure 96. Register 55h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
PDN MASK
R/W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 32. Register 55h Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
W
0h
Must write 0
PDN MASK
R/W
0h
This bit enables power-down via a register bit.
0 = Normal operation
1 = Power-down is enabled by powering down the internal
blocks as specified in the selected power-down mask
0
W
0h
Must write 0
4
3-0
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8.5.3.2.11 Register 56h (address = 56h), Master Page (080h)
Figure 97. Register 56h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
HIGH FREQ 3
R/W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 33. Register 56h Field Descriptions
Bit
Field
Type
Reset
Description
7-3
0
W
0h
Must write 0
HIGH FREQ 3
R/W
0h
Set this bit (and the HIGH FREQ[2:0] bits) high when the input
frequency > 400 MHz.
0
W
0h
Must write 0
2
1-0
8.5.3.2.12 Register 59h (address = 59h), Master Page (080h)
Figure 98. Register 59h
7
FOVR CHB
W-0h
6
0
W-0h
5
ALWAYS WRITE 1
R/W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 34. Register 59h Field Descriptions
Bit
Field
Type
Reset
Description
7
FOVR CHB
W
0h
This bit outputs the FOVR signal for channel B on the SDOUT pin.
0 = Normal operation
1 = The FOVR signal is available on the SDOUT pin
6
0
W
0h
Must write 0
5
ALWAYS WRITE 1
R/W
0h
Must write 1
0
W
0h
Must write 0
4-0
8.5.3.3 ADC Page (0Fh) Register
8.5.3.3.1 Register 5F (addresses = 5F), ADC Page (0Fh)
Figure 99. Register 5F
7
6
5
4
3
FOVR THRESHOLD PROG
R/W-E3h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 35. Register 5F Field Descriptions
52
Bit
Field
Type
Reset
Description
7-0
FOVR THRESHOLD PROG
R/W
E3h
Program the fast OVR thresholds together for channel A and B,
as described in the Overrange Indication section.
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8.5.3.4 Main Digital Page (6800h) Registers
8.5.3.4.1 Register 0h (address = 0h), Main Digital Page (6800h)
Figure 100. Register 0h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
PULSE RESET
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 36. Register 0h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
PULSE RESET
R/W
0h
This bit must be pulsed after power-up or after configuring
registers in the main digital page of the JESD bank. Any register
bits in the main digital page (6800h) take effect only after this bit
is pulsed; see the Start-Up Sequence section for the correct
sequence.
0 = Normal operation
0 → 1 → 0 = This bit is pulsed
0
8.5.3.4.2 Register 41h (address = 41h), Main Digital Page (6800h)
Figure 101. Register 41h
7
0
W-0h
6
0
W-0h
5
DECFIL MODE[3]
R/W-0h
4
DECFIL EN
R/W-0h
3
0
W-0h
2
1
DECFIL MODE[2:0]
R/W-0h
0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 37. Register 41h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
W
0h
Must write 0
5
DECFIL MODE[3]
R/W
0h
This bit selects the decimation filter mode. Table 38 lists the bit settings.
The decimation filter control (DEC MODE EN, register 4Dh, bit 3) and
decimation filter enable (DECFIL EN, register 41h, bit 4) must be enabled.
4
DECFIL EN
R/W
0h
This bit enables the digital decimation filter.
0 = Normal operation, full rate output
1 = Digital decimation enabled
3
0
W
0h
Must write 0
DECFIL MODE[2:0]
R/W
0h
These bits select the decimation filter mode. Table 38 lists the bit settings.
The decimation filter control (DEC MODE EN, register 4Dh, bit 3) and
decimation filter enable (DECFIL EN, register 41h, bit 4) must be enabled.
2-0
Table 38. DECFIL MODE Bit Settings
BITS (5, 2-0)
FILTER MODE
DECIMATION
0000
Band-pass filter centered on 3 × fS / 16
4X
0100
Band-pass filter centered on 5 × fS / 16
4X
1000
Band-pass filter centered on 1 × fS / 16
4X
1100
Band-pass filter centered on 7 × fS / 16
4X
0010
Low-pass filter
2X
0110
High-pass filter
0011
Low-pass filter with fS / 4 mixer
2X
4X (IQ)
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8.5.3.4.3 Register 42h (address = 42h), Main Digital Page (6800h)
Figure 102. Register 42h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
1
NYQUIST ZONE
R/W-0h
0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 39. Register 42h Field Descriptions
Bit
Field
Type
Reset
Description
7-3
0
W
0h
Must write 0
2-0
NYQUIST ZONE
R/W
0h
The Nyquist zone must be selected for proper interleaving
correction. Nyquist refers to the device clock / 2. For a 625MSPS device clock, the Nyquist frequency is 312.5 MHz. The
CTRL NYQUIST register bit (register 4Eh, bit 7) must also be
set.
000 = First Nyquist zone (0 MHz to 312.5 MHz)
001 = Second Nyquist zone (312.5 MHz to 625 MHz)
010 = Third Nyquist zone (625 MHz to 937.5 MHz)
All others = Not used
8.5.3.4.4 Register 43h (address = 43h), Main Digital Page (6800h)
Figure 103. Register 43h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
FORMAT SEL
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 40. Register 43h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
FORMAT SEL
R/W
0h
This bit changes the output format. Set the FORMAT EN bit to
enable control using this bit.
0 = Twos complement
1 = Offset binary
0
8.5.3.4.5 Register 44h (address = 44h), Main Digital Page (6800h)
Figure 104. Register 44h
7
0
R/W-0h
6
5
4
3
DIGITAL GAIN
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 41. Register 44h Field Descriptions
Bit
7
6-0
54
Field
Type
Reset
Description
0
R/W
0h
Must write 0
DIGITAL GAIN
R/W
0h
These bits set the digital gain setting. The DIG GAIN EN register
bit (register 52h, bit 0) must be enabled to use these bits.
Gain in dB = 20log (digital gain / 32).
7Fh = 127 equals a digital gain of 9.5 dB.
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8.5.3.4.6 Register 4Bh (address = 4Bh), Main Digital Page (6800h)
Figure 105. Register 4Bh
7
0
W-0h
6
0
W-0h
5
FORMAT EN
R/W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 42. Register 4Bh Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
W
0h
Must write 0
FORMAT EN
R/W
0h
This bit enables control for data format selection using the FORMAT
SEL register bit.
0 = Default, output is in twos complement format
1 = Output is in offset binary format after the FORMAT SEL bit is set
0
W
0h
Must write 0
5
4-0
8.5.3.4.7 Register 4Dh (address = 4Dh), Main Digital Page (6800h)
Figure 106. Register 4Dh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
DEC MOD EN
R/W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 43. Register 4Dh Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
DEC MOD EN
R/W
0h
This bit enables control of the decimation filter mode via the
DECFIL MODE[3:0] register bits.
0 = Default
1 = Decimation mode control is enabled
0
W
0h
Must write 0
3
2-0
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8.5.3.4.8 Register 4Eh (address = 4Eh), Main Digital Page (6800h)
Figure 107. Register 4Eh
7
CTRL NYQUIST
R/W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 44. Register 4Eh Field Descriptions
Bit
7
6-0
Field
Type
Reset
Description
CTRL NYQUIST
R/W
0h
This bit enables selecting the Nyquist zone using register 42h, bits 2-0.
0 = Selection disabled
1 = Selection enabled
0
W
0h
Must write 0
8.5.3.4.9 Register 52h (address = 52h), Main Digital Page (6800h)
Figure 108. Register 52h
7
BUS_REORDER EN1
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
DIG GAIN EN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 45. Register 52h Field Descriptions
Bit
7
6-1
0
Field
Type
Reset
Description
BUS_REORDER EN1
R/W
0h
Must write 1 in DDC mode only.
0
W
0h
Must write 0
DIG GAIN EN
R/W
0h
This bit enables selecting the digital gain for register 44h.
0 = Digital gain disabled
1 = Digital gain enabled
8.5.3.4.10 Register 72h (address = 72h), Main Digital Page (6800h)
Figure 109. Register 72h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
BUS_REORDER EN2
W-0h
2
0
W-0h
1
0
W-0h
0
0
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 46. Register 72h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
BUS_REORDER EN2
R/W
0h
Must write 1 in DDC mode only.
0
W
0h
Must write 0
3
2-0
56
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8.5.3.4.11 Register ABh (address = ABh), Main Digital Page (6800h)
Figure 110. Register ABh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
LSB SEL EN
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 47. Register ABh Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
LSB SEL EN
R/W
0h
This bit enables control for the LSB SELECT register bit.
0 = Default
1 = LSB of the 16-bit data (14-bit ADC data padded with two 0s
as the LSBs) can be programmed as fast OVR using the LSB
SELECT register bit.
0
8.5.3.4.12 Register ADh (address = ADh), Main Digital Page (6800h)
Figure 111. Register ADh
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
LSB SELECT
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 48. Register ADh Field Descriptions
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
1-0
LSB SELECT
R/W
0h
These bits enable the output of the FOVR flag instead of the output data
LSB. Ensure that the LSB SEL EN register bit is set to 1.
00 = Output is 16-bit data (14-bit ADC data padded with two 0s as the
LSBs)
11 = The LSB of the 16-bit output data is replaced by the FOVR
information for each channel
8.5.3.4.13 Register F7h (address = F7h), Main Digital Page (6800h)
Figure 112. Register F7h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
DIG RESET
W-0h
LEGEND: W = Write only; -n = value after reset
Table 49. Register F7h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
DIG RESET
W
0h
This bit is the self-clearing reset for the digital block and does
not include interleaving correction.
0 = Normal operation
1 = Digital reset
0
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8.5.3.5 JESD Digital Page (6900h) Registers
8.5.3.5.1 Register 0h (address = 0h), JESD Digital Page (6900h)
Figure 113. Register 0h
7
6
5
CTRL K
0
0
R/W-0h
W-0h
W-0h
4
TESTMODE
EN
R/W-0h
3
FLIP ADC
DATA
R/W-0h
2
1
0
LANE ALIGN
FRAME ALIGN
TX LINK DIS
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 50. Register 0h Field Descriptions
Bit
7
6-5
58
Field
Type
Reset
Description
CTRL K
R/W
0h
This bit is the enable bit for a number of frames per multi-frame.
0 = Default is five frames per multi-frame
1 = Frames per multi-frame can be set in register 06h
0
W
0h
Must write 0
4
TESTMODE EN
R/W
0h
This bit generates the long transport layer test pattern mode, as
per section 5.1.6.3 of the JESD204B specification.
0 = Test mode disabled
1 = Test mode enabled
3
FLIP ADC DATA
R/W
0h
0 = Normal operation
1 = Output data order is reversed: MSB to LSB.
2
LANE ALIGN
R/W
0h
This bit inserts the lane alignment character (K28.3) for the
receiver to align to the lane boundary, as per section 5.3.3.5 of
the JESD204B specification.
0 = Normal operation
1 = Inserts lane alignment characters
1
FRAME ALIGN
R/W
0h
This bit inserts the lane alignment character (K28.7) for the
receiver to align to the lane boundary, as per section 5.3.3.5 of
the JESD204B specification.
0 = Normal operation
1 = Inserts frame alignment characters
0
TX LINK DIS
R/W
0h
This bit disables sending the initial link alignment (ILA) sequence
when SYNC is de-asserted.
0 = Normal operation
1 = ILA disabled
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8.5.3.5.2 Register 1h (address = 1h), JESD Digital Page (6900h)
Figure 114. Register 1h
7
SYNC REG
R/W-0h
6
SYNC REG EN
R/W-0h
5
4
JESD FILTER
R/W-0h
3
2
1
JESD MODE
R/W-01h
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 51. Register 1h Field Descriptions
Bit
Field
Type
Reset
Description
7
SYNC REG
R/W
0h
This bit is the register control for the sync request.
0 = Normal operation
1 = ADC output data are replaced with K28.5 characters; the SYNC
REG EN register bit must also be set to 1
6
SYNC REG EN
R/W
0h
This bit enables register control for the sync request.
0 = Use the SYNC pin for sync requests
1 = Use the SYNC REG register bit for sync requests
5-3
JESD FILTER
R/W
0h
These bits and the JESD MODE bits set the correct LMFS
configuration for the JESD interface. The JESD FILTER setting
must match the configuration in the decimation filter page.
000 = Filter bypass mode
See Table 52 for valid combinations for register bits JESD FILTER
along with JESD MODE.
2-0
JESD MODE
R/W
01h
These bits select the number of serial JESD output lanes per ADC.
The JESD PLL MODE register bit located in the JESD analog page
must also be set accordingly.
001 = Default after reset(Eight active lanes)
See Table 52 for valid combinations for register bits JESD FILTER
along with JESD MODE.
Table 52. Valid Combinations for JESD FILTER and JESD MODE Bits
NUMBER OF ACTIVE LANES
PER DEVICE
REGISTER BIT JESD FILTER
REGISTER BIT JESD MODE
DECIMATION FACTOR
000
100
No decimation
Four lanes are active
000
010
No decimation
Four lanes are active
000
001
No decimation
(default after reset)
Eight lanes are active
111
001
4X (IQ)
Four lanes are active
110
001
2X
Four lanes are active
110
010
2X
Two lanes are active
100
001
4X
Two lanes are active
111
010
4X (IQ)
Two lanes are active
100
010
4X
One lane is active
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8.5.3.5.3 Register 2h (address = 2h), JESD Digital Page (6900h)
Figure 115. Register 2h
7
6
5
LINK LAYER TESTMODE
R/W-0h
4
LINK LAYER RPAT
R/W-0h
3
LMFC MASK RESET
R/W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 53. Register 2h Field Descriptions
Bit
Field
Type
Reset
Description
7-5
LINK LAYER TESTMODE
R/W
0h
These bits generate a pattern as per section 5.3.3.8.2 of the
JESD204B document.
000 = Normal ADC data
001 = D21.5 (high-frequency jitter pattern)
010 = K28.5 (mixed-frequency jitter pattern)
011 = Repeat initial lane alignment (generates a K28.5 character
and continuously repeats lane alignment sequences)
100 = 12-octet RPAT jitter pattern
All others = Not used
4
LINK LAYER RPAT
R/W
0h
This bit changes the running disparity in the modified RPAT pattern
test mode (only when the link layer test mode = 100).
0 = Normal operation
1 = Changes disparity
3
LMFC MASK RESET
R/W
0h
This bit masks the LMFC reset coming to the digital block.
0 = LMFC reset is not masked
1 = Ignore the LMFC reset request
0
W
0h
Must write 0
2-0
60
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8.5.3.5.4 Register 3h (address = 3h), JESD Digital Page (6900h)
Figure 116. Register 3h
7
FORCE LMFC COUNT
R/W-0h
6
5
4
LMFC COUNT INIT
R/W-0h
3
2
1
0
RELEASE ILANE SEQ
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 54. Register 3h Field Descriptions
Bit
Field
Type
Reset
Description
FORCE LMFC COUNT
R/W
0h
This bit forces the LMFC count.
0 = Normal operation
1 = Enables using a different starting value for the LMFC counter
6-2
MASK SYSREF
R/W
0h
When SYSREF transmits to the digital block, the LMFC count resets to
0 and K28.5 stops transmitting when the LMFC count reaches 31. The
initial value that the LMFC count resets to can be set using LMFC
COUNT INIT. In this manner, the receiver can be synchronized early
because the LANE ALIGNMENT SEQUENCE is received early. The
FORCE LMFC COUNT register bit must be enabled.
1-0
RELEASE ILANE SEQ
R/W
0h
These bits delay the generation of the lane alignment sequence by 0, 1,
2, or 3 multi-frames after the code group synchronization.
00 = 0
01 = 1
10 = 2
11 = 3
7
8.5.3.5.5 Register 5h (address = 5h), JESD Digital Page (6900h)
Figure 117. Register 5h
7
SCRAMBLE EN
R/W-Undefined
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 55. Register 5h Field Descriptions
Bit
7
6-0
Field
Type
Reset
Description
SCRAMBLE EN
R/W
Undefined
This bit is the scramble enable bit in the JESD204B interface.
0 = Scrambling disabled
1 = Scrambling enabled
0
W
0h
Must write 0
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8.5.3.5.6 Register 6h (address = 6h), JESD Digital Page (6900h)
Figure 118. Register 6h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
3
2
1
FRAMES PER MULTI FRAME (K)
R/W-8h
0
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 56. Register 6h Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
W
0h
Must write 0
4-0
FRAMES PER MULTI FRAME (K)
R/W
8h
These bits set the number of multi-frames.
Actual K is the value in hex + 1 (that is, 0Fh is K = 16).
8.5.3.5.7 Register 7h (address = 7h), JESD Digital Page (6900h)
Figure 119. Register 7h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
SUBCLASS
R/W-1h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 57. Register 7h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
SUBCLASS
R/W
1h
This bit sets the JESD204B subclass.
000 = Subclass 0 is backward compatible with JESD204A
001 = Subclass 1 deterministic latency using the SYSREF signal
0
W
0h
Must write 0
3
2-0
8.5.3.5.8 Register 16h (address = 16h), JESD Digital Page (6900h)
Figure 120. Register 16h
7
1
W-1h
6
0
W-0h
5
0
R/W-0h
4
LANE SHARE
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 58. Register 16h Field Descriptions
Bit
Field
Type
Reset
Description
7
1
W
1h
Must write 1
6-5
0
W
0h
Must write 0
LANE SHARE
R/W
0h
When using decimate-by-4, the data of both channels are output
over one lane (LMFS = 1241).
0 = Normal operation (each channel uses one lane)
1 = Lane sharing is enabled, both channels share one lane
(LMFS = 1241)
0
W
0h
Must write 0
4
3-0
62
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8.5.3.5.9 Register 31h (address = 31h), JESD Digital Page (6900h)
Figure 121. Register 31h
7
6
5
4
3
DA_BUS_REORDER[7:0]
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 59. Register 31h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DA_BUS_REORDER[7:0]
R/W
0h
Use these bits to program output connections between data
streams and output lanes in decimate-by-2 and decimate-by-4
mode. Table 13 lists the supported combinations of these bits.
8.5.3.5.10 Register 32h (address = 32h), JESD Digital Page (6900h)
Figure 122. Register 32h
7
6
5
4
3
DB_BUS_REORDER[7:0]
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; -n = value after reset
Table 60. Register 32h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DB_BUS_REORDER[7:0]
R/W
0h
Use these bits to program output connections between data
streams and output lanes in decimate-by-2 and decimate-by-4
mode. Table 13 lists the supported combinations of these bits.
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8.5.3.6 JESD Analog Page (6A00h) Registers
8.5.3.6.1 Registers 12h-5h (addresses = 12h-5h), JESD Analog Page (6A00h)
Figure 123. Register 12h
7
6
5
4
SEL EMP LANE 1
R/W-0h
3
2
1
0
W-0h
0
0
W-0h
2
1
0
W-0h
0
0
W-0h
2
1
0
W-0h
0
0
W-0h
2
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 124. Register 13h
7
6
5
4
SEL EMP LANE 0
R/W-0h
3
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 125. Register 14h
7
6
5
4
SEL EMP LANE 2
R/W-0h
3
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 126. Register 15h
7
6
5
4
SEL EMP LANE 3
R/W-0h
3
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 61. Registers 12h-15h Field Descriptions
64
Bit
Field
Type
Reset
Description
7-2
SEL EMP LANE x
(where x = 1, 0, 2, or 3)
R/W
0h
These bits select the amount of de-emphasis for the JESD
output transmitter. The de-emphasis value in decibels (dB) is
measured as the ratio between the peak value after the signal
transition to the settled value of the voltage in one bit period.
0 = 0 dB
1 = –1 dB
3 = –2 dB
7 = –4.1 dB
15 = –6.2 dB
31 = –8.2 dB
63 = –11.5 dB
1-0
0
W-0h
0h
Must write 0
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8.5.3.6.2 Register 16h (address = 16h), JESD Analog Page (6A00h)
Figure 127. Register 16h
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
JESD PLL MODE
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 62. Register 16h Field Descriptions
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
1-0
JESD PLL MODE
R/W
0h
These bits select the JESD PLL multiplication factor and must
match the JESD MODE setting.
00 = 20X mode
01 = Not used
10 = 40X mode
11 = Not used
Refer to Table 13 for Programming Summary of DDC modes
and JESD Link Configuration.
8.5.3.6.3 Register 17h (address = 17h), JESD Analog Page (6A00h)
Figure 128. Register 17h
7
0
W-0h
6
PLL RESET
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 63. Register 17h Field Descriptions
Bit
Field
Type
Reset
Description
7
0
W
0h
Must write 0
6
PLL RESET
R/W
0h
Pulse this bit after powering up the device; see Table 66.
0 = Default
0 → 1 → 0 = The PLL RESET bit is pulsed.
0
W
0h
Must write 0
5-0
8.5.3.6.4 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
Figure 129. Register 1Ah
7
0
W-0h
6
0
W-0h
5
0
W-0h
4
0
W-0h
3
0
W-0h
2
0
W-0h
1
FOVR CHA
R/W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 64. Register 1Ah Field Descriptions
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
1
FOVR CHA
R/W
0h
This bit outputs the FOVR signal for channel A on the PDN pin.
FOVR CHA EN (register 1Bh, bit 3) must be enabled for this bit
to function.
0 = Normal operation
1 = The FOVR signal of channel A is available on the PDN pin
0
0
W
0h
Must write 0
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8.5.3.6.5 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
Figure 130. Register 1Bh
7
6
JESD SWING
R/W-0h
5
4
0
W-0h
3
FOVR CHA EN
R/W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 65. Register 1Bh Field Descriptions
Bit
Field
Type
Reset
Description
7-5
JESD SWING
R/W
0h
These bits select the output amplitude VOD (mVPP) of the JESD
transmitter (for all lanes).
0 = 860 mVPP
1 = 810 mVPP
2 = 770 mVPP
3 = 745 mVPP
4 = 960 mVPP
5 = 930 mVPP
6 = 905 mVPP
7 = 880 mVPP
4
0
W
0h
Must write 0
3
FOVR CHA EN
R/W
0h
This bit enables overwrites of the PDN pin with the FOVR signal
from channel A.
0 = Normal operation
1 = PDN is overwritten
0
W
0h
Must write 0
2-0
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Start-Up Sequence
The steps described in Table 66 are recommended as the power-up sequence with the ADS54J42 in 20X mode
(LMFS = 8224).
66
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Table 66. Initialization Sequence
STEP
1
SEQUENCE
Power-up the device
PAGE BEING
PROGRAMMED
DESCRIPTION
Bring up the supplies to IOVDD = 1.15 V, DVDD = AVDD = 1.9 V, and
AVDD3V = 3.0 V.
Hardware reset
Reset the device
These supplies can be brought up in any order.
—
Apply a hardware reset by pulsing pin 48 (low → high → low).
A hardware reset clears all registers to their default values.
Register writes are equivalent to a hardware reset.
—
Write address 0-000h with 81h.
2
General register
Write address 4-001h with 00h and address 4-002h with 00h.
Unused page
Write address 4-003h with 00h and address 4-004h with 68h.
—
Main digital page
(JESD bank)
Write address 6-000h with 01h, then address 6-000h with 00h.
Write address 0-011h with 80h.
This bit is a self-clearing bit.
Clear any unwanted content from the unused pages of the JESD bank.
Select the main digital page of the JESD bank.
This bit is a self-clearing bit.
Pulse the PULSE RESET register bit for channel A.
—
Write address 0-059h with 20h.
Performance modes
Reset registers in the ADC and master pages of the analog bank.
Use the DIG RESET register bit to reset all pages in the JESD bank.
Write address 6-0F7h with 01h for channel A.
3
COMMENT
Select the master page of the analog bank.
Set the ALWAYS WRITE 1 bit.
Master page
(analog bank)
Write address 0-039h with C0h.
Write address 0-03Ah with 40h.
Write address 0-056h with 04h.
HIGH FREQ[3:0].
Set these register bits for better SFDR when input frequency > 400 MHz.
Default register writes for DDC modes and JESD link configuration (LMFS 8224).
Write address 4-003h with 00h and address 4-004h with 69h.
Write address 6-000h with 80h.
JESD link is configured with LMFS = 8224 by default with no decimation.
Write address 4-003h with 00h and address 4-004h with 6Ah.
4
Program desired registers for
decimation options and
JESD link configuration
JESD link is configured with LMFS = 8224 by default with no decimation.
Write address 6-017h with 40h.
—
JESD
digital page
(JESD bank)
—
JESD
analog page
(JESD bank)
Write address 6-017h with 00h.
Select the JESD digital page.
Set the CTRL K bit for both channels by programming K according to the
SYSREF signal later on in the sequence.
See Table 13 for configuring the JESD digital page registers for the desired
LMFS and programming appropriate DDC mode.
Select the JESD analog page.
See Table 13 for configuring the JESD analog page registers for the desired
LMFS and programming appropriate DDC mode.
PLL reset.
PLL reset.
Write address 4-003h with 00h and address 4-004h with 68h.
JESD link is configured with LMFS = 8224 by default with no decimation.
Write address 6-000h with 01h and address 6-000h with 00h.
—
Main digital page
(JESD bank)
Select the main digital page.
See Table 13 for configuring the main digital page registers for the desired
LMFS and programming appropriate DDC mode.
Pulse the PULSE RESET register bit. All settings programmed in the main
digital page take effect only after this bit is pulsed.
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Table 66. Initialization Sequence (continued)
STEP
SEQUENCE
5
Set the value of K and the
SYSREF signal frequency
accordingly
6
JESD lane alignment
PAGE BEING
PROGRAMMED
DESCRIPTION
Write address 4-003h with 00h and address 4-004h with 69h.
Write address 6-006h with XXh (choose the value of K).
—
JESD
digital page
(JESD bank)
Pull the SYNCB pin (pin 63) low.
68
Pull the SYNCB pin high.
COMMENT
Select the JESD digital page.
See the SYSREF Signal section to choose the correct frequency for SYSREF.
Transmit K28.5 characters.
—
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After the receiver is synchronized, initiate an ILA phase and subsequent
transmissions of ADC data.
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9.1.2 Hardware Reset
Figure 131 and Table 67 show the timing for a hardware reset.
Power Supplies
t1
RESET
t2
t3
SEN
Figure 131. Hardware Reset Timing Diagram
Table 67. Timing Requirements for Figure 131
MIN
t1
Power-on delay: delay from power-up to an active high RESET pulse
t2
t3
TYP
MAX
UNIT
1
ms
Reset pulse duration: active high RESET pulse duration
10
ns
Register write delay from RESET disable to SEN active
100
ns
9.1.3 SNR and Clock Jitter
The signal-to-noise ratio (SNR) of the ADC is limited by three different factors: quantization noise, thermal noise,
and jitter, as shown in Equation 4. The quantization noise is typically not noticeable in pipeline converters and is
86 dBFS for a 14-bit ADC. The thermal noise limits SNR at low input frequencies and the clock jitter sets SNR for
higher input frequencies.
(4)
The SNR limitation resulting from sample clock jitter can be calculated by Equation 5:
(5)
The total clock jitter (TJitter) has two components: the internal aperture jitter (130 fs) is set by the noise of the
clock input buffer and the external clock jitter. TJitter can be calculated by Equation 6:
(6)
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass
filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter.
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The ADS54J42 has a thermal noise of approximately 71.1 dBFS and an internal aperture jitter of 120 fS. SNR,
depending on the amount of external jitter for different input frequencies, is shown in Figure 132.
75
SNR (dBFS)
73
35 fS
50 fS
100 fS
150 fS
200 fS
71
69
67
65
10
100
Input Frequency (MHz)
D052
Figure 132. SNR versus Input Frequency and External Clock Jitter
70
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9.2 Typical Application
The ADS54J42 is designed for wideband receiver applications demanding excellent dynamic range over a large
input frequency range. A typical schematic for an ac-coupled receiver is shown in Figure 133.
DVDD
10 k
5:
50 :
Driver
0.1 PF
0.1 PF
2 pF
50 :
SPI Master
5:
GND
GND
0.1 PF
GND
0.1 PF
IOVDD
0.1 PF
100 :
SYSREFM
AVDD
AVDD
AGND
3
DB3M
AGND
SYSREFP
4
DB3P
0.1 PF
GND
5
DGND
AVDD3V
AVDD3V
6
IOVDD
AVDD
7
SDIN
GND
0.1 PF
Low-Jitter Clock
Generator
8
SCLK
AGND
9
SEN
CLKINM
DVDD
CLKINP
10
AVDD
AGND
11
AVDD3V
AVDD
AVDD
0.1 PF
GND
12
SDOUT
10 nF
AVDD3V
13
AVDD
GND
0.1 PF
AVDD3V
14
INBP
AGND
15
INBM
0.1 PF
16
AVDD
VCM
DVDD
AVDD3V
NC
NC
AVDD
AGND
NC
17
10nF
AVDD
AVDD3V
18
GND
0.1 PF
AVDD3V
AVDD
2
100-: Differential
1
10 nF
DB2P
19
72
20
71
21
70
22
69
DB2M
IOVDD
IOVDD
10 nF
DB1P
10 nF
GND
DB1M
23
68
24
67
25
66
DGND
DB0P
10 nF
GND
DB0M
26
65
IOVDD
27
64
GND Pad
(Back Side)
28
IOVDD
0.1 PF
SYNC
63
GND
DA0M
29
62
30
61
31
60
32
59
FPGA
DA0P
DGND
DA1M
10 nF
GND
DA1P
33
58
34
57
IOVDD
35
IOVDD
10 nF
10 nF
DA2M
56
GND
DA2P
36
55
GND
37
38
39
40
42
43
44
45
46
47
49
51
52
53
10 nF
54
DA3M
DA3P
DGND
IOVDD
PDN
RES
RESET
AVDD3V
GND
50
100-: Differential
10 nF
DVDD
AVDD
AVDD
48
DVDD
AVDD
AVDD3V
AVDD
AVDD
INAP
INAM
AVDD
AVDD3V
AVDD
AGND
AVDD3V
41
0.1 PF
GND
0.1 PF
GND
0.1 PF
IOVDD
GND
5:
50 :
Driver
0.1 PF
0.1 PF
50 :
GND
2 pF
5:
NOTE: GND = AGND and DGND are connected in the PCB layout.
Figure 133. AC-Coupled Receiver
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Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Transformer-Coupled Circuits
Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as
ADT1-1WT or WBC1-1) can be used up to 300 MHz to achieve good phase and amplitude balances at the ADC
inputs. When designing dc-driving circuits, the ADC input impedance must be considered. Figure 134 and
Figure 135 show the impedance (ZIN = RIN || CIN) across the ADC input pins.
5
Differential Input Capacitance (pF)
Differential Input Resistance (k:)
1.4
1.2
1
0.8
0.6
0.4
0.2
4.75
4.5
4.25
4
3.75
3.5
3.25
3
2.75
2.5
2.25
0
0
100
200
300
400 500 600 700
Frequency (MHz)
800
0
900 1000
100
200
D103
Figure 134. RIN vs Input Frequency
300
400 500 600 700
Frequency (MHz)
800
900 1000
D102
Figure 135. CIN vs Input Frequency
By using the simple drive circuit of Figure 136, uniform performance can be obtained over a wide frequency
range. The buffers present at the analog inputs of the device help isolate the external drive source from the
switching currents of the sampling circuit.
0.1 F
T1
T2
0.1 F
5
CHx_INP
25
0.1 F
RIN
0.1 F
1:1
CIN
25
5
CHx_INM
1:1
Device
Figure 136. Input Drive Circuit
9.2.2 Detailed Design Procedure
For optimum performance, the analog inputs must be driven differentially. This architecture improves commonmode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input
pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 136.
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Typical Application (continued)
9.2.3 Application Curves
0
0
-20
-20
Amplitude (dBFS)
Amplitude (dBFS)
Figure 137 and Figure 138 show the typical performance at 170 MHz and 230 MHz, respectively.
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
0
62.5
125
187.5
Input Frequency (MHz)
250
312.5
0
D103
62.5
125
187.5
Input Frequency (MHz)
250
312.5
D104
SNR = 71 dBFS, SINAD = 70.9 dBFS,
SFDR = 85 dBc, THD = 84 dBc, IL spur = 87 dBc,
non HD2, HD3 spur = 93 dBc
SNR = 70.4 dBFS, SINAD = 69.9 dBFS,
IL spur = 89 dBc, SFDR = 80 dBc, THD = 79 dBc,
non HD2, HD3 spur = 91 dBc
Figure 137. FFT for 170-MHz Input Signal
Figure 138. FFT for 230-MHz Input Signal
10 Power Supply Recommendations
The device requires a 1.9-V nominal supply for DVDD, a 1.9-V nominal supply for AVDD, and a 3.0-V nominal
supply for AVDD3V. There is no specific sequence for power-supply requirements during device power-up.
AVDD, DVDD, and AVDD3V can power-up in any order.
11 Layout
11.1 Layout Guidelines
The device evaluation module (EVM) layout can be used as a reference layout to obtain the best performance. A
layout diagram of the EVM top layer is provided in Figure 139. The ADS54J42EVM User's Guide (SLAU674),
provides a complete layout of the EVM. Some important points to remember during board layout are:
• Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package
level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as
illustrated in the reference layout of Figure 139 as much as possible.
• In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to
minimize coupling between them. This configuration is also maintained on the reference layout of Figure 139
as much as possible.
• Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output
traces must not be kept parallel to the analog input traces because this configuration can result in coupling
from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver
[such as a field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs)] must
be matched in length to avoid skew among outputs.
• At each power-supply pin (AVDD, DVDD, or AVDDD3V), keep a 0.1-µF decoupling capacitor close to the
device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF
capacitors can be kept close to the supply source.
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11.2 Layout Example
Figure 139. ADS54J42EVM Layout
74
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
ADS54J60 Data Sheet, SBAS706
ADS54J40 Data Sheet, SBAS714
ADS54J66 Data Sheet, SBAS745
ADS54J69 Data Sheet, SBAS713
ADS54J42EVM User's Guide, SLAU674
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: ADS54J42
75
PACKAGE OPTION ADDENDUM
www.ti.com
22-Mar-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS54J42IRMP
ACTIVE
VQFN
RMP
72
168
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ54J42
ADS54J42IRMPT
ACTIVE
VQFN
RMP
72
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ54J42
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
22-Mar-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADS54J42IRMPT
Package Package Pins
Type Drawing
VQFN
RMP
72
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
24.4
Pack Materials-Page 1
10.25
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.25
2.25
16.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS54J42IRMPT
VQFN
RMP
72
250
213.0
191.0
55.0
Pack Materials-Page 2
PACKAGE OUTLINE
RMP0072A
VQFN - 0.9 mm max height
SCALE 1.700
VQFN
10.1
9.9
B
A
PIN 1 ID
10.1
9.9
0.9 MAX
0.05
0.00
C
0.08 C
(0.2)
SEATING PLANE
4X (45 X0.42)
19
36
18
4X
8.5
37
SYMM
8.5 0.1
PIN 1 ID
(R0.2)
1
68X 0.5
54
55
72
SYMM
72X
0.5
0.3
72X
0.30
0.18
0.1
0.05
C B
C
A
4221047/B 02/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RMP0072A
VQFN - 0.9 mm max height
VQFN
(
8.5)
SYMM
72X (0.6)
SEE DETAILS
55
72
1
54
72X (0.24)
(0.25) TYP
(9.8)
SYMM
(1.315) TYP
68X (0.5)
( 0.2) TYP
VIA
37
18
19
36
(1.315) TYP
(9.8)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221047/B 02/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB application report
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RMP0072A
VQFN - 0.9 mm max height
VQFN
(9.8)
72X (0.6)
(1.315) TYP
72
55
1
54
72X (0.24)
(1.315)
TYP
(0.25) TYP
SYMM
(1.315)
TYP
(9.8)
68X (0.5)
METAL
TYP
37
18
( 0.2) TYP
VIA
19
36
36X ( 1.115)
(1.315) TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
62% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
4221047/B 02/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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