Texas Instruments | ADS42JB46 Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter (Rev. B) | Datasheet | Texas Instruments ADS42JB46 Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter (Rev. B) Datasheet

Texas Instruments ADS42JB46 Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter (Rev. B) Datasheet
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ADS42JB46
SBAS621B – JULY 2013 – REVISED SEPTEMBER 2015
ADS42JB46 Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter
1 Features
2 Applications
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Dual-Channel ADCs
14-Bit Resolution
Maximum Clock Rate: 160 MSPS
JESD204B Serial Interface
– Subclass 0, 1, 2 Compliant
– Up to 3.125 Gbps
– Two- and Four-Lane Support
Analog Input Buffer with High-Impedance Input
Flexible Input Clock Buffer:
Divide-by-1, -2, and -4
Differential Full-Scale Input: 2 VPP and 2.5 VPP
(Register Programmable)
Package: 9-mm × 9-mm QFN-64
Power Dissipation: 679 mW/Ch
Aperture Jitter: 85 fS rms
Internal Dither
Channel Isolation: 100 dB
Performance:
– fIN = 170 MHz at 2 VPP, –1 dBFS
– SNR: 72.9 dBFS
– SFDR: 90 dBc for HD2, HD3
– SFDR: 100 dBc for Non HD2, HD3
– fIN = 170 MHz at 2.5 VPP, –1 dBFS
– SNR: 74.2 dBFS
– SFDR: 84 dBc for HD2, HD3 and
95 dBc for Non HD2, HD3
Simplified Schematic
Device
INAP,
INAM
14-, 16-Bit
ADC
CLKINP,
CLKINM
SYSREFP,
SYSREFM
OVRA
Digital
Block
JESD204B
Digital
Gain
Test Modes
Device Information(1)
PART NUMBER
ADS42JB46
PACKAGE
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
FFT for 170-MHz Input Signal Sampled at 160
MSPS
0
FIN = 170 MHz
SFDR = 92 dBc
SNR = 73 dBFS
SINAD = 72.9 dBFS
THD = 91 dBc
SFDR Non HD2, HD3
= 100 dBc
DA1P,
DA1M
−40
14-, 16-Bit
ADC
Digital
Block
JESD204B
Digital
DB0P,
DB0M
DB1P,
DB1M
OVRB
Common
Mode
BODY SIZE (NOM)
VQFN (64)
SYNC~P,
SYNC~M
Gain
Test Modes
VCM
The ADS42JB46 is a high-linearity, dual-channel, 14bit, 160-MSPS, analog-to-digital converter (ADC).
This device supports the JESD204B serial interface
with data rates up to 3.125 Gbps. The buffered
analog input provides uniform input impedance
across a wide frequency range while minimizing
sample-and-hold glitch energy, thus making driving
analog inputs up to very high input frequencies easy.
A sampling clock divider allows more flexibility for
system clock architecture design. The device
employs internal dither algorithms to provide excellent
spurious-free dynamic range (SFDR) over a large
input frequency range.
DA0P,
DA0M
Delay
INBP,
INBM
3 Description
−20
PLL
x10, x20
Divide
by 1, 2, 4
Communication and Cable Infrastructure
Multi-Carrier, Multimode Cellular Receivers
Radar and Smart Antenna Arrays
Broadband Wireless
Test and Measurement Systems
Software-Defined and Diversity Radios
Microwave and Dual-Channel I/Q Receivers
Repeaters
Power Amplifier Linearization
Amplitude (dBFS)
1
−60
−80
Device Configuration
MODE
CTRL1
CTRL2
STBY
SDOUT
PDN
PDN_GBL
SEN
SCLK
SDATA
RESET
−100
−120
0
20
40
Frequency (MHz)
60
80
G002
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS42JB46
SBAS621B – JULY 2013 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
8
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics: ADS42JB46 ..................... 7
Electrical Characteristics: General ............................ 8
Timing Characteristics............................................... 9
Digital Characteristics ............................................. 10
Reset Timing .......................................................... 10
Serial Interface Timing .......................................... 11
Typical Characteristics: ADS42JB46 .................... 14
Typical Characteristics: Contour ........................... 20
Detailed Description ............................................ 22
8.1
8.2
8.3
8.4
8.5
8.6
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
22
22
23
24
31
34
Application and Implementation ........................ 47
9.1 Application Information............................................ 47
9.2 Typical Application .................................................. 47
10 Power Supply Recommendations ..................... 53
11 Layout................................................................... 53
11.1 Layout Guidelines ................................................. 53
11.2 Layout Example .................................................... 54
12 Device and Documentation Support ................. 55
12.1
12.2
12.3
12.4
12.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
55
55
55
55
55
13 Mechanical, Packaging, and Orderable
Information ........................................................... 55
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August 2013) to Revision B
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Original (July 2013) to Revision A
•
2
Page
Page
Changed document status to Production Data; moved from 1-page Preview ....................................................................... 1
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SBAS621B – JULY 2013 – REVISED SEPTEMBER 2015
5 Device Comparison Table
INTERFACE OPTION
14-BIT,
160 MSPS
14-BIT,
250 MSPS
16-BIT,
250 MSPS
DDR, QDR LVDS
—
ADS42LB49
ADS42LB69
JESD204B
ADS42JB46
ADS42JB46
ADS42JB69
6 Pin Configuration and Functions
DRVDD
DGND
OVRB
OVRA
DRVDD
DB1M
DB1P
DB0M
DB0P
IOVDD
DA0P
DA0M
DA1P
DA1M
DGND
DRVDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RGC Package
64-Pin VQFN
Top View
DGND
1
48
DRVDD
2
47 DRVDD
DGND
3
46 DGND
MODE
4
45 SDOUT
STBY
5
44 RESET
PDN_GBL
6
43 SCLK
DRVDD
7
42 SDATA
SYNC~M
8
SYNC~P
9
Thermal Pad
DGND
41 SEN
40 AVDD
CTRL2 10
39 CTRL1
AVDD 11
38 AVDD
AGND 12
37 AGND
INBP 13
36 INAP
32
AVDD3V
AVDD 31
SYSREFM 30
SYSREFP 29
AGND 28
AVDD 27
AGND 26
CLKINP 25
CLKINM 24
23
AVDD 22
21
VCM
AGND
20
AGND
33 AVDD
19
AVDD 16
AVDD 18
34 AGND
AGND
35 INAM
AVDD3V 17
INBM 14
AGND 15
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Pin Functions: JESD204B Output Interface
PIN
DESCRIPTION
NAME
NO.
I/O
FUNCTION
AGND
12, 15, 19, 20,
23, 26, 28, 34,
37
I
Supply
Analog ground
AVDD
11, 16, 18, 22,
27, 31, 33, 38,
40
I
Supply
1.8-V analog power supply
AVDD3V
17, 32
I
Supply
3.3-V analog supply for analog buffer
CLKINM
24
I
Clock
Differential ADC clock input (negative)
CLKINP
25
I
Clock
Differential ADC clock input (positive)
CTRL1
39
I
Control
Power-down control with an internal 150-kΩ pull-down resistor
CTRL2
10
I
Control
Power-down control with an internal 150-kΩ pull-down resistor
DA0M
53
O
Interface
JESD204B serial data output for channel A, lane 0 (negative)
DA0P
54
O
Interface
JESD204B serial data output for channel A, lane 0 (positive)
DA1M
51
O
Interface
JESD204B serial data output for channel A, lane 1 (negative)
DA1P
52
O
Interface
JESD204B serial data output for channel A, lane 1 (positive)
DB0M
57
O
Interface
JESD204B serial data output for channel B, lane 0 (negative)
DB0P
56
O
Interface
JESD204B serial data output for channel B, lane 0 (positive)
DB1M
59
O
Interface
JESD204B serial data output for channel B, lane 1 (negative)
DB1P
58
O
Interface
JESD204B serial data output for channel B, lane 1 (positive)
DGND
1, 3, 46, 48,
50, 63
I
Supply
Digital ground
DRVDD
2, 7, 47, 49,
60, 64
I
Supply
Digital 1.8-V power supply
INAM
35
I
Input
Differential analog input for channel A (negative)
INAP
36
I
Input
Differential analog input for channel A (positive)
INBM
14
I
Input
Differential analog input for channel B (negative)
INBP
13
I
Input
Differential analog input for channel B (positive)
IOVDD
55
I
Supply
Digital 1.8-V power supply for the JESD204B transmitter
MODE
4
I
Control
Connect to GND
OVRA
61
O
Interface
Overrange indication for channel A in CMOS output format
OVRB
62
O
Interface
Overrange indication for channel B in CMOS output format
PDN_GBL
6
I
Control
Global power-down. Active high with an internal 150-kΩ pull-down resistor.
RESET
44
I
Control
Hardware reset; active high. This pin has an internal 150-kΩ pull-down resistor.
SCLK
43
I
Control
Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor.
SDATA
42
I
Control
Serial interface data input. This pin has an internal 150-kΩ pull-down resistor.
SDOUT
45
O
Control
Serial interface data output
SEN
41
I
Control
Serial interface enable. This pin has an internal 150-kΩ pull-up resistor.
STBY
5
I
Control
Standby. Active high with an internal 150-kΩ pull-down resistor.
SYNC~M
8
I
Interface
Synchronization input for JESD204B port (negative)
SYNC~P
9
I
Interface
Synchronization input for JESD204B port (positive)
SYSREFM
30
I
Clock
External SYSREF input, subclass 1 (negative)
SYSREFP
29
I
Clock
External SYSREF input, subclass 1 (positive)
VCM
21
O
Output
1.9-V common-mode output voltage for analog inputs
Thermal Pad
65
GND
Ground
Connect to ground plane
4
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted. (1)
MIN
MAX
UNIT
AVDD3V
–0.3
3.6
V
AVDD
–0.3
2.1
V
DRVDD
–0.3
2.1
V
IOVDD
–0.3
2.1
V
Voltage between AGND and DGND
–0.3
0.3
V
–0.3
3
V
CLKINP, CLKINM
–0.3
minimum
(2.1, AVDD
+ 0.3)
V
SYNC~P, SYNC~M
–0.3
minimum
(2.1, AVDD
+ 0.3)
V
SYSREFP, SYSREFM
–0.3
minimum
(2.1, AVDD
+ 0.3)
V
SCLK, SEN, SDATA, RESET, PDN_GBL, CTRL1, CTRL2, STBY, MODE
–0.3
3.9
V
Operating free-air, TA
–40
85
°C
125
°C
150
°C
Supply voltage
INAP, INBP, INAM, INBM
Voltage applied to input
pins
Temperature
Operating junction, TJ
Storage, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions (1)
Over operating free-air temperature range, unless otherwise noted.
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
AVDD3V
Analog buffer supply voltage
1.7
1.8
1.9
V
3.15
3.3
3.45
DRVDD
V
Digital supply voltage
1.7
1.8
1.9
V
IOVDD
Output buffer supply voltage
1.7
1.8
1.9
V
ANALOG INPUTS
VID
Differential input voltage range
VICR
Input common-mode voltage
Default after reset
Register programmable
(2)
2
VPP
2.5
VPP
VCM ± 0.025
V
Maximum analog input frequency with 2.5-VPP input amplitude
250
MHz
Maximum analog input frequency with 2-VPP input amplitude
400
MHz
CLOCK INPUT
Input clock sample rate
Input clock amplitude differential
(VCLKP – VCLKM)
10x mode
60
160
MSPS
20x mode
40
156.25
MSPS
Sine wave, ac-coupled
(3)
1.5
VPP
LVPECL, ac-coupled
0.3
1.6
VPP
LVDS, ac-coupled
0.7
VPP
LVCMOS, single-ended, ac-coupled
Input clock duty cycle
1.5
35%
50%
V
65%
DIGITAL OUTPUTS
CLOAD
Maximum external load capacitance from each output pin to DRGND
RLOAD
Single-ended load resistance
TA
Operating free-air temperature
(1)
(2)
(3)
3.3
pF
Ω
+50
–40
85
°C
To reset the device for the first time after power-up, only use the RESET pin. Refer to the Register Initialization section.
For details, refer to the Digital Gain section.
Refer to the Performance vs Clock Amplitude curves (Figure 32 and Figure 33).
7.4 Thermal Information
ADS42JB46
THERMAL METRIC (1)
RGC (QFN)
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance
22.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
7.1
°C/W
RθJB
Junction-to-board thermal resistance
2.5
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
2.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.2
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics: ADS42JB46
Typical values are at TA = 25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle, –1dBFS differential analog input, and sampling clock rate = 160 MSPS, unless otherwise noted. Minimum and maximum values
are across the full temperature range of TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and
IOVDD = 1.8 V.
PARAMETER
SNR
Signal-to-noise ratio
SINAD Signal-to-noise and distortion ratio
SFDR
THD
HD2
HD3
Spurious-free dynamic range
(including second and third
harmonic distortion)
Total harmonic distortion
2nd-order harmonic distortion
3rd-order harmonic distortion
TEST CONDITIONS
2-VPP FULL-SCALE
MIN
TYP
MAX
2.5-VPP FULL-SCALE
MIN
TYP
MAX
UNIT
fIN = 10 MHz
73.7
75.2
dBFS
fIN = 70 MHz
73.5
74.9
dBFS
fIN = 170 MHz
72.9
74.2
dBFS
fIN = 230 MHz
69.5
72.3
73.3
dBFS
fIN = 10 MHz
73.5
75.1
dBFS
73.3
74.7
dBFS
72.8
73.6
dBFS
fIN = 230 MHz
72
72.8
dBFS
fIN = 10 MHz
96
92
dBc
94
90
dBc
90
84
dBc
fIN = 230 MHz
86
83
dBc
fIN = 10 MHz
93
90
dBc
fIN = 70 MHz
91
88
dBc
87
82
dBc
fIN = 230 MHz
84
81
dBc
fIN = 10 MHz
96
95
dBc
fIN = 70 MHz
94
90
dBc
92
89
dBc
fIN = 230 MHz
88
86
dBc
fIN = 10 MHz
97
92
dBc
fIN = 70 MHz
96
94
dBc
fIN = 70 MHz
fIN = 170 MHz
68.5
fIN = 70 MHz
fIN = 170 MHz
fIN = 170 MHz
fIN = 170 MHz
76
79
90
84
dBc
fIN = 230 MHz
86
83
dBc
fIN = 10 MHz
102
101
dBc
102
100
dBc
100
95
dBc
fIN = 230 MHz
98
92
dBc
f1 = 46 MHz, f2 = 50 MHz,
each tone at –7 dBFS
97
95
dBFS
f1 = 185 MHz, f2 = 190 MHz,
each tone at –7 dBFS
90
89
dBFS
Crosstalk
20-MHz, full-scale signal on
channel under observation;
170-MHz, full-scale signal on
other channel
100
100
dB
Input overload recovery
Recovery to within 1% (of fullscale) for 6-dB overload with sinewave input
1
1
PSRR
AC power-supply rejection ratio
For a 90-mVPP signal on AVDD
supply, up to 10 MHz
> 40
> 40
ENOB
Effective number of bits
fIN = 170 MHz
11.8
12
LSBs
DNL
Differential nonlinearity
fIN = 170 MHz
±0.4
±0.5
LSBs
INL
Integrated nonlinearity
fIN = 170 MHz
±0.75
±0.9
LSBs
Worst spur
(other than second and third
harmonics)
IMD
Two-tone intermodulation
distortion
fIN = 170 MHz
79
79
fIN = 70 MHz
fIN = 170 MHz
87
±3
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dB
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7.6 Electrical Characteristics: General
Typical values are at 25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle, –1dBFS differential analog input, , and sampling clock rate = 160 MSPS unless otherwise noted. Minimum and maximum values
are across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and
IOVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Default (after reset)
Differential input voltage
range
VID
2
VPP
Register programmed (1)
2.5
VPP
Differential input resistance (at 170
MHz)
1.2
kΩ
4
pF
Differential input capacitance (at 170
MHz)
Analog input bandwidth
VCM
With 50-Ω source impedance and 50-Ω
termination
900
MHz
Common-mode output
voltage
1.9
V
VCM output current
capability
10
mA
DC ACCURACY
Offset error
EGREF
Gain error as a result of
internal reference
inaccuracy alone
EGCHAN
Gain error of channel
alone
–20
20
mV
–2
2
%FS
–5
Temperature coefficient of
EGCHAN
%FS
Δ%/°C
0.01
POWER SUPPLY
IAVDD
Analog supply current
90
130
mA
IAVDD3V
Analog buffer supply
current
234
330
mA
IDRVDD
Digital supply current
174
207
mA
IOVDD
Output buffer supply
current
61
100
mA
50-Ω external termination from pin to
IOVDD, fIN = 2.5 MHz, 10x mode
Analog power
162
mW
Analog buffer power
772
mW
313
mW
109
mW
Digital power
Power consumption by
output buffer
50-Ω external termination from pin to
IOVDD, fIN = 2.5 MHz, 10x mode
Total power
1.36
Global power-down
(1)
8
1.64
W
160
mW
Refer to the Serial Interface section.
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7.7 Timing Characteristics
Typical values are at 25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle, –1dBFS differential analog input, and sampling clock rate = 160 MSPS, unless otherwise noted. Minimum and maximum values
are across the full temperature range of TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and
IOVDD = 1.8 V. See Figure 3.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.7
1.1
UNIT
SAMPLE TIMING CHARACTERISTICS
Aperture delay
Aperture delay
matching
0.4
Between two channels on the same device
Between two devices at the same temperature and
supply voltage
Aperture jitter
Wake-up time
ps
±150
ps
85
Time to valid data after exiting STANDBY mode
Time to valid data after exiting global power-down
ns
±70
fS rms
50
200
µs
250
1000
µs
tSU_SYNC~
Setup time for SYNC~
Referenced to input clock rising edge
400
ps
tH_SYNC~
Hold time for SYNC~
Referenced to input clock rising edge
100
ps
tSU_SYSREF
Setup time for
SYSREF
Referenced to input clock rising edge
400
ps
tH_SYSREF
Hold time for SYSREF
Referenced to input clock rising edge
100
ps
CML OUTPUT TIMING CHARACTERISTICS
Unit interval
320
Serial output data rate
TJitter
tR, tF
Total jitter
Data rise time,
data fall time
1667
ps
3.125
Gbps
0.28
P-PUI
3.125 Gbps (20x mode, fS = 156.25 MSPS)
0.3
P-PUI
Rise and fall times are measured from 20% to 80%,
differential output waveform,
600 Mbps ≤ bit rate ≤ 3.125 Gbps
105
ps
1.6 Gbps (10x mode, fS = 160 MSPS)
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7.8 Digital Characteristics
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and IOVDD = 1.8 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDATA, PDN_GBL, STBY, CTRL1, CTRL2, MODE) (1)
VIH
High-level input voltage
All digital inputs support 1.8-V and 3.3-V
logic levels
VIL
Low-level input voltage
All digital inputs support 1.8-V and 3.3-V
logic levels
IIH
High-level input current
IIL
Low-level input current
1.2
V
0.4
SEN
V
0
µA
RESET, SCLK, SDATA, PDN_GBL, STBY,
CTRL1, CTRL2, MODE
10
µA
SEN
10
µA
0
µA
RESET, SCLK, SDATA, PDN_GBL, STBY,
CTRL1, CTRL2, MODE
DIGITAL INPUTS (SYNC~P, SYNC~M, SYSREFP, SYSREFM)
VIH
High-level input voltage
1.3
V
VIL
Low-level input voltage
0.5
V
VCM_DIG
Input common-mode voltage
0.9
V
DRVDD
V
DIGITAL OUTPUTS (SDOUT, OVRA, OVRB)
VOH
High-level output voltage
VOL
Low-level output voltage
DRVDD
– 0.1
0.1
DIGITAL OUTPUTS (JESD204B Interface: DA[0,1], DB[0,1])
V
(2)
VOH
High-level output voltage
IOVDD
V
VOL
Low-level output voltage
IOVDD – 0.4
V
|VOD|
Output differential voltage
0.4
V
VOCM
Output common-mode voltage
IOVDD – 0.2
V
Transmitter short-circuit current
Transmitter terminals shorted to any voltage
between –0.25 V and 1.45 V
–100
Single-ended output impedance
COUT
(1)
(2)
Output capacitance
50
Ω
2
pF
Output capacitance inside the device,
from either output to ground
(1)
PARAMETER
TEST CONDITIONS
MIN
t1
Power-on delay
Delay from AVDD and DRVDD power-up to active RESET
pulse
t2
Reset pulse width
Active RESET signal pulse width
t3
Register write delay
Delay from RESET disable to SEN active
10
mA
The RESET, SCLK, SDATA, PDN_GBL, STBY, CTRL1, CTRL2, and MODE pins have a 150-kΩ (typical) internal pulldown resistor to
ground. The SEN pin has a 150-kΩ (typical) pullup resistor to AVDD.
50-Ω, single-ended, external termination to IOVDD.
7.9 Reset Timing
(1)
100
TYP
MAX
1
ms
10
ns
1
100
UNIT
µs
ns
Typical values are at 25°C and minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = 85°C,
unless otherwise noted.
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7.10 Serial Interface Timing (1)
PARAMETER
MIN
TYP
UNIT
20
MHz
SCLK frequency (equal to 1 / tSCLK)
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDSU
SDIO setup time
25
ns
tDH
SDIO hold time
25
ns
(1)
> dc
MAX
fSCLK
Typical values are at 25°C, minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = 85°C,
AVDD3V = 3.3 V, and AVDD = DRVDD = IOVDD = 1.8 V, unless otherwise noted.
Register Address <5:0>
SDATA
R/W
0
A5
A4
A3
A2
Register Data <7:0>
A1
A0
D7
D6
D5
D4
D3
D2
=0
D1
D0
tDH
tSCLK
tDSU
SCLK
tSLOADS
tSLOADH
SEN
RESET
Figure 1. Serial Register Write Timing Diagram
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
NOTE: After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin.
Figure 2. Reset Timing Diagram
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N+3
N+2
Sample
N
N+4
N + Latency + 1
N + Latency
N+1
N + Latency + 2
tA
CLKP
Input
Clock
CLKM
ADC Latency
(1)
tD
(2)
Dx0P, Dx0M
N - Latency-1
N + Latency
N - Latency+1 N - Latency+2
N - Latency+3
N-1
N
N+1
N+1
N - Latency-1
N + Latency
N - Latency+1 N - Latency+2
N - Latency+3
N-1
N
N+1
N+1
(2)
Dx1P, Dx1M
(1)
Overall latency = ADC latency + tD.
(2)
x = A for channel A and B for channel B.
Figure 3. ADC Latency
CLKINP
Input
Clock
CLKINM
tSU_SYNC~
tH_SYNC~
SYNC~
tD
SYNC~ Asserted Latency
Dx0P, Dx0M
Dx1P, Dx1M
(1)
CGS Phase
(1)
Data
Data
Data
Data
Data
Data
Data
Data
Data
K28.5
Data
Data
Data
Data
Data
Data
Data
Data
Data
K28.5
(1)
x = A for channel A and B for channel B.
Figure 4. SYNC~ Latency in CGS Phase (Two-Lane Mode)
12
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CLKINP
Input
Clock
CLKINM
tSU_SYNC~
tH_SYNC~
SYNC~
tD
SYNC~ Deasserted Latency
ILA Sequence
Dx0P, Dx0M
Dx1P, Dx1M
(1)
(1)
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.0
K28.0
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.0
K28.0
(1)
x = A for channel A and B for channel B.
Figure 5. SYNC~ Latency in ILAS Phase (Two-Lane Mode)
Sample N
tSU_SYSREF
tH_SYSREF
CLKIN
SYSREF
Figure 6. SYSREF Timing (Subclass 1)
Sample N
tSU_SYNC~
tH_SYNC~
CLKIN
SYNC~
Figure 7. SYNC~ Timing (Subclass 2)
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7.11 Typical Characteristics: ADS42JB46
Typical values are at TA = +25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 64k-point FFT, unless otherwise noted.
0
0
FIN = 300 MHz
SFDR = 77 dBc
SNR = 72.4 dBFS
SINAD = 71.2 dBFS
THD = 76 dBc
SFDR Non HD2, HD3
= 96 dBc
−20
−40
−60
−60
−80
−80
−100
−100
−120
0
20
40
60
−120
80
Frequency (MHz)
40
60
80
Frequency (MHz)
G004
0
0
FIN = 170 MHz
SFDR = 87 dBc
SNR = 74.3 dBFS
SINAD = 74 dBFS
THD = 85 dBc
SFDR Non HD2, HD3
= 93 dBc
Amplitude (dBFS)
−40
−60
−80
−80
−100
−100
0
20
40
60
Frequency (MHz)
−120
80
0
20
40
60
Frequency (MHz)
G005
Figure 10. FFT for 170-MHz Input Signal
(2.5-VPP Full-Scale)
80
G006
Figure 11. FFT for 300-MHz Input Signal
(2.5-VPP Full-Scale)
0
0
Each Tone at
−7 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
2−Tone IMD = 101 dBFS
SFDR = 104 dBFS
−20
Each Tone at
−36 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
2−Tone IMD = 101 dBFS
SFDR = 104 dBFS
−20
−40
Amplitude (dBFS)
−40
−60
−60
−80
−80
−100
−100
−120
FIN = 300 MHz
SFDR = 74 dBc
SNR = 73.4 dBFS
SINAD = 70.8 dBFS
THD = 73 dBc
SFDR Non HD2, HD3
= 94 dBc
−20
−60
−120
Amplitude (dBFS)
20
Figure 9. FFT for 10-MHz Input Signal
(2.5-VPP Full-Scale)
−40
0
20
40
Frequency (MHz)
60
80
−120
0
20
40
Frequency (MHz)
G007
Figure 12. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
14
0
G003
Figure 8. FFT for 300-MHz Input Signal
−20
Amplitude (dBFS)
−20
Amplitude (dBFS)
Amplitude (dBFS)
−40
FIN = 10 MHz
SFDR = 90 dBc
SNR = 75.6 dBFS
SINAD = 75.4 dBFS
THD = 89 dBc
SFDR Non HD2, HD3
= 101 dBc
60
80
G008
Figure 13. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
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Typical Characteristics: ADS42JB46 (continued)
Typical values are at TA = +25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 64k-point FFT, unless otherwise noted.
0
0
Each Tone at
−7 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
2−Tone IMD = 98 dBFS
SFDR = 105 dBFS
−20
−20
−40
Amplitude (dBFS)
Amplitude (dBFS)
−40
−60
−60
−80
−80
−100
−100
−120
Each Tone at
−36 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
2−Tone IMD = 102 dBFS
SFDR = 103 dBFS
0
20
40
60
−120
80
Frequency (MHz)
0
20
40
60
80
Frequency (MHz)
G009
G007
Figure 14. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
Figure 15. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
−98
−94
fIN1 = 46 MHz
fIN2 = 50 MHz
fIN1 = 185 MHz
fIN2 = 190 MHz
−96
−100
Two − Tone IMD (dBFS)
Two − Tone IMD (dBFS)
−98
−102
−104
−106
−100
−102
−104
−108
−106
−110
−108
−112
−36
−33
−30
−27
−24
−21
−18
−15
−12
−110
−36
−9 −7
Each Tone Amplitude (dBFS)
−33
−30
−27
−24
−21
−18
−15
−12
−9 −7
Each Tone Amplitude (dBFS)
G011
G012
Figure 16. Intermodulation Distortion vs
Input Amplitude (46 MHz and 50 MHz)
Figure 17. Intermodulation Distortion vs
Input Amplitude (185 MHz and 190 MHz)
100
76
2Vpp Fullscale
2.5Vpp Fullscale
95
2Vpp Fullscale
2.5Vpp Fullscale
75
90
74
85
SNR (dBFS)
SFDR (dBc)
73
80
75
72
71
70
70
65
69
60
55
0
50
100
150
200
250
300
Input Frequency (MHz)
350
400
G013
Figure 18. Spurious-Free Dynamic Range vs
Input Frequency
68
0
50
100
150
200
250
Input Frequency (MHz)
300
350
400
G014
Figure 19. Signal-to-Noise Ratio vs
Input Frequency
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Typical Characteristics: ADS42JB46 (continued)
Typical values are at TA = +25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 64k-point FFT, unless otherwise noted.
120
80
10 MHz
70 MHz
100 MHz
130 MHz
115
110
170 MHz
200 MHz
230 MHz
270 MHz
350 MHz
400 MHz
491 MHz
170 MHz
200 MHz
230 MHz
270 MHz
350 MHz
400 MHz
491 MHz
76
105
100
74
SNR (dBFS)
95
SFDR (dBc)
10 MHz
70 MHz
100 MHz
130 MHz
78
90
85
80
72
70
68
75
70
66
65
64
60
62
−2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Digital Gain (dB)
Figure 20. Spurious-Free Dynamic Range vs
Digital Gain
77
120
76.5
76
110
76
110
75.5
100
75.5
100
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
75
90
74.5
80
74
70
73.5
60
73
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
120
75
90
74.5
80
74
70
73.5
60
50
73
50
72.5
40
72.5
40
72
30
72
30
71.5
−70
−60
−50
−40
−30
−20
−10
0
SNR (dBFS)
SNR (dBFS)
130
Input Frequency = 170 MHz
SFDR (dBc,dBFS)
Input Frequency = 70 MHz
20
71.5
−70
−60
−50
−40
−30
−20
−10
0
20
Amplitude (dBFS)
Amplitude (dBFS)
G017
G018
Figure 22. Performance vs Input Amplitude
(70 MHz)
Figure 23. Performance vs Input Amplitude
(170 MHz)
76
100
Input Frequency = 70 MHz
75
100
SFDR
SNR
Input Frequency = 170 MHz
SFDR
SNR
75.5
97
74.5
96
75
94
74
94
74.5
91
73.5
92
74
88
73
90
73.5
85
72.5
88
73
82
72
86
1.850
1.875
1.900
1.925
72.5
1.950
Input Common−Mode Voltage (V)
SFDR (dBc)
98
SNR (dBFS)
SFDR (dBc)
G016
Figure 21. Signal-to-Noise Ratio vs
Digital Gain
130
77
76.5
79
1.85
1.875
1.9
1.925
71.5
1.95
Input Common−Mode Voltage (V)
G019
Figure 24. Performance vs
Input Common-Mode Voltage (70 MHz)
16
−2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
G015
SFDR (dBc,dBFS)
Digital Gain (dB)
SNR (dBFS)
55
G020
Figure 25. Performance vs
Input Common-Mode Voltage (170 MHz)
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Typical Characteristics: ADS42JB46 (continued)
Typical values are at TA = +25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 64k-point FFT, unless otherwise noted.
94
74.5
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
93
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.7 V
AVDD = 1.75V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
74
SNR (dBFS)
SFDR (dBc)
92
91
90
73.5
73
89
72.5
88
Input Frequency = 170 MHz
87
−40
−15
10
35
Temperature (°C)
Input Frequency = 170 MHz
60
72
−40
85
−15
10
35
Temperature (°C)
60
85
G021
G022
Figure 26. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (170 MHz)
Figure 27. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (170 MHz)
75
95
AVDD3V = 3.15 V
AVDD3V = 3.2 V
AVDD3V = 3.25 V
AVDD3V = 3.3 V
94
AVDD3V = 3.35 V
AVDD3V = 3.4 V
AVDD3V = 3.45 V
AVDD3V = 3.15 V
AVDD3V = 3.2 V
AVDD3V = 3.25 V
AVDD3V = 3.3 V
74.5
AVDD3V = 3.35 V
AVDD3V = 3.4 V
AVDD3V = 3.45 V
93
74
SNR (dBFS)
SNR (dBFS)
92
91
90
73.5
89
73
88
72.5
87
Input Frequency = 170 MHz
86
−40
−15
10
35
Temperature (°C)
Input Frequency = 170 MHz
60
72
−40
85
−15
10
35
Temperature (°C)
60
85
G023
Figure 28. Spurious-Free Dynamic Range vs AVDD3V
Supply and Temperature (170 Mhz)
G024
Figure 29. Signal-to-Noise Ratio vs
AVDD3V Supply and Temperature (170 MHz)
74.5
94
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
93
DRVDD = 1.85 V
DRVDD = 1.9 V
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
DRVDD = 1.85 V
DRVDD = 1.9 V
74
92
SNR (dBFS)
SFDR (dBc)
91
90
73.5
73
89
88
72.5
87
Input Frequency = 170 MHz
86
−40
−15
10
35
Temperature (°C)
Input Frequency = 170 MHz
60
72
−40
85
G025
Figure 30. Spurious-Free Dynamic Range vs
DRVDD Supply and Temperature (170 MHz)
−15
10
35
Temperature (°C)
60
85
G026
Figure 31. Signal-to-Noise Ratio vs
DRVDD Supply and Temperature (170 MHz)
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Typical Characteristics: ADS42JB46 (continued)
Typical values are at TA = +25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 64k-point FFT, unless otherwise noted.
Input Frequency = 170 MHz
94
75
92
74
90
73
88
72
86
71
84
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
70
2.1
1.9
74
94
72
92
70
90
68
88
66
86
0.1
Differential Clock Amplitudes (Vpp)
0.3
G027
Input Frequency = 70 MHz
0.7
0.9
1.1
1.3
1.5
1.7
1.9
64
2.1
G028
Figure 33. Performance vs Clock Amplitude
(170 MHz)
78
100
0.5
Differential Clock Amplitudes (Vpp)
Figure 32. Performance vs Clock Amplitude
(70 MHz)
77
94
SNR
SFDR
Input Frequency = 170 MHz
SNR
SFDR
98
77
92
76
96
76
90
75
94
75
88
74
92
74
86
73
90
73
84
72
88
72
82
71
71
80
86
30
40
50
60
Input Clock Duty Cycle (%)
70
SFDR (dBc)
SNR (dBFS)
SFDR (dBc)
96
30
40
50
60
Input Clock Duty Cycle (%)
70
SNR (dBFS)
76
SFDR (dBc)
96
SFDR
SNR
SNR (dBFS)
SFDR
SNR
SNR (dBFS)
SFDR (dBc)
Input Frequency = 70 MHz
76
98
77
98
70
G029
Figure 34. Performance vs Clock Duty Cycle
(70 MHz)
G030
Figure 35. Performance vs Clock Duty Cycle
(170 MHz)
0
0
−20
−10
−20
CMRR (dB)
−40
Amplitude (dBFS)
Input Frequency = 10 MHz
50−mVPP Signal Superimposed on VCM
FIN = 10 MHz
SFDR = 83 dBc
fCM = 4 MHz, 50m VPP
fIN Amplitude = −1 dBFS
fCM Amplitude = −102 dBFS
fIN + fCM Amplitude = −84.4 dBFS
fIN − fCM Amplitude = −84 dBFS
−60
−30
−40
−80
−50
−100
−120
−60
0
10
20
30
40
50
Frequency (MHz)
60
70
80
0
50
100
150
200
250
Common−Mode Test Signal Frequency (MHz)
G031
Figure 36. Common-Mode Rejection Ratio FFT
18
−70
300
G032
Figure 37. Common-Mode Rejection Ratio vs
Test Signal Frequency
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Typical Characteristics: ADS42JB46 (continued)
Typical values are at TA = +25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 64k-point FFT, unless otherwise noted.
0
0
−20
−10
−20
PSRR (dB)
−40
Amplitude (dBFS)
50−mVPP Signal Superimposed on AVDD
100−mVPP Signal Superimposed on AVDD3V
FIN = 70 MHz
SFDR = 84 dBc
fPSRR = 5 MHz, 50m VPP
fIN Amplitude = −1 dBFS
fPSRR Amplitude = −96 dBFS
fIN + fPSRR Amplitude = −85.6 dBFS
fIN − fPSRR Amplitude = −95.4 dBFS
−60
−30
−40
−80
−50
−100
−60
Input Frequency = 170MHz
−120
0
10
20
30
40
50
60
70
Frequency (MHz)
−70
80
50
100
150
200
250
300
Test Signal Frequency on Supply (MHz)
G033
Figure 38. Power-Supply Rejection Ratio FFT for AVDD
Supply
G034
Figure 39. Power-Supply Rejection Ratio vs
Test Signal Frequency
0.18
1.8
AVDD Power
DVDD Power
IOVDD Power
AVDD3V Power
Total Power
1.6
1.4
20X Mode
10X Mode
0.15
IOVDD Power (W)
1.2
Total Power (W)
0
1
0.8
0.6
0.12
0.09
0.06
0.4
0.03
0.2
0
0
20
40
60
80
100
120
Sampling Speed (MSPS)
140
0
160
Figure 40. Total Power vs Sampling Frequency
0
20
40
60
80
100
Sampling Speed (MSPS)
G035
120
140
160
G036
Figure 41. Analog Power vs Sampling Frequency
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7.12 Typical Characteristics: Contour
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 160 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 64k-point FFT, unless otherwise noted.
7.12.1 Spurious-Free Dynamic Range (SFDR)
160
fS - Sampling Frequency - MSPS
150
90
85
80
70
75
90
95
140
90
65
130
120
95
90
90
85
80
85
80
70
75
110
100
90
95
80
90
150
100
50
200
250
75
70
300
400
350
fIN - Input Frequency - MHz
70
65
75
80
85
90
95
SFDR - dBc
Figure 42. 0-dB Gain (SFDR)
160
95
95
fS - Sampling Frequency - MSPS
150
95
90
70
75
80
85
95
140
130
95
120
95
110
90
85
75
80
70
95
100
90
80
95
95
95
100
200
90
85
75
80
300
70
400
500
600
85
90
95
fIN - Input Frequency - MHz
70
75
80
SFDR - dBc
Figure 43. 6-dB Gain (SFDR)
20
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7.12.2 Signal-to-Noise Ratio (SNR)
160
73.5
fS - Sampling Frequency - MSPS
150
72.5
73
71.5
72
71
140
130
120
73.5
72.5
73
71.5
72
71
110
100
90
70.5
73.5
74
80
150
100
50
72.5
73
71.5
72
200
250
71
300
350
400
73
73.5
74
fIN - Input Frequency - MHz
70.5
71.5
71
72.5
72
SNR - dBFS
Figure 44. 0-dB Gain
160
fS - Sampling Frequency - MSPS
150
140
67.5
67.8
67.2
66.9
66.6
66.3
68.1
130
120
67.8
68.1
67.5
67.2
66.9
66.6
66.3
66
110
100
90
68.4
80
68.1
100
67.8
200
67.2
67.5
300
66.6
66.9
400
66.6
66
500
65.7
600
fIN - Input Frequency - MHz
65.5
66
66.5
67
67.5
68
SNR - dBFS
Figure 45. 6-dB Gain
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8 Detailed Description
8.1 Overview
The ADS42JB46 is a highly linear, buffered analog input, dual-channel, analog-to-digital converter (ADC) with
maximum sampling rate of 160 MSPS and JESD204B digital interface. The conversion process is initiated by a
rising edge of the external input clock which samples the analog input signal. The sampled signal is sequentially
converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At
every clock edge, the sample propagates through the pipeline, resulting in a data latency of 23 clock cycles. The
output is available in CML logic levels conforming to the JESD204B standard.
8.2 Functional Block Diagram
Device
14-, 16-Bit
ADC
INAP,
INAM
OVRA
Digital
Block
Gain
Test Modes
Divide
by 1, 2, 4
CLKINP,
CLKINM
SYSREFP,
SYSREFM
DA0P,
DA0M
JESD204B
Digital
DA1P,
DA1M
PLL
x10, x20
SYNC-P,
SYNC-M
Delay
14-, 16-Bit
ADC
INBP,
INBM
Digital
Block
DB0P,
DB0M
JESD204B
Digital
DB1P,
DB1M
Gain
Test Modes
OVRB
Common
Mode
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STBY
CTRL2
MODE
CTRL1
SDATA
SDOUT
PDN
PDN_GBL
SEN
SCLK
Device Configuration
RESET
VCM
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8.3 Feature Description
8.3.1 Digital Gain
The device includes gain settings that can be used to obtain improved SFDR performance (compared to no
gain). Gain is programmable from –2 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input fullscale range scales proportionally. Table 1 shows how full-scale input voltage changes when digital gains are
programmed in 1-dB steps. Refer to Table 13 to set digital gain with a serial interface register.
SFDR improvement is achieved at the expense of SNR; for a 1-dB increase in digital gain, SNR degrades
approximately between 0.5 dB and 1 dB. Therefore, gain can be used as a trade-off between SFDR and SNR.
Note that the default gain after reset is 0 dB with a 2.0-VPP full-scale voltage.
Table 1. Full-Scale Range Across Gains
(1)
DIGITAL GAIN
FULL-SCALE INPUT VOLTAGE
–2 dB
2.5 VPP (1)
–1 dB
2.2 VPP
0 dB (default)
2.0 VPP
1 dB
1.8 VPP
2 dB
1.6 VPP
3 dB
1.4 VPP
4 dB
1.25 VPP
5 dB
1.1 VPP
6 dB
1.0 VPP
Shaded cells indicate performance settings used in the Electrical
Characteristics and Typical Characteristics.
8.3.2 Overrange Indication
The device provides two different overrange indications. Normal OVR (default) is triggered if the final 16-bit data
output exceeds the maximum code value. Fast OVR is triggered if the input voltage exceeds the programmable
overrange threshold and is presented after only nine clock cycles, thus enabling a quicker reaction to an
overrange event. By default, the normal overrange indication is output on the OVRA and OVRB pins. Using the
FAST OVR EN register bit, the fast OVR indication can be presented on the overrange pins instead.
The input voltage level at which the overload is detected is the threshold and is programmable using the FAST
OVR THRESHOLD bits. FAST OVR is triggered nine output clock cycles after the overload condition occurs. The
threshold voltage amplitude at which fast OVR is triggered is described in Equation 1:
1 × [the decimal value of the FAST OVR THRESH bits] / 127
(1)
When digital is programmed (for gain values > 0 dB ), the threshold voltage amplitude is as given in Equation 2:
10–Gain / 20 × [the decimal value of the FAST OVR THRESH bits] / 127
(2)
8.3.3 Input Clock Divider
The device is equipped with an internal divider on the clock input. By default, the clock divider is set to divide-by1 operation. The divide-by-2 option supports a maximum 500-MHz input clock and the divide-by-4 option
supports a maximum 1-GHz input clock frequency. A 320-MHz input clock with the divide-by-2 option and a 640MHz input clock with the divide-by-4 option can be accepted because the maximum conversion rate of the device
is 160 MSPS.
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8.3.4 Pin Controls
The device power-down functions can be controlled either through the parallel control pins (STBY, PDN_GBL,
CTRL1, and CTRL2) or through an SPI register setting. Table 2, Table 3, and Table 4 describe the parallel
control pin functionality.
STBY places the device in a standby power-down mode. PDN_GBL places the device in global power-down
mode.
Table 2. CTRL1, CTRL2 Pin Functions
CTRL1
CTRL2
Low
Low
Normal operation
DESCRIPTION
High
Low
Channel A powered down
Low
High
Channel B powered down
High
High
Global power-down
Table 3. PDN_GBL Pin Function
PDN_GBL
DESCRIPTION
Low
Normal operation
High
Global power-down. Wake-up from this mode is slow.
Table 4. STBY Pin Function
STBY
DESCRIPTION
Low
Normal operation
High
The ADCs are powered down while the input clock buffer and output CML
buffers are alive. Wake-up from this mode is fast.
8.4 Device Functional Modes
8.4.1 JESD204B Interface
The JESD interface of the device, as shown in Figure 46 , supports device subclasses 0, 1, and 2 with a
maximum output data rate (per lane) of 3.125 Gbps. An external SYSREF (subclass 1) or SYNC~ (subclass 2)
signal is used to align all internal clock phases and the local multiframe clock to a specific sampling clock edge.
This alignment allows synchronization of multiple devices in a system and minimizes timing and alignment
uncertainty.
SYSREF SYNC~
INA
JESD
204B
JESD204B
D0, D1
INB
JESD
204B
JESD204B
D0, D1
Sample
Clock
Figure 46. JESD204B Interface
Depending on the ADC sampling rate, the JESD204B output interface can be operated with either one or two
lanes per ADC. The JESD204B interface can be configured with serial registers.
24
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Device Functional Modes (continued)
The JESD204B transmitter block (as shown in Figure 47) consists of the transport layer, data scrambler, and link
layer. The transport layer maps the ADC output data into the selected JESD204B frame data format and
determines whether the ADC output data or test patterns are transmitted. The link layer performs the 8b and 10b
data encoding as well as the synchronization and initial lane alignment using the SYNC~ input signal. Optionally,
data from the transport layer can be scrambled.
JESD204B Block
Transport Layer
Link Layer
Frame Data
Mapping
8b,10b
encoding
Scrambler
1+x14+x15
D0
Comma characters
Initial lane alignment
Test Patterns
D1
SYNC~
Figure 47. JESD204B Block
8.4.1.1 JESD204B Initial Lane Alignment (ILA)
When receiving, the device asserts the SYNC~ signal (that is, a logic low signal is applied on SYNC~P and
SYNC~M). The device then begins transmitting comma (K28.5) characters to establish the code group
synchronization (CGS). When synchronization completes, the receiving device de-asserts the SYNC~ signal and
the device begins the initial lane alignment (ILA) sequence with the next local multiframe clock boundary. The
device transmits four multiframes, each containing K frames (where K is SPI programmable). Each multiframe
contains the frame start and end symbols; the second multiframe also contains the JESD204 link configuration
data.
8.4.1.2 JESD204B Test Patterns
There are three different test patterns available in the transport layer of the JESD204B interface. The device
supports a clock output pattern, an encoded pattern, and a PRBS (215 – 1) pattern. These patterns can be
enabled by a serial register write in register 26h, bits D[7:6].
8.4.1.3 JESD204B Frame Assembly
The JESD204B standard defines the following parameters:
• L is the number of lanes per lane.
• M is the number of converters per device.
• F is the number of octets per frame clock period.
• S is the number of samples per frame.
Table 5 lists the available JESD204B formats and valid device ranges. Ranges are limited by the maximum ADC
sample frequency and the SERDES line rate.
Table 5. JESD240B Ranges
L
M
F
S
MAX ADC SAMPLING RATE (MSPS)
4
2
1
1
160
MAX fSERDES (Gbps)
1.6
2
2
2
1
156.25
3.125
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The detailed frame assembly in 10x and 20x modes for dual-channel operation is shown in Table 6. Note that
unused lanes in 10x mode become 3-stated.
Table 6. Frame Assembly for Dual-Channel Mode (1)
LANE
(1)
LMF = 421
LMF = 222
DA0
A0[15:8]
A1[15:8]
A2[15:8]
A0[15:8]
A0[7:0]
A1[15:8]
A1[7:0]
A2[15:8]
DA1
A0[7:0]
A1[7:0]
A2[7:0]
—
—
—
—
—
A2[7:0]
—
DB0
B0[15:8]
B1[15:8]
B2[15:8]
B0[15:8]
B0[7:0]
B1[15:8]
B1[7:0]
B2[15:8]
B2[7:0]
DB1
B0[7:0]
B1[7:0]
B2[7:0]
—
—
—
—
—
—
Two LSBs of the 16-bit data are padded with '00' in the device.
Table 7. High-Frequency Modes Summary
REGISTER
ADDRESS
VALUE
Dh
90h
High-frequency modes should be enabled for input frequencies greater than 250 MHz.
Eh
90h
High-frequency modes should be enabled for input frequencies greater than 250 MHz.
DESCRIPTION
8.4.1.4 JESD Link Configuration
During the lane alignment sequence, the device transmits JESD204B configuration parameters in the second
multiframe of the ILA sequence. Configuration bits are mapped in octets, as per the JESD204B standard
described in Figure 48 and Table 8.
Figure 48. Initial Lane Alignment Sequence
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Table 8. Mapping of Configuration Bits to Octets
OCTET NO
MSB
D6
D5
0
D4
D3
1
ADJCNT[3:0]
2
X
3
SCR[0]
ADJDIR[0]
D1
LSB
BID[3:0]
PHADJ[0]
LID[4:0]
L[4:0]
4
F[7:0]
5
K[4:0]
6
M[7:0]
7
CS[1:0]
X
8
SUBCLASSV[2:0]
9
JESDV[2:0]
10
D2
DID [7:0]
HD[0]
X
11
N[4:0]
N'[4:0]
S[4:0]
X
CF[4:0]
RES1[7:0]
12
RES2[7:0]
13
FCHK[7:0]
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8.4.1.4.1 Configuration for 2-Lane (20x) SERDES Mode
Table 9 lists the values of the JESD204B configuration bits applicable for the 2-lane SERDES mode. The default
value of these bits after reset is also specified in Table 9.
Table 9. Configuration for 2-Lane SERDES Mode
PARAMETER
DESCRIPTION
PARAMETER
RANGE
FIELD
ENCODING
DEFAULT
VALUE AFTER
RESET
ADJCNT
Number of adjustment resolution steps to adjust
the DAC LMFC. Applies to subclass 2 operation
only.
0:15
ADJCNT[3:0]
Binary value
0
ADJDIR
Direction to adjust the DAC LMFC.
0 = Advance
1 = Delay applies to subclass 2 operation only
0:1
ADJDIR[0]
Binary value
0
BID
Bank ID: extension to DID
0:15
BID[3:0]
Binary value
0
CF
Number of control words per frame clock period
per link
0:32
CF[4:0]
Binary value
0
CS
Number of control bits per sample
0:3
CS[1:0]
Binary value
0
DID
Device (= link) identification number
0:255
DID[7:0]
Binary value
0
1:256
F[7:0]
Binary value
minus 1
1
High-density format
0:1
HD[0]
Binary value
0
JESD204 version
000 = JESD204A
001 = JESD204B
0:7
JESDV[2:0]
Binary value
1
K
Number of frames per multiframe
1:32
K[4:0]
Binary value
minus 1
8
L
Number of lanes per converter device (link)
1:32
L[4:0]
Binary value
minus 1
0
Lane identification number (within link)
0:31
LID[4:0]
Binary value
LID[0] = 0,
LID[1] = 1
M
Number of converters per device
1:256
M[7:0]
Binary value
minus 1
1
N
Converter resolution
1:32
N[4:0]
Binary value
minus 1
15
N’
Total number of bits per sample
1:32
N'[4:0]
Binary value
minus 1
15
Phase adjustment request to DAC subclass 2 only
0:1
PHADJ[0]
Binary value
0
0
F
HD
JESDV
LID
PHADJ
Number of octets per frame
Number of samples per converter per frame cycle
1:32
S[4:0]
Binary value
minus 1
Scrambling enabled
0:1
SCR[0]
Binary value
0
SUBCLASSV
Device subclass version
000 = Subclass 0
001 = Subclass 1
010 = Subclass 2
0:7
SUBCLASSV[2:
0]
Binary value
2
RES1
Device subclass version
000 = Subclass 0
001 = Subclass 1
010 = Subclass 2
0:255
RES1[7:0]
Binary value
0
RES2
Reserved field 2
0:255
RES2[7:0]
Binary value
0
Checksum Σ (all above fields) mod 256
0:255
FCHK[7:0]
Binary value
44, 45
S
SCR
CHKSUM
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8.4.1.4.2 Configuration for 4-Lane (10x) SERDES Mode
Table 10 lists the values of the JESD204 configuration bits applicable for the 4-lane SERDES mode. The default
value of these bits after reset is also specified in Table 10.
Table 10. Configuration for 4-Lane SERDES Mode
PARAMETER
DESCRIPTION
PARAMETER
RANGE
FIELD
ENCODING
DEFAULT
VALUE AFTER
RESET
ADJCNT
Number of adjustment resolution steps to adjust
the DAC LMFC. Applies to subclass 2 operation
only.
0:15
ADJCNT[3:0]
Binary value
0
ADJDIR
Direction to adjust the DAC LMFC.
0 = Advance
1 = Delay applies to subclass 2 operation only
0:1
ADJDIR[0]
Binary value
0
BID
Bank ID: extension to DID
0:15
BID[3:0]
Binary value
0
CF
Number of control words per frame clock period
per link
0:32
CF[4:0]
Binary value
0
CS
Number of control bits per sample
0:3
CS[1:0]
Binary value
0
DID
Device (= link) identification number
0:255
DID[7:0]
Binary value
0
1:256
F[7:0]
Binary value
minus 1
0
High-density format
0:1
HD[0]
Binary value
1
JESD204 version
000 = JESD204A
001 = JESD204B
0:7
JESDV[2:0]
Binary value
1
K
Number of frames per multiframe
1:32
K[4:0]
Binary value
minus 1
16
L
Number of lanes per converter device (link)
1:32
L[4:0]
Binary value
minus 1
3
Lane identification number (within link)
0:31
LID[4:0]
Binary value
LID[0] = 0,
LID[1] = 1,
LID[2] = 2,
LID[3] = 3
M
Number of converters per device
1:256
M[7:0]
Binary value
minus 1
1
N
Converter resolution
1:32
N[4:0]
Binary value
minus 1
15
N’
Total number of bits per sample
1:32
N'[4:0]
Binary value
minus 1
15
PHADJ
Phase adjustment request to DAC subclass 2 only
0:1
PHADJ[0]
Binary value
0
S
Number of samples per converter per frame cycle
1:32
S[4:0]
Binary value
minus 1
0
Scrambling enabled
0:1
SCR[0]
Binary value
0
SUBCLASSV
Device subclass version
000 = Subclass 0
001 = Subclass 1
010 = Subclass 2
0:7
SUBCLASSV[2:
0]
Binary value
2
RES1
Device subclass version
000 = Subclass 0
001 = Subclass 1
010 = Subclass 2
0:255
RES1[7:0]
Binary value
0
RES2
Reserved field 2
0:255
RES2[7:0]
Binary value
0
Checksum Σ (all above fields) mod 256
0:255
FCHK[7:0]
Binary value
54, 55, 56, 57
F
HD
JESDV
LID
SCR
CHKSUM
Number of octets per frame
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Table 11. Latency in Different Modes (1) (2)
MODE
10x
20x
LATENCY (N Cycles)
TYPICAL DATA DELAY (tD, ns)
ADC latency
PARAMETER
23
0.65 × tS + 3
Normal OVR latency
14
6.7
Fast OVR latency
9
6.7
From SYNC~ falling edge to CGS phase (3)
16
0.65 × tS + 3
From SYNC~ rising edge to ILA sequence (4)
25
0.65 × tS + 3
ADC latency
22
0.85 × tS + 3
Normal OVR latency
14
6.7
Fast OVR latency
9
6.7
15
0.85 × tS + 3
16
0.85 × tS + 3
From SYNC~ falling edge to CGS phase
(3)
From SYNC~ rising edge to ILA sequence (4)
(1)
(2)
(3)
(4)
Overall latency = latency + tD.
tS is the time period of the ADC conversion clock.
Latency is specified for subclass 2. In subclass 0, the SYNC~ falling edge to CGS phase latency is 16 clock cycles in 10x mode and 15
clock cycles in 20x mode.
Latency is specified for subclass 2. In subclass 0, the SYNC~ rising edge to ILA sequence latency is 11 clock cycles in 10x mode and
11 clock cycles in 20x mode.
8.4.1.5 CML Outputs
The device JESD204B transmitter uses differential CML output drivers. The CML output current is programmable
from 5 mA to 20 mA using register settings.
The output driver includes an internal 50-Ω termination to the IOVDD supply. External 50-Ω termination resistors
connected to the receiver common-mode voltage should be placed close to the receiver pins. AC-coupling can
be used to avoid the common-mode mismatch between the transmitter and receiver, as shown in Figure 49.
Vterm
Rt= ZO
Transmission Line
Zo
Rt= ZO
0.1uF
DA/B[0,1]P
Receiver
DA/B[0,1]M
0.1uF
Figure 49. CML Output Connections
Figure 50 shows the data eye measurements of the device JESD204B transmitter against the JESD204B
transmitter mask at 3.125 Gbps (20x mode).
30
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300
Voltage (mV)
150
0
-150
-300
-200
-150
-100
-50
0
50
100
150
200
Time (ps)
Figure 50. Eye Diagram: 3.125 Gbps
8.5 Programming
The ADS42JB46 can be configured using a serial programming interface, as described in the Serial Interface
section. In addition, the device has four dedicated parallel pins (PDN_GBL, STBY, CTRL1, and CTRL2) for
controlling the power-down modes.
8.5.1 Serial Interface
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data
output) pins. Serially shifting bits into the device is enabled when SEN is low. SDATA serial data are latched at
every SCLK rising edge when SEN is active (low). Serial data are loaded into the register at every 16th SCLK
rising edge when SEN is low. When the word length exceeds a multiple of 16 bits, the excess bits are ignored.
Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The interface functions with
SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty
cycle.
8.5.1.1 Register Initialization
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin (of widths greater than 10 ns), as shown in Figure 2. During operation,
the serial interface registers can be cleared (if required) either by:
1. A hardware reset or
2. By applying a software reset. When using the serial interface, set the RESET bit (register 08h, bit D0) high.
This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In
this case, the RESET pin remains low.
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Programming (continued)
8.5.1.2 Serial Register Write
The internal device register can be programmed following these steps:
1. Drive the SEN pin low.
2. Set the R/W bit to ‘0’ (bit A7 of the 8-bit address).
3. Set bit A6 in the address field to ‘0’.
4. Initiate a serial interface cycle specifying the address of the register (A5 to A0) whose content must be
written (as shown in Figure 1 and ).
5. Write the 8-bit data that are latched on the SCLK rising edge.
32
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Programming (continued)
8.5.1.3 Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back. This readback mode
may be useful as a diagnostic check to verify the serial interface communication between the external controller
and the ADC.
1. Set the MSB of the 8-bit address A7 to '1'.
2. Write the register address on bits A5 through A0 whose contents must be read. See Figure 51.
3. The device outputs the contents (D[7:0]) of the selected register on the SDOUT pin (pin 45).
4. The external controller can latch the contents at the SCLK rising edge.
When serial registers are enabled for writing (when bit A7 of the 8-bit address bus is '0'), the SDOUT pin is in a
high-impedance mode. If serial readout is not used, the SDOUT pin must float. Figure 51 shows a timing diagram
of this readout mode. SDOUT comes out at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20
ns, as shown in Figure 52.
Register Address <5:0>
SDATA
R/W
0
A5
A4
A3
A2
A1
Register Data: don’t care
A0
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
=1
Register Read Data <7:0>
SDOUT
D7
D6
D5
D4
D3
D2
SCLK
SEN
Figure 51. Serial Register Readout Timing Diagram
SCLK
tSD_DELAY
SDOUT
Figure 52. SDOUT Timing Diagram
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8.6 Register Maps
8.6.1 Summary of Serial Interface Registers
Table 12 lists the device registers.
Table 12. Register Map
REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
06
0
0
0
0
0
0
07
0
0
0
0
0
STDBY
DATA
FORMAT
Always write 1
08
PDN CHA
PDN CHB
D0
CLK DIV
SYSREF DELAY
0
0
RESET
0
0B
CHA GAIN
CHA GAIN EN
0
0C
CHBGAIN
CHB GAIN EN
0
0
0
0
FAST OVR EN
0
0
0
0D
HIGH FREQ 1
0E
HIGH FREQ 2
0F
0
0
HIGH FREQ 1
0
0
0
HIGH FREQ 2
0
CHA TEST PATTERNS
CHB TEST PATTERNS
10
CUSTOM PATTERN[15:8]
11
CUSTOM PATTERN[15:8]
12
CUSTOM PATTERN[15:8]
13
1F
26
CUSTOM PATTERN[15:8]
Always write 0
FAST OVR THRESHOLD
SERDES TEST PATTERN
IDLE SYNC
TESTMODE
EN
FLIP ADC
DATA
LAN ALIGN
FRAME ALIGN
TX LINK
CONFIG DATA0
CTRLF
27
0
0
0
0
0
0
CTRLK
2B
SCRAMBLE EN
0
0
0
0
0
0
0
0
OCTETS PER
FRAME
0
0
2C
0
2D
0
0
0
0
0
30
SUBCLASS
36
LMFC RESET
MASK
37
38
34
D1
SYNC REQ
LINK LAYER TESTMODE
FORCE LMFC
COUNT
0
0
0
0
0
0
FRAMES PER MULTIFRAME
0
LINK LAYER
RPAT
0
OUTPUT CURRENT SEL
0
LMFC COUNT INIT
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8.6.2 Description of Serial Interface Registers
8.6.2.1 Register Address 06
Figure 53. Register Address 06
REGISTER
ADDRESS
A[7:0] (Hex)
06
REGISTER DATA
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
D2
0
D1
D0
SYSREF DELAY
CLK DIV
Default: 00h
D[1:0]
CLK DIV
00
Divide-by-1 (clock divider bypassed)
Internal clock divider for input sample clock
01
Divide-by-2
10
Divide-by-1
11
Divide-by-4
8.6.2.2 Register Address 07
Figure 54. Register Address 07
REGISTER
ADDRESS
A[7:0] (Hex)
07
REGISTER DATA
D7
0
D6
0
D5
0
D4
0
D3
0
Default: 00h
D[2:0]
SYSREF DELAY
Controls the delay of the SYSREF input with respect to the input clock.
Typical values for the expected delay of different settings are:
000
0-ps delay
001
60-ps delay
010
120-ps delay
011
180-ps delay
100
240-ps delay
101
300-ps delay
110
360-ps delay
111
420-ps delay
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8.6.2.3 Register Address 08
Figure 55. Register Address 08
REGISTER
ADDRESS
A[7:0] (Hex)
D7
D6
D5
08
PDN CHA
PDN CHB
STDBY
REGISTER DATA
D4
DATA
FORMAT
D3
Always write
1
D2
D1
D0
0
0
RESET
Default: 00h
D7
PDN CHA
Power-down channel A
0
Normal operation
1
Channel A power down
D6
PDN CHB
0
Normal operation
1
Channel B power down
D5
STBY
0
Normal operation
1
Both ADCs are powered down (input clock buffer and CML output buffers are alive)
D4
DATA
FORMAT
0
Twos complement
1
Offset binary
D3
Always write 1
Power-down channel B
Dual ADC is placed into standby mode
Digital output data format
Default value of this bit is '0'. This bit must always be set to '1'.
D0
RESET
Software reset applied
This bit resets all internal registers to the default values and self-clears to ‘0’.
36
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8.6.2.4 Register Address 0B
Figure 56. Register Address 0B
REGISTER
ADDRESS
A[7:0] (Hex)
0B
REGISTER DATA
D7
D6
D5
CHA GAIN
D4
D3
D2
CHA GAIN EN
D1
0
D0
0
Default: 00h
D[7:3]
CHA GAIN
Digital gain for channel A (must set the CHA GAIN EN bit first, bit D2)
Table 13. Digital Gain for Channel A
DIGITAL GAIN
FULL-SCALE
INPUT VOLTAGE
REGISTER VALUE
DIGITAL GAIN
FULL-SCALE
INPUT VOLTAGE
00000
0 dB
2.0 VPP
01010
1.5 dB
1.7 VPP
00001
Do not use
—
01011
2 dB
1.6 VPP
00010
Do not use
—
01100
2.5 dB
1.5 VPP
00011
–2.0 dB
2.5 VPP
01101
3 dB
1.4 VPP
00100
–1.5 dB
2.4 VPP
01110
3.5 dB
1.3 VPP
00101
–1.0 dB
2.2 VPP
01111
4 dB
1.25 VPP
00110
–0.5 dB
2.1 VPP
10000
4.5 dB
1.2 VPP
00111
0 dB
2.0 VPP
10001
5 dB
1.1 VPP
01000
0.5 dB
1.9 VPP
10010
5.5 dB
1.05 VPP
01001
1 dB
1.8 VPP
10011
6 dB
1.0 VPP
REGISTER VALUE
D2
0
1
CHA GAIN EN
Digital gain enable bit for channel A
Digital gain disabled
Digital gain enabled
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8.6.2.5 Register Address 0C
Figure 57. Register Address 0C
REGISTER
ADDRESS
A[7:0] (Hex)
REGISTER DATA
D7
D6
0C
D5
D4
D3
D2
CHB GAIN
EN
CHB GAIN
Default: 00h
D[7:3]
CHB GAIN
D1
D0
0
0
Digital gain for channel B (must set the CHA GAIN EN bit first, bit D2)
Table 14. Digital Gain for Channel B
DIGITAL GAIN
FULL-SCALE
INPUT VOLTAGE
REGISTER VALUE
DIGITAL GAIN
FULL-SCALE
INPUT VOLTAGE
00000
0 dB
2.0 VPP
01010
1.5 dB
1.7 VPP
00001
Do not use
—
01011
2 dB
1.6 VPP
00010
Do not use
—
01100
2.5 dB
1.5 VPP
00011
–2.0 dB
2.5 VPP
01101
3 dB
1.4 VPP
00100
–1.5 dB
2.4 VPP
01110
3.5 dB
1.3 VPP
00101
–1.0 dB
2.2 VPP
01111
4 dB
1.25 VPP
00110
–0.5 dB
2.1 VPP
10000
4.5 dB
1.2 VPP
00111
0 dB
2.0 VPP
10001
5 dB
1.1 VPP
01000
0.5 dB
1.9 VPP
10010
5.5 dB
1.05 VPP
01001
1 dB
1.8 VPP
10011
6 dB
1.0 VPP
REGISTER VALUE
D2
0
1
CHB GAIN EN
Digital gain disabled
Digital gain enabled
Digital gain enable bit for channel B
8.6.2.6 Register Address 0D
Figure 58. Register Address 0D
REGISTER
ADDRESS
A[7:0] (Hex)
0D
REGISTER DATA
D7
HIGH FREQ
1
D6
D5
0
0
D4
HIGH FREQ
1
D3
D2
D1
D0
0
0
0
FAST OVR EN
D7, D4
00
11
HIGH FREQ 1
High-frequency mode 1
Default
Use for input frequencies > 250 MHz along with HIGH FREQ 2
D0
0
1
FAST OVR EN
Selects if normal or fast OVR signal is presented on OVRA, OVRB pins
Normal OVR on OVRA, OVRB pins
Fast OVR on OVRA, OVRB pins
38
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8.6.2.7 Register Address 0E
Figure 59. Register Address 0E
REGISTER
ADDRESS
A[7:0] (Hex)
0E
D7, D4
00
11
REGISTER DATA
D7
HIGH FREQ
2
D6
D5
0
0
D4
HIGH FREQ
2
D3
D2
D1
D0
0
0
0
0
HIGH FREQ 2
High-frequency mode 2
Default
Use for input frequencies > 250 MHz along with HIGH FREQ 1
8.6.2.8 Register Address 0F
Figure 60. Register Address 0F
REGISTER
ADDRESS
A[7:0] (Hex)
0F
REGISTER DATA
D7
D6
D5
CHA TEST PATTERNS
D4
D3
D2
D1
CHB TEST PATTERNS
D0
Default: 00h
D[7:4]
CHA TEST PATTERNS
Channel A test pattern programmability
The 16-bit test pattern data are selected as the input to the JESD block (the last two LSBs of the 16-bit data are replaced by '00').
0000
Normal operation
0001
All '0's
0010
All '1's
0011
Toggle pattern:
Data alternate between 10101010101010 and 01010101010101.
0100
Digital ramp:
Data increment by 1 LSB every fourth clock cycle from code 0 to 16383.
0101
Do not use
0110
Single pattern:
Data are the same as that programmed by the CUSTOM PATTERN 1[15:2] register bits.
0111
Double pattern:
Data alternate between CUSTOM PATTERN 1[15:2] and CUSTOM PATTERN 2[15:2].
1000
Deskew pattern:
Data are AAA8h.
1001
Do not use
1010
PRBS pattern:
Data are a sequence of pseudo random numbers.
1011
8-point sine wave:
Data are a repetitive sequence of the following eight numbers, forming a sine-wave in twos
complement format:
0, 2399, 8192, 13984, 16383, 13984, 8192, 2399.
D3-D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
CHB TEST PATTERNS
Channel B test pattern programmability
The 16-bit test pattern data are selected as the input to the JESD block (the last two LSBs of the 16-bit data are replaced by '00').
Normal operation
All '0's
All '1's
Toggle pattern:
Data alternate between 10101010101010 and 01010101010101.
Digital ramp:
Data increment by 1 LSB every fourth clock cycle from code 0 to 16383.
Do not use
Single pattern:
Data are the same as that programmed by the CUSTOM PATTERN 1[15:2] register bits.
Double pattern:
Data alternate between CUSTOM PATTERN 1[15:2] and CUSTOM PATTERN 2[15:2].
Deskew pattern:
Data are AAA8h.
Do not use
PRBS pattern:
Data are a sequence of pseudo random numbers.
8-point sine wave:
Data are a repetitive sequence of the following eight numbers, forming a sine-wave in twos
complement format:
0, 2399, 8192, 13984, 16383, 13984, 8192, 2399.
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8.6.2.9 Register Address 10
Figure 61. Register Address 10
REGISTER
ADDRESS
A[7:0] (Hex)
10
REGISTER DATA
D7
D6
Default: 00h
D[7:0]
CUSTOM PATTERN 1[15:8]
D5
D4
D3
CUSTOM PATTERN 1[15:8]
D2
D1
D0
D2
D1
D0
D2
D1
D0
D2
D1
D0
These bits set the custom pattern 1[15:8] for both channels.
8.6.2.10 Register Address 11
Figure 62. Register Address 11
REGISTER
ADDRESS
A[7:0] (Hex)
REGISTER DATA
D7
D6
D5
11
D4
D3
CUSTOM PATTERN 1[7:0]
Default: 00h
D[7:0]
CUSTOM PATTERN 1[7:0]
These bits set the custom pattern 1[7:0] for both channels.
8.6.2.11 Register Address 12
Figure 63. Register Address 12
REGISTER
ADDRESS
A[7:0] (Hex)
12
REGISTER DATA
D7
D6
Default: 00h
D[7:0]
CUSTOM PATTERN 2[15:8]
D5
D4
D3
CUSTOM PATTERN 2[15:8]
These bits set the custom pattern 2[15:8] for both channels.
8.6.2.12 Register Address 13
Figure 64. Register Address 13
REGISTER
ADDRESS
A[7:0] (Hex)
13
REGISTER DATA
D7
D6
Default: 00h
D[7:0]
CUSTOM PATTERN 2[7:0]
40
D5
D4
D3
CUSTOM PATTERN 2[7:0]
These bits set the custom pattern 2[7:0] for both channels.
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8.6.2.13 Register Address 1F
Figure 65. Register Address 1F
REGISTER
ADDRESS
A[7:0] (Hex)
1F
REGISTER DATA
D7
Always write 0
D6
D5
D4
D3
D2
FAST OVR THRESHOLD
D1
D0
Default: FFh
D7
Always write 0
Default value of this bit is '1'. Always write this bit to '0' when the fast OVR thresholds are programmed.
D[6:0]
FAST OVR THRESHOLD
The device has a fast OVR mode that indicates an overload condition at the ADC input. The input voltage level at which the
overload is detected is referred to as the threshold and is programmable using the FAST OVR THRESHOLD bits. FAST OVR is
triggered nine output clock cycles after the overload condition occurs. The threshold at which fast OVR is triggered is (full-scale ×
[the decimal value of the FAST OVR THRESHOLD bits] / 127). See the Overrange Indication section for details.
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8.6.2.14 Register Address 26
Figure 66. Register Address 26
REGISTER
ADDRESS
A[7:0] (Hex)
26
REGISTER DATA
D7
D6
SERDES TEST
PATTERN
D5
IDLE SYNC
D4
TESTMODE
EN
D3
FLIP ADC
DATA
D2
LANE ALIGN
D1
FRANE
ALIGN
D0
TX LINK CONFIG
DATA
Default: 00h
D[7:6]
SERDES TEST PATTERN
Sets test patterns in the transport layer of the JESD204B interface.
00
Normal operation
01
Outputs clock pattern:
Output is in a 10101010 pattern
10
Encoded pattern:
Output is 1111111100000000
11
PRBS sequence:
Output is 215 – 1
D5
0
IDLE SYNC
Sets the output pattern when SYNC~ is asserted.
Sync code is k28.5 (0xBCBC)
1
Sync code is 0xBC50
D4
TESTMODE EN
0
1
Test mode disabled
Test mode enabled
D3
0
1
FLIP ADC DATA
Normal operation
Output data order is
reversed:
D2
LANE ALIGN
0
1
Lane alignment characters
are not inserted.
Inserts lane alignment characters
D1
FRAME ALIGN
0
Frame alignment
characters are not
inserted.
Inserts frame alignment
characters
1
D0
0
1
42
TX LINK CONFIG DATA
ILA enabled
ILA disabled
Generates a long transport layer test pattern mode according to clause 5.1.63 of the JESD204B
specification.
MSB – LSB
Inserts a lane alignment character (K28.3) for the receiver to align to the lane boundary, as per
section 5.3.3.5 of the JESD204B specification.
Inserts a frame alignment character (K28.7) for the receiver to align to the frame boundary, as per
section 5.3.3.4 of the JESD204B specification.
Disables sending the initial link alignment (ILA) sequence when SYNC~ is de-asserted, '0'.
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8.6.2.15 Register Address 27
Figure 67. Register Address 27
REGISTER
ADDRESS
A[7:0] (Hex)
27
REGISTER DATA
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
CTRL K
D0
CTRL F
D2
0
D1
0
D0
0
Default: 00h
D1
CTRL K
Enables bit for number of frames per multiframe.
0
Default
1
Frames per multiframe can be set in register 2Dh
D0
0
1
CTRL F
Enables bit for number of octets per frame.
Default
Octets per frame can be specified in register 2Ch
8.6.2.16 Register Address 2B
Figure 68. Register Address 2B
REGISTER
ADDRESS
A[7:0] (Hex)
2B
REGISTER DATA
D7
SCRAMBLE EN
D6
0
D5
0
D4
0
D3
0
Default: 00h
D7
SCRAMBLE EN
Scramble enable bit in the JESD204B interface
0
Scrambling disabled
1
Scrambling enabled
8.6.2.17 Register Address 2C
Figure 69. Register Address 2C
REGISTER
ADDRESS
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
2C
0
0
0
0
0
0
0
REGISTER DATA
D0
OCTETS PER
FRAME
Default: 00h
D[7:0]
OCTETS PER FRAME
Sets number of octets per frame (F).
0
10x mode using two lanes per ADC
1
20x mode using one lane per ADC
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8.6.2.18 Register Address 2D
Figure 70. Register Address 2D
REGISTER
ADDRESS
A[7:0] (Hex)
2D
REGISTER DATA
D7
0
D6
0
D5
0
D4
D3
D2
D1
FRAMES PER MULTIFRAME
D0
Default: 00h
D[4:0]
FRAMES PER MULTIFRAME
Sets number of frames per multiframe.
After reset, the default settings for frames per multiframe are:
10x
K = 16
20x
K=8
For each mode, K should not be set to a lower value.
8.6.2.19 Register Address 30
Figure 71. Register Address 30
REGISTER
ADDRESS
A[7:0] (Hex)
30
Default: 40h
D[7:5]
SUBCLASS
000
001
010
44
Subclass 0
Subclass 1
Subclass 2
REGISTER DATA
D7
D6
SUBCLASS
D5
D4
0
D3
0
D2
0
D1
0
D0
0
Sets JESD204B subclass. Note that the default value of these bits after reset is '010', which makes subclass 2
the default class.
Backward compatibility with JESD204A
Deterministic latency using the SYSREF signal
Deterministic latency using SYNC~ detection (default subclass after reset)
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8.6.2.20 Register Address 36
Figure 72. Register Address 36
REGISTER
ADDRESS
A[7:0] (Hex)
36
REGISTER DATA
D7
SYNC REQ
D6
LMFC RESET MASK
Default: 00h
D7
SYNC REQ
0
Normal operation
1
Generates sync request
D6
0
1
D3-D0
0000
0001
0010
0011
0100
0101
0110
0111
D5
0
D4
0
D3
D2
D1
OUTPUT CURRENT SEL
D0
Generates a synchronization request.
LMFC RESET MASK
LMFC reset is not
masked
Ignores LMFC reset
Mask the LMFC reset coming to digital.
OUTPUT CURRENT
SEL
16 mA
15 mA
14 mA
13 mA
20 mA
19 mA
18 mA
17 mA
Changes the JESD output buffer current.
1000
1001
1010
1011
1100
1101
1110
1111
8 mA
7 mA
6 mA
5 mA
12 mA
11 mA
10 mA
9 mA
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8.6.2.21 Register Address 37
Figure 73. Register Address 37
REGISTER
ADDRESS
A[7:0] (Hex)
37
REGISTER DATA
D7
D6
D5
LINK LAYER TESTMODE
D4
LINK LAYER RPAT
D3
0
D2
D1
D0
PULSE DET MODES
Default: 00h
D[7:5] LINK LAYER TESTMODE
Generates a pattern according to clause 5.3.3.8.2 of the JESD204B document.
000
Normal ADC data
001
D21.5 (high-frequency jitter pattern)
010
K28.5 (mixed-frequency jitter pattern)
011
Repeats initial lane alignment (generates a K28.5 character and continuously repeats the lane
alignment sequences)
100
12-octet RPAT jitter pattern
D4
LINK LAYER RPAT
0
1
Normal operation
Changes disparity
D[2:0]
PULSE DET MODES
Changes the running disparity in the modified RPAT pattern test mode (only when the link layer test
mode = 100).
Selects different detection modes for SYSREF (subclass 1) and SYNC (subclass 2).
D2
D1
D0
FUNCTIONALITY
0
Don’t care
0
Allows all pulses to reset input clock dividers
1
Don’t care
0
Do not allow reset of analog clock dividers
Don’t care
0 -> 1
transition
1
Allows one pulse immediately after the 0 -> 1 transition to reset the divider
8.6.2.22 Register Address 38
Figure 74. Register Address 38
REGISTER
ADDRESS
A[7:0] (Hex)
38
REGISTER DATA
D7
FORCE LMFC COUNT
D6
D5
D4
D3
LMFC COUNT INIT
D2
D1
D0
RELEASE ILANE SEQ
Default: 00h
D7
FORCE LMFC COUNT
Forces an LMFC count.
0
Normal operation
1
Enables using a different starting value for the LMFC counter
D[6:2]
D[1:0]
00
01
10
11
46
LMFC COUNT INIT
SYSREF receives the digital block and resets the LMFC count to '0'.
K28.5 stops transmitting when the LMFC count reaches 31. The initial value that the LMFC count resets to can be set using
LMFC COUNT INIT. In this manner, the Rx can be synchronized early because the Rx gets the LANE ALIGNMENT SEQUENCE
early. The FORCE LMFC COUNT register bit must be enabled.
RELEASE ILANE SEQ
Delays the generation of the lane alignment sequence by 0, 1, 2, or 3 multiframes after the code group
synchronization.
0
1
2
3
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A device clock and sysref signal must be provided to the ADC and it is recommended that these are source
synchronous (generated from a common source with match trace lengths) if synchronizing multiple ADCs. An
example of a device that can be used to generate source synchronous device clock and sysref is the LMK04828.
The device clock frequency must be the same frequency as the desired sampling rate. The sysref period is
required to be an integer multiple of the period of the multi-frame clock. Consequently, the frequency of sysref
must be restricted to (Device Clock Frequency) / (2×n×K),n = 1,2,3… K is set by the value in spi register 0x2D
and it ranges from 1 to 32. A large enough K is recommended (greater than 16) to absorb the lane skews and
avoid data transmission errors across the JESD204B interface. The sync~ signal is used by the FPGA or ASIC to
acknowledge the correct reception of comma characters from the ADC during the JESD204B link initialization
process. During normal operation this signal should be logic 1 if there are no errors in the data transmission from
the ADC to the FPGA or ASIC.
9.2 Typical Application
In a typical application, such as a dual channel digitizer, the ADS42JB46 is connected to an FPGA or ASIC as
shown in Figure 75.
Device clock
Device clock
sysref
sysref
Lanes
J
E
S
D
2
0
4
B
CHA
CHB
BASEBAND PROCESSOR
(FPGA/ASIC)
Sync~
ADS42JBxx
Figure 75. ADS42JBxx in a Dual-Channel Digitizer
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 15 as the input parameters.
Table 15. Design Parameters
PARAMETER
EXAMPLE VALUE
Fsampling
160 MSPS
IF
10 MHz,170 MHz
SNR
>72 dBc
SFDR
>80 dBc
HD2
>90 dBc
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9.2.2 Detailed Design Procedure
9.2.2.1 Analog Input
The analog input pins have analog buffers (running from the AVDD3V supply) that internally drive the differential
sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external
driving source (10-kΩ dc resistance and 4-pF input capacitance). The buffer helps isolate the external driving
source from the switching currents of the sampling circuit. This buffering makes driving the buffered inputs easier
than when compared to an ADC without the buffer.
The input common-mode is set internally using a 5-kΩ resistor from each input pin to VCM so the input signal
can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.5 V) and
(VCM – 0.5 V), resulting in a 2-V PP differential input swing. When programmed for a 2.5-V PP full-scale, each
input pin must swing symmetrically between (VCM + 0.625 V) and (VCM – 0.625 V).
The input sampling circuit has a high 3-dB bandwidth that extends up to 900 MHz (measured with a 50-Ω source
driving a 50-Ω termination between INP and INM). The dynamic offset of the first-stage sub-ADC limits the
maximum analog input frequency to approximately 250 MHz (with a 2.5-VPP full-scale amplitude) and to
approximately 400 MHz (with a 2-VPP full-scale amplitude). This 3-dB bandwidth is different than the analog
bandwidth of 900 MHz, which is only an indicator of signal amplitude versus frequency.
9.2.2.1.1 Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This technique improves the commonmode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input
pin is recommended to damp out ringing caused by package parasitics.
Figure 76, Figure 77, and Figure 78 show the differential impedance (ZIN = RIN || CIN) at the ADC input pins. The
presence of the analog input buffer results in an almost constant input capacitance up to 1 GHz.
INxP(1)
ZIN(2)
RIN
CIN
INxM
(1)
X = A or B.
(2)
ZIN = RIN || (1 / jωCIN).
Figure 76. ADC Equivalent Input Impedance
5
Differential Capacitance, Cin (pF)
Differential Resistance, Rin (kΩ)
10
1
0.1
0.05
0
200
400
600
Frequency (MHz)
800
1000
3
2
1
0
0
G073
Figure 77. ADC Analog Input Resistance (RIN) Across
Frequency
48
4
200
400
600
Frequency (MHz)
800
1000
G074
Figure 78. ADC Analog Input Capacitance (CIN) Across
Frequency
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9.2.2.1.2 Driving Circuit
An example driving circuit configuration is shown in Figure 79. To optimize even-harmonic performance at high
input frequencies (greater than the first Nyquist), the use of back-to-back transformers is recommended, as
shown in Figure 79. Note that the drive circuit is terminated by 50 Ω near the ADC side. The ac-coupling
capacitors allow the analog inputs to self-bias around the required common-mode voltage. An additional R-C-R
(39 Ω – 6.8 pF – 39 Ω) circuit placed near the device pins helps further improve HD3.
0.1µF
0.1µF
5Q
INP
RINT
39 Ÿ
25 Ÿ
0.1µF
6.8 pF
25 Ÿ
RINT
39 Ÿ
INM
1:1
5Ÿ
0.1µF
1:1
Device
Figure 79. Drive Circuit for Input Frequencies up to 250 MHz
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and
good performance is obtained for high-frequency input signals. An additional termination resistor pair may be
required between the two transformers, as shown in Figure 79. The center point of this termination is connected
to ground to improve the balance between the P (positive) and M (negative) sides. The values of the terminations
between the transformers and on the secondary side must be chosen to obtain an effective 50 Ω (for a 50-Ω
source impedance). For high input frequencies (> 250 MHz), the R-C-R circuit can be removed, as indicated in
Figure 80.
0.1µF
0.1µF
5Q
INP
RINT
0.1µF
25 Ÿ
25 Ÿ
RINT
INM
1:1
1:1
0.1µF
5Ÿ
Device
Figure 80. Drive Circuit for Input Frequencies > 250 MHz
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9.2.2.2 Clock Input
The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with
little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 1.4 V
using internal 5-kΩ resistors. The self-bias clock inputs of the device can be driven by the transformer-coupled,
sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in Figure 81,
Figure 82, and Figure 83. Figure 84 details the internal clock buffer.
0.1 mF
0.1 mF
Zo
CLKP
Differential
Sine-Wave
Clock Input
CLKP
RT
Typical LVDS
Clock Input
0.1 mF
100 W
CLKM
Device
0.1 mF
Zo
NOTE: RT = termination resistor, if necessary.
CLKM
Figure 81. Differential Sine-Wave Clock Driving
Circuit
Zo
Device
Figure 82. LVDS Clock Driving Circuit
0.1 mF
CLKP
150 W
Typical LVPECL
Clock Input
100 W
Zo
0.1 mF
CLKM
Device
150 W
Figure 83. LVPECL Clock Driving Circuit
Clock Buffer
LPKG
2 nH
20 W
CLKP
CBOND
1 pF
5 kW
RESR
100 W
LPKG
2 nH
CEQ
CEQ
1.4 V
20 W
5 kW
CLKM
CBOND
1 pF
RESR
100 W
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 84. Internal Clock Buffer
50
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A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF
capacitor, as shown in Figure 85. However, for best performance, the clock inputs must be driven differentially,
thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using
a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter.
There is no change in performance with a non-50% duty cycle clock input.
0.1 mF
CMOS
Clock Input
CLKP
0.1 mF
CLKM
Device
Figure 85. Single-Ended Clock Driving Circuit
9.2.2.3 SNR and Clock Jitter
The signal-to-noise ratio (SNR) of the ADC is limited by three different factors, as shown in Equation 3.
Quantization noise is typically not noticeable in pipeline converters and is 96 dBFS for a 16-bit ADC. Thermal
noise limits SNR at low input frequencies and clock jitter sets SNR for higher input frequencies.
SNRQuantization _ Noise
æ
SNR ADC [dBc] = -20 ´ log çç 10 20
è
2
2
2
ö æ
SNRThermalNoise ö æ
SNRJitter ö
÷÷ + ç 10 ÷ + ç 10 ÷
20
20
ø è
ø
ø è
SNR limitation is a result of sample clock jitter and can be calculated by Equation 4:
SNRJitter [dBc] = -20 ´ log(2p ´ fIN ´ tJitter)
(3)
(4)
The total clock jitter (TJitter) has three components: the internal aperture jitter (85 fS for the device) is set by the
noise of the clock input buffer, the external clock jitter, and the jitter from the analog input signal. TJitter can be
calculated by Equation 5:
TJitter =
(TJitter,Ext.Clock_Input)2 + (TAperture_ADC)2
(5)
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass
filters at the clock input while a faster clock slew rate improves ADC aperture jitter. The device has a 74.1-dBFS
thermal noise and an 85-fS internal aperture jitter. The SNR value depends on the amount of external jitter for
different input frequencies, as shown in Figure 86.
76
SNR (dBFS)
74
72
35 fs
70
50 fs
68
100 fs
150 fs
66
200 fs
64
10
100
1000
Fin (MHz)
Figure 86. SNR versus Input Frequency and External Clock Jitter
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9.2.3 Application Curves
0
0
FIN = 10 MHz
SFDR = 94 dBc
SNR = 73.9 dBFS
SINAD = 73.8 dBFS
THD = 92 dBc
SFDR Non HD2, HD3
= 103 dBc
−20
−40
−60
−60
−80
−80
−100
−100
−120
0
20
40
60
Frequency (MHz)
80
−120
0
20
40
60
Frequency (MHz)
G001
Figure 87. FFT for 10-MHz Input Signal
52
−20
Amplitude (dBFS)
Amplitude (dBFS)
−40
FIN = 170 MHz
SFDR = 92 dBc
SNR = 73 dBFS
SINAD = 72.9 dBFS
THD = 91 dBc
SFDR Non HD2, HD3
= 100 dBc
80
G002
Figure 88. FFT for 170-MHz Input Signal
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10 Power Supply Recommendations
Four different power supply rails are required for ADS42JBxx device family:
• 3.3-V AVDD3V is used to supply power to the analog buffers.
• 1.8-V AVDD is used to supply power to the analog core of the ADC.
• 1.8-V DRVDD is used to supply power to the digital core of the ADC.
• 1.8-V IOVDD is used to supply power to the output buffers.
Because of the switching activities on the digital rail, it is recommended to provide the 1.8-V digital and analog
supplies from separate sources. Both IOVDD and DRVDD may be supplied from a common source and a ferrite
bead is recommended to separate these two supply rails. An example power supply scheme suitable for the
ADS42JB46 is shown in Figure 89. In this example supply scheme, AVDD3V, AVDD, DRVDD and IOVDD are
supplied from LDOs. To improve on the efficiency of the power supply scheme and to minimize heat dissipation,
it is recommended that a DC-DC converter (or switcher) is used before the LDOs if the input voltage is greater
than 4.5 V.
LDO
Input Voltage
(>4.5V)
3.3V(340mA)
AVDD3V
1.8V(130mA)
4V
LDO
DC-DC converter
LDO
AVDD
1.8V(207mA)
DRVDD
IOVDD
1.8V(100mA)
Figure 89. Example Power Supply Scheme
11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
The length of the positive and negative traces of a differential pair should be matched to within 2 mils
(0.051mm) of each other.
Each differential pair length should be matched within 10 mils (0.254 mm) of each other.
When the ADC is used on the same PCB with a digital intensive component such as FPGA or ASIC, separate
digital and analog ground planes should be used. These separate ground planes should not overlap to
minimize undesired coupling.
Connect decoupling caps directly to ground and place close to the ADC power pins and the power supply
pins to filter high-frequency current transients directly to the ground plane. This is illustrated in Figure 90.
Ground and power planes should be wide enough to keep the impedance very low. In a multi-layer PCB, one
layer each should be dedicated to ground and power planes.
All high speed serdes traces should be routed straight with minimum curves and bends. Where a bend is
necessary, avoid making very sharp right angle bends in the trace.
FR4 material may be used for the PCB core dielectric up to the maximum 3.125-Gbps bit rate supported by
ADS42JBxx device family. Path loss can be compensated for by adjusting the drive strength from the
ADS42JBxx using SPI register 0x36.
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Layout Guidelines (continued)
10 F
AVDD
DRVDD
10 F
Place de-coupling capacitor close to
power supply pin
10 F
10 F
Place de-coupling capacitor close to
ADC power supply pin
ADS42LBxx
Figure 90. Recommended Placement of Power Supply De-coupling Capacitors
11.2 Layout Example
Figure 91. Layout Recommendation
54
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS42JB46IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-3-260C-168 HR
-40 to 85
AZ42JB46
ADS42JB46IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-3-260C-168 HR
-40 to 85
AZ42JB46
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS42JB46IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS42JB46IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS42JB46IRGCR
VQFN
RGC
64
2000
350.0
350.0
43.0
ADS42JB46IRGCT
VQFN
RGC
64
250
213.0
191.0
55.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGC 64
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
9 x 9, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
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PACKAGE OUTLINE
RGC0064H
VQFN - 1 mm max height
SCALE 1.500
PLASTIC QUAD FLATPACK - NO LEAD
A
9.15
8.85
B
PIN 1 INDEX AREA
9.15
8.85
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2X 7.5
EXPOSED
THERMAL PAD
SYMM
(0.2) TYP
17
32
16
33
65
SYMM
2X 7.5
7.4 0.1
60X
0.5
1
48
49
64
PIN 1 ID
64X
0.5
0.3
64X
0.30
0.18
0.1
0.05
C A B
4219011/A 05/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGC0064H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 7.4)
SEE SOLDER MASK
DETAIL
SYMM
64X (0.6)
49
64
64X (0.24)
1
48
60X (0.5)
(3.45) TYP
(R0.05) TYP
(1.16) TYP
65
SYMM
(8.8)
( 0.2) TYP
VIA
33
16
32
17
(1.16) TYP
(3.45) TYP
(8.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK DEFINED
SOLDER MASK DETAILS
4219011/A 05/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGC0064H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
64X (0.6)
64X (0.24)
64
49
1
48
60X (0.5)
(R0.05) TYP
(1.16) TYP
65
SYMM
(8.8)
(0.58)
36X ( 0.96)
33
16
17
32
(0.58)
(1.16)
TYP
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
61% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219011/A 05/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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