Texas Instruments | TLV2553 12-Bit, 200-KSPS, 11-Channel, Low-Power, Serial ADC (Rev. C) | Datasheet | Texas Instruments TLV2553 12-Bit, 200-KSPS, 11-Channel, Low-Power, Serial ADC (Rev. C) Datasheet

Texas Instruments TLV2553 12-Bit, 200-KSPS, 11-Channel, Low-Power, Serial ADC (Rev. C) Datasheet
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TLV2553
SLAS354C – SEPTEMBER 2001 – REVISED SEPTEMBER 2015
TLV2553 12-Bit, 200-KSPS, 11-Channel, Low-Power, Serial ADC
1 Features
3 Description
•
•
The TLV2553 is a 12-bit, switched-capacitor,
successive-approximation, analog-to-digital converter.
The ADC has three control inputs [chip select (CS),
the input-output clock, and the address/control input
(DATAIN)], designed for communication with the
serial port of a host processor or peripheral through a
serial 3-state output.
1
•
•
•
•
•
•
•
•
•
•
12-Bit-Resolution A/D Converter
Up to 200 KSPS (150 KSPS for 3 V) Throughput
Over Operating Temperature Range With 12-Bit
Output Mode
11 Analog Input Channels
3 Built-In Self-Test Modes
Inherent Sample and Hold Function
Linearity Error, ±1 LSB Maximum
On-Chip Conversion Clock
Unipolar or Bipolar Output Operation
Programmable MSB or LSB First
Programmable Power Down
Programmable Output Data Length
SPI Compatible Serial Interface With I/O Clock
Frequencies up to 15 MHz (CPOL=0, CPHA=0)
In addition to the high-speed converter and versatile
control capability, the device has an on-chip 14channel multiplexer that can select any one of 11
inputs or any one of three internal self-test voltages
using configuration register 1. The sample-and-hold
function is automatic. At the end of conversion, when
programmed as EOC, the pin 19 output goes high to
indicate that conversion is complete. The converter
incorporated in the device features differential, highimpedance reference inputs that facilitate ratiometric
conversion, scaling, and isolation of analog circuitry
from logic and supply noise. A switched-capacitor
design allows low-error conversion over the full
operating temperature range.
2 Applications
•
•
•
Process Control
Portable Data Logging
Battery-Powered Instruments
The TLV2553I is characterized for operation from
TA = –40°C to 85°C.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TLV2553IPW
TSSOP (20)
6.50 mm × 4.40 mm
TLV2553IDW
SOIC (20)
12.80 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
VCC
20
REF +
14
REF −
13
3
AIN0 1
AIN1 2
AIN2 3
AIN3 4
AIN4 5
AIN5 6
AIN6 7
AIN7 8
AIN8 9
AIN9 11
AIN10 12
DATA IN
CS
I/O CLOCK
Self Test
14-Channel
Analog
Multiplexer
Low Power
12-Bit
SAR ADC
Sample
and Hold
4
18
19
EOC
12
Input Address
Register
Output Data
Register
12
12-to-1
Data
Selector
and Driver
17
15
Reference CTRL
Control Logic
and I/O
Counters
16 DATA
OUT
4
Internal OSC
10
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV2553
SLAS354C – SEPTEMBER 2001 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
External Reference Specifications ............................ 7
Operating Characteristics.......................................... 7
Timing Requirements: VREF+ = 5 V........................... 8
Timing Requirements: VREF+ = 2.5 V........................ 9
Typical Characteristics .......................................... 13
Parameter Measurement Information ................ 18
Detailed Description ............................................ 20
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
20
20
20
21
Application and Implementation ........................ 26
9.1 Application Information............................................ 26
9.2 Typical Application .................................................. 27
10 Power Supply Recommendations ..................... 29
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 30
12 Device and Documentation Support ................. 31
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2002) to Revision C
Page
•
ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section,
Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Deleted Available Options table ............................................................................................................................................. 3
•
Deleted Lead temperature row from Absolute Maximum Ratings ......................................................................................... 4
2
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SLAS354C – SEPTEMBER 2001 – REVISED SEPTEMBER 2015
5 Pin Configuration and Functions
DW or PW Package
20-Pin SOIC or TSSOP
Top View
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
EOC
I/O CLOCK
DATA IN
DATA OUT
CS
REF +
REF –
AIN10
AIN9
Pin Functions
PIN
NAME
AIN0 to AIN10
CS
DATA IN
NO.
I/O
DESCRIPTION
1 to 9, 11, 12
I
Analog input. These 11 analog-signal inputs are internally multiplexed.
15
I
Chip select. A high-to-low transition on CS resets the internal counters and controls and
enables DATA OUT, DATA IN, and I/O CLOCK. A low-to-high transition disables DATA IN and
I/O CLOCK within a setup time.
I
Serial data input. The 4-bit serial data can be used as address selects the desired analog input
channel or test voltage to be converted next, or a command to activate other features. The
input data is presented with the MSB (D7) first and is shifted in on the first four rising edges of
the I/O CLOCK. After the four address/command bits are read into the command register
CMR, I/O CLOCK clocks the remaining four bits of configuration in.
17
DATA OUT
16
O
3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state
when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the
high-impedance state and is driven to the logic level corresponding to the MSB/LSB value of
the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the
logic level corresponding to the next MSB/LSB, and the remaining bits are shifted out in order.
EOC
19
O
End-of-convertions status. Used to indicate the end of conversion (EOC) to the host processor.
EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and
remains low until the conversion is complete and the data is ready for transfer.
GND
10
—
Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all
voltage measurements are with respect to GND.
Input /output clock. I/O CLOCK receives the serial input and performs the following four
functions:
1. It clocks the eight input data bits into the input data register on the first eight rising edges
of I/O CLOCK with the multiplexer address available after the fourth rising edge.
2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected
multiplexer input begins charging the capacitor array and continues to do so until the last
falling edge of I/O CLOCK.
3. The remaining 11 bits of the previous conversion data are shifted out on DATA OUT.
Data changes on the falling edge of I/O CLOCK.
4. Control of the conversion is transferred to the internal state controller on the falling edge
of the last I/O CLOCK.
I/O CLOCK
18
I
REF+
14
I/O
Positive reference voltage The upper reference voltage value (nominally VCC) is applied to
REF+. The maximum analog input voltage range is determined by the difference between the
voltage applied to terminals REF+ and REF–.
REF–
13
I/O
Negative reference voltage. The lower reference voltage value (nominally ground) is applied to
REF–. This pin is connected to analog ground (GND of the ADC) when internal reference is
used.
VCC
20
—
Positive supply voltage
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VCC
Supply voltage (2)
–0.5
6.5
VI
Input voltage (any input)
–0.3
VCC + 0.3
VO
Output voltage
–0.3
VCC + 0.3
Vref+
Positive reference voltage
–0.3
VCC + 0.3
Vref–
Negative reference voltage
–0.3
VCC + 0.3
II
Peak input current (any input)
–20
20
Peak total input current (all inputs)
–30
30
TJ
Operating virtual junction temperature
–40
150
TA
Operating free-air temperature
–40
85
Tstg
Storage temperature
–65
150
(1)
(2)
UNIT
V
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND terminal with REF– and GND wired together (unless otherwise noted).
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC
specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
Supply voltage
I/O CLOCK frequency
2.7
5.5
0.01
15
VCC = 4.5 V to 5.5 V 12-bit I/O
0.01
15
0.01
15
0.01
10
8-bit I/O
Tolerable clock jitter
VCC = 4.5 V to 5.5 V
Aperature jitter
VCC = 4.5 V to 5.5 V
Analog input voltage (1)
VIH
High-level control input voltage
VIL
Low-level control input voltage
TA
Operating free-air temperature
(1)
MAX
16-bit I/O
VCC = 2.7 V to 3.6 V
I/O
CLOCK
NOM
V
MHz
0.38
ns
100
ps
VCC = 4.5 V to 5.5 V
0
(REF+ ) – (REF– )
VCC = 3 V to 3.6 V
0
(REF+ ) – (REF– )
VCC = 2.7 V to 3 V
0
(REF+ ) – (REF– )
VCC = 4.5 V to 5.5 V
2
VCC = 2.7 V to 3.6 V
2.1
V
V
VCC = 4.5 V to 5.5 V
0.8
VCC = 2.7 V to 3.6 V
0.6
TLV2553I
UNIT
–40
V
85
°C
Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the
voltage applied to REF– convert as all zeros (000000000000).
6.4 Thermal Information
TLV2553
THERMAL METRIC
(1)
DW (SOIC)
PW (TSSOP)
20 PINS
20 PINS
UNIT
66
88.1
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
31.4
21.6
°C/W
RθJB
Junction-to-board thermal resistance
33.7
40.4
°C/W
ψJT
Junction-to-top characterization parameter
7.4
0.8
°C/W
ψJB
Junction-to-board characterization parameter
33.3
39.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range, when VCC = 5 V: VREF+ = 5 V, I/O CLOCK frequency = 15 MHz,
when VCC = 2.7 V: VREF+ = 2.5 V, I/O CLOCK frequency = 10 MHz (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
VCC = 4.5 V, IOH = –1.6 mA
VCC = 2.7 V, IOH = –0.2 mA
High-level output voltage
VOL
VCC = 4.5 V, IOH = –20 μA
VCC = 2.7 V, IOH = –20 μA
VCC = 4.5 V, IOL = –1.6 mA
VCC = 2.7 V, IOL = –0.8 mA
Low-level output voltage
VCC = 4.5 V, IOL = –20 μA
VCC = 2.7 V, IOL = –20 μA
MIN
TYP (1)
MAX
UNIT
2.4
30 pF
V
VCC – 0.1
0.4
30 pF
V
0.1
VO = VCC, CS = VCC
1
2.5
VO = 0 V, CS = VCC
–1
–2.5
μA
IOZ
High-impedance off-state output current
ICC
Operating supply current
CS = 0 V,
External reference
ICC(PD)
Power-down current
For all digital inputs, Software power down
0 ≤ VI ≤ 0.5 V or
VI ≥ VCC – 0.5 V,
Auto power down
I/O CLOCK = 0 V
IIH
High-level input current
VI = VCC
0.005
2.5
μA
IIL
Low-level input current
VI = 0 V
–0.005
–2.5
μA
Ilkg
Selected channel leakage current
fOSC
Internal oscillator frequency
tconvert
Conversion time
(13.5 × (1/fOSC) + 25 ns)
VCC = 5 V
1.2
VCC = 2.7 V
0.9
Input impedance (2)
Ci
Input capacitance
(1)
(2)
6
Analog inputs
1
0.1
10
Selected channel at VCC ,
Unselected channel at 0 V
1
Selected channel at 0 V,
Unselected channel at VCC
–1
μA
μA
VCC = 4.5 V to 5.5 V
3.27
VCC = 2.7 V to 3.6 V
2.56
MHz
VCC = 4.5 V to 5.5 V
4.15
VCC = 2.7 V to 3.6 V
5.54
Internal oscillator frequency voltage
Zi
0.1
mA
3.6
4.1
VCC = 4.5 V
500
VCC = 2.7 V
600
Analog inputs
45
55
Control inputs
5
15
μs
V
Ω
pF
All typical values are at VCC = 5 V, TA = 25°C.
The switch resistance is very nonlinear and varies with input voltage and supply voltage. This is the worst case.
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6.6 External Reference Specifications
MIN
TYP (1)
MAX
VCC = 4.5 V to 5.5 V
–0.1
0
0.1
VCC = 2.7 V to 3.6 V
–0.1
0
0.1
VCC = 4.5 V to 5.5 V
2
VCC
VCC = 2.7 V to 3.6 V
2
VCC
External reference input voltage difference,
(REF+) – (REF–) (2)
VCC = 4.5 V to 5.5 V
1.9
VCC
VCC = 2.7 V to 3.6 V
1.9
VCC
External reference supply current
CS at 0 V
PARAMETER
REF–
Reference input voltage
REF+
Reference input voltage
TEST CONDITIONS
VCC = 5 V
Reference input impedance
VCC = 2.7 V
(1)
(2)
VCC = 4.5 V to 5.5 V
0.94
VCC = 2.7 V to 3.6 V
0.62
Static
1
During
sampling/conversion
6
Static
1
During
sampling/conversion
6
UNIT
V
V
V
mA
MΩ
9
kΩ
MΩ
9
kΩ
All typical values are at TA = 25°C.
Add a 0.1-µF capacitor between REF+ and REF– pins when external reference is used.
6.7 Operating Characteristics
over recommended operating free-air temperature range, VREF+ = 5 V, I/O CLOCK frequency = 15 MHz when VCC = 5 V,
VREF+ = 2.5 V, I/O CLOCK frequency = 10 MHz when VCC = 2.7 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(2)
INL
Integral linearity error
DNL
Differential linearity error
EO
Offset error (3)
See
(3)
EQ
Gain error
ET
Total unadjusted error (5)
See
(4)
(4)
(1)
(2)
(3)
(4)
(5)
(6)
MAX
UNIT
–1
1
LSB
–1
1
LSB
–2
2
mV
–3
3
±15
Address data input = 1011
Self-test output code Table 2,
MIN TYP (1)
(6)
mV
LSB
2048
Address data input = 1100
0
Address data input = 1101
4095
All typical values are at TA = 25°C.
Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain
point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal
midstep value at the offset point.
Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the
voltage applied to REF– convert as all zeros (000000000000).
Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
Both the input address and the output codes are expressed in positive logic.
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6.8 Timing Requirements: VREF+ = 5 V
over recommended operating free-air temperature range, I/O CLOCK frequency = 15 MHz, VCC = 5 V, load = 25 pF (unless
otherwise noted)
MIN
tw1
Pulse duration I/O CLOCK high or low
26.7
tsu1
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 32)
th1
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 32)
tsu2
Setup time CS low before first rising I/O CLOCK edge (1) (see Figure 33)
th2
Hold time CS pulse duration high time (see Figure 33)
th3
th4
TYP
MAX
100000
UNIT
ns
12
ns
0
ns
25
ns
100
ns
Hold time CS low after last I/O CLOCK falling edge (see Figure 33)
0
ns
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 34)
2
ns
th5
Hold time CS high after EOC rising edge when CS is toggled (see Figure 37)
0
ns
td1
Delay time CS falling edge to DATA OUT valid
(MSB or LSB) (see Figure 31)
td2
Delay time CS rising edge to DATA OUT high impedance (see Figure 31)
td3
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 34)
td4
Delay time Last I/O CLOCK falling edge to EOC falling edge
55
ns
td5
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion
1.5
µs
tt1
Transition time I/O CLOCK
1
µs
tt2
Transition time DATA OUT (see Figure 34)
5
ns
tt3
Transition time INT/EOC, CL at 7 pF (see Figure 36)
2.4
ns
tt4
Transition time DATA IN, CS
10
µs
tcycle
Total cycle time (sample, conversion and delays) (1)
MAX(tconvert) +
I/O period
(8/12/16 CLKs)
µs
tsample
Load = 25 pF
28
ns
Load = 10 pF
20
ns
10
ns
20
ns
(1)
(see Figure 34)
Channel acquisition time (sample), at 1 kΩ,
(See Figure 1 through Figure 6)
(1)
Source impedance = 25 Ω
600
Source impedance = 100 Ω
650
Source impedance = 500 Ω
700
Source impedance = 1 kΩ
(1)
8
2
ns
1000
I/O CLOCK period = 8X [1/(I/O CLOCK frequency)] or 12X [1/(I/O CLOCK frequency)] or 16X [1/(I/O CLOCK frequency)] depends on I/O
format selected.
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6.9 Timing Requirements: VREF+ = 2.5 V
over recommended operating free-air temperature range, I/O CLOCK frequency = 10 MHz, VCC = 2.7 V, load = 25 pF (unless
otherwise noted)
MIN
TYP
MAX
UNIT
tw1
Pulse duration I/O CLOCK high or low
40
tsu1
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 32)
22
ns
th1
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 32)
0
ns
tsu2
Setup time CS low before first rising I/O CLOCK edge (1) (see Figure 33)
33
ns
th2
Hold time CS pulse duration high time (see Figure 33)
100
ns
th3
Hold time CS low after last I/O CLOCK falling edge (see Figure 33)
0
ns
th4
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 33)
2
ns
th5
Hold time CS high after EOC rising edge when CS is toggled (see Figure 37)
0
ns
td1
Delay time CS falling edge to DATA OUT valid
(MSB or LSB) (see Figure 31)
td2
Delay time CS rising edge to DATA OUT high impedance (see Figure 31)
td3
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 34)
td4
Delay time Last I/O CLOCK falling edge to EOC falling edge
td5
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion
tt1
Transition time I/O CLOCK
tt2
tt3
tt4
Transition time DATA IN, CS
tcycle
Total cycle time (sample, conversion and delays) (1)
(1)
ns
Load = 25 pF
30
ns
Load = 10 pF
22
ns
10
ns
33
ns
75
ns
1.5
µs
1
µs
Transition time DATA OUT (see Figure 34)
5
ns
Transition time INT/EOC, CL at 7 pF (see Figure 36)
4
ns
10
µs
MAX(tconvert) +
I/O period
(8/12/16 CLKs)
µs
2
(1)
(see Figure 34)
Source impedance = 25 Ω
tsample
100000
Channel acquisition time (sample), at 1 kΩ,
(See Figure 1 through Figure 6)
(1)
800
Source impedance = 100 Ω
850
Source impedance = 500 Ω
1000
Source impedance = 1 kΩ
1600
ns
I/O CLOCK period = 8X [1/(I/O CLOCK frequency)] or 12X [1/(I/O CLOCK frequency)] or 16X [1/(I/O CLOCK frequency)] depends on I/O
format selected.
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
1
3
2
Sample Cycle
4
I/O
CLOCK
5
6
7
8
9
10
11
12
Previous Conversion Data
DATA
OUT
MSB
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
Channel
Address
DATA
IN
D7
D6
D5
3
2
1
Hi−Z State
LSB
MSB
MSB−1 MSB−2
Output Data
Format
D4
D3
D2
D1
D0
D7
D6
D5
A/D Conversion Interval
t CONV
EOC
Initialize
Initialize
Figure 1. Timing for 12-Clock Transfer Using CS With DATA OUT Set for MSB First
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Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
1
Sample Cycle
3
2
4
5
6
11
12
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
LSB
7
89
10
1
I/O
CLOCK
3
2
Previous Conversion Data
DATA
OUT
MSB
Channel
Address
D7
DATA IN
D6
Low Level
MSB
MSB−1 MSB−2
Output Data
Format
D5
D4
D3
D2
D1
D0
D7
D6
D5
A/D Conversion Interval
t CONV
EOC
Initialize
Initialize
NOTE: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 2. Timing for 12-Clock Transfer Not Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
1
Sample Cycle
3
2
4
5
6
7
8
1
2
3
4
5
6
7
I/O
CLOCK
Previous Conversion Data
Hi−Z State
DATA
OUT
MSB
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5
Channel
Address
D7
DATA IN
D6
D5
LSB+1
LSB
MSB
D0
D7
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6
Output Data
Format
D4
D3
D2
D1
D6
D5
D4
D3
D2
D1
A/D Conversion Interval
t CONV
EOC
Initialize
Initialize
Figure 3. Timing for 8-Clock Transfer Using CS With DATA OUT Set for MSB First
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Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
1
Access
Cycle
3
2
I/O
CLOCK
Sample Cycle
4
5
6
7
8
2
1
3
4
5
7
6
Previous Conversion Data
DATA
OUT
MSB
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5
Channel
Address
D7
DATA IN
D6
LSB+1
LSB
MSB
Low Level
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6
Output Data
Format
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
A/D Conversion Interval
t CONV
EOC
Initialize
Initialize
NOTE: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 4. Timing for 8-Clock Transfer Not Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access Cycle
1
3
2
Sample Cycle
4
I/O
CLOCK
5
6
7
8
9
10
11
Pad
Zeros
Previous Conversion Data
DATA
OUT
MSB
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
Channel
Address
DATA IN
D7
D6
D5
16
12
1
Hi−Z State
LSB
MSB
Output Data
Format
D4
D3
D2
D1
D0
D7
A/D Conversion Interval
t CONV
EOC
Initialize
Initialize
Figure 5. Timing for 16-Clock Transfer Using CS With DATA OUT Set for MSB First
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Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access Cycle
1
3
2
Sample Cycle
4
I/O
CLOCK
5
6
7
8
9
10
11
12
MSB
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9
Channel
Address
DATA IN
D7
D6
D5
1
Pad
Zeros
Previous Conversion Data
DATA
OUT
16
LSB+1
LSB
Low Level
MSB
Output Data
Format
D4
D3
D2
D1
D0
D7
A/D Conversion Interval
t CONV
EOC
Initialize
Initialize
NOTE: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 6. Timing for 16-Clock Transfer Not Using CS With DATA OUT Set for MSB First
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6.10 Typical Characteristics
I CC – Supply Current – mA
0.620
0.615
0.43
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
0.42
External Reference Current – mA
0.625
0.610
0.605
0.600
0.595
0.590
0.41
0.40
0.39
0.38
0.37
0.36
0.35
0.585
0.58
–40
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
0.34
–25
–10
5
20
35
50
65
0.33
–40
80
–25
TA – Free-Air Temperature – °C
Figure 7. Supply Current
vs Free-Air Temperature
0.45
0.40
0.35
5
20
35
50
65
80
Figure 8. External Reference Current
vs Free-air Temperature
0.06
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
0.05
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
0.04
Current – μA
0.30
Current – μA
–10
TA – Free-Air Temperature – °C
0.25
0.20
0.15
0.03
0.02
0.10
0.01
0.05
0.0
–40
–25
–10
5
20
35
50
65
0
–40
80
–25
Figure 9. Software Power Down vs Free-air Temperature
0.9
0.8
20
35
50
65
80
–0.0
VCC = 2.7 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
–40
5
Free-Air Temperature – °C
Figure 10. Auto Power Down vs Free-air Temperature
–25
–10
5
20
–0.1
Minimum Differential Nonlinearity – LSB
Maximum Differential Nonlinearity – LSB
1.0
–10
T
TA – Free-Air Temperature – °C
35
50
65
VCC = 2.7 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–40
80
–25
–10
5
20
35
50
65
80
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
Figure 11. Maximum Differential Nonlinearity
vs Free-air Temperature
Figure 12. Minimum Differential Nonlinearity
vs Free-air Temperature
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Typical Characteristics (continued)
0.8
0.6
0.5
0.4
0.3
0.2
0.1
0.0
–40
–25
–10
5
20
VCC = 2.7 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
–0.1
Minimum Integral Nonlinearity – LSB
Maximum Integral Nonlinearity – LSB
0.7
–0.0
VCC = 2.7 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
35
50
65
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–40
80
–25
TA – Free-Air Temperature – °C
Figure 13. Maximum Integral Nonlinearity
vs Free-air Temperature
DNL – Differential Nonlinearity – LSB
–10
5
20
35
50
65
80
TA – Free-Air Temperature – °C
Figure 14. Minimum Integral Nonlinearity
vs Free-air Temperature
0.5
VCC = 2.7 V, VREF+ = 2.5 V, V REF– = 0 V, I/O CLOCK = 10 MHz, TA = 25°C
0.4
0.3
0.2
0.1
–0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
1024
2048
3072
4096
Digital Output Code
INL – Integral Nonlinearity – LSB
Figure 15. Differential Nonlinearity vs Digital Output Code
0.8
VCC = 2.7 V, VREF+ = 2.5 V, V REF– = 0 V, I/O CLOCK = 10 MHz, TA = 25°C
0.6
0.4
0.2
–0.0
–0.2
–0.4
–0.6
–0.8
0
1024
2048
3072
4096
Digital Output Code
Figure 16. Integral Nonlinearity vs Digital Output Code
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Typical Characteristics (continued)
1.4
0.6
1.2
EG – Gain Error – mV
EO – Offset Error – mV
0.5
0.4
0.3
0.2
1.0
0.8
0.6
0.4
0.1
0.0
–40
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
–25
–10
5
20
0.2
35
50
65
0.0
–40
80
VCC = 3.3 V
VREF+ = 2.5 V
VREF– = 0 V
I/O CLOCK = 10 MHz
–25
TA – Free-Air Temperature – °C
Figure 17. Offset Error vs Free-air Temperature
External Reference Current – mA
I CC – Supply Current – mA
0.90
0.88
0.86
50
65
80
0.6
0.5
0.4
0.3
0.2
0.1
–25
–10
5
20
35
50
65
0
–40
80
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
–25
–10
5
20
35
50
65
80
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
Figure 20. External Reference Current
vs Free-air Temperature
Figure 19. Supply Current
vs Free-air Temperature
0.45
0.35
35
0.7
0.92
0.40
20
0.8
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
0.94
0.84
–40
5
Figure 18. Gain Error vs Free-air Temperature
0.98
0.96
–10
TA – Free-Air Temperature – °C
0.14
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
0.12
Current – μA
Current – μA
0.10
0.30
0.25
0.20
0.08
0.06
0.15
0.04
0.10
0.02
0.05
0.0
–40
–25
–10
5
20
35
50
65
0
–40
80
TA – Free-Air Temperature – °C
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
–25
–10
5
20
35
50
65
80
TA – Free-Air Temperature – °C
Figure 21. Software Power Down vs Free-air Temperature
Figure 22. Auto Power Down vs Free-air Temperature
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Typical Characteristics (continued)
–0.00
0.9
0.8
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
–40
–25
–10
5
20
35
50
65
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
–0.05
Minimum Differential Nonlinearity – LSB
Maximum Differential Nonlinearity – LSB
1.0
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
–0.45
–40
80
–25
Figure 23. Maximum Differential Nonlinearity
vs Free-air Temperature
–0.330
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
0.84
0.82
0.80
0.78
0.76
0.74
–40
–25
–10
5
20
35
50
65
–0.331
35
50
65
80
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
–0.332
–0.333
–0.334
–0.335
–0.336
–0.337
–0.338
–40
80
–25
–10
5
20
35
50
65
80
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
Figure 25. Maximum Integral Nonlinearity
vs Free-air Temperature
DNL – Differential Nonlinearity – LSB
20
–0.329
Minimum Integral Nonlinearity – LSB
Maximum Integral Nonlinearity – LSB
0.86
5
Figure 24. Minimum Differential Nonlinearity
vs Free-air Temperature
0.90
0.88
–10
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
Figure 26. Minimum Integral Nonlinearity
vs Free-air Temperature
0.3
VCC = 5.5 V, VREF+ = 4.096 V, V REF– = 0 V, I/O CLOCK = 15 MHz, TA = 25°C
0.2
0.1
–0.0
–0.1
–0.2
–0.3
0
1024
2048
3072
4096
Digital Output Code
Figure 27. Differential Nonlinearity vs Digital Output Code
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INL – Integral Nonlinearity – LSB
Typical Characteristics (continued)
0.8
0.6
0.4
0.2
–0.0
–0.2
–0.4
–0.6
VCC = 5.5 V, VREF+ = 4.096 V, V REF– = 0 V, I/O CLOCK = 15 MHz, TA = 25°C
–0.8
0
1024
2048
3072
4096
Digital Output Code
Figure 28. Integral Nonlinearity vs Digital Output Code
–0.0
–0.00
EO – Offset Error – mV
–0.10
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
–0.1
–0.2
EG – Gain Error – mV
–0.05
–0.15
–0.20
–0.25
–0.30
–0.35
–0.3
–0.4
–0.5
–0.6
–0.7
–0.40
–0.8
–0.45
–0.9
–0.5
–40
–25
–10
5
20
35
50
65
–1
–40
80
VCC = 5.5 V
VREF+ = 4.096 V
VREF– = 0 V
I/O CLOCK = 15 MHz
–25
–10
5
20
35
50
65
80
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
Figure 29. Offset Error vs Free-air Temperature
Figure 30. Gain Error vs Free-air Temperature
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7 Parameter Measurement Information
VIH
VIL
CS
td1
td2
VOH
VOL
Data Out
Figure 31. DATA OUT to Hi-Z Voltage Waveforms
Data Valid
VIH
VIL
DATA IN
th1
tsu1
I/O
CLOCK
VIH
VIL
Figure 32. DATA IN and I/O CLOCK Voltage
VIH
VIL
CS
th2
th3
tsu2
I/O
CLOCK
VIH
VIL
Last
Clock
Figure 33. CS and I/O CLOCK
Voltage Waveforms
tt1
tt1
VIH
VIL
I/O
CLOCK
I/O CLK Period
td3
th4
VOH
VOL
Data Out
tt2
Figure 34. I/O CLOCK and DATA OUT
Voltage Waveforms
I/O
CLOCK
VIH
VIL
Last
Clock
tconvert
VOH
td2
EOC
VOL
tt3
Figure 35. I/O CLOCK and EOC
Voltage Waveforms
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Parameter Measurement Information (continued)
tt3
VOH
VOL
tt3
VOH
VOL
Data Out
MSB
Valid
Figure 36. EOC and DATA OUT
Voltage Waveforms
VIH
VIL
CS
th5
VOH
VOL
EOC
Figure 37. CS and EOC Waveforms
1
I/O
CLOCK
VIH
VIL
VOH
VOL
EOC
Figure 38. I/O CLOCK and DATA OUT Voltage
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8 Detailed Description
8.1 Overview
Initially, with chip select (CS) high, I/O CLOCK and DATA IN are disabled and DATA OUT is in the highimpedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA IN and
removes DATA OUT from the high-impedance state. The input data is an 8–bit data stream consisting of a 4-bit
address or command (D7–D4) and a 4-bit configuration data (D3–D0). Configuration register 1, CFGR1, which
controls output data format configuration, consists of a 2-bit data length select (D3–D2), an output MSB or LSB
first bit (D1), and a unipolar or bipolar output select bit (D0) that are applied to any command (from DATA IN)
except for command 1111b. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to
the input data register. During this transfer, the I/O CLOCK sequence also shifts the previous conversion result
from the output data register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock cycles
long depending on the data-length selection in the input data register. Sampling of the analog input begins on the
fourth falling edge of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK
sequence. The last falling edge of the I/O CLOCK sequence also takes EOC low and begins the conversion.
8.2 Functional Block Diagram
VCC
20
REF +
14
REF –
13
3
AIN0 1
AIN1 2
AIN2 3
AIN3 4
AIN4 5
AIN5 6
AIN6 7
AIN7 8
AIN8 9
AIN9 11
AIN10 12
DATA IN
CS
I/O CLOCK
Self Test
14-Channel
Analog
Multiplexer
Low Power
12-Bit
SAR ADC
Sample
and Hold
4
Reference CTRL
Input Address
Register
18
EOC
12
Output Data
Register
12
12-to-1
Data
Selector
and Driver
17
15
19
Control Logic
and I/O
Counters
16
DATA
OUT
4
Internal OSC
10
GND
8.3 Feature Description
8.3.1 Analog MUX
The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer
according to the input addresses shown in Table 2. The input multiplexer is a break-before-make type to reduce
input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on the falling
edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held on the
falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, then
sampled and converted in the same manner as the external analog inputs. The first conversion after the device
has returned from the power-down state may not read accurately due to internal device settling.
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Feature Description (continued)
8.3.2 Reference
An external reference can be used through two reference input pins, REF+ and REF–. The voltage levels applied
to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale
reading respectively. The values of REF+, REF–, and the analog input should not exceed the positive supply or
be lower than GND consistent with the specified absolute maximum ratings. The digital output is at full scale
when the input signal is equal to or higher than REF+ and at zero when the input signal is equal to or lower than
REF–.
Analog
Supply
VCC
REF+
Sample
C1
0.1 μF
Decoupling Cap
Convert
~50 pF
CDAC
REF–
GND
Figure 39. Reference Block Diagram
8.4 Device Functional Modes
8.4.1 Converter Operation
The operation of the converter is organized as a succession of three distinct cycles: 1) the data I/O cycle, 2) the
sampling cycle and 3) the conversion cycle. The first two are partially overlapped.
8.4.2 Data I/O Cycle
The data I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods,
depending on the selected output data length. During the I/O cycle, the following two operations take place
simultaneously. An 8-bit data stream consisting of address/command and configuration information is provided to
DATA IN. This data is shifted into the device on the rising edge of the first eight I/O CLOCK clocks. DATA INPUT
is ignored after the first eight clocks during 12- or 16-clock I/O transfers. The data output, with a length of 8, 12,
or 16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on the rising
edge of EOC. When CS is toggled between conversions, the first output data bit occurs on the falling edge of
CS. This data is the result of the previous conversion period, and after the first output data bit, each succeeding
bit is clocked out on the falling edge of each succeeding I/O CLOCK.
8.4.3 Sampling Cycle
During the sampling cycle, one of the analog inputs is internally connected to the capacitor array of the converter
to store the analog input signal. The converter starts sampling the selected input immediately after the four
address/command bits have been clocked into the input data register. Sampling starts on the fourth falling edge
of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge of
the I/O CLOCK depending on the data-length selection.
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Device Functional Modes (continued)
After the 8-bit data stream has been clocked in, DATA IN should be held at a fixed digital level until EOC goes
high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the influence
of external digital noise.
8.4.4 Conversion Cycle
A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external
digital noise on the accuracy of the conversion. This cycle is transparent to the user because it is controlled by
an internal clock (oscillator). The total conversion time is equal to 13.5 OSC clocks plus a small delay
(approximately Í25 ns) to start the OSC. During the conversion period, the device performs a successiveapproximation conversion on the analog input voltage.
EOC goes low at the start of the conversion cycle and goes high when the conversion is complete and the output
data register is latched. After EOC goes low, the analog input can be changed without affecting the conversion
result. Because the delay from the falling edge of the last I/O CLOCK to the falling edge of EOC is fixed, any
time-varying analog input signals can be digitized at a fixed rate without introducing systematic harmonic
distortion or noise due to timing uncertainty.
8.4.5 Power Up and Initialization
After power up, CS must be taken from high to low to begin an I/O cycle. The EOC pin is initially high, and the
configuration register is set to all zeroes. The contents of the output data register are random, and the first
conversion result should be ignored. To initialize during operation, CS is taken high and is then returned low to
begin the next I/O cycle. The first conversion after the device has returned from the power-down state may not
read accurately due to internal device settling.
Table 1. Operational Terminology
TERMINOLOGY
DESCRIPTION
Current (N) I/O cycle
The entire I/O CLOCK sequence that transfers address and control data into the data register and
clocks the digital result from the previous conversion from DATA OUT.
Current (N) conversion cycle
The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is
the last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded into the
output register when conversion is complete.
Current (N) conversion result
The current conversion result is serially shifted out on the next I/O cycle.
Previous (N–1) conversion cycle
The conversion cycle just before the current I/O cycle
Next (N+1) I/O cycle
The I/O period that follows the current conversion cycle
8.4.5.1 Example
In 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during the
next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even when this
corrupts the output data from the previous conversion. The current conversion is begun immediately after the
twelfth falling edge of the current I/O cycle.
8.4.6 Data Input
The data input is internally connected to an 8-bit serial-input address and control register. The register defines
the operation of the converter and the output data length. The host provides the input data byte with the MSB
first. Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data inputregister format).
22
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Table 2. Command Set (CMR) and Configuration
SDI D[7:4]
COMMAND
Binary
HEX
0000b
0h
SELECT analog input channel 0
SDI D[3:0]
CFGR1
0001b
1h
SELECT analog input channel 1
D[3:2]
0010b
2h
SELECT analog input channel 2
0011b
3h
SELECT analog input channel 3
0100b
4h
SELECT analog input channel 4
0101b
5h
SELECT analog input channel 5
0110b
6h
SELECT analog input channel 6
0111b
7h
SELECT analog input channel 7
1000b
8h
SELECT analog input channel 8
1001b
9h
SELECT analog input channel 9
1010b
Ah
SELECT analog input channel 10
1011b
Bh
SELECT TEST, Voltage = (VREF+ + VREF–)/2
1100b
Ch
SELECT TEST, Voltage = REFM
1101b
Dh
SELECT TEST, Voltage = REFP
1110b
Eh
SW POWERDOWN (analog + reference)
1111b
Fh
Reserved
CONFIGURATION
01: 8-bit output length
X0: 12-bit output length (see Note)
11: 16-bit output length
D1
0: MSB out first
1: LSB out first
D0
0: Unipolar binary
1: Bipolar 2s complement
Note: Select 12-bit output mode to achieve 200 KSPS sampling rate.
8.4.7 Data Input—Address/Command Bits
The four MSBs (D7–D4) of the input data register are the address or command. These can be used to address
one of the 11 input channels, address one of three reference-test voltages, or activate software power-down
mode. All address/command bits affect the current conversion, which is the conversion that immediately follows
the current I/O cycle. They also have access to CFGR1 except for command 1111b, which is reserved.
8.4.8 Data Output Length
CFGR1 bits (D3 and D2) of the data register select the output data length. The data-length selection is valid for
the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current
I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be
selected. Because the converter has 12-bit resolution, a data length of 12 bits is suggested.
With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be
exactly 12 bits long for proper synchronization, even when this means corrupting the output data from a previous
conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.
With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication
with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial
data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must
be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the
previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current
I/O cycle.
With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream
during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even
when this means corrupting the output data from the previous conversion. The four LSBs of the conversion result
are truncated and discarded. The current conversion is started immediately after the eighth falling edge of the
current I/O cycle.
Because the D3 and D2 register settings take effect on the I/O cycle when the data length is programmed, there
can be a conflict with the previous cycle if the data-word length was changed. This may occur when the data
format is selected to be least significant bit first, because at the time the data length change becomes effective
(six rising edges of I/O CLOCK), the previous conversion result has already started shifting out. In actual
operation, when different data lengths are required within an application and the data length is changed between
two conversions, no more than one conversion result can be corrupted and only when it is shifted out in LSB-first
format.
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8.4.9 LSB Out First
D1 in the CFGR1 controls the direction of the output (binary) data transfer. When D1 is reset to 0, the conversion
result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of MSB first or LSB first
always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to
another, the current I/O cycle is never disrupted.
8.4.10 Bipolar Output Format
D0 in the CFGR1 controls the binary data format used to represent the conversion result. When D0 is cleared to
0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result of an
input voltage equal to or less than VREF– is a code with all zeros (000 . . . 0) and the conversion result of an input
voltage equal to or greater than VREF+ is a code of all ones (111 . . . 1). The conversion result of (VREF+ +
VREF–)/2 is a code of a one followed by zeros (100 ...0).
When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion
of an input voltage equal to or less than VREF– is a code of a one followed by zeros (100 . . . 0), and the
conversion of an input voltage equal to or greater than VREF+ is a code of a zero followed by all ones (011 . . . 1).
The conversion result of (VREF+ + VREF–)/2 is a code of all zeros (000 . . . 0). The MSB is interpreted as the sign
bit. The bipolar data format is related to the unipolar format in that the MSBs are always each other’s
complement.
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.
8.4.11 EOC Output
Pin 19 outputs the status of the ADC conversion. When programmed as EOC, the output indicates the beginning
and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after
the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the
converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O
CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes
low, the analog input signal can be changed without affecting the conversion result.
The EOC signal goes high again after the conversion is completed and the conversion result is latched into the
output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When
CS is toggled between conversions, the first bit of the current conversion result occurs on DATA OUT at the
falling edge of CS.
24
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8.4.12 Chip-Select Input (CS)
CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not
necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data
transfer of several devices sharing the same bus.
When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing its
output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK is
inhibited, thus preventing any further change in the internal state.
When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce
time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low)
for a minimum time before a new I/O cycle can start.
CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough
before the end of the current conversion cycle, the previous conversion result is saved in the internal output
buffer and shifted out during the next I/O cycle.
When CS is held low continuously for multiple cycles, the first data bit of the newly completed conversion occurs
on DATA OUT on the rising edge of EOC.
NOTE
the first cycle in the series still requires a transition CS from high to low. When a new
conversion is started after the last falling edge of I/O CLOCK, EOC goes low and the
serial output is forced low until EOC goes high again.
When CS is toggled between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On
each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit in
the serial conversion result until the required number of bits has been output.
8.4.13 Power-Down Features
When command (D7–D4) 1110b is clocked into the input data register during the first four I/O CLOCK cycles, the
software power-down mode is selected. Software power down is activated on the falling edge of the fourth I/O
CLOCK pulse.
During software power-down, all internal circuitry is put in a low-current standby mode. No conversions is
performed. The internal output buffer keeps the previous conversion cycle data results, provided that all digital
inputs are greater than VCC – 0.5 V or less than 0.5 V. The I/O logic remains active so the current I/O cycle must
be completed even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle,
the converter normally begins in the power-down mode. The device remains in the software power-down mode
until a valid input address (other than command 1110b or 1111b) is clocked in. Upon completion of that I/O cycle,
a normal conversion is performed with the results being shifted out during the next I/O cycle.
The ADC also has an auto power-down mode. This is transparent to users. The ADC gets into auto power-down
within 1 I/O CLOCK cycle after the conversion is complete and resumes, with a small delay, after an active CS is
sent to the ADC. The resumption is fast enough to be used between cycles.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
As with most SAR ADCs, the inputs of the TLV2553 are not high-impedance ports. At the start of the sampling
phase, the selected input channel experiences a load current, as the internal analog switches close and the
sampling capacitor starts to charge (or discharge). This load current decays over time and varies in a nonlinear
fashion with respect to input voltage.
The load current is supplied by the input signal source which has non-zero output impedance. As a result, the
load current drops non-zero voltage across the output impedance of the signal source creating a time-decaying,
nonlinear error between the signal source output and the ADC input. This is called sampling error, and if the
sampling error does not decay to less than 1 LSB before the end of the sampling window when the sampling
switch opens and conversion begins, the ADC output is inaccurate.
The rate of decay of the sampling error and its nonlinearity over input voltage are highly sensitive to source
impedance. In other words, for larger values of source impedance, the sampling error decays more slowly over
time, resulting in greater residual error at the end of the sampling window that is also more non-linear over the
ADC input voltage range. Nonlinearity in the ADC input translates to nonlinearity or harmonic distortion in the
ADC output. Harmonic distortion degrades ADC resolution and translates to a decrease in the ADC’s effective
number of bits (ENOB). Therefore, driving the ADC input with a low-impedance source is critical for conversion
accuracy.
In addition to keeping source impedance as low as possible, TI recommends the following measures for
minimizing input sampling error and harmonic distortion associated with the TLV2553 while operating the device
at maximum 200-KSPS throughput:
• For AC inputs, the maximum input signal frequency on all channels should be limited to well less than the
maximum Nyquist rate of 100 kHz. Figure 40 shows how ENOB degrades as input frequency increases.
12
11.5
ENOB (bits)
11
10.5
10
9.5
9
0
20
Rsource = 50 Ω
40
60
Input Frequency (kHz)
80
100
D025
ƒs = 200KSPS
Figure 40. ENOB as a Function of Input Signal Frequency
•
26
For DC inputs, ensure that there are no large step-function changes (greater than VREF / 4) between
successive input channels in the scanning order at the highest throughput. If possible, it is advisable to scan
the input channels so that the difference in the DC voltage levels between any two successive channels is
minimized to ensure 12-bit sampling accuracy. For larger voltage changes between channels, higher
accuracy can be achieved by reducing the throughput.
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Application Information (continued)
•
The stability of the ADC reference input voltage, which is a DC signal, is critical for ADC accuracy. The
reference source experiences large instantaneous changes in load current during the ADC conversion phase,
and therefore, low source impedance is required for excellent load regulation and stability.
9.2 Typical Application
Figure 41 shows a typical application where the TLV2553 is used to acquire multiple AC signals while operating
at its maximum sampling rate of 200 KSPS.
Rsource
Rsource
1 nF
/CS
1 nF
I/O CLOCK
ADC
DATA IN
EOC
DATA OUT
Rsource
1 nF
REF+
±
OPA320
+
REF3240
1k
1 µF
2.5
10 µF
Figure 41. Typical Application Block Diagram
9.2.1 Design Requirements
The design is optimized for superior dynamic performance (low harmonic distortion, high ENOB) while the ADC
is multiplexing input channels at maximum sampling rate. Of course, the underlying assumption, based on , is
that the bandwidths of the input signals are much less than 100 kHz. For example, according to , the TLV2553
provides better than 11.5 ENOB for AC inputs less than 10 kHz.
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Typical Application (continued)
9.2.2 Detailed Design Procedure
Good dynamic performance while the ADC is multiplexing inputs at maximum sampling rate requires low source
impedance on the input channels being addressed. To make the input source impedance less sensitive to line
inductance, especially in cases where the signal sources may be located far away from the ADC, it may be
necessary to use operational amplifier buffers located close to the ADC input pins.
The procedure for estimating the maximum tolerable value of input source impedance on a given channel for
achieving the desired ENOB (for example ENOB > 11.5) in a multiplexed application is as follows:
1. Using a low impedance signal source, apply a full-scale sinusoidal signal of suitably low frequency to the
ADC input channel of interest, CHx.
2. Using a second low impedance source, apply a full-scale sinusoid that has the same frequency as the signal
on CHx but is 180˚ out-of-phase, to a second ADC input channel, CHy, that will serve as the control element
in the experiment.
3. Initiate conversions with the ADC continuously multiplexing between CHx and CHy in each conversion cycle.
4. Rearrange the output data by channel, and for each of the two channels, compute SINAD from its FFT and
estimate ENOB for that channel as ENOB = (SINAD[dB] – 1.76) / 6.02.
5. Increase the series resistance on CHx by a discrete amount and repeat steps 1 through 5 until the ENOB of
CHx has degraded sufficiently relative to CHy (which should remain unchanged).
The external 1-nF decoupling capacitors (recommend C0G/NP0 type for constant capacitance versus voltage) on
the input channels are required for supplying the instantaneous change in the ADC’s load current demand during
the sampling phase after an input channel is selected. In other words, the decoupling capacitor effectively
reduces the output impedance of the source at high frequencies.
Similarly, the reference pin also requires decoupling for low-output impedance at high frequency. However, the
larger magnitude of reference pin load currents during the ADC conversion phase necessitates a decoupling
capacitor of a much higher value. The extra ESR (2.5 Ω) is required for stabilizing the OPA320 output as it drives
the 10-μF load.
The OPA320 is a wide-band, low-noise, low-power operational amplifier that is unity gain stable and can operate
on a single 5-V system supply while supporting rail-to-rail signal swing at its input and output. These properties
make it an ideal choice for being used as a high-precision (stable, low-noise) reference buffer that has enough
loop gain over frequency to support low-output impedance over a wide bandwidth.
9.2.3 Application Curve
was generated by sweeping Rsource from 50 Ω to 1 kΩ following the procedure detailed in .
12
11
ENOB (bits0
10
9
8
7
6
0
100
200
ƒIN = 1 kHz
300
400 500 600
Rsource (:)
700
800
900 1000
D026
ƒs = 200 KSPS
Figure 42. ENOB as a Function of Input Source Impedance
28
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10 Power Supply Recommendations
The TLV2553 is designed to operate from a single power supply voltage from 2.7 V ti 5.5 V. The ADC supply
voltage must be well-regulated. A 1-μF ceramic decoupling capacitor is required and must be placed as close as
possible to the device to minimize inductance along the load current path.
Many modern microcontrollers have interfaces that support only up to 3.3-V logic levels, which is incompatible
with the TLV2553 when the device is operated on a 5-V power supply. In such cases, 5-V to 3.3-V digital level
translators may be used to facilitate communication between the TLV2553 and the microcontroller host.
11 Layout
11.1 Layout Guidelines
•
•
•
•
All decoupling capacitors must be located as close as possible to the loads they are supplying.
TI recommends large copper fill areas or thick traces wherever possible to provide low inductance current
paths between decoupling capacitors and their loads
Ensure that there are no vias or discontinuities in the forward or return current paths that can cause the
current loop area and therefore the loop inductance to increase.
For high-frequency current paths routed across PCB layers, multiple vias can be placed close together (but
not obstructing the current path) to lower inductance.
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11.2 Layout Example
GND Plane
1µF
VCC
Plane
1nF 1nF 1nF 1nF 1nF
A
n
a
l
o
g
VCC
TLV2553
REF+
REF-
I
n
p
u
t
s
GND
1nF 1nF 1nF 1nF
2.5O 1nF
OPA320
10µF
1µF
1µF
Voltage
Reference
Output
1kO
Figure 43. Layout Example Schematic
30
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV2553IDW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLV2553I
TLV2553IDWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLV2553I
TLV2553IDWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLV2553I
TLV2553IPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TY2553
TLV2553IPWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TY2553
TLV2553IPWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TY2553
TLV2553IPWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TY2553
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2553 :
• Automotive: TLV2553-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLV2553IDWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
TLV2553IPWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV2553IDWR
SOIC
DW
20
2000
350.0
350.0
43.0
TLV2553IPWR
TSSOP
PW
20
2000
350.0
350.0
43.0
Pack Materials-Page 2
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