Texas Instruments | ADC080x 8-Bit, µP-Compatible, Analog-to-Digital Converters (Rev. C) | Datasheet | Texas Instruments ADC080x 8-Bit, µP-Compatible, Analog-to-Digital Converters (Rev. C) Datasheet

Texas Instruments ADC080x 8-Bit, µP-Compatible, Analog-to-Digital Converters (Rev. C) Datasheet
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ADC0801, ADC0802, ADC0803, ADC0804, ADC0805
SNOSBI1C – NOVEMBER 2009 – REVISED JUNE 2015
ADC080x 8-Bit, µP-Compatible, Analog-to-Digital Converters
1 Features
3 Description
•
The ADC0801, ADC0802, ADC0803, ADC0804, and
ADC0805 devices are CMOS 8-bit successive
approximation converters (ADC) that use a differential
potentiometric ladder — similar to the 256R products.
These converters are designed to allow operation
with the NSC800 and INS8080A derivative control
bus with Tri-state output latches directly driving the
data bus. These ADCs appear like memory locations
or I/O ports to the microprocessor and no interfacing
logic is needed.
1
•
•
•
•
•
•
•
•
•
•
•
Compatible With 8080-µP Derivatives – No
Interfacing Logic Needed – Access Time 135 ns
Easy Interface to All Microprocessors, or Operates
as a Stand-Alone Deivce
Differential Analog Voltage Inputs
Logic Inputs and Outputs Meet Both MOS and
TTL Voltage-Level Specifications
Works With 2.5-V (LM336) Voltage Reference
On-Chip Clock Generator
0-V to 5-V Analog Input Voltage Range With
Single 5-V Supply
No Zero Adjust Required
0.3-Inch Standard Width 20-Pin DIP Package
20-Pin Molded Chip Carrier or Small Outline
Package
Operates Ratiometrically or With 5 VDC, 2.5 VDC,
or Analog Span Adjusted Voltage Reference
Key Specifications
– Resolution: 8 Bits
– Total Error: ±1/4 LSB, ±1/2 LSB and ±1 LSB
– Conversion Time: 100 µs
Differential analog voltage inputs allow increasing the
common-mode rejection and offsetting the analog
zero input voltage value. In addition, the voltage
reference input can be adjusted to allow encoding
any smaller analog voltage span to the full 8 bits of
resolution.
Device Information(1)
PART NUMBER
ADC0801,
ADC0803
ADC0802,
ADC0804
PACKAGE
BODY SIZE (NOM)
PDIP (20)
26.073 mm × 6.604 mm
PDIP (20)
26.073 mm × 6.604 mm
SOIC (20)
12.80 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
Operates With Any 8-Bit µP Processors or as a
Stand-Alone Device
Interface to Temp Sensors, Voltage Sources, and
Transducers
Typical Application Schematic
ADC0801 Specified With ±¼ LSB Accuracy
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADC0801, ADC0802, ADC0803, ADC0804, ADC0805
SNOSBI1C – NOVEMBER 2009 – REVISED JUNE 2015
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
5
5
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Operating Ratings .....................................................
Electrical Characteristics...........................................
AC Electrical Characteristics.....................................
Typical Characteristics ..............................................
7
Parameter Measurement Information ................ 10
8
Detailed Description ............................................ 11
7.1 Tri-State Test Circuits and Waveforms ................... 10
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 14
9
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Applications ................................................ 22
9.3 System Examples ................................................... 40
10 Power Supply Recommendations ..................... 48
11 Layout................................................................... 48
11.1 Layout Guidelines ................................................. 48
12 Device and Documentation Support ................. 49
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
49
49
49
49
49
13 Mechanical, Packaging, and Orderable
Information ........................................................... 49
4 Revision History
Changes from Revision B (Feburary 2013) to Revision C
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Removed Ordering Information table .................................................................................................................................... 4
2
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SNOSBI1C – NOVEMBER 2009 – REVISED JUNE 2015
5 Pin Configuration and Functions
NFH and DW Package
20-Pin PDIP and SOIC
Top View
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
CS
I
Chip Select
2
RD
I
Read
3
WR
I
Write
4
CLK IN
I
External Clock input or use internal clock gen with external RC elements
5
INTR
O
Interrupt request
6
VIN(+)
I
Differential analog input+
7
VIN(–)
I
Differential analog input–
8
A GND
I
Analog ground pin
9
VREF/2
I
Reference voltage input for adjustment to correct full scale reading
10
D GND
I
Digital ground pin
11
DB7
O
Data bit 7
12
DB6
O
Data bit 6
13
DB5
O
Data bit 5
14
DB4
O
Data bit 4
15
DB3
O
Data bit 3
16
DB2
O
Data bit 2
17
DB1
O
Data bit 1
18
DB0 (LSB)
O
Data bit 0
19
CLK R
I
RC timing resistor input pin for internal clock gen
20
VCC (or VREF)
I
+5V supply voltage, also upper reference input to the ladder
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
Supply voltage (VCC) (3)
Voltage
Lead Temperature
(Soldering, 10
seconds)
V
–0.3
18
At other input and outputs
–0.3
(VCC +0.3)
Dual-In-Line Package (plastic
260
Dual-In-Line Package (ceramic)
300
Surface Mount Package Vapor Phase (60 seconds)
215
Infrared (15 seconds)
220
–65
V
°C
150
Package Dissipation at TA = 25°C
(2)
(3)
UNIT
6.5
Logic control inputs
Storage Temperature
(1)
MAX
875
mW
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the Sales Office/Distributors for availability and specifications.
A Zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC.
6.2 ESD Ratings
V(ESD)
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Electrostatic discharge
VALUE
UNIT
±800
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Analog Input Voltage
MIN
NOM
MAX
4.5
5
5.5
GND – 0.05
VCC + 0.05
UNIT
V
VDC
6.4 Thermal Information
THERMAL METRIC
ADC080x
ADC0802,
ADC0804
NFH (PDIP)
DW (SOIC)
(1)
UNIT
20 PINS
20 PINS
RθJA
Junction-to-ambient thermal resistance
38.5
63.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
23.4
27.2
°C/W
RθJB
Junction-to-board thermal resistance
19.5
31.8
°C/W
ψJT
Junction-to-top characterization parameter
8.7
5.7
°C/W
ψJB
Junction-to-board characterization parameter
19.4
31.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Operating Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2).
Temperature
MIN
MAX
ADC0804LCJ
–40
85
ADC0801/02/03/05LCN
–40
85
ADC0804LCN
0
70
ADC0802/04LCWM
0
70
4.5
6.3
Range of VCC
(1)
(2)
UNIT
°C
VDC
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its specified operating conditions.
All voltages are measured with respect to GND, unless otherwise specified. The separate A GND point should always be wired to the D
GND.
6.6 Electrical Characteristics
The following specifications apply for VCC = 5 VDC, TMIN ≤ TA ≤ TMAX and fCLK = 640 kHz (unless otherwise specified).
PARAMETER
ADC0801: Total Adjusted Error
TEST CONDITIONS
(1)
MIN
TYP
MAX
With Full-Scale Adj. (See Full-Scale)
±1/4
ADC0802: Total Unadjusted
Error (1)
VREF/2=2.500 VDC
±1/2
ADC0803: Total Adjusted Error (1)
With Full-Scale Adj. (See Full-Scale)
±1/2
ADC0804: Total Unadjusted Error
(1)
ADC0805: Total Unadjusted Error
(1)
VREF/2 Input Resistance (Pin 9)
VREF/2=2.500 VDC
±1
VREF/2-No Connection
±1
ADC0801/02/03/05
ADC0804
(2)
Analog Input Voltage Range
V(+) or V(–) (3)
DC Common-Mode Error
Over Analog Input Voltage Range
Power Supply Sensitivity
VCC=5 VDC ±10% Over Allowed VIN(+) and VIN(–)
Voltage Range (3)
(1)
(2)
(3)
2.5
8
0.75
1.1
GND–0.05
UNIT
LSB
kΩ
VCC+0.05
VDC
±1/16
±1/8
LSB
±1/16
±1/8
LSB
None of these ADCs requires a zero adjust (see Zero Error). To obtain zero code at other analog input voltages see Errors and
Reference Voltage Adjustments.
The VREF/2 pin is the center point of a two-resistor divider connected from VCC to ground. In all versions of the ADC0801, ADC0802,
ADC0803, and ADC0805, and in the ADC0804LCJ, each resistor is typically 16 kΩ. In all versions of the ADC0804 except the
ADC0804LCJ, each resistor is typically 2.2 kΩ.
For VIN(−)≥ VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram)
which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be
careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct–especially at
elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This
means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To
achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature
variations, initial tolerance and loading.
6.7 AC Electrical Characteristics
The following specifications apply for VCC=5 VDC and TMIN≤ TA≤TMAX (unless otherwise specified)
PARAMETER
TC
fCLK
CR
(1)
(2)
TEST CONDITIONS
fCLK = 640 kHz (1)
Conversion Time
See
Clock Frequency
(2) (1)
VCC = 5V (2)
Clock Duty Cycle
Conversion Rate in Free-Running Mode
INTR tied to WR with CS = 0 VDC,
fCLK = 640 kHz
MIN
TYP
MAX
UNIT
103
114
µs
66
73
1/fCLK
100
640
1460
40%
60%
8770
9708
kHz
conv/s
Accuracy is specified at fCLK = 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle
limits can be extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.
With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the
conversion process. The start request is internally latched. Refer to Detailed Description.
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AC Electrical Characteristics (continued)
The following specifications apply for VCC=5 VDC and TMIN≤ TA≤TMAX (unless otherwise specified)
PARAMETER
tW(WR)
TEST CONDITIONS
MIN
(3)
TYP
MAX
Width of WR Input (Start Pulse Width)
CS = 0 VDC
tACC
Access Time (Delay from Falling Edge of RD to
Output Data Valid)
CL = 100 pF
135
200
t1H,
t0H
Tri-State Control (Delay from Rising Edge of RD
to Hi-Z State)
CL = 10 pF, RL = 10k (See Tri-State
Test Circuits and Waveforms)
125
200
tWI, tRI
Delay from Falling Edge of WR or RD to Reset
of INTR
300
450
CIN
Input Capacitance of Logic Control Inputs
5
7.5
COUT
Tri-State Output Capacitance (Data Buffers)
5
7.5
UNIT
100
L
ns
pF
CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]
VIN (1) Logical “1” Input Voltage (Except Pin 4 CLK IN)
VCC = 5.25 VDC
VIN (0) Logical “0” Input Voltage (Except Pin 4 CLK IN)
VCC = 4.75 VDC
IIN (1)
Logical “1” Input Current (All Inputs)
VIN = 5 VDC
IIN (0)
Logical “0” Input Current (All Inputs)
VIN = 0 VDC
2
15
0.8
0.005
–1
–0.005
1
VDC
µADC
CLOCK IN AND CLOCK R
VT+
CLK IN (Pin 4) Positive Going Threshold Voltage
2.7
3.1
3.5
VT−
CLK IN (Pin 4) Negative Going Threshold
Voltage
1.5
1.8
2.1
VH
CLK IN (Pin 4) Hysteresis (VT+)–(VT−)
0.6
1.3
2
VOUT
(0)
Logical “0” CLK R Output Voltage
IO = 360 µA, VCC = 4.75 VDC
VOUT
(1)
Logical “1” CLK R Output Voltage
IO = −360 µA, VCC = 4.75 VDC
VDC
0.4
2.4
DATA OUTPUTS AND INTR
VOUT
(0)
Logical “0” Output Data Outputs
Voltage
INTR Output
VOUT
(1)
Logical “1” Output Voltage
IOUT
Tri-State Disabled Output Leakage (All Data
Buffers)
ISOURC
IOUT = 1.6 mA, VCC = 4.75 VDC
ISINK
0.4
IO = −360 µA, VCC = 4.75 VDC
2.4
IO = −10 µA, VCC = 4.75 VDC
4.5
VOUT = 0 VDC
–3
VOUT = 5 VDC
VOUT Short to GND, TA = 2 5°C
E
0.4
IOUT = 1.0 mA, VCC = 4.75 VDC
VOUT Short to VCC, TA = 25°C
3
4.5
6
9
16
VDC
µADC
mADC
POWER SUPPLY
ICC
(3)
6
Supply Current
(Includes Ladder
Current)
ADC0801/02/03/04LCJ/05
ADC0804LCN/LCWM
fCLK = 640 kHz, VREF/2 = NC,
TA = 25°C and CS = 5 V
1.1
1.8
1.9
2.5
mA
The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide
pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse.
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Figure 1. Start Conversion
Note:
Read strobe must occur 8 clock periods (8/fCLK) after assertion of interrupt to specify reset of INTR.
Figure 2. Output Enable and Reset With INTR
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6.8 Typical Characteristics
8
Figure 3. Logic Input Threshold Voltage vs Supply Voltage
Figure 4. Delay From Falling Edge of RD to Output Data
Valid vs Load Capacitance
Figure 5. CLK IN Schmitt Trip Levels vs Supply Voltage
Figure 6. fCLK vs Clock Capacitor
Figure 7. Full-Scale Error vs Conversion Time
Figure 8. Effect of Unadjusted Offset Error vs VREF/2 Voltage
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Typical Characteristics (continued)
Figure 9. Output Current vs Temperature
Figure 10. Power Supply Current vs Temperature (1)
Figure 11. Linearity Error at Low VREF/2 Voltages
(1)
The VREF/2 pin is the center point of a two-resistor divider connected from VCC to ground. In all versions of the ADC0801, ADC0802,
ADC0803, and ADC0805, and in the ADC0804LCJ, each resistor is typically 16 kΩ. In all versions of the ADC0804 except the
ADC0804LCJ, each resistor is typically 2.2 kΩ.
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7 Parameter Measurement Information
7.1 Tri-State Test Circuits and Waveforms
CL = 10 pF
Figure 12. RD to Data Output Falling Edge Test
Load Condition
Figure 13. RD to Data Output Falling Edge Test
Timing
CL = 10 pF
Figure 14. RD to Data Output Rising Edge Test
Load Condition
10
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Figure 15. RD to Data Output Rising Edge Test
Timing
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8 Detailed Description
8.1 Overview
The ADC0801 series are versatile 8-Bit µP compatible general purpose ADC converters operate on single 5-V
supply. These devices are treated as a memory location or I/O port to a micro-processor system without
additional interface logic. The outputs are Tri-state latched which facilitate interfacing to micro-processor control
bus. The converter is designed with a differential potentiometric ladder, a circuit equivalent of the 256R network.
It contains analog switches sequenced by successive approximation logic. A functional diagram of the ADC
converter is shown in Functional Block Diagram. All of the package pinouts are shown and the major logic control
paths are drawn in heavier weight lines. The differential analog voltage input has good common mode-rejection
and permits offsetting the analog zero-input voltage value. Moreover, the input reference voltage can be adjusted
to allow encoding small analog voltage span to the full 8-bits resolution. To ensure start-up under all possible
conditions, an external WR pulse is required during the first power-up cycle.
Using a SAR logic the most significant bit is tested first and after 8 comparisons (64 clock cycles) a digital 8-bit
binary code (1111 1111 = full-scale) is transferred to an output latch and then an interrupt is asserted (INTR
makes a high-to-low transition). A conversion in process can be interrupted by issuing a second start command.
The device may be operated in the free-running mode by connecting INTR to the WR input with CS=0.
On the high-to-low transition of the WR input the internal SAR latches and the shift register stages are reset. As
long as the CS input and WR input remain low, the ADC will remain in a reset state. Conversion will start from 1
to 8 clock periods after at least one of these inputs makes a low-to-high transition.
The converter is started by having CS and WR simultaneously low. This sets the start flip-flop (F/F) and the
resulting “1” level resets the 8-bit shift register, resets the Interrupt (INTR) F/F and inputs a “1” to the D flop,
F/F1, which is at the input end of the 8-bit shift register. Internal clock signals then transfer this “1” to the Q
output of F/F1. The AND gate, G1, combines this “1” output with a clock signal to provide a reset signal to the
start F/F. If the set signal is no longer present (either WR or CS is a “1”) the start F/F is reset and the 8-bit shift
register then can have the “1” clocked in, which starts the conversion process. If the set signal were to still be
present, this reset pulse would have no effect (both outputs of the start F/F would momentarily be at a “1” level)
and the 8-bit shift register would continue to be held in the reset mode. This logic therefore allows for wide CS
and WR signals and the converter will start after at least one of these signals returns high and the internal clocks
again provide a reset signal for the start F/F.
After the “1” is clocked through the 8-bit shift register (which completes the SAR search) it appears as the input
to the D-type latch, LATCH 1. As soon as this “1” is output from the shift register, the AND gate, G2, causes the
new digital word to transfer to the Tri-state output latches. When LATCH 1 is subsequently enabled, the Q output
makes a high-to-low transition which causes the INTR F/F to set. An inverting buffer then supplies the INTR input
signal.
Note this SET control of the INTR F/F remains low for 8 of the external clock periods (as the internal clocks run
at 1/8 of the frequency of the external clock). If the data output is continuously enabled (CS and RD both held
low), the INTR output will still signal the end of conversion (by a high-to-low transition), because the SET input
can control the Q output of the INTR F/F even though the RESET input is constantly at a M "1M " level in this
operating mode. This INTR output will therefore stay low for the duration of the SET signal, which is 8 periods of
the external clock frequency (assuming the ADC is not started during this interval).
When operating in the free-running or continuous conversion mode (INTR pin tied to WR and CS wired low – see
Continuous Conversions), the START F/F is SET by the high-to-low transition of the INTR signal. This resets the
SHIFT REGISTER which causes the input to the D-type latch, LATCH 1, to go low. As the latch enable input is
still present, the Q output will go high, which then allows the INTR F/F to be RESET. This reduces the width of
the resulting INTR output pulse to only a few propagation delays (approximately 300 ns).
When data is to be read, the combination of both CS and RD being low will cause the INTR F/F to be reset and
the Tri-state output latches will be enabled to provide the 8-bit digital outputs.
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8.2 Functional Block Diagram
(1)
CS shown twice for clarity.
(2)
SAR = Successive Approximation Register.
8.3 Feature Description
8.3.1 Understanding ADC Error Specs
A perfect ADC transfer characteristic (staircase waveform) is shown in Figure 16 and Figure 17. The horizontal
scale is analog input voltage and the particular points labeled are in steps of 1 LSB (19.53 mV with 2.5V tied to
the VREF/2 pin). The digital output codes that correspond to these inputs are shown as D−1, D, and D+1. For
the perfect ADC, not only will center- value (A−1, A, A+1, . . . . ) analog inputs produce the cor- rect output digital
codes, but also each riser (the transitions between adjacent output codes) will be located ±1⁄2 LSB away from
each center-value. As shown, the risers are ideal and have no width. Correct digital output codes will be provided
for a range of analog input voltages that extend ±1⁄2 LSB from the ideal center-values. Each tread (the range of
analog input voltage that provides the same digital output code) is therefore 1 LSB wide.
Figure 19 shows a worst case error plot for the ADC0801. All center-valued inputs are guaranteed to produce the
correct output codes and the adjacent risers are specified to be no closer to the center-value points than ±1/4
LSB. In other words, if we apply an analog input equal to the center-value ±1/4 LSB, we guarantee that the ADC
will produce the correct digital code. The maximum range of the position of the code transition is indicated by the
horizontal arrow and it is specified to be no more than 1/2 LSB.
The error curve of Figure 21 shows a worst case error plot for the ADC0802. Here we guarantee that if we apply
an analog input equal to the LSB analog voltage center-value the ADC will produce the correct digital code.
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Feature Description (continued)
Next to each transfer function is shown the corresponding error plot. Many people may be more familiar with
error plots than transfer functions. The analog input voltage to the ADC is provided by either a linear ramp or by
the discrete output steps of a high resolution DAC. Notice that the error is continuously displayed and includes
the quantization uncertainty of the ADC. For example the error at point 1 of Figure 21 is +1⁄2 LSB because the
digital code appeared 1⁄2 LSB in advance of the center-value of the tread. The error plots always have a
constant negative slope and the abrupt up-side steps are always 1 LSB in magnitude.
Figure 16. Transfer Function of Analog Input vs Digital
Output Code in Ideal ADC
Figure 17. Clarifying the Error Specs of an ADC Converter
Accuracy=±0 LSB: A Perfect ADC
Figure 18. Transfer Function of Analog Input vs Digital
Output Code for ±1/4 LSB Accuracy ADC
Figure 19. Clarifying the Error Specs of an ADC Converter
Accuracy =±1⁄4 LSB
Figure 20. Transfer Function of Analog Input vs Digital
Output Code for ±1/2 LSB Accuracy ADC
Figure 21. Clarifying the Error Specs of an ADC Converter
Accuracy = ±1⁄2 LSB
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Feature Description (continued)
8.3.2 Digital Control Inputs
The digital control inputs (CS, RD, and WR) meet standard TLL logic voltage levels. These signals have been
renamed when compared to the standard ADC Start and Output Enable labels. In addition, these inputs are
active low to allow an easy interface to microprocessor control busses. For non-microprocessor based
applications, the CS input (pin 1) can be grounded and the standard ADC Start function is obtained by an active
low pulse applied at the WR input (pin 3) and the Output Enable function is caused by an active low pull at the
RD input (pin 2).
8.4 Device Functional Modes
8.4.1 Analog Input Modes
8.4.1.1 Normal Mode
Due to the internal switching action, displacement currents will flow at the analog inputs. This is due to on-chip
stray capacitance to ground as shown in Figure 22.
rON of SW 1 and SW 2.5 kΩ
r=rON CSTRAY × 5 kΩ x 12 pF = 60 ns
Figure 22. Analog Input Impedance
The voltage on this capacitance is switched and will result in currents entering the VIN(+) input pin and leaving
the VIN(−) input which will depend on the analog differential input voltage levels. These current transients occur
at the leading edge of the internal clocks. They rapidly decay and do not cause errors as the on-chip comparator
is strobed at the end of the clock period.
8.4.1.2 Fault Mode
If the voltage source applied to the VIN(+) or VIN(−) pin exceeds the allowed operating range of VCC+50 mV, large
input currents can flow through a parasitic diode to the VCC pin. If these currents can exceed the 1 mA max
allowed spec, an external diode (1N914) should be added to bypass this current to the VCC pin (with the current
bypassed with this diode, the voltage at the VIN(+) pin can exceed the VCC voltage by the forward voltage of this
diode).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The following sections give example circuits and suggestions for using the ADC080X in typical application
situation with a typical 8-bit micro-processor.
9.1.1 Testing the ADC Converter
There are many degrees of complexity associated with testing an ADC converter. One of the simplest tests is to
apply a known analog input voltage to the converter and use LEDs to display the resulting digital output code as
shown in Figure 23.
For ease of testing, the VREF/2 (pin 9) should be supplied with 2.560 VDC and a VCC supply voltage of 5.12 VDC
should be used. This provides an LSB value of 20 mV.
If a full-scale adjustment is to be made, an analog input voltage of 5.090 VDC (5.120–1/⁄2 LSB) should be applied
to the VIN(+) pin with the VIN(−) pin grounded. The value of the VREF/2 input voltage should then be adjusted until
the digital output code is just changing from 1111 1110 to 1111 1111. This value of VREF/2 should then be used
for all the tests.
The digital output LED display can be decoded by dividing the 8 bits into 2 hex characters, the 4 most significant
(MS) and the 4 least significant (LS). Table 1 shows the fractional binary equivalent of these two 4-bit groups. By
adding the voltages obtained from the "VM" and "VLS" columns in Table 1, the nominal value of the digital
display (when VREF/2 = 2.560V) can be determined. For example, for an output LED display of 1011 0110 or B6
(in hex), the voltage values from the table are 3.520 + 0.120 or 3.640 VDC. These voltage values represent the
center-values of a perfect ADC converter. The effects of quantization error have to be accounted for in the
interpretation of the test results.
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Application Information (continued)
Figure 23. Basic ADC Tester
For a higher speed test system, or to obtain plotted data, a digital-to-analog converter is needed for the test setup. An accurate 10-bit DAC can serve as the precision voltage source for the ADC. Errors of the ADC under test
can be expressed as either analog voltages or differences in 2 digital words.
A basic ADC tester that uses a DAC and provides the error as an analog output voltage is shown in Figure 35.
The 2 op amps can be eliminated if a lab DVM with a numerical subtraction feature is available to read the
difference voltage, "A–C", directly. The analog input voltage can be supplied by a low frequency ramp generator
and an X-Y plotter can be used to provide analog error (Y axis) versus analog input (X axis).
For operation with a microprocessor or a computer-based test system, it is more convenient to present the errors
digitally. This can be done with the circuit of Figure 25, where the output code transitions can be detected as the
10-bit DAC is incremented. This provides 1⁄4 LSB steps for the 8-bit ADC under test. If the results of this test are
automatically plotted with the analog input on the X axis and the error (in LSB’s) as the Y axis, a useful transfer
function of the ADC under test results. For acceptance testing, the plot is not necessary and the testing speed
can be increased by establishing internal limits on the allowed error for each code.
9.1.2 Microprocessor Interfacing
To discuss the interface with 8080A and 6800 microprocessors, a common sample subroutine structure is used.
The microprocessor starts the ADC, reads and stores the results of 16 successive conversions, then returns to
the user’s program. The 16 data bytes are stored in 16 successive memory locations. All Data and Addresses
will be given in hexadecimal form. Software and hardware details are provided separately for each type of
microprocessor.
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Application Information (continued)
9.1.2.1 Interfacing 8080 Microprocessor Derivatives (8048, 8085)
This converter has been designed to directly interface with derivatives of the 8080 microprocessor. The ADC can
be mapped into memory space (using standard memory address decoding for CS and the MEMR and MEMW
strobes) or it can be controlled as an I/O device by using the I/O R and I/O W strobes and decoding the address
bits A0 → A7 (or address bits A8 → A15 as they will contain the same 8-bit address information) to obtain the
CS input. Using the I/O space provides 256 additional addresses and may allow a simpler 8-bit address decoder
but the data can only be input to the accumulator. To make use of the additional memory reference instructions,
the ADC should be mapped into memory space. An example of an ADC in I/O space is shown in Figure 26.
Figure 24. ADC Tester with Analog Error Output
Figure 25. Basic “Digital” ADC Tester
Table 1. Decoding the Digital Output LEDs
HEX
MS GROUP
(1)
OUTPUT VOLTAGE CENTER VALUES
WITH VREF/2=2.560 VDC
FRACTIONAL BINARY VALUE FOR
BINARY
F
1
1
1
1
E
1
1
1
0
D
1
1
0
1
C
1
1
0
0
B
1
0
1
1
LS GROUP
15/16
15/256
7/8
7/128
13/16
3/4
13/256
3/64
11/16
11/256
VMS GROUP (1)
VLS GROUP (1)
4.800
0.300
4.480
0.280
4.160
0.260
3.840
0.240
3.520
0.220
Display Output=VMS Group + VLS Group
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Application Information (continued)
Table 1. Decoding the Digital Output LEDs (continued)
HEX
OUTPUT VOLTAGE CENTER VALUES
WITH VREF/2=2.560 VDC
FRACTIONAL BINARY VALUE FOR
BINARY
MS GROUP
A
1
0
1
0
9
1
0
0
1
8
1
0
0
0
7
0
1
1
1
6
0
1
1
0
5
0
1
0
1
4
0
1
0
0
3
0
0
1
1
2
0
0
1
0
1
0
0
0
1
0
0
0
0
0
LS GROUP
5/8
5/128
9/16
1/2
9/256
1/32
7/16
7/256
3/8
3/128
5/16
1/4
2/256
1/64
163
1/8
3/256
1/128
1/16
1/256
VMS GROUP (1)
VLS GROUP (1)
3.200
0.200
2.880
0.180
2.560
0.160
2.240
0.140
1.920
0.120
1.600
0.100
1.280
0.080
0.960
0.060
0.640
0.040
0.320
0.020
0
0
(1)
*Pin numbers for the DP8228 system controller, others are INS8080A
(2)
Pin 23 of the INS8228 must be tied to +12V through a 1 kΩ resistor to generate the RST 7 instruction when an
interrupt is acknowledged as required by the accompanying sample program.
Figure 26. ADC0801_INS8080A CPU Interface
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Note: The stack pointer must be dimensioned because a RST 7 instruction pushes the PC onto the stack.
Note: All address used were arbitrarily chosen.
Figure 27. Sample Program for Figure 26 ADC0801–INS8080A CPU Interface
The standard control bus signals of the 8080 CS, RD and WR) can be directly wired to the digital control inputs
of the ADC and the bus timing requirements are met to allow both starting the converter and outputting the data
onto the data bus. A bus driver should be used for larger microprocessor systems where the data bus leaves the
PCB and/or must drive capacitive loads larger than 100 pF.
9.1.2.2 Sample 8080A CPU Interfacing Circuitry and Program
The following sample program and associated hardware shown in Figure 26 may be used to input data from the
converter to the INS8080A CPU chip set (comprised of the INS8080A microprocessor, the INS8228 system
controller and the INS8224 clock generator). For simplicity, the ADC is controlled as an I/O device, specifically an
8-bit bi-directional port located at an arbitrarily chosen port address, E0. The Tri-state output capability of the
ADC eliminates the need for a peripheral interface device, however address decoding is still required to generate
the appropriate CS for the converter.
It is important to note in systems where the ADC converter is 1-of-8 or less I/O mapped devices, no address
decoding circuitry is necessary. Each of the 8 address bits (A0 to A7) can be directly used as CS inputs — one
for each I/O device.
9.1.2.3 INS8048 Interface
The INS8048 interface technique with the ADC0801 series (see Figure 28) is simpler than the 8080A CPU
interface. There are 24 I/O lines and three test input lines in the 8048. With these extra I/O lines available, one of
the I/O lines (bit 0 of port 1) is used as the chip select signal to the ADC, thus eliminating the use of an external
address decoder. Bus control signals RD, WR and INT of the 8048 are tied directly to the ADC. The 16
converted data words are stored at on-chip RAM locations from 20 to 2F (Hex). The RD and WR signals are
generated by reading from and writing into a dummy address, respectively. A sample interface program is shown
below.
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Figure 28. INS8048 Interface
Figure 29. Sample Program for Figure 28 INS8048 Interface
9.1.2.4 Interfacing the Z-80
The Z-80 control bus is slightly different from that of the 8080. General RD and WR strobes are provided and
separate memory request, MREQ, and I/O request, IORQ, signals are used which have to be combined with the
generalized strobes to provide the equivalent 8080 signals. An advantage of operating the ADC in I/O space with
the Z-80 is that the CPU will automatically insert one wait state (the RD and WR strobes are extended one clock
period) to allow more time for the I/O devices to respond. Logic to map the ADC in I/O space is shown in
Figure 30.
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Figure 30. Mapping the ADC as an I/O Device for Use With the Z-80 CPU
Additional I/O advantages exist as software DMA routines are available and use can be made of the output data
transfer which exists on the upper 8 address lines (A8 to A15) during I/O input instructions. For example, MUX
channel selection for the ADC can be accomplished with this operating mode.
9.1.2.5 Interfacing 6800 Microprocessor Derivatives (6502, etc.)
The control bus for the 6800 microprocessor derivatives does not use the RD and WR strobe signals. Instead it
employs a single R/W line and additional timing, if needed, can be derived from the φ2 clock. All I/O devices are
memory mapped in the 6800 system, and a special signal, VMA, indicates that the current address is valid.
Figure 36 shows an interface schematic where the ADC is memory mapped in the 6800 system. For simplicity,
the CS decoding is shown using 1/2 DM8092. Note in many 6800 systems, an already decoded 4/5 line is
brought out to the common bus at pin 21. This can be tied directly to the CS pin of the ADC, provided that no
other devices are addressed at HX ADDR: 4XXX or 5XXX.
The following subroutine performs essentially the same function as in the case of the 8080A interface and it can
be called from anywhere in the user’s program.
In Figure 38 the ADC0801 series is interfaced to the M6800 microprocessor through (the arbitrarily chosen) Port
B of the MC6820 or MC6821 Peripheral Interface Adapter, (PIA).
Here the CS pin of the ADC is grounded because the PIA is already memory mapped in the M6800 system and
no CS decoding is necessary. Also notice that the ADC output data lines are connected to the microprocessor
bus under program control through the PIA and therefore the ADC RD pin can be grounded.
A sample interface program equivalent to the previous one is shown below Figure 38. The PIA Data and Control
Registers of Port B are located at HEX addresses 8006 and 8007, respectively.
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9.2 Typical Applications
9.2.1 8080 Interface
Figure 31. Generic Interface Between ADC and 8-Bit µPs
ERROR SPECIFICATION (Includes Full-Scale, Zero Error, and Non-Linearity)
PART NUMBER
FULL-SCALE
ADJUSTED
ADC0801
±1⁄4 LSB
ADC0802
ADC0803
ADC0804
ADC0805
VREF/2 = 2.500 VDC
(No Adjustments)
VREF/2 = No Connection
(No Adjustments)
±1⁄2 LSB
±1⁄2 LSB
±1 LSB
±1 LSB
9.2.1.1 Design Requirements
For these example applications, the input analog signal is differential to illustrate the offset and common mode
reduction merits. An example of the use of an adjusted reference voltage is to accommodate a reduced span or
dynamic voltage range of the analog input voltage is also depicted.
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Table 2. Design Parameters
PARAMETER
EXAMPLE VALUE
ADC clock frequency, FCLK
640 KHz
Input source resistance, RIN
100 Ω
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Analog Differential Voltage Inputs and Common-Mode Rejection
This ADC has additional applications flexibility due to the analog differential voltage input. The VIN(−) input (pin 7)
can be used to automatically subtract a fixed voltage value from the input reading (tare correction). This is also
useful in 4 mA–20 mA current loop conversion. In addition, common-mode noise can be reduced by use of the
differential input.
The time interval between sampling VIN(+) and VIN(−) is 4-1/2 clock periods. The maximum error voltage due to
this slight time difference between the input voltage samples is given by:
where
•
•
•
∆Ve is the error voltage due to sampling delay
VP is the peak value of the common-mode voltage
fcm is the common-mode frequency
(1)
As an example, to keep this error to 1/4 LSB (∼5 mV) when operating with a 60 Hz common-mode frequency,
fcm, and using a 640 kHz ADC clock, fCLK, would allow a peak value of the common-mode voltage, VP, which is
given by:
(2)
or
(3)
which gives VP–1.9 V.
The allowed range of analog input voltages usually places more severe restrictions on input common-mode noise
levels.
An analog input voltage with a reduced span and a relatively large zero offset can be handled easily by making
use of the differential input (see Reference Voltage).
9.2.1.2.2 Analog Inputs — Input Current
9.2.1.2.2.1 Input Bypass Capacitors
Bypass capacitors at the inputs will average these charges and cause a DC current to flow through the output
resistances of the analog signal sources. This charge pumping action is worse for continuous conversions with
the VIN(+) input voltage at full-scale. For continuous conversions with a 640 kHz clock frequency with the VIN(+)
input at 5V, this DC current is at a maximum of approximately 5 µA. Therefore, bypass capacitors should not be
used at the analog inputs or the VREF/2 pin for high resistance sources (> 1 kΩ). If input bypass capacitors are
necessary for noise filtering and high source resistance is desirable to minimize capacitor size, the detrimental
effects of the voltage drop across this input resistance, which is due to the average value of the input current,
can be eliminated with a full-scale adjustment while the given source resistor and input bypass capacitor are both
in place. This is possible because the average value of the input current is a precise linear function of the
differential input voltage.
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9.2.1.2.2.2 Input Source Resistance
Large values of source resistance where an input bypass capacitor is not used, will not cause errors as the input
currents settle out prior to the comparison time. If a low pass filter is required in the system, use a low valued
series resistor (≤ 1 kΩ) for a passive RC section or add an op amp RC active low pass filter. For low source
resistance applications, (≤ 1 kΩ), a 0.1 μF bypass capacitor at the inputs will prevent noise pickup due to series
lead inductance of a long wire. A 100Ω series resistor can be used to isolate this capacitor — both the R and C
are placed outside the feedback loop — from the output of an op amp, if used.
9.2.1.2.2.3 Noise
The leads to the analog inputs (pins 6 and 7) should be kept as short as possible to minimize input noise
coupling. Both noise and undesired digital clock coupling to these inputs can cause system errors. The source
resistance for these inputs should, in general, be kept below 5 kΩ. Larger values of source resistance can cause
undesired system noise pickup. Input bypass capacitors, placed from the analog inputs to ground, will eliminate
system noise pickup but can create analog scale errors as these capacitors will average the transient input
switching currents of the ADC (see Analog Inputs — Input Current). This scale error depends on both a large
source resistance and the use of an input bypass capacitor. This error can be eliminated by doing a full-scale
adjustment of the ADC (adjust VREF/2 for a proper full-scale reading — see Full-Scale) with the source resistance
and input bypass capacitor in place.
Noise spikes on the VCC supply line can cause conversion errors as the comparator will respond to this noise. A
low inductance tantalum filter capacitor should be used close to the converter VCC pin and values of 1 µF or
greater are recommended. If an unregulated voltage is available in the system, a separate LM340LAZ-5.0, TO92, 5-V voltage regulator for the converter (and other analog circuitry) will greatly reduce digital noise on the VCC
supply.
9.2.1.2.3 Reference Voltage
9.2.1.2.3.1 Span Adjust
For maximum applications flexibility, these ADCs have been designed to accommodate a 5 VDC, 2.5 VDC or an
adjusted voltage reference. This has been achieved in the design of the IC as shown in Figure 32.
Figure 32. The VREFERENCE Design on the IC
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Notice that the reference voltage for the IC is either 1/2 of the voltage applied to the VCC supply pin, or is equal to
the voltage that is externally forced at the VREF/2 pin. This allows for a ratiometric voltage reference using the
VCC supply, a 5 VDC reference voltage can be used for the VCC supply or a voltage less than 2.5 VDC can be
applied to the VREF/2 input for increased application flexibility. The internal gain to the VREF/2 input is 2, making
the full-scale differential input voltage twice the voltage at pin 9.
An example of the use of an adjusted reference voltage is to accommodate a reduced span — or dynamic
voltage range of the analog input voltage. If the analog input voltage were to range from 0.5 VDC to 3.5 VDC,
instead of 0V to 5 VDC, the span would be 3 V as shown in Figure 33. With 0.5 VDC applied to the VIN(−) pin to
absorb the offset, the reference voltage can be made equal to 1/2 of the 3V span or 1.5 VDC. The ADC now will
encode the VIN(+) signal from 0.5V to 3.5 V with the 0.5V input corresponding to zero and the 3.5 VDC input
corresponding to full-scale. The full 8 bits of resolution are therefore applied over this reduced analog input
voltage range.
9.2.1.2.3.2 Reference Accuracy Requirements
The converter can be operated in a ratiometric mode or an absolute mode. In ratiometric converter applications,
the magnitude of the reference voltage is a factor in both the output of the source transducer and the output of
the ADC converter and therefore cancels out in the final digital output code. The ADC0805 is specified
particularly for use in ratiometric applications with no adjustments required. In absolute conversion applications,
both the initial value and the temperature stability of the reference voltage are important factors in the accuracy
of the ADC converter. For VREF/2 voltages of 2.4 VDC nominal value, initial errors of ±10 mVDC will cause
conversion errors of ±1 LSB due to the gain of 2 of the VREF/2 input. In reduced span applications, the initial
value and the stability of the VREF/2 input voltage become even more important. For example, if the span is
reduced to 2.5 V, the analog input LSB voltage value is correspondingly reduced from 20 mV (5V span) to 10 mV
and 1 LSB at the VREF/2 input becomes 5 mV. As can be seen, this reduces the allowed initial tolerance of the
reference voltage and requires correspondingly less absolute change with temperature variations. Note that
spans smaller than 2.5 V place even tighter requirements on the initial accuracy and stability of the reference
source.
In general, the magnitude of the reference voltage will require an initial adjustment. Errors due to an improper
value of reference voltage appear as full-scale errors in the ADC transfer function. IC voltage regulators may be
used for references if the ambient temperature changes are not excessive. The LM336B 2.5-V IC reference
diode (from National Semiconductor) has a temperature stability of 1.8 mV typical (6 mV maximum) over
0°C≤TA≤+70°C. Other temperature range parts are also available.
Figure 33. Analog Input Signal Example
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*Add if VREF/2 ≤ 1 VDC with LM358 to draw 3 mA to ground.
Figure 34. Accommodating an Analog Input from 0.5V (Digital Out = 00HEX) to 3.5 V (Digital Out=FFHEX)
9.2.1.2.4 Errors and Reference Voltage Adjustments
9.2.1.2.4.1 Zero Error
The zero of the ADC does not require adjustment. If the minimum analog input voltage value, VIN(MIN), is not
ground, a zero offset can be done. The converter can be made to output 0000 0000 digital code for this minimum
input voltage by biasing the ADC VIN(−) input at this VIN(MIN) value (see Application Information). This uses the
differential mode operation of the ADC.
The zero error of the ADC converter relates to the location of the first riser of the transfer function and can be
measured by grounding the VIN(−) input and applying a small magnitude positive voltage to the VIN(+) input. Zero
error is the difference between the actual DC input voltage that is necessary to just cause an output digital code
transition from 0000 0000 to 0000 0001 and the ideal 1/2 LSB value (1/2 LSB = 9.8 mV for VREF/2=2.500 VDC).
9.2.1.2.4.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage that is 11/2 LSB less than the
desired analog full-scale voltage range and then adjusting the magnitude of the VREF/2 input (pin 9 or the VCC
supply if pin 9 is not used) for a digital output code that is just changing from 1111 1110 to 1111 1111.
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9.2.1.2.4.3 Adjusting for an Arbitrary Analog Input Voltage Range
If the analog zero voltage of the ADC is shifted away from ground (for example, to accommodate an analog input
signal that does not go to ground) this new zero reference should be properly adjusted first. A VIN(+) voltage that
equals this desired zero reference plus 1/2 LSB (where the LSB is calculated for the desired analog span, 1
LSB=analog span/256) is applied to pin 6 and the zero reference voltage at pin 7 should then be adjusted to just
obtain the 00HEX to 01HEX code transition.
The full-scale adjustment should then be made (with the proper VIN(−) voltage applied) by forcing a voltage to the
VIN(+) input which is given by:
where
•
•
VMAX = The high end of the analog input range
VMIN = the low end (the offset zero) of the analog range. (Both are ground referenced.)
(4)
The VREF/2 (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the
adjustment procedure
9.2.1.2.5 Clocking Option
The clock for the ADC can be derived from the CPU clock or an external RC can be added to provide selfclocking. The CLK IN (pin 4) makes use of a Schmitt trigger as shown in Figure 35.
1
fCLK =
éæ VCC - V - ö æ V + ö ù
T ÷ ç T ÷ú
RC ln êç
ç
÷ ç V ÷ú
V
V
êëè CC
T + ø è T - øû
R @ 10 kΩ
Figure 35. Self-Clocking the ADC
Heavy capacitive or DC loading of the clock R pin should be avoided as this will disturb normal converter
operation. Loads less than 50 pF, such as driving up to 7 ADC converter clock inputs from a single clock R pin of
1 converter, are allowed. For larger clock line loading, a CMOS or low power TTL buffer or PNP input logic
should be used to minimize the loading on the clock R pin (do not use a standard TTL buffer).
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9.2.1.2.6 Restart During a Conversion
If the ADC is restarted (CS and WR go low and return high) during a conversion, the converter is reset and a
new conversion is started. The output data latch is not updated if the conversion in process is not allowed to be
completed, therefore the data of the previous conversion remains in this latch. The INTR output simply remains
at the “1” level.
9.2.1.2.7 Continuous Conversions
For operation in the free-running mode an initializing pulse should be used, following power up, to ensure circuit
operation. In this application, the CS input is grounded and the WR input is tied to the INTR output. This WR and
INTR node should be momentarily forced to logic low following a power-up cycle to ensure operation.
9.2.1.2.8 Driving the Data Bus
This MOS ADC, like MOS microprocessors and memories, will require a bus driver when the total capacitance of
the data bus gets large. Other circuitry, which is tied to the data bus, will add to the total capacitive loading, even
in Tri-state (high impedance mode). Backplane bussing also greatly adds to the stray capacitance of the data
bus.
There are some alternatives available to the designer to handle this problem. Basically, the capacitive loading of
the data bus slows down the response time, even though DC specifications are still met. For systems operating
with a relatively slow CPU clock frequency, more time is available in which to establish proper logic levels on the
bus and therefore higher capacitive loads can be driven (see typical characteristics curves).
At higher CPU clock frequencies time can be extended for I/O reads (and/or writes) by inserting wait states
(8080) or using clock extending circuits (6800).
Finally, if time is short and capacitive loading is high, external bus drivers must be used. These can be Tri-state
buffers (low power Schottky such as the DM74LS240 series is recommended) or special higher drive current
products which are designed as bus drivers. High current bipolar bus drivers with PNP inputs are recommended.
9.2.1.2.9 Wiring and Hook-Up Precautions
Standard digital wire wrap sockets are not satisfactory for breadboarding this ADC converter. Sockets on PCBs
can be used and all logic signal wires and leads should be grouped and kept as far away as possible from the
analog signal leads. Exposed leads to the analog inputs can cause undesired digital noise and hum pickup,
therefore shielded leads may be necessary in many applications.
A single point analog ground that is separate from the logic ground points should be used. The power supply
bypass capacitor and the self-clocking capacitor (if used) should both be returned to digital ground. Any VREF/2
bypass capacitors, analog input filter capacitors, or input signal shielding should be returned to the analog
ground point. A test for proper grounding is to measure the zero error of the ADC converter. Zero errors in
excess of 1/4 LSB can usually be traced to improper board layout and wiring (see Zero Error for measuring the
zero error).
9.2.2 Multiple ADC0801 Series to MC6800 CPU Interface
To transfer analog data from several channels to a single microprocessor system, a multiple converter scheme
presents several advantages over the conventional multiplexer single-converter approach. With the ADC0801
series, the differential inputs allow individual span adjustment for each channel. Furthermore, all analog input
channels are sensed simultaneously, which essentially divides the total system servicing time of the
microprocessor by the number of channels, because all conversions occur simultaneously. This scheme is
shown in Figure 40.
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*Numbers in parentheses refer to MC6800 CPU pin out.
**Number or letters in brackets refer to standard M6800 system common bus code.
Figure 36. ADC0801-MC6800 CPU Interface
In order for the microprocessor to service subroutines and inter- rupts, the stack pointer must be dimensioned in the
user’s program.
Figure 37. Sample Program for Figure 36 ADC0801-MC6800 CPU Interface
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Figure 38. ADC0801–MC6820 PIA Interface
Figure 39. Sample Program for Figure 38 ADC0801–MC6820 PIA Interface
The following schematic and sample subroutine (DATA IN) in Auto-Zeroed Differential Transducer Amplifier and
ADC Converter section may be used to interface (up to) 8 ADC0801’s directly to the MC6800 CPU. This scheme
can easily be extended to allow the interface of more converters. In this configuration the converters are
(arbitrarily) located at HEX address 5000 in the MC6800 memory space. To save components, the clock signal is
derived from just one RC pair on the first converter. This output drives the other ADCs.
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All the converters are started simultaneously with a STORE instruction at HEX address 5000. Note any other
HEX address of the form 5XXX will be decoded by the circuit, pulling all the CS inputs low. This can easily be
avoided by using a more definitive address decoding scheme. All the interrupts are ORed together to insure that
all ADCs have completed their conversion before the microprocessor is interrupted.
The subroutine, DATA IN, may be called from anywhere in the user’s program. Once called, this routine
initializes the CPU, starts all the converters simultaneously and waits for the interrupt signal. Upon receiving the
interrupt, it reads the converters (from HEX addresses 5000 through 5007) and stores the data successively at
(arbitrarily chosen) HEX addresses 0200 to 0207, before returning to the user’s pro- gram. All CPU registers then
recover the original data they had before servicing DATA IN.
9.2.3 Auto-Zeroed Differential Transducer Amplifier and ADC Converter
The differential inputs of the ADC0801 series eliminate the need to perform a differential to single ended
conversion for a differential transducer. Thus, one op amp can be eliminated because the differential to single
ended conversion is provided by the differential input of the ADC0801 series. In general, a transducer preamp is
required to take advantage of the full ADC converter input dynamic range.
*Numbers in parentheses refer to MC6800 CPU pin out.
**Numbers of letters in brackets refer to standard M6800 system common bus code.
Figure 40. Interfacing Multiple ADCs in an MC6800 System
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Figure 41. Sample Program for Figure 40 Interfacing Multiple ADC’s in an MC6800 System
Figure 42. Sample Program for Figure 40 Interfacing Multiple ADC’s in an MC6800 System
Note: In order for the microprocessor to service subroutines and interrupts, the stack pointer must be
dimensioned in the user’s program.
For amplification of DC input signals, a major system error is the input offset voltage of the amplifiers used for
the preamp. Figure 43 is a gain of 100 differential preamp whose offset voltage errors will be cancelled by a
zeroing subroutine which is performed by the INS8080A microprocessor system. The total allowable input offset
voltage error for this preamp is only 50 µV for /⁄4 LSB error. This would obviously require very precise amplifiers.
The expression for the differential output voltage of the preamp is:
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R2 = 49.5 R1
Switches are LMC13334 CMOS analog switches.
The 9 resistors used in the auto-zero section can be ±5% tolerance.
Figure 43. Gain of 100 Differential Transducer Preamp
where
•
IX is the current through resistor RX
(5)
All of the offset error terms can be cancelled by making ±IXRX= VOS1 + VOS3 − VOS2. This is the principle of this
auto-zeroing scheme.
The INS8080A uses the 3 I/O ports of an INS8255 Programable Peripheral Interface (PPI) to control the auto
zeroing and input data from the ADC0801 as shown in Figure 44. The PPI is programmed for basic I/O operation
(mode 0) with Port A being an input port and Ports B and C being output ports. Two bits of Port C are used to
alternately open or close the 2 switches at the input of the preamp. Switch SW1 is closed to force the preamp’s
differential input to be zero during the zeroing subroutine and then opened and SW2 is then closed for
conversion of the actual differential input signal. Using 2 switches in this manner eliminates concern for the ON
resistance of the switches as they must conduct only the input bias current of the input amplifiers.
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Output Port B is used as a successive approximation register by the 8080 and the binary scaled resistors in
series with each output bit create a D/A converter. During the zeroing subroutine, the voltage at Vx increases or
decreases as required to make the differential output voltage equal to zero. This is accomplished by ensuring
that the voltage at the output of A1 is approximately 2.5V so that a logic "1" (5V) on any output of Port B will
source current into node VX thus raising the voltage at VX and making the output differential more negative.
Conversely, a logic "0" (0V) will pull current out of node VX and decrease the voltage, causing the differential
output to become more positive. For the resistor values shown, VX can move ±12 mV with a resolution of 50 µV,
which will null the offset error term to /⁄4 LSB of full-scale for the ADC0801. It is important that the voltage levels
that drive the auto-zero resistors be constant. Also, for symmetry, a logic swing of 0V to 5V is convenient. To
achieve this, a CMOS buffer is used for the logic output signals of Port B and this CMOS package is powered
with a stable 5V source. Buffer amplifier A1 is necessary so that it can source or sink the D/A output current.
Figure 44. Microprocessor Interface Circuitry for Differential Preamp
A flow chart for the zeroing subroutine is shown in Figure 45. It must be noted that the ADC0801 series will
output an all zero code when it converts a negative input [VIN(−) ≥ VIN(+)]. Also, a logic inversion exists as all of
the I/O ports are buffered with inverting gates.
Basically, if the data read is zero, the differential output voltage is negative, so a bit in Port B is cleared to pull VX
more negative which will make the output more positive for the next conversion. If the data read is not zero, the
output voltage is positive so a bit in Port B is set to make VX more positive and the output more negative. This
continues for 8 approximations and the differential output eventually converges to within 5 mV of zero.
The actual program is given in Figure 46. All addresses used are compatible with the BLC 80/10 microcomputer
system. In particular:
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•
•
•
•
•
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Port A and the ADC0801 are at port address E4
Port B is at port address E5
Port C is at port address E6
PPI control word port is at port address E7
Program Counter automatically goes to ADDR:3C3D upon acknowledgment of an interrupt from the ADC0801
9.2.4 Multiple ADC Converters in a Z-80 Interrupt Driven Mode
In data acquisition systems where more than one ADC converter (or other peripheral device) will be interrupting
pro- gram execution of a microprocessor, there is obviously a need for the CPU to determine which device
requires servicing. Figure 47 and the accompanying software is a method of determining which of 7 ADC0801
converters has completed a conversion (INTR asserted) and is requesting an interrupt. This circuit allows starting
the ADC converters in any sequence, but will input and store valid data from the converters with a priority
sequence of ADC 1 being read first, ADC 2 second, etc., through ADC 7 which would have the lowest priority for
data being read. Only the converters whose INT is asserted will be read.
The key to decoding circuitry is the DM74LS373, 8-bit D type flip-flop. When the Z-80 acknowledges the
interrupt, the program is vectored to a data input Z-80 subroutine. This subroutine will read a peripheral status
word from the DM74LS373 which contains the logic state of the INTR outputs of all the converters. Each
converter which initiates an interrupt will place a logic "0" in a unique bit position in the status word and the
subroutine will determine the identity of the converter and execute a data read. An identifier word (which
indicates which ADC the data came from) is stored in the next sequential memory location above the location of
the data so the program can keep track of the identity of the data entered.
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Figure 45. Flow Chart for Auto-Zero Routine
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NOTE: All numerical values are hexadecimal representations.
Figure 46. Software for Auto-Zeroed Differential ADC
The following notes apply:
• It is assumed that the CPU automatically performs a RST 7 instruction when a valid interrupt is acknowledged
(CPU is in interrupt mode 1). Hence, the subroutine starting address of X0038.
• The address bus from the Z-80 and the data bus to the Z-80 are assumed to be inverted by bus drivers.
• ADC data and identifying words will be stored in sequential memory locations starting at the arbitrarily chosen
address X 3E00.
• The stack pointer must be dimensioned in the main program as the RST 7 instruction automatically pushes
the PC onto the stack and the subroutine uses an additional 6 stack addresses.
• The peripherals of concern are mapped into I/O space with the following port assignments:
Table 3. Port Assignment Where Peripherals are Mapped into I/O Space
HEX PORT ADDRESS
PERIPHERAL
HEX PORT ADDRESS
PERIPHERAL
00
MM74C374 8-bit flip-flop
04
ADC 4
01
ADC 1
05
ADC 5
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Table 3. Port Assignment Where Peripherals are Mapped into I/O Space (continued)
HEX PORT ADDRESS
PERIPHERAL
HEX PORT ADDRESS
PERIPHERAL
02
ADC 2
06
ADC 6
03
ADC 3
07
ADC 7
This port address also serves as the ADC identifying word in the program.
Figure 47. Multiple ADCs With Z-80 Type Microprocessor
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9.3 System Examples
*For low power, see also LM385–2.5
Figure 48. 6800 Interface
Figure 49. Absolute With a 2.5-V Reference
Note: before using caps at VIN or VREF/2, see section Input Bypass
Capacitors.
Figure 50. Ratiometeric With Full-Scale Adjust
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Figure 51. Absolute With a 5-V Reference
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System Examples (continued)
Figure 52. Zero-Shift and Span Adjust: 2 V ≤ VIN ≤ 5
V
Figure 53. Span Adjust: 0 V ≤ VIN ≤ 3 V
VREF/2 = 256 mV
For: VIN(+)>VIN(−); Output = FFHEX
For: VIN(+) < VIN(−); Output = 00HEX
Figure 54. Directly Converting a Low-Level Signal
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Figure 55. A µP Interfaced Comparator
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System Examples (continued)
VREF/2=128 mV; 1 LSB =1 mV; VDAC ≤ VIN ≤ (VDAC + 256 mV); 0 ≤
VDAC < 2.5 V
Figure 56. 1-mV Resolution With µP-Controlled
Range
Figure 57. Digitizing a Current Flow
*After power up, a momentary grounding of the WR input is needed
to ensure operation.
* Use a large R value to reduce loading at CLK R output.
Figure 58. Self-Clocking Multiple ADCs
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Figure 59. Self-Clocking in Free-Running Mode
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System Examples (continued)
100 kHz ≤ fCLK ≤ 1460 kHz
Figure 60. µP Interface for Free-Running ADC
Figure 61. External clocking
J
*VIN(−) = 0.15 VCC
15% of VCC ≤ VXDR ≤ 85% of VCC
Figure 62. Operating With “Automotive”
Ratiometric Transducers
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Figure 63. Ratiometric With VREF/2 Forced
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System Examples (continued)
*Select R value DB7 = “1” for VIN(+)>VIN(−)+(VREF/2). Omit circuitry
within the dotted area if hysteresis is not needed.
*Beckman Instruments #694-3-R10K resistor array
Figure 64. µP-Compatible Differential-Input
Comparator With Pre-Set VOS (With or Without
Hysteresis)
Figure 65. Handling ±10-V Analog Inputs
**Can calibrate each sensor to allow easy replacement, then ADC
can be calibrated with a pre-set input voltage.
Figure 66. Low-Cost, µP-Interfaced, Temperatureto-Digital Converter
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Figure 67. µP-Interfaced Temperature-to-Digital
Converter
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System Examples (continued)
*Beckman Instruments #694-3-R10K resistor array
Figure 68. Handling ±5-V Analog Inputs
Figure 69. Read-Only Interface
Diodes are 1N914
Figure 70. µP-Interfaced Comparator With
Hysteresis
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Figure 71. Protecting the Input
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System Examples (continued)
*LM389 transistors A, B, C, D = LM324A quad op amp
Figure 72. Analog Self-Test for a System
Figure 73. A Low-Cost, 3-Decade Logarithmic
Converter
fC=20 Hz
Uses Chebyshev implementation for steeper roll-off unity-gain, 2nd
order, low-pass filter
Adding a separate filter for each channel increases system response
time if an analog multiplexer is used
Figure 74. 3-Decade Logarithmic ADC Converter
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Figure 75. Noise Filtering the Analog Input
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System Examples (continued)
*ADC output data is updated 1 CLK period prior to assertion of INTR
Figure 76. Output Buffers With ADC Data Enabled
Figure 77. Multiplexing Differential Inputs
(2) Consider the amplitude errors which are introduced within the
passband of the filter.
*Allows output data to set-up at falling edge of CS
Figure 78. Increasing Bus Drive and/or
Reducing Time on Bus
Figure 79. Sampling an AC Input Signal
(Complete shutdown takes ≈ 30 seconds.)
Buffer prevents data bus from overdriving output of ADC when in
shutdown mode.
Figure 80. 70% Power Savings by Clock Gating
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Figure 81. Power Savings by ADC and VREF
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10 Power Supply Recommendations
Precautions should be taken to insure that the power supply for the integrated circuit never becomes reversed in
polarity or that the unit is not inadvertently installed backwards in a test socket as an unlimited current surge
through the resulting forward diode within the device could cause fusing of the internal conductors and result in a
destroyed unit.
Noise spikes on the VCC supply line can cause conversion errors as the comparator will respond to this noise. A
low-inductance, low-ESR tantalum bypass capacitor should be used close to the converter VCC pin, and a 10-µF
is recommended. If an unregulated voltage is available in the system, a separate 5-V voltage regulator for the
converter (and other analog circuitry) will greatly reduce digital noise on the VCC supply.
11 Layout
11.1 Layout Guidelines
All logic signal wires and leads should be grouped and kept as far away as possible from the analog signal
leads. Exposed leads to the analog inputs can cause undesired digital noise and 60-Hz pickup. Shielded leads
for the analog inputs may be required in sensitive applications. A single-point analog ground should be used that
is also separated from the logic ground points. The power supply bypass capacitor should be returned to digital
ground. Any VREF/2 bypass capacitors, analog input filter capacitors, or input signal shielding should be returned
to the analog ground point. A test for proper grounding is to measure the zero error of the ADC converter. Zero
errors in excess of 1/4 LSB is generally traceable to improper PCB layout and/or wiring.
To minimize potential offset issues, TI recommends to route the signal traces differentially next to each other so
that they will see the same thermal gradients and the same number of feedthroughs. Furthermore, inductance is
determined by the size of the loop of current. Providing a path for return currents next to the signal trace will
reduce the inductance. A solid ground plane is very advantageous in this regard. Ensure to minimize the loop
area formed by the bypass capacitor connection between VCC and ground. The ground pin should be connected
to the PCB ground plane at the pin of the device.
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ADC0801
Click here
Click here
Click here
Click here
Click here
ADC0802
Click here
Click here
Click here
Click here
Click here
ADC0803
Click here
Click here
Click here
Click here
Click here
ADC0804
Click here
Click here
Click here
Click here
Click here
ADC0805
Click here
Click here
Click here
Click here
Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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49
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADC0802LCWM/NOPB
ACTIVE
SOIC
DW
20
36
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
0 to 70
ADC0802
LCWM
ADC0804LCWM/NOPB
ACTIVE
SOIC
DW
20
36
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
0 to 70
ADC0804
LCWM
ADC0804LCWMX/NOPB
ACTIVE
SOIC
DW
20
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
0 to 70
ADC0804
LCWM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADC0804LCWMX/NOPB
Package Package Pins
Type Drawing
SOIC
DW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
10.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.3
3.25
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADC0804LCWMX/NOPB
SOIC
DW
20
1000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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