Texas Instruments | DAC7551-Q1 12-Bit, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter (Rev. B) | Datasheet | Texas Instruments DAC7551-Q1 12-Bit, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter (Rev. B) Datasheet

Texas Instruments DAC7551-Q1 12-Bit, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter (Rev. B) Datasheet
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DAC7551-Q1
SLAS767B – JUNE 2011 – REVISED MARCH 2015
DAC7551-Q1 12-Bit, Ultra-Low Glitch, Voltage Output
Digital-to-Analog Converter
1 Features
3 Description
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The DAC7551-Q1 device is a single-channel, voltageoutput digital-to-analog converter (DAC) with
exceptional linearity and monotonicity, and a
proprietary architecture that minimizes glitch energy.
The low-power DAC7551-Q1 device operates from a
single 2.7- to 5.5-V supply. The DAC7551-Q1 output
amplifiers can drive a 2-kΩ, 200-pF load rail-to-rail
with 5-μs settling time. The output range is set using
an external voltage reference.
1
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Qualified for Automotive Applications
Relative Accuracy (INL): ±0.35 LSB
Ultra-Low Glitch Energy: 0.1 nV-s
Low-Power Operation: 100 μA at 2.7 V
Power-On Reset-to-Zero Scale
Power Supply: 2.7- to 5.5-V Single Supply
Power-Down: 0.05 μA at 2.7 V
12-Bit Linearity and Monotonicity
Rail-to-Rail Voltage Output
Settling Time: 5 μs (Max)
SPI-Compatible Serial Interface With SchmittTrigger Input: Up to 50 MHz
Daisy-Chain Capability
Asynchronous Hardware Clear-to-Zero Scale
Specified Temperature Range:
–40°C to +105°C
Small, 2-mm × 3-mm, 12-Lead USON Package
Z-Suffix Offers Improved Delamination
The 3-wire serial interface operates at clock rates up
to 50 MHz and is compatible with SPI™, QSPI™,
microwire, and DSP interface standards. The device
incorporates a power-on-reset (POR) circuit to ensure
that the DAC output powers up to 0 V and remains at
that voltage until a valid write cycle to the device
occurs. The device contains a power-down feature
that reduces the current consumption of the device to
under 2 μA.
Small size and low-power operation make the
DAC7551-Q1 device ideally suited for batteryoperated,
portable
applications.
The
power
consumption is typically 0.5 mW at 5 V, 0.23 mW at
3 V, and reduces to 1 μW in power-down mode.
2 Applications
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The DAC7551-Q1 device is available in a 12-pin
USON package and is specified over –40°C to
+105°C. The Z-suffix offers reduced delamination
compared to standard device.
Portable, Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
ADAS Radar Applications
Collision Warning
Blind-Spot Detection
Device Information(1)
PART NUMBER
DAC7551-Q1
PACKAGE
USON (12)
BODY SIZE (NOM)
2.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
VDD
VREFH
IOVDD
VFB
SCLK
_
SYNC
Interface
Logic
Shift
Register
DAC
Register
String
DAC
VOUT
+
SDIN
Power-On
Reset
SDO
CLR
Power-Down
Logic
GND
VREFL
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC7551-Q1
SLAS767B – JUNE 2011 – REVISED MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
4
4
4
4
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 13
7.5 Programming........................................................... 14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 16
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
Changes from Revision A (February 2015) to Revision B
Page
•
Added ADAS radar, collision warning, and blind-spot detection to Applications list ............................................................. 1
•
Changed the thermal information values for the DRN (USON) package in the Thermal Information table .......................... 4
Changes from Original (June 2011) to Revision A
Page
•
Added the ESD Ratings table, Recommended Operating Conditions table, Feature Description section, Device
Functional Modes section, Application and Implementation section, Power Supply Recommendations section,
Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
•
Released the Z-suffix orderable part number, DAC7551ZTDRNRQ1, which offers improved delamination ........................ 1
2
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SLAS767B – JUNE 2011 – REVISED MARCH 2015
5 Pin Configuration and Functions
DRN Package
12-Pin USON With Exposed Thermal Pad
Top View
(1)
VDD
1
12
IOVDD
VREFH
2
11
SDO
VREFL
3
10
SDIN
VFB
4
9
SCLK
VOUT
5
8
SYNC
GND
6
7
CLR
Thermal
Pad(1)
The thermal pad should be connected to GND.
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
VDD
I
Analog voltage supply input
2
VREFH
I
Positive reference voltage input
3
VREFL
I
Negative reference voltage input
4
VFB
I
DAC amplifier sense input.
5
VOUT
O
Analog output voltage from DAC
6
GND
—
Ground.
7
CLR
I
Asynchronous input to clear the DAC registers. When the CLR pin is low, the DAC register is set to
000h and the output voltage to 0 V.
8
SYNC
I
Frame synchronization input. The falling edge of the SYNC pulse indicates the start of a serial data
frame shifted out to the DAC7551-Q1 device.
9
SCLK
I
Serial clock input
10
SDIN
I
Serial data input
11
SDO
O
Serial data output
12
IOVDD
I
I/O voltage supply input
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). (1)
MIN
MAX
UNIT
VDD , IOVDD to GND
–0.3
6
V
Digital input voltage to GND
–0.3
VDD + 0.3
V
VOUT to GND
–0.3
VDD + 0.3
V
Operating temperature range
–40
105
°C
150
°C
Junction temperature, TJ max
Power dissipation (DRN)
(TJ max – TA) / RθJA
Storage temperature, Tstg
–65
(1)
150
°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
All pins
±500
Corner pins (1, 6, 7, and
12)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
VREFH
0.25
VREFL
0
VFB
VI
Input voltage
Output voltage
TJ
Operating junction temperature
MAX
UNIT
5.5
VDD
GND
0
IOVDD
VO
NOM
2.7
VDD
VDD
1.8
VDD
CLR
0
IOVDD
SYNC
0
IOVDD
SCLK
0
IOVDD
SDIN
0
IOVDD
SDO
0
IOVDD
VOUT
0
VDD
150
V
V
°C
6.4 Thermal Information
DRN (USON)
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
49.8
RθJC(top)
Junction-to-case (top) thermal resistance
45.8
RθJB
Junction-to-board thermal resistance
18.2
ψJT
Junction-to-top characterization parameter
0.8
ψJB
Junction-to-board characterization parameter
18.3
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.9
(1)
UNIT
12 PINS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
all specifications at –40°C to +105°C, VDD = 2.7 to 5.5 V, VREFH = VDD, VREFL = GND, RL = 2 kΩ to GND, and CL = 200 pF to
GND (unless otherwise noted).
PARAMETER
STATIC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±0.35
±1
LSB
±0.08
±0.5
LSB
±12
mV
(1)
Resolution
12
Relative accuracy
Differential nonlinearity
Specified monotonic by design
Bits
Offset error
Zero-scale error
All zeroes loaded to DAC register
±12
Gain error
Full-scale error
Zero-scale error drift
Gain temperature coefficient
(1)
4
mV
±0.15
%FSR
±0.5
%FSR
7
μV/°C
3
ppm of
FSR/°C
Linearity tested using a reduced code range of 30 to 4065; output unloaded.
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Electrical Characteristics (continued)
all specifications at –40°C to +105°C, VDD = 2.7 to 5.5 V, VREFH = VDD, VREFL = GND, RL = 2 kΩ to GND, and CL = 200 pF to
GND (unless otherwise noted).
PARAMETER
PSRR
Power-supply rejection ratio
TEST CONDITIONS
MIN
VDD = 5 V
TYP
MAX
0.75
UNIT
mV/V
OUTPUT CHARACTERISTICS (2)
2×
VREFL
Output voltage range
Output voltage settling time
RL = 2 kΩ, 0 pF < CL < 200 pF
1.8
Capacitive load stability
Digital-to-analog glitch impulse
V
μs
5
Slew rate
RL = ∞
V/μs
470
RL = 2 kΩ
pF
1000
1 LSB change around major carry
0.1
Digital feedthrough
THD
VREFH
nV-s
0.1
nV-s
Output noise density
10kHz offset frequency
120
nV/√Hz
Total harmonic distortion
fOUT = 1 kHz, fS = 1 MSPS, BW = 20 kHz
–85
dB
1
Ω
DC output impedance
Short-circuit current
Power-up time
VDD = 5 V
50
VDD = 3 V
20
Coming out of power-down mode, VDD = 5 V
15
Coming out of power-down mode, VDD = 3 V
15
mA
μs
REFERENCE INPUT
VREFH input range
0
VREFL input range
VREFL < VREFH
0
Reference input impedance
Reference current
VDD
GND
V
VDD
100
V
kΩ
VREF = VDD = 5 V
50
100
VREF = VDD = 3 V
30
60
μA
LOGIC INPUTS (2)
Input current
VIN_L
Input low voltage
IOVDD ≥ 2.7 V
VIN_H
Input high voltage
IOVDD ≥ 2.7 V
±1
μA
0.3
IOVDD
V
0.7
IOVDD
V
Pin capacitance
3
pF
POWER REQUIREMENTS
VDD
Supply voltage
2.7
5.5
V
IOVDD
I/O supply voltage (3)
1.8
VDD
V
IDD
Supply current (4)
Normal operation
VDD = 3.6 to 5.5 V, VIH = IOVDD, VIL = GND
(DAC active and
excluding load current) VDD = 2.7 to 3.6 V, VIH = IOVDD, VIL = GND
All power-down modes
150
200
100
150
VDD = 3.6 to 5.5 V, VIH = IOVDD, VIL = GND
0.2
2
VDD = 2.7 to 3.6 V, VIH = IOVDD, VIL = GND
0.05
2
ILOAD = 2 mA, VDD = 5 V
93%
μA
μA
POWER EFFICIENCY
IOUT/IDD
TEMPERATURE RANGE
Specified performance
(2)
(3)
(4)
–40
105
°C
Specified by design and characterization; not production tested. For 1.8 V < IOVDD < 2.7 V, TI recommends that VIH ≥ 0.8 IOVDD, and
VIL ≤ 0.2 IOVDD.
IOVDD operates down to 1.8 V with slightly degraded timing, as long as VIH ≥ 0.8 IOVDD and VIL ≤ 0.2 IOVDD.
IDD tested with digital input code = 0032.
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6.6 Timing Requirements (1)
All specifications at –40°C to +105°C, VDD = 2.7 to 5.5 V, and RL = 2 kΩ to GND (unless otherwise noted). See Figure 1.
MIN
t1 (2)
SCLK cycle time
t2
SCLK HIGH time
t3
SCLK LOW time
t4
SYNC falling edge to SCLK falling edge setup time
t5
Data setup time
t6
Data hold time
t7
SCLK falling edge to SYNC rising edge
t8
Minimum SYNC HIGH time
t9
SCLK falling edge to SDO valid
t10
CLR pulse width low
(1)
(2)
(3)
MAX
VDD = 2.7 V to 3.6 V
20
VDD = 3.6 V to 5.5 V
20
VDD = 2.7 V to 3.6 V
6.5
VDD = 3.6 V to 5.5 V
6.5
VDD = 2.7 V to 3.6 V
6.5
VDD = 3.6 V to 5.5 V
6.5
VDD = 2.7 V to 3.6 V
4
VDD = 3.6 V to 5.5 V
4
VDD = 2.7 V to 3.6 V
3
VDD = 3.6 V to 5.5 V
3
VDD = 2.7 V to 3.6 V
3
VDD = 3.6 V to 5.5 V
3
VDD = 2.7 V to 3.6 V
0
t1 – 10 ns (3)
VDD = 3.6 V to 5.5 V
0
t1 – 10 ns (3)
VDD = 2.7 V to 3.6 V
20
VDD = 3.6 V to 5.5 V
20
VDD = 2.7 V to 3.6 V
10
VDD = 3.6 V to 5.5 V
10
VDD = 2.7 V to 3.6 V
10
VDD = 3.6 V to 5.5 V
10
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH) / 2.
Maximum SCLK frequency is 50 MHz at VDD = 2.7 to 5.5 V.
SCLK falling edge to SYNC rising edge time shold not exceed (t1 – 10 ns) to latch the correct data.
t1
SCLK
t8
t2
t3
t4
t7
SYNC
t5
SDIN
D15
t6
D14
D13
D12
D11
D1
D0
Input Word n
SDO
D15
D0
t9
D15
Input Word n+1
D14
D0
Input Word n
Undefined
t10
CLR
Figure 1. Serial Write Operation Timing Diagram
6
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6.7 Typical Characteristics
1.0
1.0
0.5
0.5
LE (LSB)
LE (LSB)
At TA = 25°C, unless otherwise noted.
0
-1.0
-1.0
0.50
0.50
0.25
0.25
DLE (LSB)
DLE (LSB)
0
-0.5
-0.5
0
-0.25
0
-0.25
-0.50
-0.50
0
512
1024
1536
2048
2560
3072
3584
0
4096
512
1024
VREFH = 4.096 V
VDD = 2.7 V
VREFL = GND
2560
3072
3584
4096
VREFH = 2.5 V
VREFL = GND
Figure 3. Linearity Error and Differential Linearity Error vs
Digital Input Code
1.00
1.00
0.75
0.75
0.50
0.25
0.50
0.25
0
0
-40
-10
20
50
80
105
-40
-10
VDD = 5 V
VREFH = 4.096 V
20
50
80
105
Free-Air Temperature (°C)
Free-Air Temperature (°C)
VREFL = GND
VDD = 2.7 V
VREFH = 2.5 V
VREFL = GND
Figure 4. Zero-Scale Error vs Free-Air Temperature
Figure 5. Zero-Scale Error vs Free-Air Temperature
0
0
-0.25
-0.25
Full-Scale Error (mV)
Full-Scale Error (mV)
2048
Figure 2. Linearity Error and Differential Linearity Error vs
Digital Input Code
Zero-Scale Error (mV)
Zero-Scale Error (mV)
VDD = 5 V
1536
Digital Input Code
Digital Input Code
-0.50
-0.75
-1.00
-0.50
-0.75
-1.00
-40
-10
20
50
80
105
-40
Free-Air Temperature (°C)
VDD = 5 V
VREFH = 4.096 V
-10
20
50
80
105
Free-Air Temperature (°C)
VREFL = GND
Figure 6. Full-Scale Error vs Free-Air Temperature
VDD = 2.7 V
VREFH = 2.5 V
VREFL = GND
Figure 7. Full-Scale Error vs Free-Air Temperature
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Typical Characteristics (continued)
At TA = 25°C, unless otherwise noted.
5.5
VDD = VREFH = 5.5V
0.15
Output Voltage, VO (V)
Output Voltage, VO (V)
0.20
VDD = 2.7 V
VREFH = 2.5 V
VREFL = GND
0.10
VDD = 5.5 V
VREFH = 4.096 V
VREFL = GND
0.05
VREFL = GND
5.4
5.3
DAC Loaded with FFFFh
0
5.2
0
5
10
15
0
5
Sink Current, ISINK (mA)
10
15
ISOURCE (mA)
DAC loaded with 0000h
Figure 8. Sink Current at Negative Rail (Typical)
Figure 9. Source Current at Positive Rail
250
VDD = VREFH = 2.7V
VREFL = GND
2.6
VDD = 5.5 V
VREFH = 4.096 V
VREFL = GND
200
Supply Current (µA)
Output Voltage, VO (V)
2.7
2.5
150
VDD = 2.7 V
VREFH = 2.5 V
VREFL = GND
100
50
DAC Loaded with FFFFh
0
2.4
0
5
10
512
0
15
1024
ISOURCE (mA)
1536 2048 2560
Digital Input Code
Powered
4096
No load
110
200
VDD = 5.5 V
VREFH = 4.096 V
VREFL = GND
175
150
Supply Current (µA)
Supply Current (µA)
3584
Figure 11. Supply Current vs Digital Input Code
Figure 10. Source Current at Positive Rail
VDD = 2.7 V
VREFH = 2.5 V
VREFL = GND
125
105
100
95
90
100
-40
-10
20
50
80
110
3.1
2.7
3.5
Powered
3.9
4.3
4.7
5.1
5.5
Supply Voltage (V)
Free-Air Temperature (°C)
No load
DAC powered, no load
Figure 12. Supply Current vs Free-Air Temperature
8
3072
VREFH = 2.5 V
VREFL = GND
Figure 13. Supply Current vs Supply Voltage
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Typical Characteristics (continued)
At TA = 25°C, unless otherwise noted.
2000
1200
1500
VDD = 5.5 V
VREFH = 4.096 V
VREFL = GND
800
Frequency (Hz)
Supply Current (µA)
1600
1000
VDD = 2.7 V
VREFH = 2.5 V
VREFL = GND
400
500
0
0
0
1
2
3
4
5
128
136
VLOGIC (V)
TA = 25°C
SCLK input
Digital input code = 2048
VDD = 5.5 V
VREFH = 4.096 V
All other inputs = GND
1500
2
Total Error (mV)
Frequency (Hz)
4
500
192
VREFL = GND
0
-2
0
-4
117
124
131 138 145 152 159
Current Consumption (µA)
Digital input code = 2048
VDD = 2.7 V
VREFH = 2.5 V
166
0
173
512
VDD = 5 V
TA = 25°C
VREFL = GND
Figure 16. Histogram of Current Consumption, 2.7 V
1024
1536 2048 2560
Digital Input Code
3072
VREFH = 4.096 V
3584
4096
VREFL = GND
Figure 17. Total Error, 5 V
5
Output Voltage, VO (V)
4
2
Total Error (mV)
184
Figure 15. Histogram of Current Consumption, 5.5 V
Figure 14. Supply Current vs Logic Input Voltage
2000
1000
144 152 160 168 176
Current Consumption (µA)
0
-2
4
3
2
1
0
-4
0
512
1024
1536
2048
2560
3072
3584
Digital Input Code
VDD = 2.7 V
TA = 25°C
VREFH = 2.5 V
Time (4 µs/div)
4096
VREFL = GND
Power-up code = 4000
VDD = 5 V
VREFH = 4.096 V
Figure 18. Total Error, 2.7 V
VREFL = GND
Figure 19. Exiting Power-Down Mode
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Typical Characteristics (continued)
At TA = 25°C, unless otherwise noted.
3
4
Output Voltage, VO (V)
Output Voltage, VO (V)
5
3
2
1
0
2
1
0
Time (5 µs/div)
Time (5 µs/div)
Output loaded with 200 pF to GND
Code 0041 to 4055
VDD = 5 V
VREFH = 4.096 V
VREFL = GND
Output loaded with 200 pF to GND
Code 0041 to 4055
VDD = 2.7 V
VREFH = 2.5 V
VREFL = GND
Figure 21. Large-Signal Settling Time, 2.7 V
Output Voltage, VO (5 mV/div)
Output Voltage, VO (5 mV/div)
Figure 20. Large-Signal Settling Time, 5 V
Trigger Pulse
Trigger Pulse
Time (400 ns/div)
Time (400 ns/div)
Figure 22. Midscale Glitch
Figure 23. Worst-Case Glitch
VO (5mV/div)
Total Harmonic Distortion (dB)
-40
Trigger Pulse
-50
-60
-70
THD
-80
2nd Harmonic
-90
3rd Harmonic
-100
0
Time (400ns/div)
1
2
3
4
5
6
7
Output Frequency, Tone (kHz)
8
9
10
VDD = 5.5 V
VREFH = 4.096 V
VREFL = GND
fS = 1 MSPS
–1-dB FSR digital input
Measurement bandwidth = 20 kHz
Figure 24. Digital Feedthrough Error
10
Figure 25. Total Harmonic Distortion vs Output Frequency
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7 Detailed Description
7.1 Overview
The DAC7551-Q1 device is a 12-bit resistor-string digital-to-analog converter (DAC). Unbuffered external
reference inputs allow for a positive voltage reference as low as 0.25 V and as high as VDD. An amplifierfeedback input is available for better DC accuracy at the load point. The device is controlled over a 16-bit word
three-wire serial peripheral interface (SPI) up to 50 MHz with an option to daisy-chain multiple devices. An
asynchronous clear function along with power-down features allows for software controlled resets and low-power
consumption. A separate logic-supply input means the device can be used with different logic families across a
wide range of supply voltages.
7.2 Functional Block Diagram
VDD
VREFH
IOVDD
VFB
SCLK
_
Interface
Logic
SYNC
Shift
Register
DAC
Register
VOUT
String
DAC
+
SDIN
Power-On
Reset
SDO
Power-Down
Logic
CLR
GND
VREFL
7.3 Feature Description
7.3.1 Digital-to-Analog Converter
The architecture of the DAC7551-Q1 device consists of a string DAC followed by an output buffer amplifier.
Figure 26 shows a generalized block diagram of the DAC architecture.
VREFH
100 kW
100 kW
VFB
50 kW
DAC
Register
REF(+)
Resistor String
REF(-)
VOUT
VREFL
Figure 26. Typical DAC Architecture
The input coding to the DAC7551-Q1 device is unsigned binary, which gives the ideal output voltage as show in
Equation 1.
VOUT = 2 × VREFL + (VREFH – VREFL) × D / 4096
where
•
D is the decimal equivalent of the binary code that is loaded to the DAC register, which ranges from 0 to 4095.
(1)
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Feature Description (continued)
7.3.2 Resistor String
Figure 27 shows the resistor string section. This section is simply a string of resistors, each of value R. The
digital code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed
into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the
amplifier. The output of the DAC is specified monotonic because it is a string of resistors.
VREFH
RDIVIDER
VREFH - VREFL
2
R
R
To Output Amplifier
(2× Gain)
R
R
VREFL
Figure 27. Typical Resistor String
7.3.3 Output Buffer Amplifiers
The output buffer amplifier is capable of generating rail-to-rail voltages on the output, providing an output range
of 0 V to VDD. The amplifier is capable of driving a load of 2 kΩ in parallel with up to 1000 pF to ground. Figure 8,
Figure 9, and Figure 10 show the sink and source capabilities of the output amplifier. The slew rate is 1.8 V/μs
with a half-scale settling time of 3 μs with the output unloaded.
7.3.3.1 DAC External Reference Input
The DAC7551-Q1 device contains VREFH and VREFL reference inputs which are unbuffered. The VREFH reference
voltage can be as low as 0.25 V, and as high as VDD because there is no restriction of headroom and footroom
from any reference amplifier.
Using a buffered reference in the external circuit is recommended (for example, the REF3140 device). The input
impedance is typically 100 kΩ.
12
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Feature Description (continued)
7.3.3.2 Amplifier Sense Input
The DAC7551-Q1 device contains an amplifier-feedback input pin, VFB. For voltage output operation, VFB must
be externally connected to VOUT. For better DC accuracy, this connection should be made at load points. The VFB
pin is also useful for a variety of applications, including digitally-controlled current sources. The feedback input
pin is internally connected to the DAC amplifier negative input terminal through a 100-kΩ resistor. The amplifier
negative input terminal internally connects to ground through another 100-kΩ resistor (see Figure 26). These
connections form a gain-of-two, noninverting, amplifier configuration. Overall gain remains 1 because the resistor
string has a divide-by-two configuration. The resistance seen at the VFB pin is approximately 200 kΩ to ground.
7.3.3.3 Power-On Reset
On power up, all registers are cleared and the DAC channel is updated with zero-scale voltage. The DAC output
remains in this state until valid data are written. This setup is particularly useful in applications where knowing the
state of the DAC output while the device is powering up is important. To not turn on ESD protection devices, VDD
and IOVDD should be applied before any other pin (such as VREFH) is brought high. The power-up sequence of
VDD and IOVDD is irrelevant. Therefore, IOVDD can be brought up before VDD, or the other way around.
7.3.3.4 Power Down
The DAC7551-Q1 device has a flexible power-down capability. During a power-down condition, the user has
flexibility to select the output impedance of the DAC. During power-down operation, the DAC can have either
1kΩ, 100kΩ, or Hi-Z output impedance to ground.
7.3.3.5 Asynchronous Clear
The DAC7551-Q1 output is asynchronously set to zero-scale voltage immediately after the CLR pin is brought
low. The CLR signal resets all internal registers and therefore functions similar to the power-on reset. The
DAC7551-Q1 device updates at the first rising edge of the SYNC signal that occurs after the CLR pin is brought
back to high.
7.3.3.6 IOVDD and Level Shifters
The DAC7551-Q1 device can be used with different logic families that require a wide range of supply voltages.
To enable this useful feature, the IOVDD pin must be connected to the logic supply voltage of the system. All
DAC7551-Q1 digital input and output pins are equipped with level-shifter circuits. Level shifters at the input pins
ensure that external logic-high voltages are translated to the internal logic-high voltage, with no additional power
dissipation. Similarly, the level shifter for the SDO pin translates the internal logic-high voltage (VDD) to the
external logic-high level (IOVDD). For single-supply operation, the IOVDD pin can be tied to the VDD pin.
7.3.4 Integral and Differential Linearity
The DAC7551-Q1 device uses precision thin-film resistors providing exceptional linearity and monotonicity.
Integral linearity error is typically within ±0.35 LSBs, and differential linearity error is typically within ±0.08 LSBs.
7.3.5 Glitch Energy
The DAC7551-Q1 device uses a proprietary architecture that minimizes glitch energy. The code-to-code glitches
are so low that they are usually buried within the wide-band noise and cannot be easily detected. The
DAC7551-Q1 glitch is typically well under 0.1 nV-s. Such low glitch energy provides more than a ten-time
improvement over industry alternatives.
7.4 Device Functional Modes
The DAC7551-Q1 device uses four modes of operation. These modes are accessed by setting bit PD0 (DB13)
and PD1 (DB14) in the control register. Table 1 shows how to control the operating mode with data bits PD0
(DB13) and PD1 (DB14). The DAC7551-Q1 device treats the power-down condition as data; all the operation
modes are still valid for power down. Broadcasting a power-down condition to all the DAC7551-Q1 devices in a
system is possible. Powering down a channel and updating data on other channels is also possible. Furthermore,
writing to the DAC register or buffer of the DAC channel that is powered down is also possible. When the DAC is
the powered on, the DAC contains this new value.
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Device Functional Modes (continued)
When both the PD0 and PD1 bits are set to 0, the device works normally with the typical consumption of 100 µA
at 2.7 V. For the three power-down modes, the supply current falls to 0.05 µA at 2.7 V. As listed in Table 1, three
different power-down options are available. The VOUT pin can be connected internally to GND through a 1-kΩ
resistor or a 100-kΩ resistor or can be open circuited (High-Z). In other words, DB14 and DB13 = 11 represent a
power-down condition with High-Z output impedance for a selected channel. DB14 and DB13 = 01 and 10
represent a power-down condition with a 1-kΩ and 100-kΩ output impedance respectively.
7.5 Programming
7.5.1 Serial Interface
The DAC7551-Q1 device is controlled over a versatile 3-wire serial interface, which operates at clock rates up to
50 MHz and is compatible with SPI, QSPI, Microwire, and DSP interface standards.
Table 1. Serial Interface Programming
CONTROL
DATA BITS
FUNCTION
DB15
DB14
DB13
(PD1)
DB12
(PD0)
DB11–DB0
X
X
0
0
data
Normal mode
X
X
0
1
X
Powerdown 1kΩ
X
X
1
0
X
Powerdown 100kΩ
X
X
1
1
X
Powerdown Hi-Z
7.5.1.1 16-Bit Word and Input Shift Register
The input shift register is 16 bits wide. DAC data are loaded into the device as a 16-bit word under the control of
a serial clock input, SCLK, as shown in Figure 1. The 16-bit word, listed in Table 1, consists of four control bits
followed by 12 bits of DAC data. The data format is straight binary with all 0s corresponding to 0-V output and all
1s corresponding to full-scale output (VREF – 1 LSB). Data are loaded MSB first (bit 15) where the first two bits
(DB15 and DB14) are don't care bits. Bit 13 and bit 12 (DB13 and DB12) determine either normal mode
operation or power-down mode (see Table 1).
The SYNC input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can
only be transferred into the device while the SYNC pin is low. To begin the serial data transfer, the SYNC pin
should be taken low, observing the minimum SYNC-to-SCLK falling edge setup time, t4. After the SYNC pin goes
low, serial data is shifted into the device input shift register on the falling edges of SCLK for 16 clock pulses.
The SPI is enabled after the SYNC pin becomes low and the data are continuously shifted into the shift register
at each falling edge of the SCLK input. When the SYNC pin is brought high, the last 16 bits stored in the shift
register are latched into the DAC register, and the DAC updates.
7.5.1.2 Daisy-Chain Operation
Daisy-chain operation is used for updating serially-connected devices on the rising edge of the SYNC in.
As long as the SYNC pin is high, the SDO pin is in a high-impedance state. When the SYNC pin is brought low
the output of the internal shift register is tied to the SDO pin. As long as the SYNC pin is low, the SDO pin
duplicates the SDIN signal with a 16-cycle delay. To support multiple devices in a daisy chain, the SCLK and
SYNC signals are shared across all devices, and the SDO pin of one DAC7551-Q1 device should be tied to the
SDIN pin of the next DAC7551-Q1 device. For n devices in such a daisy chain, 16n SCLK cycles are required to
shift the entire input data stream. After 16n SCLK falling edges are received, following a falling SYNC signal, the
data stream becomes complete and the SYNC pin can be brought high to update n devices simultaneously. SDO
operation is specified at a maximum SCLK speed of 10 MHz.
In daisy-chain mode, the use of a weak pulldown resistor on the SDO output pin, which provides the SDIN data
for the next device in the chain, is recommended. For standalone operation, the maximum clock speed is
50 MHz. For daisy-chain operation, the maximum clock speed is 10 MHz.
14
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Waveform Generation
As a result of the exceptional linearity and low glitch of the DAC7551-Q1 device, the device is well-suited for
waveform generation (from DC to 10kHz). The DAC7551-Q1 large-signal settling time is 5 μs, supporting an
update rate of 200 kSPS. However, the update rates can exceed 1 MSPS if the waveform to be generated
consists of small voltage steps between consecutive DAC updates. To obtain a high dynamic range, the
REF3140 device (4.096 V) or the REF02 device (5 V) is recommended for reference-voltage generation.
8.1.2 Generating ±5-V, ±10-V, and ±12-V Outputs For Precision Industrial Control
Industrial control applications can require multiple feedback loops consisting of sensors, analog-to-digital
converters (ADCs), microcontrollers (MCUs), DACs, and actuators. Loop accuracy and loop speed are the two
important parameters of such control loops.
8.1.2.1 Loop Accuracy
DAC offset, gain, and the integral linearity errors are not factors in determining the accuracy of the loop. As long
as a voltage exists in the transfer curve of a monotonic DAC, the loop can find this voltage and settle to it. On the
other hand, DAC resolution and differential linearity do determine the loop accuracy, because each DAC step
determines the minimum incremental change the loop can generate. A DNL error less than –1 LSB (nonmonotonicity) can create loop instability. A DNL error greater than 1 LSB implies unnecessarily large voltage
steps and missed voltage targets. With high DNL errors, the loop loses stability, resolution, and accuracy.
Offering 12-bit ensured monotonicity and ±0.08-LSB typical DNL error, the DAC755x devices are great choices
for precision control loops.
8.1.2.2 Loop Speed
Many factors determine the control-loop speed, such as ADC conversion time, MCU speed, and DAC settling
time. Typically, the ADC conversion time, and the MCU computation time are the two major factors that dominate
the time constant of the loop. DAC settling time is rarely a dominant factor because ADC conversion times
usually exceed DAC conversion times. DAC offset, gain, and linearity errors can slow the loop down only during
the startup. When the loop reaches the steady-state operation, these errors do not affect loop speed any further.
Depending on the ringing characteristics of the loop-transfer function, DAC glitches can also slow the loop down.
With a 1-MSPS (small-signal) maximum data-update rate, the DAC7551-Q1 device can support high-speed
control loops. Ultralow glitch energy of the DAC7551-Q1 device significantly improves loop stability and loop
settling time.
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8.2 Typical Application
8.2.1 Generating Industrial Voltage Ranges
For control-loop applications, DAC gain and offset errors are not important parameters. This consideration could
be exploited to lower trim and calibration costs in a high-voltage control-circuit design. Using a quad operational
amplifier (OPA4130), and a voltage reference (REF3140), the DAC7551-Q1 can generate the wide voltage
swings required by the control loop.
DAC7551
Vtail
R1
REF3140
R2
VREF
VREFH
_
DAC7551
Vdac
OPA4130
VOUT
+
Figure 28. Low-cost, Wide-swing Voltage Generator for Control-Loop Applications
8.2.1.1 Design Requirements
For ±5-V operation:
R1 = 10 kΩ
R2 = 15 kΩ
Vtail = 3.33 V
VREF = 4.096 V
For ±10-V operation:
R1 = 10 kΩ
R2 = 39 kΩ
Vtail = 2.56 V
VREF = 4.096 V
For ±12-V operation:
R1 = 10 kΩ
R2 = 49 kΩ
Vtail = 2.45 V
VREF = 4.096 V
8.2.1.2 Detailed Design Procedure
Use Equation 2 to calculate the output voltage of the configuration.
æ R2 ö SDIN
æ R2 ö
VOUT = VREF ç
+ 1÷
- Vtail ç
÷
è R1 ø 4096
è R1 ø
(2)
Fixed R1 and R2 resistors can be used to coarsely set the gain required in the first term of the equation. When
R2 and R1 set the gain to include some minimal over-range gain, a single DAC7551-Q1 device can be used to
set the required offset voltages. Residual errors are not an issue for loop accuracy because offset and gain
errors can be tolerated. One DAC7551-Q1 device can provide the Vtail voltages, while four additional DAC7551Q1 devices can provide the Vdac voltages to generate four high-voltage outputs. A single SPI is sufficient to
control all five DAC7551-Q1 devices in a daisy-chain configuration.
16
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Typical Application (continued)
8.2.1.3 Application Curves
Figure 29. SDIN Step Increments of 273 for
±5-V Operation
Figure 30. SDIN Step Increments of 273 for
±10-V Operation
Figure 31. SDIN Step Increments of 273 for
±12-V Operation
9 Power Supply Recommendations
The power applied to the VDD pin should be well regulated and low noise. Switching power supplies and DC-DC
converters often have high frequency glitches or spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes as the internal logic switches states. This noise can easily
couple into the DAC output voltage through various paths between power connections and analog output. As
with the GND connection, the VDD pin should be connected to a power-supply plane of trace that is separate from
the connection for digital logic until they are connected at the power-entry point. In addition, the use of a 1-µF
and 10-µF capacitor and a 0.1-µF bypass capacitor is strongly recommended. In some situations, additional
bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and
capacitors. These bypassing methods are all designed to low-pass filter the supply and remove the highfrequency noise.
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10 Layout
10.1 Layout Guidelines
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies. The DAC7551-Q1 device offers single-supply operation, and is often used in close proximity with digital
logic, microcontrollers, microprocessors, digital signal processors, or a combination. The more digital logic
present in the design and the higher the switching speed, the more difficult it is to prevent digital noise from
appearing at the output. As a result of the single ground pin of the DAC7551-Q1 device, all return currents
(including digital and analog return currents for the DAC) must flow through a single point. Ideally, the GND
should be connected directly to an analog ground plane. This plane should be separate from the ground
connection for the digital components until these components were connected at the power-entry point of the
system.
10.2 Layout Example
VI
VI
HighHigh-input frequency
bypass
bypass
capacitor capacitor
VI
IOVDD
12
SDO
11
Power Ground
SDIN
10
Thermal Pad
SCLK
9
VOUT
SYNC
8
GND
CLR
7
1
VDD
2
VREFH
3
VREFL
4
VFB
5
6
Point-of-load
Via to power ground plane
Connection to MCU, MPU, or DSP
Figure 32. DAC7551-Q1 Layout Example
18
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• OPA4130 Low Power, Precision FET-INPUT OPERATIONAL AMPLIFIERS, SBOS053
• REF02 +5V Precision VOLTAGE REFERENCE, SBVS003
• REF3140 15ppm/°C Max, 100μA, SOT23-3 SERIES VOLTAGE REFERENCE, SBVS046
11.2 Trademarks
SPI, QSPI are trademarks of Motorola, Inc.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC7551TDRNRQ1
ACTIVE
USON
DRN
12
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
RAN
DAC7551ZTDRNRQ1
ACTIVE
USON
DRN
12
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
SJT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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6-Nov-2018
OTHER QUALIFIED VERSIONS OF DAC7551-Q1 :
• Catalog: DAC7551
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC7551TDRNRQ1
USON
DRN
12
3000
330.0
12.4
2.3
3.3
0.85
4.0
12.0
Q1
DAC7551ZTDRNRQ1
USON
DRN
12
3000
330.0
12.4
2.3
3.3
0.85
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC7551TDRNRQ1
USON
DRN
12
3000
350.0
350.0
43.0
DAC7551ZTDRNRQ1
USON
DRN
12
3000
350.0
350.0
43.0
Pack Materials-Page 2
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