Texas Instruments | ADS42JBx9 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters (Rev. F) | Datasheet | Texas Instruments ADS42JBx9 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters (Rev. F) Datasheet

Texas Instruments ADS42JBx9 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters (Rev. F) Datasheet
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ADS42JB49, ADS42JB69
SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
ADS42JBx9 Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters
1 Features
2 Applications
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Dual-Channel ADCs
14- and 16-Bit Resolution
Maximum Clock Rate: 250 MSPS
JESD204B Serial Interface
– Subclass 0, 1, 2 Compliant
– Up to 3.125 Gbps
– Two and Four Lanes Support
Analog Input Buffer with High-Impedance Input
Flexible Input Clock Buffer:
Divide-by-1, -2, and -4
Differential Full-Scale Input: 2 VPP and 2.5 VPP
(Register Programmable)
Package: 9-mm × 9-mm VQFN-64
Power Dissipation: 850 mW/Ch
Aperture Jitter: 85 fS rms
Internal Dither
Channel Isolation: 100 dB
Performance:
– fIN = 170 MHz at 2 VPP, –1 dBFS
– SNR: 73.3 dBFS
– SFDR: 93 dBc for HD2, HD3
– SFDR: 100 dBc for Non HD2, HD3
– fIN = 170 MHz at 2.5 VPP, –1 dBFS
– SNR: 74.7 dBFS
– SFDR: 89 dBc for HD2, HD3 and
95 dBc for Non HD2, HD3
Communication and Cable Infrastructure
Multi-Carrier, Multimode Cellular Receivers
Radar and Smart Antenna Arrays
Broadband Wireless
Test and Measurement Systems
Software-Defined and Diversity Radios
Microwave and Dual-Channel I/Q Receivers
Repeaters
Power Amplifier Linearization
3 Description
The ADS42JB69 and ADS42JB49 are high-linearity,
dual-channel, 16- and 14-bit, 250-MSPS, analog-todigital converters (ADCs). These devices support the
JESD204B serial interface with data rates up to
3.125 Gbps. The buffered analog input provides
uniform input impedance across a wide frequency
range while minimizing sample-and-hold glitch energy
making it easy to drive analog inputs up to very high
input frequencies. A sampling clock divider allows
more flexibility for system clock architecture design.
The devices employ internal dither algorithms to
provide excellent spurious-free dynamic range
(SFDR) over a large input frequency range.
Device Information(1)
PART NUMBER
PACKAGE
ADS42JB49
VQFN (64)
ADS42JB69
VQFN (64)
INTERFACE OPTION
14-bit DDR or QDR LVDS
14-bit JESD204B
16-bit DDR or QDR LVDS
16-bit JESD204B
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
space
space
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS42JB49, ADS42JB69
SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
www.ti.com
Simplified Schematic
Device
14-, 16-Bit
ADC
CLKINP,
CLKINM
Gain
Test Modes
-20
SYNC~P,
SYNC~M
Delay
INBP,
INBM
-40
14-, 16-Bit
ADC
Digital
Block
DB0P,
DB0M
JESD204B
Digital
DB1P,
DB1M
Gain
Test Modes
OVRB
Common
Mode
-60
-80
MODE
CTRL1
CTRL2
STBY
SDOUT
PDN
PDN_GBL
SEN
SCLK
SDATA
Device Configuration
RESET
VCM
Fs = 250Msps
Fin = 170MHz
Ain = -1dBFS
HD2 = 90dBc
HD3 = 89dBc
Non HD2,3 = 100dBc
DA1P,
DA1M
PLL
x10, x20
Divide
by 1, 2, 4
FFT for 170MHz Input Signal
0
DA0P,
DA0M
JESD204B
Digital
Amplitude (dB)
SYSREFP,
SYSREFM
OVRA
Digital
Block
INAP,
INAM
-100
-120
0
2
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25
50
75
Frequency (MHz)
100
125
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Product Folder Links: ADS42JB49 ADS42JB69
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SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
8
9
1
1
1
3
5
5
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 8
Thermal Information .................................................. 8
Electrical Characteristics: ADS42JB69 (16-Bit) ........ 9
Electrical Characteristics: ADS42JB49 (14-Bit) ...... 10
Electrical Characteristics: General .......................... 11
Digital Characteristics ............................................. 12
Timing Characteristics............................................. 13
Typical Characteristics: ADS42JB69 .................... 15
Typical Characteristics: ADS42JB49 .................... 20
Typical Characteristics: Common ......................... 25
Typical Characteristics: Contour ........................... 26
Parameter Measurement Information ................ 29
Detailed Description ............................................ 31
9.1
9.2
9.3
9.4
9.5
9.6
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
31
31
31
33
39
42
10 Application and Implementation........................ 57
10.1 Application Information.......................................... 57
10.2 Typical Application ................................................ 57
11 Power Supply Recommendations ..................... 63
12 Layout................................................................... 63
12.1 Layout Guidelines ................................................. 63
12.2 Layout Example .................................................... 65
13 Device and Documentation Support ................. 66
13.1
13.2
13.3
13.4
13.5
13.6
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
66
68
68
68
68
68
14 Mechanical, Packaging, and Orderable
Information ........................................................... 68
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (August 2013) to Revision F
Page
•
Changed format to meet latest data sheet standards ............................................................................................................ 1
•
Added ESD Ratings table and Feature Description, Device Functional Modes, Application and
Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical,
Packaging, and Orderable Information sections..................................................................................................................... 1
•
Changed title of Device Comparison Table............................................................................................................................ 5
•
Changed title of Pin Functions table....................................................................................................................................... 6
•
Deleted Ordering Information table ........................................................................................................................................ 7
•
Corrected names of registers 10h, 11h, 12h, and 13h in Table 13 ..................................................................................... 42
Changes from Revision D (August 2013) to Revision E
•
Page
Changed document status to Production Data....................................................................................................................... 1
Changes from Revision C (July 2013) to Revision D
Page
•
Updated front page block diagram ......................................................................................................................................... 2
•
Changed 2-VPP Full-Scale INL maximum specification in ADS42JB49 Electrical Characteristics table .............................. 10
Changes from Revision B (July 2013) to Revision C
Page
•
Added Internal Dither in Features Section ............................................................................................................................. 1
•
Changed From "The devices provide excellent" to "The devices employ internal dither algorithms to provide" ................... 1
•
Changed 2-VPP Full-Scale INL maximum specification in ADS42JB69 Electrical Characteristics table ................................ 9
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•
Deleted 2.5-VPP Full-Scale INL maximum specification in ADS42JB69 Electrical Characteristics table ............................... 9
•
Changed 2-VPP Full-Scale INL maximum specification in ADS42JB49 Electrical Characteristics table .............................. 10
•
Deleted 2.5-VPP Full-Scale INL maximum specification in ADS42JB49 Electrical Characteristics table ............................. 10
•
Changed EGREF specifications in General Electrical Characteristics table ........................................................................... 11
Changes from Revision A (November 2012) to Revision B
•
4
Page
Changed document status to Mixed Status............................................................................................................................ 1
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SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
5 Device Comparison Table
INTERFACE OPTION
14-BIT,
160 MSPS
14-BIT,
250 MSPS
16-BIT,
250 MSPS
DDR or QDR LVDS
—
ADS42LB49
ADS42LB69
JESD204B
ADS42JB46
ADS42JB49
ADS42JB69
6 Pin Configuration and Functions
DRVDD
DGND
OVRB
OVRA
DRVDD
DB1M
DB1P
DB0M
DB0P
IOVDD
DA0P
DA0M
DA1P
DA1M
DGND
DRVDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RGC Package
VQFN-64
(Top View)
DGND
1
48
DRVDD
2
47 DRVDD
DGND
3
46 DGND
MODE
4
45 SDOUT
STBY
5
44 RESET
PDN_GBL
6
43 SCLK
DRVDD
7
42 SDATA
SYNC~M
8
SYNC~P
9
Thermal Pad
DGND
41 SEN
40 AVDD
CTRL2 10
39 CTRL1
AVDD 11
38 AVDD
AGND 12
37 AGND
INBP 13
36 INAP
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32
AVDD3V
AVDD 31
SYSREFM 30
SYSREFP 29
AGND 28
AVDD 27
AGND 26
CLKINP 25
CLKINM 24
23
AVDD 22
21
VCM
AGND
20
AGND
33 AVDD
19
AVDD 16
AVDD 18
34 AGND
AGND
35 INAM
AVDD3V 17
INBM 14
AGND 15
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Pin Functions: JESD204B Output Interface
PIN
NAME
DESCRIPTION
NO.
I/O
FUNCTION
AGND
12, 15, 19, 20,
23, 26, 28, 34,
37
I
Supply
Analog ground
AVDD
11, 16, 18, 22,
27, 31, 33, 38,
40
I
Supply
1.8-V analog power supply
AVDD3V
17, 32
I
Supply
3.3-V analog supply for analog buffer
CLKINM
24
I
Clock
Differential ADC clock input
CLKINP
25
I
Clock
Differential ADC clock input
CTRL1
39
I
Control
Power-down control with an internal 150-kΩ pull-down resistor
Power-down control with an internal 150-kΩ pull-down resistor
CTRL2
10
I
Control
DA0P/M
54, 53
O
Interface
JESD204B serial data output for channel A, lane 0
DA1P/M
52,51
O
Interface
JESD204B serial data output for channel A, lane 1
DB0P/M
56,57
O
Interface
JESD204B serial data output for channel B, lane 0
DB1P/M
58,59
O
Interface
JESD204B serial data output for channel B, lane 1
DGND
1, 3, 46, 48,
50, 63
I
Supply
Digital ground
DRVDD
2, 7, 47, 49,
60, 64
I
Supply
Digital 1.8-V power supply
INAM
35
I
Input
Differential analog input for channel A
INAP
36
I
Input
Differential analog input for channel A
INBM
14
I
Input
Differential analog input for channel B
INBP
13
I
Input
Differential analog input for channel B
IOVDD
55
I
Supply
Digital 1.8-V power supply for the JESD204B transmitter
MODE
4
I
Control
Connect to GND
OVRA
61
O
Interface
Overrange indication channel A in CMOS output format.
OVRB
62
O
Interface
Overrange indication channel B in CMOS output format.
PDN_GBL
6
I
Control
Global power down. Active high with an internal 150-kΩ pull-down resistor.
RESET
44
I
Control
Hardware reset; active high. This pin has an internal 150-kΩ pull-down resistor.
SCLK
43
I
Control
Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor.
SDATA
42
I
Control
Serial interface data input. This pin has an internal 150-kΩ pull-down resistor.
SDOUT
45
O
Control
Serial interface data output
SEN
41
I
Control
Serial interface enable. This pin has an internal 150-kΩ pull-up resistor.
STBY
5
I
Control
Standby. Active high with an internal 150-kΩ pull-down resistor.
SYNC~P
9
I
Interface
Synchronization input for JESD204B port
SYNC~M
8
I
Interface
Synchronization input for JESD204B port
SYSREFM
30
I
Clock
External SYSREF input (subclass 1)
SYSREFP
29
I
Clock
External SYSREF input (subclass 1)
VCM
21
O
Output
1.9-V common-mode output voltage for analog inputs
Thermal pad
—
GND
Ground
Connect to ground plane
6
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SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
MIN
MAX
UNIT
AVDD3V
–0.3
3.6
V
AVDD
–0.3
2.1
V
DRVDD
–0.3
2.1
V
IOVDD
–0.3
2.1
V
Voltage between AGND and DGND
Voltage applied to input pins
Temperature
–0.3
0.3
V
INAP, INBP, INAM, INBM
–0.3
3
V
CLKINP, CLKINM
–0.3
minimum (2.1, AVDD + 0.3)
V
SYNC~P, SYNC~M
–0.3
minimum (2.1, AVDD + 0.3)
V
SYSREFP, SYSREFM
–0.3
minimum (2.1, AVDD + 0.3)
V
SCLK, SEN, SDATA, RESET, PDN_GBL,
CTRL1, CTRL2, STBY, MODE
–0.3
3.9
V
Operating free-air, TA
–40
Operating junction, TJ
Storage, Tstg
(1)
–65
+85
°C
+125
°C
+150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
AVDD3V
Analog buffer supply voltage
1.7
1.8
1.9
V
3.15
3.3
3.45
DRVDD
V
Digital supply voltage
1.7
1.8
1.9
V
IOVDD
Output buffer supply voltage
1.7
1.8
1.9
V
ANALOG INPUTS
VID
Differential input voltage range
VICR
Input common-mode voltage
Default after reset
Register programmable
(2)
2
VPP
2.5
VPP
VCM ± 0.025
V
Maximum analog input frequency with 2.5-VPP input amplitude
250
MHz
Maximum analog input frequency with 2-VPP input amplitude
400
MHz
CLOCK INPUT
Input clock sample rate
Input clock amplitude differential
(VCLKP – VCLKM)
10x mode
60
250
MSPS
20x mode
40
156.25
MSPS
Sine wave, ac-coupled
(3)
1.5
VPP
LVPECL, ac-coupled
0.3
1.6
VPP
LVDS, ac-coupled
0.7
VPP
LVCMOS, single-ended, ac-coupled
Input clock duty cycle
1.5
35%
50%
V
65%
DIGITAL OUTPUTS
CLOAD
Maximum external load capacitance from each output pin to DRGND
RLOAD
Single-ended load resistance
TA
Operating free-air temperature
(1)
(2)
(3)
3.3
pF
Ω
+50
–40
+85
°C
After power-up, to reset the device for the first time, use the RESET pin only. Refer to the Register Initialization section.
For details, refer to the Digital Gain section.
Refer to the Performance vs Clock Amplitude curves, Figure 28 and Figure 29.
7.4 Thermal Information
ADS42JBx9
THERMAL METRIC (1)
RGC (QFN)
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance
22.9
RθJC(top)
Junction-to-case (top) thermal resistance
7.1
RθJB
Junction-to-board thermal resistance
2.5
ψJT
Junction-to-top characterization parameter
0.1
ψJB
Junction-to-board characterization parameter
2.5
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.2
(1)
8
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics: ADS42JB69 (16-Bit)
Typical values are at TA = +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle,
–1-dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values
are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V,
and IOVDD = 1.8 V.
PARAMETER
SNR
Signal-to-noise ratio
SINAD Signal-to-noise and distortion ratio
TEST CONDITIONS
2-VPP FULL-SCALE
MIN
TYP
THD
HD2
HD3
Total harmonic distortion
2nd-order harmonic distortion
3rd-order harmonic distortion
TYP
MAX
UNIT
74
75.9
dBFS
fIN = 70 MHz
73.8
75.6
dBFS
fIN = 170 MHz
73.3
74.7
dBFS
fIN = 230 MHz
70.8
72.6
74
dBFS
fIN = 10 MHz
73.9
75.7
dBFS
73.7
75.3
dBFS
73.2
74.5
dBFS
72.2
73.1
dBFS
95
90
dBc
91
88
dBc
93
89
dBc
fIN = 230 MHz
84
82
dBc
fIN = 10 MHz
92
88
dBc
fIN = 70 MHz
89
86
dBc
91
86
dBc
fIN = 230 MHz
82
80
dBc
fIN = 10 MHz
95
95
dBc
fIN = 70 MHz
91
88
dBc
93
94
dBc
fIN = 230 MHz
84
82
dBc
fIN = 10 MHz
95
90
dBc
fIN = 70 MHz
96
93
dBc
fIN = 70 MHz
fIN = 170 MHz
69.6
fIN = 10 MHz
SFDR
MIN
fIN = 10 MHz
fIN = 230 MHz
Spurious-free dynamic range
(including second and third
harmonic distortion)
MAX
2.5-VPP FULL-SCALE
fIN = 70 MHz
fIN = 170 MHz
fIN = 170 MHz
fIN = 170 MHz
78
81
94
89
dBc
fIN = 230 MHz
86
84
dBc
fIN = 10 MHz
102
102
dBc
103
103
dBc
100
95
dBc
fIN = 230 MHz
99
93
dBc
f1 = 46 MHz, f2 = 50 MHz,
each tone at –7 dBFS
97
95
dBFS
f1 = 185 MHz, f2 = 190 MHz,
each tone at –7 dBFS
90
89
dBFS
Crosstalk
20-MHz, full-scale signal on
channel under observation;
170-MHz, full-scale signal on
other channel
100
100
dB
Input overload recovery
Recovery to within 1% (of fullscale) for 6-dB overload with sinewave input
1
1
PSRR
AC power-supply rejection ratio
For 50-mVPP signal on AVDD
supply, up to 10 MHz
> 40
> 40
dB
ENOB
Effective number of bits
fIN = 170 MHz
11.9
12.1
LSBs
DNL
Differential nonlinearity
fIN = 170 MHz
±0.6
±0.6
LSBs
INL
Integrated nonlinearity
fIN = 170 MHz
±3
±3.5
LSBs
Worst spur
(other than second and third
harmonics)
IMD
Two-tone intermodulation
distortion
fIN = 170 MHz
81
81
fIN = 70 MHz
fIN = 170 MHz
87
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cycle
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7.6 Electrical Characteristics: ADS42JB49 (14-Bit)
Typical values are at TA = +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle,
–1-dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values
are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V,
and IOVDD = 1.8 V.
PARAMETER
SNR
Signal-to-noise ratio
SINAD Signal-to-noise and distortion ratio
TEST CONDITIONS
2-VPP FULL-SCALE
MIN
TYP
THD
HD2
HD3
Total harmonic distortion
2nd-order harmonic distortion
3rd-order harmonic distortion
TYP
MAX
UNIT
73.4
75
dBFS
fIN = 70 MHz
73.2
74.7
dBFS
fIN = 170 MHz
72.7
74
dBFS
fIN = 230 MHz
69.5
72.2
73.4
dBFS
fIN = 10 MHz
73.3
74.8
dBFS
73.1
74.5
dBFS
72.7
73.8
dBFS
71.8
72.6
dBFS
95
90
dBc
91
88
dBc
93
89
dBc
fIN = 230 MHz
84
82
dBc
fIN = 10 MHz
92
88
dBc
fIN = 70 MHz
89
86
dBc
90
86
dBc
fIN = 230 MHz
82
80
dBc
fIN = 10 MHz
95
95
dBc
fIN = 70 MHz
91
88
dBc
93
94
dBc
fIN = 230 MHz
84
82
dBc
fIN = 10 MHz
95
90
dBc
fIN = 70 MHz
96
93
dBc
fIN = 70 MHz
fIN = 170 MHz
68.5
fIN = 10 MHz
SFDR
MIN
fIN = 10 MHz
fIN = 230 MHz
Spurious-free dynamic range
(including second and third
harmonic distortion)
MAX
2.5-VPP FULL-SCALE
fIN = 70 MHz
fIN = 170 MHz
fIN = 170 MHz
fIN = 170 MHz
76
79
94
89
dBc
fIN = 230 MHz
86
84
dBc
fIN = 10 MHz
102
102
dBc
103
103
dBc
101
95
dBc
fIN = 230 MHz
99
93
dBc
f1 = 46 MHz, f2 = 50 MHz,
each tone at –7 dBFS
97
95
dBFS
f1 = 185 MHz, f2 = 190 MHz,
each tone at –7 dBFS
90
89
dBFS
Crosstalk
20-MHz, full-scale signal on
channel under observation;
170-MHz, full-scale signal on
other channel
100
100
dB
Input overload recovery
Recovery to within 1% (of fullscale) for 6-dB overload with sinewave input
1
1
PSRR
AC power-supply rejection ratio
For a 50-mVPP signal on AVDD
supply, up to 10 MHz
> 40
> 40
ENOB
Effective number of bits
fIN = 170 MHz
11.8
12
LSBs
DNL
Differential nonlinearity
fIN = 170 MHz
±0.15
±0.15
LSBs
INL
Integrated nonlinearity
fIN = 170 MHz
±0.75
±0.9
LSBs
Worst spur
(other than second and third
harmonics)
IMD
10
Two-tone intermodulation
distortion
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fIN = 170 MHz
79
79
fIN = 70 MHz
fIN = 170 MHz
87
±3
Clock
cycle
dB
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SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
7.7 Electrical Characteristics: General
Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle, –1dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are
across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and
IOVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Differential input voltage
range
VID
Default (after reset)
2
VPP
Register programmed (1)
2.5
VPP
Differential input resistance (at 170 MHz)
1.2
kΩ
4
pF
Differential input capacitance (at 170 MHz)
Analog input bandwidth
VCM
With 50-Ω source impedance, and 50-Ω
termination
900
MHz
Common-mode output voltage
1.9
V
VCM output current capability
10
mA
DC ACCURACY
Offset error
–20
20
mV
EGREF
Gain error as a result of
internal reference inaccuracy
alone
±2
%FS
EGCHAN
Gain error of channel alone
–5
%FS
Temperature coefficient of
EGCHAN
Δ%/°C
0.01
POWER SUPPLY
IAVDD
Analog supply current
128
160
mA
IAVDD3V
Analog buffer supply current
290
330
mA
IDRVDD
Digital supply current
228
252
mA
60
100
mA
IOVDD
Output buffer supply current
50-Ω external termination from pin to IOVDD,
fIN = 2.5 MHz
Analog power
231
mW
Analog buffer power
957
mW
Digital power
410
mW
109
mW
Power consumption by output
buffer
50-Ω external termination from pin to IOVDD,
fIN = 2.5 MHz
Total power
1.7
Global power-down
(1)
1.96
W
160
mW
Refer to the Serial Interface section.
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7.8 Digital Characteristics
The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level '0' or '1'. AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and IOVDD = 1.8 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDATA, PDN_GBL, STBY, CTRL1, CTRL2, MODE) (1)
High-level input voltage
All digital inputs support 1.8-V and 3.3-V logic
levels
Low-level input voltage
All digital inputs support 1.8-V and 3.3-V logic
levels
1.2
V
0.4
SEN
V
0
µA
RESET, SCLK, SDATA, PDN_GBL, STBY,
CTRL1, CTRL2, MODE
10
µA
SEN
10
µA
0
µA
High-level input voltage
1.3
V
Low-level input voltage
0.5
V
Input common-mode voltage
0.9
V
DRVDD
V
High-level input current
Low-level input current
RESET, SCLK, SDATA, PDN_GBL, STBY,
CTRL1, CTRL2, MODE
DIGITAL INPUTS (SYNC~P, SYNC~M, SYSREFP, SYSREFM)
VCM_DIG
DIGITAL OUTPUTS (SDOUT, OVRA, OVRB)
DRVDD
– 0.1
High-level output voltage
Low-level output voltage
0.1
DIGITAL OUTPUTS (JESD204B Interface: DA[0,1], DB[0,1])
High-level output voltage
IOVDD
V
Low-level output voltage
IOVDD – 0.4
V
0.4
V
IOVDD – 0.2
V
|VOD|
Output differential voltage
VOCM
Output common-mode voltage
Transmitter short-circuit current
Transmitter terminals shorted to any voltage
between –0.25 V and 1.45 V
Single-ended output impedance
Output capacitance
(1)
(2)
12
V
(2)
Output capacitance inside the device,
from either output to ground
–100
100
mA
50
Ω
2
pF
RESET, SCLK, SDATA, PDN_GBL, STBY, CTRL1, CTRL2 and MODE pins have 150-kΩ (typical) internal pull-down resistor to ground,
while SEN pin has 150-kΩ (typical) pull-up resistor to AVDD.
50-Ω, single-ended external termination to IOVDD.
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SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
7.9 Timing Characteristics
Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle, –1dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are
across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and
IOVDD = 1.8 V. See Figure 1.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.7
1.1
UNIT
SAMPLE TIMING CHARACTERISTICS
Aperture delay
0.4
Between two channels on the same device
Aperture delay matching
Between two devices at the same temperature and supply
voltage
Aperture jitter
Wake-up time
ps
±150
ps
85
Time to valid data after coming out of STANDBY mode
Time to valid data after coming out of global power-down
ns
±70
fS rms
50
200
µs
250
1000
µs
tSU_SYNC~
Setup time for SYNC~
Referenced to input clock rising edge
400
ps
tH_SYNC~
Hold time for SYNC~
Referenced to input clock rising edge
100
ps
tSU_SYSREF
Setup time for SYSREF
Referenced to input clock rising edge
400
ps
tH_SYSREF
Hold time for SYSREF
Referenced to input clock rising edge
100
ps
CML OUTPUT TIMING CHARACTERISTICS
Unit interval
320
Serial output data rate
Total jitter
Data rise time,
data fall time
tR, tF
2.5 Gbps (10x mode, fS = 250 MSPS)
1667
ps
3.125
Gbps
0.28
P-PUI
3.125 Gbps (20x mode, fS = 156.25 MSPS)
0.3
P-PUI
Rise and fall times measured from 20% to 80%,
differential output waveform,
600 Mbps ≤ bit rate ≤ 3.125 Gbps
105
ps
Table 1. Latency in Different Modes (1) (2)
MODE
10x
PARAMETER
LATENCY (N Cycles)
TYPICAL DATA DELAY (tD, ns)
ADC latency
23
0.65 × tS + 3
Normal OVR latency
14
6.7
Fast OVR latency
9
6.7
from SYNC~ falling edge to CGS phase
20x
(1)
(2)
(3)
(4)
(3)
16
0.65 × tS + 3
from SYNC~ rising edge to ILA sequence (4)
25
0.65 × tS + 3
ADC latency
22
0.85 × tS + 3
Normal OVR latency
14
6.7
Fast OVR latency
9
6.7
from SYNC~ falling edge to CGS phase (3)
15
0.85 × tS + 3
from SYNC~ rising edge to ILA sequence (4)
16
0.85 × tS + 3
Overall latency = latency + tD.
tS is the time period of the ADC conversion clock.
Latency is specified for subclass 2. In subclass 0, the SYNC~ falling edge to CGS phase latency is 16 clock cycles in 10x mode and 15
clock cycles in 20x mode.
Latency is specified for subclass 2. In subclass 0, the SYNC~ rising edge to ILA sequence latency is 11 clock cycles in 10x mode and
11 clock cycles in 20x mode.
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N+2
Sample
N
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N+3
N+4
N+1
N + Latency + 1
N + Latency
N + Latency + 2
tA
Input
Clock
CLKP
CLKM
ADC Latency
(1)
tD
(2)
Dx0P, Dx0M
N - Latency-1
N + Latency
N - Latency+1 N - Latency+2
N - Latency+3
N-1
N
N+1
N+1
N - Latency-1
N + Latency
N - Latency+1 N - Latency+2
N - Latency+3
N-1
N
N+1
N+1
(2)
Dx1P, Dx1M
(1) Overall latency = ADC latency + tD.
(2) x = A for channel A and B for channel B.
Figure 1. ADC Latency
14
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7.10 Typical Characteristics: ADS42JB69
Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
0
0
fIN = 10 MHz
SFDR = 96 dBc
SNR = 74 dBFS
SINAD = 73.9 dBFS
THD = 94 dBc
SFDR Non HD2, HD3
= 102 dBc
−40
−60
−80
−100
−120
fIN = 170 MHz
SFDR = 88 dBc
SNR = 73.3 dBFS
SINAD = 73 dBFS
THD = 87 dBc
SFDR Non HD2, HD3
= 101 dBc
−20
Amplitude (dBFS)
Amplitude (dBFS)
−20
−40
−60
−80
−100
0
25
50
75
Frequency (MHz)
100
−120
125
0
Figure 2. FFT for 10-MHz Input Signal
fIN = 300 MHz
SFDR = 74 dBc
SNR = 72.4 dBFS
SINAD = 69.9 dBFS
THD = 73 dBc
SFDR Non HD2,HD3
= 96
−40
−60
Amplitude (dBFS)
Amplitude (dBFS)
125
G002
fIN = 10 MHz
SFDR = 90 dBc
SNR = 75.8 dBFS
SINAD = 75.7 dBFS
THD = 89 dBc
SFDR Non HD2, HD3
= 105 dBc
−20
−80
−100
−40
−60
−80
−100
0
25
50
75
Frequency (MHz)
100
−120
125
0
25
G003
Figure 4. FFT for 300-MHz Input Signal
50
75
Frequency (MHz)
100
125
G004
Figure 5. FFT for 10-MHz Input Signal
(2.5-VPP Full-Scale)
0
0
fIN = 170 MHz
SFDR = 87 dBc
SNR = 74.7 dBFS
SINAD = 74.4 dBFS
THD = 84 dBc
SFDR Non HD2, HD3
= 94 dBc
−40
−60
fIN = 300 MHz
SFDR = 71 dBc
SNR = 73.4 dBFS
SINAD = 69 dBFS
THD = 70 dBc
SFDR Non HD2, HD3
= 94 dBc
−20
Amplitude (dBFS)
−20
Amplitude (dBFS)
100
0
−20
−80
−100
−120
50
75
Frequency (MHz)
Figure 3. FFT for 170-MHz Input Signal
0
−120
25
G001
−40
−60
−80
−100
0
25
50
75
Frequency (MHz)
100
Figure 6. FFT for 170-MHz Input Signal
(2.5-VPP Full-Scale)
125
−120
0
25
G005
50
75
Frequency (MHz)
100
125
G006
Figure 7. FFT for 300-MHz Input Signal
(2.5-VPP Full-Scale)
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Typical Characteristics: ADS42JB69 (continued)
Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
0
0
Each Tone at
−7 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
2−Tone IMD = 98 dBFS
SFDR = 105 dBFS
−40
−20
Amplitude (dBFS)
Amplitude (dBFS)
−20
−60
−80
−100
−120
Each Tone at
−36 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
2−Tone IMD = 101 dBFS
SFDR = 106 dBFS
−40
−60
−80
−100
0
25
50
75
Frequency (MHz)
100
−120
125
0
Figure 8. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
125
G008
−40
Each Tone at
−36 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
2−Tone IMD = 101 dBFS
SFDR = 104 dBFS
−20
Amplitude (dBFS)
Amplitude (dBFS)
100
0
Each Tone at
−7 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
2−Tone IMD = 90 dBFS
SFDR = 102 dBFS
−20
−60
−80
−100
−40
−60
−80
−100
0
25
50
75
Frequency (MHz)
100
−120
125
0
50
75
Frequency (MHz)
100
125
G010
Figure 11. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
−98
−90
fIN1 = 46 MHz
fIN2 = 50 MHz
−92
Two − Tone IMD (dBFS)
−100
25
G009
Figure 10. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
Two − Tone IMD (dBFS)
50
75
Frequency (MHz)
Figure 9. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
0
−120
25
G007
−102
−104
−106
−108
fIN1 = 185 MHz
fIN2 = 190 MHz
−94
−96
−98
−100
−102
−104
−106
−108
−110
−36
−33
−30
−27 −24 −21 −18 −15
Each Tone Amplitude (dBFS)
−12
Figure 12. Intermodulation Distortion vs
Input Amplitude (46 MHz and 50 MHz)
16
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−9 −7
−110
−36
−33
−30
G011
−27 −24 −21 −18 −15
Each Tone Amplitude (dBFS)
−12
−9 −7
G012
Figure 13. Intermodulation Distortion vs
Input Amplitude (185 MHz and 190 MHz)
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Typical Characteristics: ADS42JB69 (continued)
Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
100
77
2−VPP Full−Scale
2.5−VPP Full−Scale
95
2−VPP Full−Scale
2.5−VPP Full−Scale
76
75
85
SNR (dBFS)
SFDR (dBc)
90
80
75
70
74
73
72
65
71
60
0
50
100
150
200
250
300
Input Frequency (MHz)
350
70
400
0
50
Figure 14. Spurious-Free Dynamic Range vs
Input Frequency
170 MHz
230 MHz
270 MHz
350 MHz
400 MHz
491 MHz
10 MHz
70 MHz
100 MHz
130 MHz
78
76
100
SNR (dBFS)
SFDR (dBc)
350
400
G014
80
10 MHz
70 MHz
100 MHz
130 MHz
110
90
80
170 MHz
230 MHz
270 MHz
350 MHz
400 MHz
491 MHz
74
72
70
70
68
66
−2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Digital Gain (dB)
G015
−2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Digital Gain (dB)
G016
Figure 16. Spurious-Free Dynamic Range vs
Digital Gain
Figure 17. Signal-to-Noise Ratio vs
Digital Gain
130
77
120
120
76.5
110
76
110
76
100
75.5
100
75.5
90
75
80
74.5
70
74
60
73.5
50
75
90
74.5
80
74
70
73.5
60
73
50
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
72.5
72
71.5
−70
Input Frequency = 70 MHz
−60
−50
−40
−30
−20
Amplitude (dBFS)
−10
0
Figure 18. Performance vs Input Amplitude
(70 MHz)
SNR (dBFS)
77
76.5
SFDR (dBc,dBFS)
SNR (dBFS)
150
200
250
300
Input Frequency (MHz)
Figure 15. Signal-to-Noise Ratio vs
Input Frequency
120
60
100
G013
40
72.5
30
72
20
40
73
71.5
−70
Input Frequency = 170 MHz
−60
−50
G017
−40
−30
−20
Amplitude (dBFS)
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
−10
SFDR (dBc,dBFS)
55
30
20
0
10
G018
Figure 19. Performance vs Input Amplitude
(170 MHz)
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Typical Characteristics: ADS42JB69 (continued)
Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
Input Frequency = 70 MHz
SFDR
SNR
Input Frequency = 170 MHz
75
95
74.5
92
74.5
92
74
89
74
89
73.5
86
73.5
86
73
84
73
83
72.5
SFDR (dBc)
94
SNR (dBFS)
98
82
1.85
72.5
1.95
1.87
1.9
1.93
Input Common−Mode Voltage (V)
80
1.85
G019
G020
Figure 21. Performance vs
Input Common-Mode Voltage (170 MHz)
75
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.7 V
AVDD = 1.75V
AVDD = 1.8 V
74.5
SNR (dBFS)
SFDR (dBc)
99
98
97
96
95
94
93
92
91
90
89
75
72
1.95
1.87
1.9
1.93
Input Common−Mode Voltage (V)
Figure 20. Performance vs
Input Common-Mode Voltage (70 MHz)
AVDD = 1.85 V
AVDD = 1.9 V
74
73.5
73
72.5
88
Input Frequency = 170 MHz
87
−40
−15
10
35
Temperature (°C)
Input Frequency = 170 MHz
60
72
−40
85
96
95
10
35
Temperature (°C)
60
85
G022
Figure 23. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (170 MHz)
98
97
−15
G021
Figure 22. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (170 MHz)
75
AVDD3V = 3.15 V
AVDD3V = 3.2 V
AVDD3V = 3.25 V
AVDD3V = 3.3 V
AVDD3V = 3.35 V
AVDD3V = 3.4 V
AVDD3V = 3.45 V
AVDD3V = 3.15 V
AVDD3V = 3.2 V
AVDD3V = 3.25 V
AVDD3V = 3.3 V
74.5
94
SNR (dBFS)
SFDR (dBc)
SFDR
SNR
75.5
96
SFDR (dBc)
75.5
101
SNR (dBFS)
76
99
93
92
91
AVDD3V = 3.35 V
AVDD3V = 3.4 V
AVDD3V = 3.45 V
74
73.5
73
90
89
88
87
−40
72.5
Input Frequency = 170 MHz
−15
Input Frequency = 170 MHz
10
35
Temperature (°C)
60
85
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−15
G023
Figure 24. Spurious-free Dynamic Range vs AVDD_BUF
Supply and Temperature (170 MHz)
18
72
−40
10
35
Temperature (°C)
60
85
G024
Figure 25. Signal-to-Noise Ratio vs
AVDD_BUF Supply and Temperature (170 MHz)
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Typical Characteristics: ADS42JB69 (continued)
Typical values are at TA = +25°C, ADC sampling rate = 250 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V,
DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
97
75
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
96
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
74.5
94
SNR (dBFS)
SFDR (dBc)
95
DRVDD = 1.85 V
DRVDD = 1.9 V
93
92
91
DRVDD = 1.85 V
DRVDD = 1.9 V
74
73.5
73
90
72.5
Input Frequency = 170 MHz
−15
Input Frequency = 170 MHz
10
35
Temperature (°C)
60
72
−40
85
Figure 26. Spurious-Free Dynamic Range vs
DRVDD Supply and Temperature (170 MHz)
75
90
74
88
73
86
72
84
0.1
0.3
0.5 0.7 0.9 1.1 1.3 1.5 1.7
Differential Clock Amplitudes (Vpp)
1.9
94
76
92
71
2.1
74
88
72
86
70
84
68
90
75
88
74
86
73
84
40
50
60
Input Clock Duty Cycle (%)
70
1.9
66
2.1
G028
77
96
77
76
30
0.5 0.7 0.9 1.1 1.3 1.5 1.7
Differential Clock Amplitudes (Vpp)
Input Frequency = 170 MHz
92
82
0.3
Figure 29. Performance vs Clock Amplitude
(170 MHz)
94
SNR
SFDR
76
92
75
90
74
88
73
72
86
72
71
84
Figure 30. Performance vs Clock Duty Cycle
(70 MHz)
SFDR (dBc)
SNR (dBFS)
SFDR (dBc)
94
78
90
82
0.1
78
SNR
SFDR
SFDR
SNR
76
Figure 28. Performance vs Clock Amplitude
(70 MHz)
Input Frequency = 70 MHz
G026
92
G027
96
85
80
Input Frequency =170 MHz
SFDR (dBc)
SFDR (dBc)
94
60
96
SNR (dBFS)
SFDR
SNR
10
35
Temperature (°C)
Figure 27. Signal-to-Noise Ratio vs
DRVDD Supply and Temperature (170 MHz)
77
96
Input Frequency = 70 MHz
−15
G025
SNR (dBFS)
88
−40
G029
30
40
50
60
Input Clock Duty Cycle (%)
70
SNR (dBFS)
89
71
G030
Figure 31. Performance vs Clock Duty Cycle
(170 MHz)
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7.11 Typical Characteristics: ADS42JB49
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 32k-point FFT, unless otherwise noted.
0
0
fIN = 10 MHz
SFDR = 97 dBc
SNR = 73.4 dBFS
SINAD = 73.3 dBFS
THD = 95 dBc
SFDR Non HD2, HD3
= 103 dBc
−40
−60
−20
Amplitude (dBFS)
Amplitude (dBFS)
−20
−80
−100
−120
fIN = 170 MHz
SFDR = 89 dBc
SNR = 72.8 dBFS
SINAD = 72.5 dBFS
THD = 88 dBc
SFDR Non HD2, HD3
= 100 dBc
−40
−60
−80
−100
0
25
50
75
Frequency (MHz)
100
−120
125
0
Figure 32. FFT for 10-MHz Input Signal
fIN = 300 MHz
SFDR = 74 dBc
SNR = 72.1 dBFS
SINAD = 69.8 dBFS
THD = 72 dBc
SFDR Non HD2, HD3
= 96 dBc
−60
Amplitude (dBFS)
Amplitude (dBFS)
−40
−80
−40
−60
G032
−80
−100
0
25
50
75
Frequency (MHz)
100
−120
125
0
25
G033
Figure 34. FFT for 300-MHz Input Signal
50
75
Frequency (MHz)
100
125
G034
Figure 35. FFT for 10-MHz Input Signal
(2.5-VPP Full-Scale)
0
0
fIN = 170 MHz
SFDR = 87 dBc
SNR = 73.9 dBFS
SINAD = 73.7 dBFS
THD = 85 dBc
SFDR Non HD2, HD3
= 94 dBc
−40
−60
fIN = 300 MHz
SFDR = 71 dBc
SNR = 73.1 dBFS
SINAD = 68.4 dBFS
THD = 69 dBc
SFDR Non HD2, HD3
= 93 dBc
−20
Amplitude (dBFS)
−20
Amplitude (dBFS)
125
fIN = 10 MHz
SFDR = 89 dBc
SNR = 75 dBFS
SINAD = 74.8 dBFS
THD = 88 dBc
SFDR Non HD2, HD3
= 103 dBc
−20
−100
−80
−100
−40
−60
−80
−100
0
25
50
75
Frequency (MHz)
100
Figure 36. FFT for 170-MHz Input Signal
(2.5-VPP Full-Scale)
20
100
0
−20
−120
50
75
Frequency (MHz)
Figure 33. FFT for 170-MHz Input Signal
0
−120
25
G031
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125
−120
0
25
G035
50
75
Frequency (MHz)
100
125
G036
Figure 37. FFT for 300-MHz Input Signal
(2.5-VPP Full-Scale)
Copyright © 2012–2014, Texas Instruments Incorporated
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SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
Typical Characteristics: ADS42JB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 32k-point FFT, unless otherwise noted.
0
0
Each Tone at
−7 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
2−Tone IMD = 98 dBFS
SFDR = 105 dBFS
−40
−60
−80
−100
−120
Each Tone at
−36 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
2−Tone IMD = 101 dBFS
SFDR = 106 dBFS
−20
Amplitude (dBFS)
Amplitude (dBFS)
−20
−40
−60
−80
−100
0
25
50
75
Frequency (MHz)
100
−120
125
0
Figure 38. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
125
G038
−40
Each Tone at
−36 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
2−Tone IMD = 101 dBFS
SFDR = 104 dBFS
−20
Amplitude (dBFS)
Amplitude (dBFS)
100
0
Each Tone at
−7 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
2−Tone IMD = 90 dBFS
SFDR = 102 dBFS
−20
−60
−80
−100
−40
−60
−80
−100
0
25
50
75
Frequency (MHz)
100
−120
125
0
50
75
Frequency (MHz)
100
125
G040
Figure 41. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
−98
−90
fIN1 = 46 MHz
fIN2 = 50 MHz
−92
Two − Tone IMD (dBFS)
−100
25
G039
Figure 40. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
Two − Tone IMD (dBFS)
50
75
Frequency (MHz)
Figure 39. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
0
−120
25
G037
−102
−104
−106
−108
fIN1 = 185 MHz
fIN2 = 190 MHz
−94
−96
−98
−100
−102
−104
−106
−108
−110
−36
−33
−30
−27 −24 −21 −18 −15
Each Tone Amplitude (dBFS)
−12
Figure 42. Intermodulation Distortion vs
Input Amplitude (46 MHz and 50 MHz)
−9 −7
−110
−36
−33
−30
G041
−27 −24 −21 −18 −15
Each Tone Amplitude (dBFS)
−12
−9 −7
G042
Figure 43. Intermodulation Distortion vs
Input Amplitude (185 MHz and 190 MHz)
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Typical Characteristics: ADS42JB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 32k-point FFT, unless otherwise noted.
100
76
2−VPP Full−Scale
2.5−VPP Full−Scale
95
74
SNR (dBFS)
SFDR (dBc)
90
85
80
75
73
72
71
70
70
65
60
2−VPP Full−Scale
2.5−VPP Full−Scale
75
0
50
100
150
200
250
300
Input Frequency (MHz)
350
69
400
0
50
Figure 44. Spurious-Free Dynamic Range vs
Input Frequency
150
200
250
300
Input Frequency (MHz)
350
400
G044
Figure 45. Signal-to-Noise Ratio vs
Input Frequency
78
120
10 MHz
70 MHz
100 MHz
130 MHz
110
170 MHz
230 MHz
270 MHz
350 MHz
400 MHz
491 MHz
10 MHz
70 MHz
100 MHz
130 MHz
77
76
75
SNR (dBFS)
100
SFDR (dBc)
100
G043
90
80
170 MHz
230 MHz
270 MHz
350 MHz
400 MHz
491 MHz
74
73
72
71
70
69
70
68
67
−2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Digital Gain (dB)
G045
−2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Digital Gain (dB)
G046
Figure 46. Spurious-Free Dynamic Range vs
Digital Gain
SNR (dBFS)
75.5
130
76.5
120
76
110
75.5
110
100
75
100
90
80
74.5
70
60
73.5
50
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
72.5
71.5
−70
−60
−50
−40
−30
−20
Amplitude (dBFS)
−10
0
Figure 48. Performance vs Input Amplitude
(70 MHz)
22
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SNR (dBFS)
Input Frequency = 70 MHz
SFDR (dBc,dBFS)
77
76.5
Figure 47. Signal-to-Noise Ratio vs
Digital Gain
130
Input Frequency = 170 MHz
120
74.5
90
74
80
73.5
70
73
60
50
72.5
40
72
30
71.5
20
71
−70
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
−60
−50
G047
−40
−30
−20
Amplitude (dBFS)
−10
SFDR (dBc,dBFS)
60
40
30
0
20
G048
Figure 49. Performance vs Input Amplitude
(170 MHz)
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: ADS42JB49 ADS42JB69
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SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
Typical Characteristics: ADS42JB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 32k-point FFT, unless otherwise noted.
Input Frequency = 70 MHz
SFDR
SNR
Input Frequency = 170 MHz
74.5
95
74
92
74
92
73.5
89
73.5
89
73
86
73
86
72.5
84
72.5
83
72
SFDR (dBc)
94
SNR (dBFS)
98
82
1.85
72
1.95
1.87
1.9
1.93
Input Common−Mode Voltage (V)
80
1.85
G049
99
98
97
96
95
94
93
92
91
90
89
74.5
71.5
1.95
1.87
1.9
1.93
Input Common−Mode Voltage (V)
G050
Figure 51. Performance vs
Input Common-Mode Voltage (170 MHz)
74.5
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.7 V
AVDD = 1.75V
AVDD = 1.8 V
74
AVDD = 1.85 V
AVDD = 1.9 V
73.5
SNR (dBFS)
SFDR (dBc)
Figure 50. Performance vs
Input Common-Mode Voltage (70 MHz)
73
72.5
72
71.5
88
Input Frequency = 170 MHz
87
−40
−15
10
35
Temperature (°C)
Input Frequency = 170 MHz
60
71
−40
85
−15
G051
Figure 52. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (170 MHz)
10
35
Temperature (°C)
60
85
G052
Figure 53. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (170 MHz)
99
74.5
AVDD3V = 3.15 V
AVDD3V = 3.2 V
AVDD3V = 3.25 V
AVDD3V = 3.3 V
98
97
96
AVDD3V = 3.35 V
AVDD3V = 3.4 V
AVDD3V = 3.45 V
AVDD3V = 3.15 V
AVDD3V = 3.2 V
AVDD3V = 3.25 V
AVDD3V = 3.3 V
74
95
SNR (dBFS)
SNR (dBFS)
SFDR
SNR
75
96
SFDR (dBc)
75
101
SNR (dBFS)
75.5
99
94
93
92
AVDD3V = 3.35 V
AVDD3V = 3.4 V
AVDD3V = 3.45 V
73.5
73
72.5
91
90
89
88
−40
72
Input Frequency = 170 MHz
−15
Input Frequency = 170 MHz
10
35
Temperature (°C)
60
85
71.5
−40
−15
G053
Figure 54. Spurious-Free Dynamic Range vs AVDD_BUF
Supply and Temperature (170 MHz)
10
35
Temperature (°C)
60
85
G054
Figure 55. Signal-to-Noise Ratio vs AVDD_BUF Supply and
Temperature (170 MHz)
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Typical Characteristics: ADS42JB49 (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 32k-point FFT, unless otherwise noted.
97
74.5
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
96
95
DRVDD = 1.85 V
DRVDD = 1.9 V
DRVDD = 1.85 V
DRVDD = 1.9 V
73.5
SNR (dBFS)
94
SFDR (dBc)
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
74
93
92
91
73
72.5
72
90
71.5
Input Frequency = 170 MHz
−15
Input Frequency = 170 MHz
10
35
Temperature (°C)
60
71
−40
85
Figure 56. Spurious-Free Dynamic Range vs
DRVDD Supply and Temperature (170 MHz)
96
76
92
75
90
74
88
73
72
86
84
0.1
0.3
0.5 0.7 0.9 1.1 1.3 1.5 1.7
Differential Clock Amplitudes (Vpp)
1.9
71
2.1
76
90
74
88
72
86
70
84
68
0.5 0.7 0.9 1.1 1.3 1.5 1.7
Differential Clock Amplitudes (Vpp)
1.9
66
2.1
G058
Figure 59. Performance vs Clock Amplitude
(170 MHz)
74.5
96
Input Frequency = 170 MHz
SNR
SFDR
94
92
74
92
73.5
90
73.5
90
73
88
73
88
72.5
86
72.5
86
72
84
72
84
71.5
71.5
82
82
30
40
50
60
Input Clock Duty Cycle (%)
70
Figure 60. Performance vs Clock Duty Cycle
(70 MHz)
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SFDR (dBc)
SNR (dBFS)
SFDR (dBc)
0.3
74.5
94
24
80
92
82
0.1
75
SNR
SFDR
SFDR
SNR
78
Figure 58. Performance vs Clock Amplitude
(70 MHz)
Input Frequency = 70 MHz
G056
94
G057
96
85
82
Input Frequency = 170 MHz
SFDR (dBc)
SFDR (dBc)
94
60
98
SNR (dBFS)
SFDR
SNR
10
35
Temperature (°C)
Figure 57. Signal-to-Noise Ratio vs
DRVDD Supply and Temperature (170 MHz)
77
96
Input Frequency = 70 MHz
−15
G055
SNR (dBFS)
88
−40
G059
30
40
50
60
Input Clock Duty Cycle (%)
70
74
SNR (dBFS)
89
71
G060
Figure 61. Performance vs Clock Duty Cycle
(170 MHz)
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SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
7.12 Typical Characteristics: Common
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 64k-point FFT, unless otherwise noted.
0
Amplitude (dBFS)
−20
−40
−60
CMRR (dB)
fIN = 100 MHz
SFDR = 86 dBc
fCM = 5 MHz, 50 mVPP
Amplitude (fIN) = −1 dBFS
Amplitude (fCM) = −105 dBFS
Amplitude (fIN + fCM) = −90 dBFS
Amplitude (fIN − fCM) = −87 dBFS
−80
−100
−120
0
20
40
60
80
Frequency (MHz)
100
120
0
−5
−10
−15
−20
−25
−30
−35
−40
−45
−50
−55
−60
−65
0
G061
Figure 62. Common-Mode Rejection Ratio FFT
50
100
150
200
250
Common−Mode Test Signal Frequency (MHz)
300
G062
Figure 63. Common-Mode Rejection Ratio vs
Test Signal Frequency
0
−20
fIN = 20 MHz
SFDR = 87 dBc
fPSRR = 5 MHz, 50 mVPP
Amplitude (fIN) = −1 dBFS
Amplitude (fPSRR) = −88 dBFS
Amplitude (fIN + fPSRR) = −97.8 dBFS
−40
50−mVPP Signal Superimposed on AVDD
100−mVPP Signal Superimposed on AVDD3V
−30
−40
PSRR (dB)
−20
Amplitude (dBFS)
Input Frequency = 10MHz
50−mVPP Signal Superimposed on VCM
−60
−80
−50
−60
−70
−100
−80
Input Frequency = 20MHz
−120
0
20
40
60
80
Frequency (MHz)
100
−90
120
0
G063
Figure 64. Power-Supply Rejection Ratio FFT for AVDD
Supply
300
G064
Figure 65. Power-Supply Rejection Ratio vs
Test Signal Frequency
0.18
2
AVDD Power
DVDD Power
IOVDD Power
AVDD3V Power
Total Power
1.6
1.4
20X Mode
10X Mode
0.15
IOVDD Power (W)
1.8
Total Power (W)
50
100
150
200
250
Test Signal Frequency on Supply (MHz)
1.2
1
0.8
0.6
0.4
0.12
0.09
0.06
0.03
0.2
0
0
50
100
150
Sampling Speed (MSPS)
200
Figure 66. Total Power vs Sampling Frequency
250
0
0
50
G065
100
150
Sampling Speed (MSPS)
200
250
G066
Figure 67. IOVDD Power vs Sampling Frequency
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7.13 Typical Characteristics: Contour
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 250 MSPS,
50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 64k-point FFT, unless otherwise noted.
7.13.1 Spurious-Free Dynamic Range (SFDR): General
240
fS - Sampling Frequency - MSPS
220
75
80
85
95
70
90
200
180
160
80
85
68
75
70
65
90
95
140
90
120
95
90
100
80
85
80
150
100
50
200
250
75
70
300
61
400
350
fIN - Input Frequency - MHz
65
70
80
75
85
90
95
SFDR - dBc
Figure 68. 0-dB Gain (SFDR)
95
240
fS - Sampling Frequency - MSPS
220
95
90
85
75
80
70
95
200
95
180
95
90
160
140
85
75
80
70
95
120
95
100
95
80
100
200
90
85
300
75
70
80
400
500
600
85
90
95
fIN - Input Frequency - MHz
70
75
80
SFDR - dBc
Figure 69. 6-dB Gain (SFDR)
26
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7.13.2 Signal-to-Noise Ratio (SNR): ADS42JB69
240
220
fS - Sampling Frequency - MSPS
73.2
73.6
72.8
72.4
72
71.5
74
200
180
73.2
73.6
160
72.8
72
72.4
71.5
71
140
74
120
100
73.6
73.2
72.4
72.8
72
71.5
80
50
70.5
71
74
150
100
250
200
300
350
400
73
73.5
74
fIN - Input Frequency - MHz
70.5
71
71.5
72
72.5
SNR - dBFS
Figure 70. 0-dB Gain (SNR, ADS42JB69)
240
68.1
220
fS - Sampling Frequency - MSPS
67.5
67.2
67.5
67.2
66.9
66.4
67.8
200
68.1
180
67.8
160
140
66.4
66.9
68.1
120
67.8
100
80
68.1
68.4
50
100
150
67.2
67.5
200
250
350
300
400
65.9
66.4
66.9
450
550
500
600
fIN - Input Frequency - MHz
65.5
66
66.5
67
67.5
68
SNR - dBFS
Figure 71. 6-dB Gain (SNR, ADS42JB69)
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7.13.3 Signal-to-Noise Ratio (SNR): ADS42JB49
240
72.6
73
fS - Sampling Frequency - MSPS
220
72.2
71.3
71.8
73.4
200
180
70.8
160
140
72.6
73
72.2
71.3
71.8
73.4
120
70.8
100
73
71.3
71.8
72.2
72.6
70.3
73.4
80
71
150
100
50
200
250
300
400
350
fIN - Input Frequency - MHz
70.5
70
71
71.5
72
72.5
73
SNR - dBFS
Figure 72. 0-dB Gain (SNR, ADS42JB49)
240
67.3
67.6
67.9
67
66.7
66.4
fS - Sampling Frequency - MSPS
220
200
67.9
180
67.3
67.6
160
67
66.7
66.4
67.9
140
120
67.9
100
67.6
68.2
80
200
100
67
67.3
300
66.7
65.9
66.4
400
500
600
fIN - Input Frequency - MHz
65.5
66
66.5
67
67.5
68
SNR - dBFS
Figure 73. 6-dB Gain (SNR, ADS42JB49)
28
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8 Parameter Measurement Information
CLKINP
Input
Clock
CLKINM
tSU_SYNC~
tH_SYNC~
SYNC~
tD
SYNC~ Asserted Latency
Dx0P, Dx0M
Dx1P, Dx1M
CGS Phase
(1)
Data
Data
Data
Data
Data
Data
Data
Data
Data
K28.5
Data
Data
Data
Data
Data
Data
Data
Data
Data
K28.5
(1)
(1) x = A for channel A and B for channel B.
Figure 74. SYNC~ Latency in CGS Phase (Two-Lane Mode)
CLKINP
Input
Clock
CLKINM
tSU_SYNC~
tH_SYNC~
SYNC~
tD
SYNC~ Deasserted Latency
ILA Sequence
Dx0P, Dx0M
Dx1P, Dx1M
(1)
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.0
K28.0
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.0
K28.0
(1)
(1) x = A for channel A and B for channel B.
Figure 75. SYNC~ Latency in ILAS Phase (Two-Lane Mode)
Sample N
tSU_SYSREF
tH_SYSREF
CLKIN
SYSREF
Figure 76. SYSREF Timing (Subclass 1)
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Parameter Measurement Information (continued)
Sample N
tSU_SYNC~
tH_SYNC~
CLKIN
SYNC~
Figure 77. SYNC~ Timing (Subclass 2)
30
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9 Detailed Description
9.1 Overview
The ADS42JB69 and ADS42JB49 is a family of high linearity, buffered analog input, dual-channel ADCs with
maximum sampling rates up to 250 MSPS employing JESD204B interface. The conversion process is initiated by
a rising edge of the external input clock and the analog input signal is sampled. The sampled signal is
sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction
logic block. At every clock edge the sample propagates through the pipeline, resulting in a data latency of 23
clock cycles. The output is available in CML logic levels following JESD204B standard.
9.2 Functional Block Diagram
Device
OVRA
Digital
Block
INAP,
INAM
14-, 16-Bit
ADC
CLKINP,
CLKINM
Gain
Test Modes
PLL
x10, x20
Divide
by 1, 2, 4
SYSREFP,
SYSREFM
JESD204B
Digital
DA0P,
DA0M
DA1P,
DA1M
SYNC~P,
SYNC~M
Delay
INBP,
INBM
14-, 16-Bit
ADC
Digital
Block
JESD204B
Digital
Gain
Test Modes
DB0P,
DB0M
DB1P,
DB1M
OVRB
Common
Mode
MODE
CTRL1
CTRL2
STBY
PDN
PDN_GBL
SDOUT
SEN
SCLK
SDATA
Device Configuration
RESET
VCM
9.3 Feature Description
9.3.1 Digital Gain
The device includes gain settings that can be used to obtain improved SFDR performance (compared to no
gain). Gain is programmable from –2 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input fullscale range scales proportionally. Table 2 shows how full-scale input voltage changes when digital gain are
programmed in 1-dB steps. Refer to Table 19 to set digital gain using a serial interface register.
SFDR improvement is achieved at the expense of SNR; for 1 dB increase in digital gain, SNR degrades
approximately between 0.5 dB and 1 dB. Therefore, gain can be used as a trade-off between SFDR and SNR.
Note that the default gain after reset is 0 dB with a 2.0-VPP full-scale voltage.
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Table 2. Full-Scale Range Across Gains
(1)
DIGITAL GAIN
FULL-SCALE INPUT VOLTAGE
–2 dB
2.5 VPP (1)
–1 dB
2.2 VPP
0 dB (default)
2.0 VPP
1 dB
1.8 VPP
2 dB
1.6 VPP
3 dB
1.4 VPP
4 dB
1.25 VPP
5 dB
1.1 VPP
6 dB
1.0 VPP
Shaded cells indicate performance settings used in the Electrical
Characteristics and Typical Characteristics.
9.3.2 Input Clock Divider
The device is equipped with an internal divider on the clock input. This divider allows operation with a faster input
clock, simplifying the system clock distribution design. The clock divider can be bypassed (divide-by-1) for
operation with a 250-MHz clock. The divide-by-2 option supports a maximum 500-MHz input clock and the
divide-by-4 option supports a maximum 1-GHz input clock frequency.
9.3.3 Overrange Indication
The device provides two different overrange indications. Normal OVR (default) is triggered if the final 16-bit data
output exceeds the maximum code value. Fast OVR is triggered if the input voltage exceeds the programmable
overrange threshold and is presented after only nine clock cycles, thus enabling a quicker reaction to an
overrange event. By default, the normal overrange indication is output on the OVRA and OVRB pins. Using the
register bit FAST OVR EN, the fast OVR indication can be presented on the overrange pins instead.
The input voltage level at which the overload is detected is referred to as the threshold and is programmable
using the FAST OVR THRESHOLD bits. FAST OVR is triggered nine output clock cycles after the overload
condition occurs. The threshold voltage amplitude at which fast OVR is triggered is:
1 × [the decimal value of the FAST OVR THRESH bits] / 127
When digital is programmed (for gain values > 0 dB), the
10–Gain / 20 × [the decimal value of the FAST OVR THRESH bits] / 127
threshold
voltage
amplitude
is:
9.3.4 Pin Controls
The device power-down functions can be controlled either through the parallel control pins (STBY, PDN_GBL,
CTRL1, and CTRL2) or through an SPI register setting.
STBY places the device in a standby power-down mode. PDN_GBL places the device in global power-down
mode.
Table 3. CTRL1, CTRL2 Pin Functions
CTRL1
CTRL2
DESCRIPTION
Low
Low
Normal operation
High
Low
Channel A powered down
Low
High
Channel B powered down
High
High
Global power-down
Table 4. PDN_GBL Pin Function
32
PDN_GBL
DESCRIPTION
Low
Normal operation
High
Global power-down. Wake-up from this mode is slow.
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Table 5. STBY Pin Function
STBY
DESCRIPTION
Low
Normal operation
High
ADCs are powered down while the input clock buffer and output CML buffers
are alive. Wake-up from this mode is fast.
9.4 Device Functional Modes
9.4.1 JESD204B Interface
The JESD interface of ADS42JB49 and ADS42JB69, as shown in Figure 78, supports device subclasses 0, 1,
and 2 with a maximum output data rate (per lane) of 3.125 Gbps.
An external SYSREF (subclass 1) or SYNC~ (subclass 2) signal is used to align all internal clock phases and the
local multiframe clock to a specific sampling clock edge. This alignment allows synchronization of multiple
devices in a system and minimizes timing and alignment uncertainty.
SYSREF SYNC~
INA
JESD
204B
JESD204B
D0, D1
INB
JESD
204B
JESD204B
D0, D1
Sample
Clock
Figure 78. JESD204B Interface
Depending on the ADC sampling rate, the JESD204B output interface can be operated with either one or two
lanes per ADC. The JESD204B interface can be configured using serial registers.
The JESD204B transmitter block (Figure 79) consists of the transport layer, the data scrambler, and the link
layer. The transport layer maps the ADC output data into the selected JESD204B frame data format and
manages if the ADC output data or test patterns are transmitted. The link layer performs the 8b and 10b data
encoding as well as the synchronization and initial lane alignment using the SYNC~ input signal. Optionally, data
from the transport layer can be scrambled.
JESD204B Block
Transport Layer
Frame Data
Mapping
Link Layer
Scrambler
1+x14+x15
Test Patterns
8b,10b
encoding
Comma characters
Initial lane alignment
D0
D1
SYNC~
Figure 79. JESD204B Block
9.4.1.1 JESD204B Initial Lane Alignment (ILA)
When receiving device asserts the SYNC~ signal ( i.e a logic low signal is applied on SYNC~P - SYNC~M), the
device begins transmitting comma (K28.5) characters to establish code group synchronization (CGS).
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Device Functional Modes (continued)
When synchronization is complete, the receiving device de-asserts the SYNC~ signal and the ADS42JB49 and
ADS42JB69 begin the initial lane alignment (ILA) sequence with the next local multiframe clock boundary. The
device transmits four multiframes, each containing K frames (where K is SPI programmable). Each multiframe
contains the frame start and end symbols; the second multiframe also contains the JESD204 link configuration
data.
9.4.1.2 JESD204B Test Patterns
There are three different test patterns available in the transport layer of the JESD204B interface. The device
supports a clock output, an encoded, and a PRBS (215 – 1) pattern. These patterns can be enabled by serial
register write in address 26h, bits D[7:6].
9.4.1.3 JESD204B Frame Assembly
The JESD204B standard defines the following parameters:
• L is the number of lanes per Lane.
• M is the number of converters per device.
• F is the number of octets per frame clock period.
• S is the number of samples per frame.
Table 6 lists the available JESD204B formats and valid device ranges. Ranges are limited by the maximum ADC
sample frequency and the SERDES line rate.
Table 6. JESD240B Ranges
L
M
F
S
MAX ADC SAMPLING RATE (MSPS)
MAX fSERDES (Gbps)
4
2
1
1
250
2.5
2
2
2
1
156.25
3.125
The detailed frame assembly in 10x and 20x modes for dual-channel operation is shown in Table 7. Note that
unused lanes in 10x mode become 3-stated.
Table 7. Frame Assembly for Dual-Channel Mode (1)
LANE
(1)
34
LMF = 421
LMF = 222
DA0
A0[15:8]
A1[15:8]
A2[15:8]
A0[15:8]
A0[7:0]
A1[15:8]
A1[7:0]
A2[15:8]
DA1
A0[7:0]
A1[7:0]
A2[7:0]
—
—
—
—
—
A2[7:0]
—
DB0
B0[15:8]
B1[15:8]
B2[15:8]
B0[15:8]
B0[7:0]
B1[15:8]
B1[7:0]
B2[15:8]
B2[7:0]
DB1
B0[7:0]
B1[7:0]
B2[7:0]
—
—
—
—
—
—
In ADS42JB49 two LSBs of 16-bit data are padded with 00.
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9.4.1.4 JESD Link Configuration
During the lane alignment sequence, the ADS42JB69 and ADS42JB49 transmit JESD204B configuration
parameters in the second multi-frame of the ILA sequence. Configuration bits are mapped in octets, as per the
JESD204B standard described in Figure 80 and Table 8.
Figure 80. Initial Lane Alignment Sequence
Table 8. Mapping of Configuration Bits to Octets
OCTET NO.
MSB
D6
D5
0
D4
D3
1
ADJCNT[3:0]
2
X
3
SCR[0]
ADJDIR[0]
D1
LSB
BID[3:0]
PHADJ[0]
LID[4:0]
L[4:0]
4
F[7:0]
5
K[4:0]
6
M[7:0]
7
CS[1:0]
X
8
SUBCLASSV[2:0]
9
JESDV[2:0]
10
D2
DID[7:0]
HD[0]
N[4:0]
N'[4:0]
S[4:0]
X
X
11
CF[4:0]
RES1[7:0]
12
RES2[7:0]
13
FCHK[7:0]
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9.4.1.4.1 Configuration for 2-Lane (20x) SERDES Mode
Table 9 lists the values of the JESD204B configuration bits applicable for the 2-lane SERDES Mode. The default
value of these bits after reset is also specified in the table.
Table 9. Configuration for 2-Lane SERDES Mode
PARAMETER
DESCRIPTION
PARAMETER
RANGE
FIELD
ENCODING
DEFAULT
VALUE AFTER
RESET
ADJCNT
Number of adjustment resolution steps
to adjust DAC LMFC. Applies to
subclass 2 operation only.
0-15
ADJCNT[3:0]
Binary value
0
ADJDIR
Direction to adjust DAC LMFC
0 : Advance
1 : Delay applies to subclass 2
operation only
0-1
ADJDIR[0]
Binary value
0
BID
Bank ID – extension to DID
0-15
BID[3:0]
Binary value
0
CF
No. of control words per frame clock
period per link
0-32
CF[4:0]
Binary value
0
CS
No. of control bits per sample
0-3
CS[1:0]
Binary value
0
DID
Device (= link) identification no.
0-255
DID[7:0]
Binary value
0
1-256
F[7:0]
Binary value
minus 1
1
High-density format
0-1
HD[0]
Binary value
0
JESD204 version
000 : JESD204A
001 : JESD204B
0-7
JESDV[2:0]
Binary value
1
K
No. of frames per multi-frame
1-32
K[4:0]
Binary value
minus 1
8
L
No. of lanes per converter device (link)
1-32
L[4:0]
Binary value
minus 1
0
Lane identification no. (within link)
0-31
LID[4:0]
Binary value
LID[0] = 0,
LID[1] = 1
M
No. of converters per device
1-256
M[7:0]
Binary value
minus 1
1
N
Converter resolution
1-32
N[4:0]
Binary value
minus 1
15
N’
Total no. of bits per sample
1-32
N'[4:0]
Binary value
minus 1
15
Phase adjustment request to DAC
subclass 2 only.
0-1
PHADJ[0]
Binary value
0
No. of samples per converter per frame
cycle
1-32
S[4:0]
Binary value
minus 1
0
Scrambling enabled
0-1
SCR[0]
Binary value
0
SUBCLASSV
Device subclass version
000 : Subclass 0
001 : Subclass 1
010 : Subclass 2
0-7
SUBCLASSV[2:0]
Binary value
2
RES1
Device subclass version
000 : Subclass 0
001 : Subclass 1
010 : Subclass 2
0-255
RES1[7:0]
Binary value
0
RES2
Reserved field 2
0-255
RES2[7:0]
Binary value
0
Checksum Σ (all above fields) mod 256
0-255
FCHK[7:0]
Binary value
44, 45
F
HD
JESDV
LID
PHADJ
S
SCR
CHKSUM
36
No. of octets per frame
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9.4.1.4.2 Configuration for 4-Lane (10x) SERDES Mode
Table 10 lists the values of the JESD204 configuration bits applicable for the 4-lane SERDES Mode. The default
value of these bits after reset is also specified in the table.
Table 10. Configuration for 4-Lane SERDES Mode
PARAMETER
DESCRIPTION
PARAMETER
RANGE
FIELD
ENCODING
DEFAULT
VALUE AFTER
RESET
ADJCNT
Number of adjustment resolution steps
to adjust DAC LMFC. Applies to
subclass 2 operation only.
0-15
ADJCNT[3:0]
Binary value
0
ADJDIR
Direction to adjust DAC LMFC
0 : Advance
1 : Delay applies to subclass 2
operation only
0-1
ADJDIR[0]
Binary value
0
BID
Bank ID; extension to DID
0-15
BID[3:0]
Binary value
0
CF
No. of control words per frame clock
period per link
0-32
CF[4:0]
Binary value
0
CS
No. of control bits per sample
0-3
CS[1:0]
Binary value
0
DID
Device (= link) identification no.
0-255
DID[7:0]
Binary value
0
1-256
F[7:0]
Binary value
minus 1
0
High-density format
0-1
HD[0]
Binary value
1
JESD204 version
000 : JESD204A
001 : JESD204B
0-7
JESDV[2:0]
Binary value
1
K
No. of frames per multi-frame
1-32
K[4:0]
Binary value
minus 1
16
L
No. of lanes per converter device (link)
1-32
L[4:0]
Binary value
minus 1
3
Lane identification no (within link)
0-31
LID[4:0]
Binary value
LID[0] = 0,
LID[1] = 1,
LID[2] = 2,
LID[3] = 3
M
No. of converters per device
1-256
M[7:0]
Binary value
minus 1
1
N
Converter resolution
1-32
N[4:0]
Binary value
minus 1
15
N’
Total no. of bits per sample
1-32
N'[4:0]
Binary value
minus 1
15
Phase adjustment request to DAC
subclass 2 only.
0-1
PHADJ[0]
Binary value
0
No. of samples per converter per frame
cycle
1-32
S[4:0]
Binary value
minus 1
0
Scrambling enabled
0-1
SCR[0]
Binary value
0
SUBCLASSV
Device subclass version
000 : Subclass 0
001 : Subclass 1
010 : Subclass 2
0-7
SUBCLASSV[2:0]
Binary value
2
RES1
Device subclass version
000 : Subclass 0
001 : Subclass 1
010 : Subclass 2
0-255
RES1[7:0]
Binary value
0
RES2
Reserved field 2
0-255
RES2[7:0]
Binary value
0
Checksum Σ (all above fields) mod 256
0-255
FCHK[7:0]
Binary value
54, 55, 56, 57
F
HD
JESDV
LID
PHADJ
S
SCR
CHKSUM
No. of octets per frame
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9.4.1.5 CML Outputs
The device JESD204B transmitter uses differential CML output drivers. The CML output current is programmable
from 5 mA to 20 mA using register settings.
The output driver includes an internal 50-Ω termination to IOVDD supply. External 50-Ω termination resistors
connected to receiver common-mode voltage should be placed close to receiver pins. AC coupling can be used
to avoid the common-mode mismatch between transmitter and receiver, as shown in Figure 81.
Vterm
Rt= ZO
Transmission Line
Zo
Rt= ZO
0.1uF
DA/B[0,1]P
Receiver
DA/B[0,1]M
0.1uF
Figure 81. CML Output Connections
Figure 82 and Figure 83 show the data eye measurements of the device JESD204B transmitter against the
JESD204B transmitter mask at 2.5 GBPS (10x mode) and 3.125 GBPS (20x mode), respectively.
300
300
150
Voltage (mV)
Voltage (mV)
150
0
0
-150
-150
-300
-300
-200
-300
-200
-100
0
100
200
-150
-100
300
-50
0
50
100
150
200
Time (ps)
Time (ps)
Figure 82. Eye Diagram: 2.5 Gbps
38
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Figure 83. Eye Diagram: 3.125 Gbps
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9.5 Programming
9.5.1 Device Configuration
The ADS42JB49 and ADS42JB69 can be configured using a serial programming interface, as described in the
Serial Interface section. In addition, the device has four dedicated parallel pins (PDN_GBL, STBY, CTRL1, and
CTRL2) for controlling the power-down modes.
9.5.2 Details of Serial Interface
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data
output) pins. Serially shifting bits into the device is enabled when SEN is low. SDATA serial data are latched at
every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 16th
SCLK rising edge when SEN is low. When the word length exceeds a multiple of 16 bits, the excess bits are
ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The interface functions
with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with non-50% SCLK duty
cycle.
9.5.2.1 Register Initialization
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin (of widths greater than 10 ns), as shown in Figure 84. Later during
operation, if required serial interface registers can be cleared by:
1. Either through a hardware reset or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 08h)
high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.
In this case, the RESET pin is kept low.
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
NOTE: After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on
the RESET pin.
Figure 84. Reset Timing Diagram
Table 11. Reset Timing
(1)
TEST CONDITIONS
MIN
t1
Power-on delay
Delay from AVDD and DRVDD power-up to active RESET
pulse
t2
Reset pulse width
Active RESET signal pulse width
t3
Register write delay
Delay from RESET disable to SEN active
(1)
TYP
MAX
UNIT
1
ms
10
ns
1
100
µs
ns
Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, unless
otherwise noted.
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9.5.2.2 Serial Register Write
The internal device register can be programmed following these steps:
1. Drive the SEN pin low.
2. Set the R/W bit to ‘0’ (bit A7 of the 8-bit address).
3. Set bit A6 in the address field to ‘0’.
4. Initiate a serial interface cycle specifying the address of the register (A5 to A0) whose content must be
written (as shown in Figure 85 and Table 12).
5. Write the 8-bit data that is latched on the SCLK rising edge.
Register Address <5:0>
SDATA
R/W
0
A5
A4
A3
A2
A1
Register Data <7:0>
A0
D7
D6
D5
D4
D3
=0
D2
D1
D0
tDH
tSCLK
tDSU
SCLK
tSLOADS
tSLOADH
SEN
RESET
Figure 85. Serial Register Write Timing Diagram
Table 12. Serial Interface Timing (1)
MIN
MAX
UNIT
20
MHz
SCLK frequency (equal to 1 / tSCLK)
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDSU
SDIO setup time
25
ns
tDH
SDIO hold time
25
ns
(1)
40
> dc
TYP
fSCLK
Typical values are at +25°C, minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C,
AVDD3V = 3.3 V, and AVDD = DRVDD = IOVDD = 1.8 V, unless otherwise noted.
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9.5.2.3 Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back. This readback mode
may be useful as a diagnostic check to verify the serial interface communication between the external controller
and the ADC.
1. Set bit A7 (MSB) of 8 bit address to '1'.
2. Write the address of register on bits A5 through A0 whose contents must be read. See Figure 86
3. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin (pin 45).
4. The external controller can latch the contents at the SCLK rising edge.
When serial registers are enabled for writing (bit A7 of 8-bit address bus is 0), the SDOUT pin is in a highimpedance mode. If serial readout is not used, the SDOUT pin must float. Figure 86 shows a timing diagram of
this readout mode. SDOUT comes out at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns,
as shown in Figure 87.
Register Address <5:0>
SDATA
R/W
0
A5
A4
A3
A2
A1
Register Data: don’t care
A0
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
=1
Register Read Data <7:0>
SDOUT
D7
D6
D5
D4
D3
D2
SCLK
SEN
Figure 86. Serial Register Readout Timing Diagram
SCLK
tSD_DELAY
SDOUT
Figure 87. SDOUT Timing Diagram
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9.6 Register Maps
Table 13 lists a summary of the serial interface registers.
Table 13. Summary of Serial Interface Registers
REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
06
0
0
0
0
0
0
07
0
0
0
0
0
08
PDN CHA
PDN CHB
STDBY
DATA
FORMAT
Always write
1
D1
D0
CLK DIV
SYSREF DELAY
0
0
RESET
0B
CHA GAIN
CHA GAIN
EN
0
0
0C
CHBGAIN
CHB GAIN
EN
0
0
0D
HIGH FREQ
1
0
0
HIGH FREQ
1
0
0
0
FAST OVR
EN
0E
HIGH FREQ
2
0
0
HIGH FREQ
2
0
0
0
0
0F
CHA TEST PATTERNS
CHB TEST PATTERNS
10
CUSTOM PATTERN 1[15:8]
11
CUSTOM PATTERN 1[7:0]
12
CUSTOM PATTERN 2[15:8]
13
CUSTOM PATTERN 2[7:0]
1F
26
Always write
0
FAST OVR THRESHOLD
SERDES TEST PATTERN
IDLE SYNC
TESTMODE
EN
FLIP ADC
DATA
LAN ALIGN
FRAME
ALIGN
TX LINK
CONFIG
DATA0
27
0
0
0
0
0
0
CTRLK
CTRLF
2B
SCRAMBLE
EN
0
0
0
0
0
0
0
2C
0
0
0
0
0
0
0
OCTETS
PER FRAME
2D
0
0
0
0
0
30
SUBCLASS
36
LMFC
RESET
MASK
37
38
SYNC REQ
0
0
LINK LAYER TESTMODE
FORCE
LMFC
COUNT
FRAMES PER MULTIFRAME
0
0
0
LINK LAYER
RPAT
OUTPUT CURRENT SEL
0
PULSE DET MODES
LMFC COUNT INIT
RELEASE ILANE SEQ
Table 14. High-Frequency Modes Summary
42
REGISTER
ADDRESS
VALUE
Dh
90h
High-frequency modes should be enabled for input frequencies greater than 250 MHz.
Eh
90h
High-frequency modes should be enabled for input frequencies greater than 250 MHz.
DESCRIPTION
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9.6.1 Description of Serial Interface Registers
9.6.1.1 Register 6 (offset = 06h) [reset = 00h]
Figure 88. Register 6
D7
0
W-0h
D6
0
W-0h
D5
0
W-0h
D4
0
W-0h
D3
0
W-0h
D2
0
W-0h
D1
D0
CLK DIV
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. Register 6 Field Descriptions
Bit
D[7:2]
D[1:0]
Field
Type
Reset
Description
0
W
0h
Always write '0'
0h
Internal clock divider for input sample clock
00 : Divide-by-1 (clock divider bypassed)
01 : Divide-by-2
10 : Divide-by-1
11 : Divide-by-4
CLK DIV
R/W
9.6.1.2 Register 7 (offset = 07h) [reset = 00h]
Figure 89. Register 7
D7
0
W-0h
D6
0
W-0h
D5
0
W-0h
D4
0
W-0h
D3
0
W-0h
D2
0
W-0h
D1
D0
SYSREF DELAY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. Register 7 Field Descriptions
Bit
D[7:2]
D[1:0]
Field
Type
Reset
Description
0
W
0h
Always write '0'
0h
Controls the delay of the SYSREF input with respect to the input
clock. Typical values for the expected delay of different settings
are:
000 : 0-ps delay
001 : 60-ps delay
010 : 120-ps delay
011 : 180-ps delay
100 : 240-ps delay
101 : 300-ps delay
110 : 360-ps delay
111 : 420-ps delay
SYSREF DELAY
R/W
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9.6.1.3 Register 8 (offset = 08h) [reset = 00h]
Figure 90. Register 8
D7
D6
D5
PDN CHA
PDN CHB
STDBY
R/W-0h
R/W-0h
R/W-0h
D4
DATA
FORMAT
R/W-0h
D3
D2
D1
D0
1
0
0
RESET
W-1h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. Register 8 Field Descriptions
Bit
Field
Type
Reset
Description
D7
PDN CHA
R/W
0h
Power-down channel A
0 : Normal operation
1 : Channel A power-down
D6
PDN CHB
R/W
0h
Power-down channel B
0 : Normal operation
1 : Channel B power-down
D5
STBY
R/W
0h
Dual ADC is placed into standby mode
0 : Normal operation
1 : Both ADCs are powered down (input clock buffer and CML
output buffers are alive)
D4
DATA FORMAT
R/W
0h
Digital output data format
0 : Twos complement
1 : Offset binary
D3
1
W
1h
Always write '1'
Default value of this bit is '0'. This bit must always be set to '1'.
D[2:1]
0
W
0h
Always write '0'
RESET
R/W
0h
Software reset applied
This bit resets all internal registers to the default values and selfclears to ‘0’.
D0
44
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9.6.1.4 Register B (offset = 0Bh) [reset = 00h]
Figure 91. Register B
D7
D6
D5
CHA GAIN
R/W-0h
D4
D3
D2
CHA GAIN EN
R/W-0h
D1
0
W-0h
D0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. Register B Field Descriptions
Bit
D[7:3]
D2
D[1:0]
Field
Type
Reset
Description
CHA GAIN
R/W
0h
Digital gain for channel A (must set the CHA GAIN EN bit first,
bit D2). Bit descriptions are listed in Table 19.
CHA GAIN EN
R/W
0h
Digital gain enable bit for channel A
0 : Digital gain disabled
1 : Digital gain enabled
0
W
0h
Always write '0'
Table 19. Digital Gain for Channel A
REGISTER VALUE
DIGITAL GAIN
FULL-SCALE
INPUT VOLTAGE
REGISTER VALUE
DIGITAL GAIN
FULL-SCALE
INPUT VOLTAGE
00000
0 dB
2.0 VPP
01010
1.5 dB
1.7 VPP
00001
Do not use
—
01011
2 dB
1.6 VPP
00010
Do not use
—
01100
2.5 dB
1.5 VPP
00011
–2.0 dB
2.5 VPP
01101
3 dB
1.4 VPP
00100
–1.5 dB
2.4 VPP
01110
3.5 dB
1.3 VPP
00101
–1.0 dB
2.2 VPP
01111
4 dB
1.25 VPP
00110
–0.5 dB
2.1 VPP
10000
4.5 dB
1.2 VPP
00111
0 dB
2.0 VPP
10001
5 dB
1.1 VPP
01000
0.5 dB
1.9 VPP
10010
5.5 dB
1.05 VPP
01001
1 dB
1.8 VPP
10011
6 dB
1.0 VPP
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9.6.1.5 Register C (offset = 0Ch) [reset = 00h]
Figure 92. Register C
D7
D6
D5
CHB GAIN
R/W-0h
D4
D3
D2
CHB GAIN EN
R/W-0h
D1
0
W-0h
D0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. Register C Field Descriptions
Bit
D[7:3]
D2
D[1:0]
Field
Type
Reset
Description
CHB GAIN
R/W
0h
Digital gain for channel B (must set the CHA GAIN EN bit first,
bit D2). Bit descriptions are listed in Table 21.
CHB GAIN EN
R/W
0h
Digital gain enable bit for channel B
0 : Digital gain disabled
1 : Digital gain enabled
0
W
0h
Always write '0'
Table 21. Digital Gain for Channel B
REGISTER VALUE
DIGITAL GAIN
FULL-SCALE
INPUT VOLTAGE
REGISTER VALUE
DIGITAL GAIN
FULL-SCALE
INPUT VOLTAGE
00000
0 dB
2.0 VPP
01010
1.5 dB
1.7 VPP
00001
Do not use
—
01011
2 dB
1.6 VPP
00010
Do not use
—
01100
2.5 dB
1.5 VPP
00011
–2.0 dB
2.5 VPP
01101
3 dB
1.4 VPP
00100
–1.5 dB
2.4 VPP
01110
3.5 dB
1.3 VPP
00101
–1.0 dB
2.2 VPP
01111
4 dB
1.25 VPP
00110
–0.5 dB
2.1 VPP
10000
4.5 dB
1.2 VPP
00111
0 dB
2.0 VPP
10001
5 dB
1.1 VPP
01000
0.5 dB
1.9 VPP
10010
5.5 dB
1.05 VPP
01001
1 dB
1.8 VPP
10011
6 dB
1.0 VPP
46
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9.6.1.6 Register D (offset = 0Dh) [reset = 00h]
Figure 93. Register D
D7
HIGH FREQ 1
R/W-0h
D6
0
W-0h
D5
0
W-0h
D4
HIGH FREQ 1
R/W-0h
D3
0
W-0h
D2
0
W-0h
D1
0
W-0h
D0
FAST OVR EN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. Register D Field Descriptions
Bit
D7
D[6:5]
D4
D[3:1]
D0
Field
Type
Reset
Description
HIGH FREQ 1
R/W
0h
High-frequency mode 1
00 : Default
11 : Use for input frequencies > 250 MHz along with HIGH
FREQ 2
0
W
0h
Always write '0'
HIGH FREQ 1
R/W
0h
High-frequency mode 1
00 : Default
11 : Use for input frequencies > 250 MHz along with HIGH
FREQ 2
0
W
0h
Always write '0'
FAST OVR EN
R/W
0h
Selects if normal or fast OVR signal is presented on OVRA,
OVRB pins
0 : Normal OVR on OVRA, OVRB pins
1 : Fast OVR on OVRA, OVRB pins
9.6.1.7 Register E (offset = 0Eh) [reset = 00h]
Figure 94. Register E
D7
HIGH FREQ 2
R/W-0h
D6
0
W-0h
D5
0
W-0h
D4
HIGH FREQ 2
R/W-0h
D3
0
W-0h
D2
0
W-0h
D1
0
W-0h
D0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. Register E Field Descriptions
Bit
Field
Type
Reset
Description
D7
HIGH FREQ 2
R/W
0h
High-frequency mode 2
00 : Default
11 : Use for input frequencies > 250 MHz along with HIGH
FREQ 1
0
W
0h
Always write '0'
HIGH FREQ 2
R/W
0h
High-frequency mode 2
00 : Default
11 : Use for input frequencies > 250 MHz along with HIGH
FREQ 1
0
W
0h
Always write '0'
D[6:5]
D4
D[3:0]
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9.6.1.8 Register F (offset = 0Fh) [reset = 00h]
Figure 95. Register F
D7
D6
D5
CHA TEST PATTERNS
R/W-0h
D4
D3
D2
D1
CHB TEST PATTERNS
R/W-0h
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. Register F Field Descriptions
Bit
Field
D[7:4]
48
CHA TEST PATTERNS
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Type
R/W
Reset
Description
0h
Channel A test pattern programmability
The 16-bit test pattern data are selected as an input to the JESD
block (in the ADS42JB49, the last two LSBs of the 16-bit data
are replaced by 00).
0000 : Normal operation
0001 : All '0's
0010 : All '1's
0011 : Toggle pattern: In the ADS42JB69, data are an
alternating sequence of 1010101010101010 and
0101010101010101. In the ADS42JB49, data alternate between
10101010101010 and 01010101010101.
0100 : Digital ramp: In the ADS42JB69, data increment by 1
LSB every clock cycle from code 0 to 65535. In the ADS42JB49,
data increment by 1 LSB every 4th clock cycle from code 0 to
16383.
0101 : Do not use
0110 : Single pattern: In the ADS42JB69, data are the same as
programmed by the CUSTOM PATTERN 1[15:0] registers bits.
In the ADS42JB49, data are the same as programmed by the
CUSTOM PATTERN 1[15:2] register bits.
0111 : Double pattern: In the ADS42JB69, data alternate
between CUSTOM PATTERN 1[15:0] and CUSTOM PATTERN
2[15:0]. In the ADS42JB49 data alternate between CUSTOM
PATTERN 1[15:2] and CUSTOM PATTERN 2[15:2].
1000 : Deskew pattern: In the ADS42JB69, data are AAAAh. In
the ADS42JB49, data are 3AAAh.
1001 : Do not use
1010 : PRBS pattern: Data are a sequence of pseudo random
numbers.
1011 : 8-point sine wave: In the ADS42JB69, data are a
repetitive sequence of the following eight numbers, forming a
sine-wave in twos complement format:
1, 9598, 32768, 55938, 65535, 55938, 32768, 9598.
In the ADS42JB49, data are a repetitive sequence of the
following eight numbers, forming a sine-wave in twos
complement format:
0, 2399, 8192, 13984, 16383, 13984, 8192, 2399.
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Table 24. Register F Field Descriptions (continued)
Bit
D[3:0]
Field
Type
CHB TEST PATTERNS
R/W
Reset
Description
0h
Channel B test pattern programmability
16-bit test pattern data are selected as an input to the JESD
block (in the ADS42JB49, the last two LSBs of the 16-bit data
are replaced by 00).
0000 : Normal operation
0001 : All '0's
0010 : All '1's
0011 : Toggle pattern: In the ADS42JB69, data are an
alternating sequence of 1010101010101010 and
0101010101010101. In the ADS42JB49, data alternate between
10101010101010 and 01010101010101.
0100 : Digital ramp: In the ADS42JB69, data increment by 1
LSB every clock cycle from code 0 to 65535. In the ADS42JB49,
data increment by 1 LSB every 4th clock cycle from code 0 to
16383.
0101 : Do not use
0110 : Single pattern: In the ADS42JB69, data are the same as
programmed by the CUSTOM PATTERN 1[15:0] registers bits.
In the ADS42JB49, data are the same as programmed by the
CUSTOM PATTERN 1[15:2] register bits.
0111 : Double pattern: In the ADS42JB69, data alternate
between CUSTOM PATTERN 1[15:0] and CUSTOM PATTERN
2[15:0]. In the ADS42JB49, data alternate between CUSTOM
PATTERN 1[15:2] and CUSTOM PATTERN 2[15:2].
1000 : Deskew pattern: In the ADS42JB69, data are AAAAh. In
the ADS42JB49, data are 3AAAh.
1001 : Do not use
1010 : PRBS pattern: Data are a sequence of pseudo random
numbers.
1011 : 8-point sine wave: In the ADS42JB69, data are a
repetitive sequence of the following eight numbers, forming a
sine-wave in twos complement format:
1, 9598, 32768, 55938, 65535, 55938, 32768, 9598.
In the ADS42JB49, data are a repetitive sequence of the
following eight numbers, forming a sine-wave in twos
complement format:
0, 2399, 8192, 13984, 16383, 13984, 8192, 2399.
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9.6.1.9 Register 10 (offset = 10h) [reset = 00h]
Figure 96. Register 10
D7
D6
D5
D4
D3
CUSTOM PATTERN 1[15:8]
R/W-0h
D2
D1
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25. Register 10 Field Descriptions
Bit
D[7:0]
Field
Type
Reset
Description
CUSTOM PATTERN 1[15:8]
R/W
0h
Sets CUSTOM PATTERN 1[15:8] using these bits for both
channels
9.6.1.10 Register 11 (offset = 11h) [reset = 00h]
Figure 97. Register 11
D7
D6
D5
D4
D3
CUSTOM PATTERN 1[7:0]
R/W-0h
D2
D1
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26. Register 11 Field Descriptions
Bit
D[7:0]
Field
Type
Reset
Description
CUSTOM PATTERN 1[7:0]
R/W
0h
Sets CUSTOM PATTERN 1[7:0] using these bits for both
channels
9.6.1.11 Register 12 (offset = 12h) [reset = 00h]
Figure 98. Register 12
D7
D6
D5
D4
D3
CUSTOM PATTERN 2[15:8]
R/W-0h
D2
D1
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 27. Register 12 Field Descriptions
Bit
D[7:0]
Field
Type
Reset
Description
CUSTOM PATTERN 2[15:8]
R/W
0h
Sets CUSTOM PATTERN 2[15:8] using these bits for both
channels
9.6.1.12 Register 13 (offset = 13h) [reset = 00h]
Figure 99. Register 13
D7
D6
D5
D4
D3
CUSTOM PATTERN 2[7:0]
R/W-0h
D2
D1
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. Register 13 Field Descriptions
Bit
D[7:0]
50
Field
Type
Reset
Description
CUSTOM PATTERN 2[7:0]
R/W
0h
Sets CUSTOM PATTERN 2[7:0] using these bits for both
channels
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9.6.1.13 Register 1F (offset = 1Fh) [reset = FFh]
Figure 100. Register 1F
D7
0
W-1h
D6
D5
D4
D3
FAST OVR THRESHOLD
R/W-0h
D2
D1
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 29. Register 1F Field Descriptions
Bit
Field
Type
Reset
Description
D7
0
W
W-1h
Always write '0'
The default value of this bit is '1'. Always write this bit to '0' when
fast OVR thresholds are programmed.
0h
The device has a fast OVR mode that indicates an overload
condition at the ADC input. The input voltage level at which the
overload is detected is referred to as the threshold and is
programmable using the FAST OVR THRESHOLD bits. FAST
OVR is triggered nine output clock cycles after the overload
condition occurs. The threshold at which fast OVR is triggered is
(full-scale × [the decimal value of the FAST OVR THRESHOLD
bits] / 127). See the Overrange Indication section for details.
D[6:0]
FAST OVR THRESHOLD
R/W
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9.6.1.14 Register 26 (offset = 26h) [reset = 00h]
Figure 101. Register 26
D7
D6
D5
SERDES TEST PATTERN
IDLE SYNC
R/W-0h
R/W-0h
D4
TESTMODE
EN
R/W-0h
D3
FLIP ADC
DATA
R/W-0h
D2
D1
LANE ALIGN
FRANE ALIGN
R/W-0h
R/W-0h
D0
TX LINK
CONFIG DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30. Register 26 Field Descriptions
Bit
Field
Type
Reset
Description
SERDES TEST PATTERN
R/W
0h
Sets test patterns in the transport layer of the JESD204B
interface
00 : Normal operation
01 : Outputs clock pattern: Output is a 10101010 pattern
10 : Encoded pattern: Output is 1111111100000000
11 : PRBS sequence: Output is 215 – 1
D5
IDLE SYNC
R/W
0h
Sets output pattern when SYNC~ is asserted
0 : Sync code is k28.5 (0xBCBC)
1 : Sync code is 0xBC50
D4
TESTMODE EN
R/W
0h
Generates a long transport layer test pattern mode according to
the 5.1.63 clause of the JESD204B specification
0 : Test mode disabled
1 : Test mode enabled
D3
FLIP ADC DATA
R/W
0h
0 : Normal operation
1 : Output data order is reversed: MSB – LSB
0h
Inserts a lane alignment character (K28.3) for the receiver to
align to the lane boundary per section 5.3.3.5 of the JESD204B
specification.
0 : Lane alignment characters are not inserted.
1 : Inserts lane alignment characters
D[7:6]
D2
LANE ALIGN
R/W
D1
FRAME ALIGN
R/W
0h
Inserts a frame alignment character (K28.7) for the receiver to
align to the frame boundary per section 5.3.3.4 of the JESD204B
specification.
0 : Frame alignment characters are not inserted.
1 : Inserts frame alignment characters
D0
TX LINK CONFIG DATA
R/W
0h
Disables sending initial link alignment (ILA) sequence when
SYNC~ is de-asserted, '0'
0 : ILA enabled
1 : ILA disabled
9.6.1.15 Register 27 (offset = 27h) [reset = 00h]
Figure 102. Register 27
D7
0
W-0h
D6
0
W-0h
D5
0
W-0h
D4
0
W-0h
D3
0
W-0h
D2
0
W-0h
D1
CTRL K
R/W-0h
D0
CTRL F
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31. Register 27 Field Descriptions
Bit
Field
Type
Reset
Description
0
W
0h
Always write '0'
D1
CTRL K
R/W
0h
Enables bit for number of frames per multiframe
0 : Default
1 : Frames per multiframe can be set in register 2Dh
D0
CTRL F
R/W
0h
Enables bit for number of octets per frame
0 : Default
1 : Octets per frame can be specified in register 2Ch
D[7:2]
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9.6.1.16 Register 2B (offset = 2Bh) [reset = 00h]
Figure 103. Register 2B
D7
SCRAMBLE EN
R/W-0h
D6
0
W-0h
D5
0
W-0h
D4
0
W-0h
D3
0
W-0h
D2
0
W-0h
D1
0
W-0h
D0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 32. Register 2B Field Descriptions
Bit
Field
Type
Reset
Description
D7
SCRAMBLE EN
R/W
0h
Scramble enable bit in the JESD204B interface
0 : Scrambling disabled
1 : Scrambling enabled
0
W
0h
Always write '0'
D[6:0]
9.6.1.17 Register 2C (offset = 2Ch) [reset = 00h]
Figure 104. Register 2C
D7
0
W-0h
D6
0
W-0h
D5
0
W-0h
D4
0
W-0h
D3
0
W-0h
D2
0
W-0h
D1
0
W-0h
D0
OCTETS PER FRAME
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 33. Register 2C Field Descriptions
Bit
D[7:1]
D0
Field
Type
Reset
Description
0
W
0h
Always write '0'
OCTETS PER FRAME
R/W
0h
Sets number of octets per frame (F)
0 : 10x mode using two lanes per ADC
1 : 20x mode using one lane per ADC
9.6.1.18 Register 2D (offset = 2Dh) [reset = 00h]
Figure 105. Register 2D
D7
0
W-0h
D6
0
W-0h
D5
0
W-0h
D4
D3
D2
D1
FRAMES PER MULTIFRAME
R/W-0h
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34. Register 2D Field Descriptions
Bit
D[7:5]
D[4:0]
Field
Type
Reset
Description
0
W
0h
Always write '0'
0h
Sets number of frames per multiframe
After reset, the default settings for frames per multiframe are:
10x : K = 16
20x : K = 8
For each mode, K must not be set to a lower value.
FRAMES PER MULTIFRAME
R/W
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9.6.1.19 Register 30 (offset = 30h) [reset = 40h]
Figure 106. Register 30
D7
D6
SUBCLASS
R/W-0h
D5
D4
0
W-0h
D3
0
W-0h
D2
0
W-0h
D1
0
W-0h
D0
0
W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 35. Register 30 Field Descriptions
Bit
Field
Type
Reset
Description
D[7:5]
SUBCLASS
R/W
0h
Sets JESD204B subclass. Note that the default value of these
bits after reset is 010, which makes subclass 2 the default class.
000 : Subclass 0. Backward compatibility with JESD204A.
001 : Subclass 1. Deterministic latency using the SYSREF
signal.
010 : Subclass 2. Deterministic latency using SYNC~ detection
(default subclass after reset).
D[4:0]
0
W
0h
Always write '0'
9.6.1.20 Register 36 (offset = 36h) [reset = 00h]
Figure 107. Register 36
D7
SYNC REQ
R/W-0h
D6
LMFC RESET MASK
R/W-0h
D5
0
W-0h
D4
0
W-0h
D3
D2
D1
OUTPUT CURRENT SEL
R/W-0h
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 36. Register 36 Field Descriptions
Bit
Field
Type
Reset
Description
D7
SYNC REQ
R/W
0h
Generates synchronization request
0 : Normal operation
1 : Generates sync request
D6
LMFC RESET MASK
R/W
0h
Mask LMFC reset coming to digital
0 : LMFC reset is not masked
1 : Ignores LMFC reset
0
W
0h
Always write '0'
0h
Changes JESD output buffer current
0000 : 16 mA
0001 : 15 mA
0010 : 14 mA
0011 : 13 mA
0100 : 20 mA
0101 : 19 mA
0110 : 18 mA
0111 : 17 mA
1000 : 8 mA
1001 : 7 mA
1010 : 6 mA
1011 : 5 mA
1100 : 12 mA
1101 : 11 mA
1110 : 10 mA
1111 : 9 mA
D[5:4]
D[3:0]
54
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9.6.1.21 Register 37 (offset = 37h) [reset = 00h]
Figure 108. Register 37
D7
D6
D5
LINK LAYER TESTMODE
R/W-0h
D4
LINK LAYER RPAT
R/W-0h
D3
0
W-0h
D2
D1
PULSE DET MODES
R/W-0h
D0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 37. Register 37 Field Descriptions
Bit
D[7:5]
Field
Type
LINK LAYER TESTMODE
R/W
Reset
Description
0h
Generates a pattern according to clause 5.3.3.8.2 of the
JESD204B document
000 : Normal ADC data
001 : D21.5 (high-frequency jitter pattern)
010 : K28.5 (mixed-frequency jitter pattern)
011 : Repeats initial lane alignment (generates a K28.5
character and repeats lane alignment sequences continuously)
100 : 12-octet RPAT jitter pattern
D4
LINK LAYER RPAT
R/W
0h
Changes the running disparity in modified RPAT pattern test
mode (only when link layer test mode = 100)
0 : Normal operation
1 : Changes disparity
D3
0
W
0h
Always write '0'
PULSE DET MODES
R/W
0h
Selects different detection modes for SYSREF (subclass 1) and
SYNC (subclass 2)
D[2:0]
D2
D1
D0
FUNCTIONALITY
0
Don’t care
0
Allows all pulses to reset input clock dividers
1
Don’t care
0
Do not allow reset of analog clock dividers
Don’t care
0 to 1
transition
1
Allows one pulse immediately after the 0 to 1 transition to reset the divider
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9.6.1.22 Register 38 (offset = 38h) [reset = 00h]
Figure 109. Register 38
D7
FORCE LMFC COUNT
R/W-0h
D6
D5
D4
LMFC COUNT INIT
R/W-0h
D3
D2
D1
D0
RELEASE ILANE SEQ
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 38. Register 38 Field Descriptions
Bit
Field
Type
Reset
Description
D7
FORCE LMFC COUNT
R/W
0h
Forces LMFC count
0 : Normal operation
1 : Enables using a different starting value for the LMFC counter
0h
SYSREF receives the digital block and resets the LMFC count to
'0'. K28.5 stops transmitting when the LMFC count reaches 31.
The initial value that the LMFC count resets to can be set using
LMFC COUNT INIT. In this manner, the Rx can be synchronized
early because the Rx gets the LANE ALIGNMENT SEQUENCE
early. The FORCE LMFC COUNT register bit must be enabled.
0h
Delays the generation of the lane alignment sequence by 0, 1, 2,
or 3 multiframes after the code group synchronization.
00 : 0
01 : 1
10 : 2
11 : 3
D[6:2]
D[1:0]
56
LMFC COUNT INIT
RELEASE ILANE SEQ
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R/W
R/W
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
In a typical application (such as a dual-channel digitizer) the ADS42JBx9 is connected to a field-programmable
gate array (FPGA) or application-specific integrated circuit (ASIC), as shown in Figure 110. A device clock and
SYSREF signal must be provided to the ADC. TI recommends that the device clock and SYSREF are source
synchronous (generated from a common source with matched trace lengths) if synchronizing multiple ADCs. An
example of a device that can be used to generate a source-synchronous device clock and SYSREF is the
LMK04828. The device clock frequency must be the same frequency as the desired sampling rate. The SYSREF
period is required to be an integer multiple of the period of the multi-frame clock. Consequently, the frequency of
SYSREF must be restricted to Equation 1
Device Clock Frequency / (n × K × F)
where:
•
•
•
n = 1, 2, 3 and so forth,
1< K < 32 (set by SPI register address 2Dh), and
F = 1, (two lanes per ADC mode), F = 2 (one lane per ADC mode).
(1)
A large enough K is recommended (greater than 16) to absorb the lane skews and avoid data transmission
errors across the JESD204B interface. The SYNC~ signal is used by the FPGA or ASIC to acknowledge the
correction reception of comma characters from the ADC during the JESD204B link initialization process. During
normal operation this signal must be logic 1 if there are no errors in the data transmission from the ADC to the
FPGA or ASIC.
10.2 Typical Application
Device Clock
Device Clock
SYSREF
SYSREF
Lanes
Ch A
JESD
204B
Baseband Processor
(FPGA, ASIC)
Ch B
SYNC~
ADS42JBxx
Figure 110. The ADS42JBx9 in a Dual-Channel Digitizer
10.2.1 Design Requirements
For this design example, use the parameters listed in Table 39 as the input parameters.
Table 39. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
fSAMPLE
245.76 MSPS
Input frequency (IF)
10 MHz (Figure 122), 170 MHz (Figure 123)
Signal-to-noise ratio (SNR)
> 72 dBc
Spurious-free dynamic range (SFDR)
> 80 dBc
Second-order harmonic distortion (HD2)
> 90 dBc
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10.2.2 Detailed Design Procedure
10.2.2.1 Analog Input
The analog input pins have analog buffers (running from the AVDD3V supply) that internally drive the differential
sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external
driving source (10-kΩ dc resistance and 4-pF input capacitance). The buffer helps isolate the external driving
source from the switching currents of the sampling circuit. This buffering makes driving the buffered inputs easier
than when compared to an ADC without the buffer.
The input common-mode is set internally using a 5-kΩ resistor from each input pin to VCM so the input signal
can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between VCM + 0.5 V and
VCM – 0.5 V, resulting in a 2-V PP differential input swing. When programmed for 2.5-V PP full-scale, each input
pin must swing symmetrically between VCM + 0.625 V and VCM – 0.625 V.
The input sampling circuit has a high 3-dB bandwidth that extends up to 900 MHz (measured with a 50-Ω source
driving a 50-Ω termination between INP and INM). The dynamic offset of the first-stage sub-ADC limits the
maximum analog input frequency to approximately 250 MHz (with a 2.5-VPP full-scale amplitude) and to
approximately 400 MHz (with a 2-VPP full-scale amplitude). This 3-dB bandwidth is different than the analog
bandwidth of 900 MHz, which is only an indicator of signal amplitude versus frequency.
10.2.2.1.1 Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This technique improves the commonmode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input
pin is recommended to damp out ringing caused by package parasitics.
Figure 111, Figure 112, and Figure 113 illustrate the differential impedance (ZIN = RIN || CIN) at the ADC input
pins. The presence of the analog input buffer results in an almost constant input capacitance up to 1 GHz.
INxP(1)
ZIN(2)
RIN
CIN
INxM
(1) X = A or B.
(2) ZIN = RIN || (1 / jωCIN).
Figure 111. ADC Equivalent Input Impedance
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5
Differential Capacitance, Cin (pF)
Differential Resistance, Rin (kΩ)
10
1
0.1
0.05
0
200
400
600
Frequency (MHz)
800
4
3
2
1
0
1000
0
200
G073
Figure 112. ADC Analog Input Resistance (RIN) Across
Frequency
400
600
Frequency (MHz)
800
1000
G074
Figure 113. ADC Analog Input Capacitance (CIN) Across
Frequency
10.2.2.1.2 Driving Circuit
An example driving circuit configuration is shown in Figure 114. To optimize even-harmonic performance at high
input frequencies (greater than the first Nyquist), the use of back-to-back transformers is recommended, as
shown in Figure 114. Note that the drive circuit is terminated by 50 Ω near the ADC side. The ac-coupling
capacitors allow the analog inputs to self-bias around the required common-mode voltage. An additional R-C-R
(39 Ω - 6.8 pF - 39 Ω) circuit placed near device pins helps further improve HD3.
0.1µF
0.1µF
5Q
INP
RINT
0.1µF
39 Ÿ
25 Ÿ
6.8 pF
25 Ÿ
RINT
39 Ÿ
INM
1:1
1:1
0.1µF
5Ÿ
Device
Figure 114. Drive Circuit for Input Frequencies up to 250 MHz
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and
good performance is obtained for high-frequency input signals. An additional termination resistor pair may be
required between the two transformers, as shown in Figure 114. The center point of this termination is connected
to ground to improve the balance between the P (positive) and M (negative) sides. The values of the terminations
between the transformers and on the secondary side must be chosen to obtain an effective 50 Ω (for a 50-Ω
source impedance). For high input frequencies (> 250 MHz), the R-C-R circuit can be removed as indicated in
Figure 115.
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0.1µF
0.1µF
5Q
INP
RINT
25 Ÿ
0.1µF
25 Ÿ
RINT
INM
1:1
5Ÿ
0.1µF
1:1
Device
Figure 115. Drive Circuit for Input Frequencies > 250 MHz
10.2.2.2 Clock Input
The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with
little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 1.4 V
using internal 5-kΩ resistors. The self-bias clock inputs of the ADS42JB69 and ADS42JB49 can be driven by the
transformer-coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown
in Figure 116, Figure 117, and Figure 118. Figure 119 details the internal clock buffer.
Note:
RT = termination resistor, if necessary.
0.1 mF
0.1 mF
Zo
CLKP
Differential
Sine-Wave
Clock Input
CLKP
RT
Typical LVDS
Clock Input
0.1 mF
100 W
CLKM
Device
0.1 mF
Zo
CLKM
Figure 116. Differential Sine-Wave Clock Driving
Circuit
Zo
Device
Figure 117. LVDS Clock Driving Circuit
0.1 mF
CLKP
150 W
Typical LVPECL
Clock Input
100 W
Zo
0.1 mF
CLKM
Device
150 W
Figure 118. LVPECL Clock Driving Circuit
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Clock Buffer
LPKG
2 nH
20 W
CLKP
CBOND
1 pF
5 kW
RESR
100 W
CEQ
CEQ
1.4 V
LPKG
2 nH
20 W
5 kW
CLKM
CBOND
1 pF
RESR
100 W
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 119. Internal Clock Buffer
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF
capacitor, as shown in Figure 120. However, for best performance the clock inputs must be driven differentially,
thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using
a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter.
There is no change in performance with a non-50% duty cycle clock input.
0.1 mF
CMOS
Clock Input
CLKP
0.1 mF
CLKM
Device
Figure 120. Single-Ended Clock Driving Circuit
10.2.2.2.1 SNR and Clock Jitter
The signal-to-noise ratio (SNR) of the ADC is limited by three different factors, as shown in Equation 2.
Quantization noise is typically not noticeable in pipeline converters and is 96 dBFS for a 16-bit ADC. Thermal
noise limits SNR at low input frequencies and clock jitter sets SNR for higher input frequencies.
SNRQuantization _ Noise
æ
SNR ADC [dBc] = -20 ´ log çç 10 20
è
2
2
2
ö æ
SNRThermalNoise ö æ
SNRJitter ö
+
10
+
10
÷÷ ç
÷ ç
÷
20
20
ø è
ø
ø è
SNR limitation is a result of sample clock jitter and can be calculated by Equation 3:
SNRJitter [dBc] = -20 ´ log(2p ´ fIN ´ tJitter)
(2)
(3)
The total clock jitter (TJitter) has three components: the internal aperture jitter (85 fS for the device) is set by the
noise of the clock input buffer, the external clock jitter, and the jitter from the analog input signal. TJitter can be
calculated by Equation 4:
TJitter =
(TJitter,Ext.Clock_Input)2 + (TAperture_ADC)2
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External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass
filters at the clock input while a faster clock slew rate improves ADC aperture jitter. The device has a 74.1-dBFS
thermal noise and an 85-fS internal aperture jitter. The SNR value depends on the amount of external jitter for
different input frequencies, as shown in Figure 121.
76
SNR (dBFS)
74
72
35 fs
70
50 fs
68
100 fs
150 fs
66
200 fs
64
10
100
1000
Fin (MHz)
Figure 121. SNR versus Input Frequency and External Clock Jitter
10.2.3 Application Curves
0
0
fIN = 10 MHz
SFDR = 97 dBc
SNR = 73.4 dBFS
SINAD = 73.3 dBFS
THD = 95 dBc
SFDR Non HD2, HD3
= 103 dBc
−40
−60
−80
−100
−120
−40
−60
−80
−100
0
25
50
75
Frequency (MHz)
100
Figure 122. FFT for 10-MHz Input Signal
62
fIN = 170 MHz
SFDR = 89 dBc
SNR = 72.8 dBFS
SINAD = 72.5 dBFS
THD = 88 dBc
SFDR Non HD2, HD3
= 100 dBc
−20
Amplitude (dBFS)
Amplitude (dBFS)
−20
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125
−120
0
25
G031
50
75
Frequency (MHz)
100
125
G032
Figure 123. FFT for 170-MHz Input Signal
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11 Power Supply Recommendations
Four different power supply rails are required for ADS42JBxx device family:
• A 3.3-V AVDD3V supply is used to supply power to the analog buffers.
• A 1.8-V AVDD supply is used to supply power to the analog core of the ADC.
• A 1.8-V DRVDD supply is used to supply power to the digital core of the ADC.
• A 1.8-V IOVDD supply is used to supply power to the output buffers.
TI recommends providing the 1.8-V digital and analog supplies from separate sources because of the switching
activities on the digital rail. Both IOVDD and DRVDD can be supplied from a common source and a ferrite bead
is recommended on each rail. An example power-supply scheme suitable for the ADS42JBx9 device family is
shown in Figure 124. In this example supply scheme, AVDD is provided from a dc-dc converter and a lowdropout (LDO) regulator to increase the efficiency of the implementation. Where cost and area rather than powersupply efficiency are the main design goals, AVDD can be provided using only the LDO.
3.3 V (330 mA)
AVDD3V
3.3 V
DC-DC Converter
2V
1.8 V (160 mA)
LDO
AVDD
1.8 V (252 mA)
DC-DC Converter
DRVDD
1.8 V (100 mA)
IOVDD
Figure 124. Example Power-Supply Scheme
12 Layout
12.1 Layout Guidelines
•
•
•
•
The length of the positive and negative traces of a differential pair must be matched to within 2 mils of each
other.
Each differential pair length must be matched within 10 mils of each other.
When the ADC is used on the same printed circuit board (PCB) with a digital intensive component (such as
an FPGA or ASIC), separate digital and analog ground planes must be used. Do not overlap these separate
ground planes to minimize undesired coupling.
Connect decoupling capacitors directly to ground and place these capacitors close to the ADC power pins
and the power-supply pins to filter high-frequency current transients directly to the ground plane, as shown in
Figure 125.
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Layout Guidelines (continued)
AVDD DRVDD
10 F
10 F
Place the decoupling capacitor close to
the power- supply pin.
10 F
10 F
Place the decoupling capacitor close to
the ADC power-supply pin.
Device
Figure 125. Recommended Placement of Power-Supply Decoupling Capacitors
•
•
•
64
Ground and power planes must be wide enough to keep the impedance very low. In a multilayer PCB, one
layer each must be dedicated to ground and power planes.
All high-speed SERDES traces must be routed straight with minimum bends. Where a bend is necessary,
avoid making very sharp right angle bends in the trace.
FR4 material can be used for the PCB core dielectric, up to the maximum 3.125 Gbps bit rate supported by
the ADS42JBx9 device family. Path loss can be compensated for by adjusting the drive strength from the
device using SPI register 36h.
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ADS42JB49, ADS42JB69
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SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
12.2 Layout Example
LMK04828
Power Supply
management
Channel B input
ADS42JBxx
Channel A input
High Speed Lanes
(route straight to FPGA)
Balun
Figure 126. ADS42JBx9 EVM Top Layer
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Product Folder Links: ADS42JB49 ADS42JB69
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Device Nomenclature
13.1.1.1 Definition of Specifications
AC Power-Supply Rejection Ratio (AC PSRR): AC PSRR is the measure of rejection of variations in the
supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant
change of the ADC output code (referred to the input), then:
DVOUT
PSRR = 20Log 10
(Expressed in dBc)
DVSUP
(5)
Analog Bandwidth: The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low-frequency value.
Aperture Delay: The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay is different across channels. The maximum variation is
specified as aperture delay variation (channel-to-channel).
Aperture Uncertainty (Jitter): The sample-to-sample variation in aperture delay.
Clock Pulse Width and Duty Cycle: The duty cycle of a clock signal is the ratio of the time the clock signal
remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically
expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Common-Mode Rejection Ratio (CMRR): CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins
and ΔVOUT is the resulting change of the ADC output code (referred to the input), then:
DVOUT
CMRR = 20Log10
(Expressed in dBc)
DVCM
(6)
Crosstalk (only for Multichannel ADCs): Crosstalk is a measure of the internal coupling of a signal from an
adjacent channel into the channel of interest. Crosstalk is specified separately for coupling from the
immediate neighboring channel (near-channel) and for coupling from channel across the package
(far-channel). Crosstalk is usually measured by applying a full-scale signal in the adjacent channel.
Crosstalk is the ratio of the power of the coupling signal (as measured at the output of the channel
of interest) to the power of the signal applied at the adjacent channel input. Crosstalk is typically
expressed in dBc.
DC Power-Supply Rejection Ratio (DC PSRR): DC PSSR is the ratio of the change in offset error to a change
in analog supply voltage. The dc PSRR is typically given in units of mV/V.
Differential Nonlinearity (DNL): An ideal ADC exhibits code transitions at analog input values spaced exactly 1
LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of
LSBs.
Effective Number of Bits (ENOB): ENOB is a measure of the converter performance as compared to the
theoretical limit based on quantization noise.
ENOB =
SINAD - 1.76
6.02
(7)
Gain Error: Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range. Gain error has two components:
error as a result of reference inaccuracy (EGREF) and error as a result of the channel (EGCHAN). Both
errors are specified independently as EGREF and EGCHAN.
To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN.
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5 / 100) x FSideal to (1
+ 0.5 / 100) × FSideal.
66
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SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
Device Support (continued)
Integral Nonlinearity (INL): The INL is the deviation of the ADC transfer function from a best fit line determined
by a least squares curve fit of that transfer function, measured in units of LSBs.
Maximum Conversion Rate: The maximum sampling rate at which specified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate: The minimum sampling rate at which the ADC functions.
Offset Error: The offset error is the difference, given in number of LSBs, between the ADC actual average idle
channel output code and the ideal average idle channel output code. This quantity is often mapped
into millivolts.
Signal-to-Noise and Distortion (SINAD): SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
SNR = 10Log10
PS
PN
SINAD = 10Log10
(8)
PS
PN + PD
(9)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the
fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the
fundamental is extrapolated to the converter full-scale range.
Signal-to-Noise Ratio (SNR): SNR is the ratio of the power of the fundamental (PS) to the noise floor power
(PN), excluding the power at dc and the first nine harmonics.
SNR is either given in units of dBc (dB to carrier) when the absolute power of the
fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the
fundamental is extrapolated to the converter full-scale range.
Spurious-Free Dynamic Range (SFDR): The ratio of the power of the fundamental to the highest other spectral
component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Temperature Drift: The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. Temperature drift is calculated by
dividing the maximum deviation of the parameter across the TMIN to TMAX range by the difference
TMAX – TMIN.
Total Harmonic Distortion (THD): THD is the ratio of the power of the fundamental (PS) to the power of the first
nine harmonics (PD).
THD = 10Log10
PS
PN
(10)
THD is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion (IMD3): IMD3 is the ratio of the power of the fundamental (at
frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or
2f2 – f1. IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the
fundamental is used as the reference, or dBFS (dB to full-scale) when the power of the
fundamental is extrapolated to the converter full-scale range.
Voltage Overload Recovery: The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6 dB
positive and negative overload. The deviation of the first few samples after the overload (from the
expected values) is noted.
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Product Folder Links: ADS42JB49 ADS42JB69
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SLAS900F – OCTOBER 2012 – REVISED DECEMBER 2014
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13.2 Documentation Support
13.2.1 Related Documentation
LMK04828 Data Sheet, SNAS605
13.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 40. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ADS42JB49
Click here
Click here
Click here
Click here
Click here
ADS42JB69
Click here
Click here
Click here
Click here
Click here
13.4 Trademarks
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
68
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Product Folder Links: ADS42JB49 ADS42JB69
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS42JB49IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-3-260C-168 HR
-40 to 85
AZ42JB49
ADS42JB49IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-3-260C-168 HR
-40 to 85
AZ42JB49
ADS42JB69IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ42JB69
ADS42JB69IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ42JB69
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2018
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADS42JB49IRGCR
VQFN
RGC
64
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2000
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS42JB49IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS42JB69IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS42JB69IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-May-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS42JB49IRGCR
VQFN
RGC
64
2000
350.0
350.0
43.0
ADS42JB49IRGCT
VQFN
RGC
64
250
213.0
191.0
55.0
ADS42JB69IRGCR
VQFN
RGC
64
2000
350.0
350.0
43.0
ADS42JB69IRGCT
VQFN
RGC
64
250
213.0
191.0
55.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGC 64
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
9 x 9, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
www.ti.com
PACKAGE OUTLINE
RGC0064H
VQFN - 1 mm max height
SCALE 1.500
PLASTIC QUAD FLATPACK - NO LEAD
A
9.15
8.85
B
PIN 1 INDEX AREA
9.15
8.85
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2X 7.5
EXPOSED
THERMAL PAD
SYMM
(0.2) TYP
17
32
16
33
65
SYMM
2X 7.5
7.4 0.1
60X
0.5
1
48
49
64
PIN 1 ID
64X
0.5
0.3
64X
0.30
0.18
0.1
0.05
C A B
4219011/A 05/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGC0064H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 7.4)
SEE SOLDER MASK
DETAIL
SYMM
64X (0.6)
49
64
64X (0.24)
1
48
60X (0.5)
(3.45) TYP
(R0.05) TYP
(1.16) TYP
65
SYMM
(8.8)
( 0.2) TYP
VIA
33
16
32
17
(1.16) TYP
(3.45) TYP
(8.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK DEFINED
SOLDER MASK DETAILS
4219011/A 05/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGC0064H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
64X (0.6)
64X (0.24)
64
49
1
48
60X (0.5)
(R0.05) TYP
(1.16) TYP
65
SYMM
(8.8)
(0.58)
36X ( 0.96)
33
16
17
32
(0.58)
(1.16)
TYP
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
61% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219011/A 05/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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