Texas Instruments | ADSxx53 Dual, High-Speed, 16-, 14-, and 12-Bit, Simultaneous-Sampling, Analog-to-Digital Converters (Rev. B) | Datasheet | Texas Instruments ADSxx53 Dual, High-Speed, 16-, 14-, and 12-Bit, Simultaneous-Sampling, Analog-to-Digital Converters (Rev. B) Datasheet

Texas Instruments ADSxx53 Dual, High-Speed, 16-, 14-, and 12-Bit, Simultaneous-Sampling, Analog-to-Digital Converters (Rev. B) Datasheet
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ADS8353, ADS7853, ADS7253
SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014
ADSxx53 Dual, High-Speed, 16-, 14-, and 12-Bit,
Simultaneous-Sampling, Analog-to-Digital Converters
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
16-, 14-, and 12-Bit, Pin-Compatible Family
Simultaneous Sampling of Two Channels
Supports Single-Ended and Pseudo-Differential
Inputs
High Speed:
– ADS8353: 16 Bits, 600 kSPS
– ADS7853: 14 Bits, 1 MSPS
– ADS7253: 12 Bits, 1 MSPS
Excellent DC Performance:
– ADS8353:
– 16-Bit NMC DNL, ±2.5-LSB Max INL
– ADS7853:
– 14-Bit NMC DNL, ±2-LSB Max INL
– ADS7253:
– 12-Bit NMC DNL, ±1-LSB Max INL
Excellent AC Performance:
– ADS8353:
– 89-dB SNR, –100-dB THD
– ADS7853:
– 82-dB SNR, –90-dB THD
– ADS7253:
– 72-dB SNR, –90-dB THD
Dual, Programmable, and Buffered
2.5-V Internal Reference
Fully-Specified Over the Extended Industrial
Temperature Range: –40°C to 125°C
Small Footprint:
WQFN-16 (3-mm × 3-mm) and TSSOP-16
•
•
•
•
•
Motor Control:
Position Measurement Using Encoders
Optical Networking: EDFA Gain Control Loops
Protection Relays
Power Quality Measurement
Three-Phase Power Controls
Programmable Logic Controllers
3 Description
The ADS8353, ADS7853, and ADS7253 belong to a
family
of
pin-compatible,
dual,
high-speed,
simultaneous-sampling, analog-to-digital converters
(ADCs) that support single-ended and pseudodifferential analog inputs.
Each device includes two individually programmable
reference sources that can be used for system-level
gain calibration. Also, a flexible serial interface that
can operate over a wide power-supply range enables
easy communication with a large variety of host
controllers. Power consumption for a given
throughput can be optimized by using the two lowpower modes supported by the device. All devices
are fully specified over the extended industrial
temperature range (–40°C to 125°C) and are
available in pin-compatible, WQFN-16 (3-mm ×
3-mm) and TSSOP-16 packages.
Device Information(1)
PART NUMBER
ADSxx53
PACKAGE
BODY SIZE (NOM)
TSSOP (16)
5.00 mm × 4.40 mm
WQFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Diagram
AVDD
VCM
AVDD
OPA836
+
+
1k 4
+
AVDD
-
AINP
VIN+
1.8 nF
1k ADSxx53
AINM
GND
4
VDC
INPUT DRIVER
ADS8353 : 16-bit, 600 kSPS
ADS7853 : 14-bit, 1 MSPS
ADS7253 : 12-bit, 1 MSPS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS8353, ADS7853, ADS7253
SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configurations and Functions .......................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
1
1
1
2
3
4
5
Absolute Maximum Ratings ..................................... 5
Handling Ratings....................................................... 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics: ADS8353 ......................... 6
Electrical Characteristics: ADS7853 ......................... 7
Electrical Characteristics: ADS7253 ......................... 8
Electrical Characteristics: All Devices....................... 9
Timing Requirements: Interface Mode.................... 11
Timing Characteristics: Serial Interface ................ 11
Typical Characteristics: ADS8353 ........................ 13
Typical Characteristics: ADS7853 ........................ 17
Typical Characteristics: ADS7253 ........................ 22
Typical Characteristics: Common to ADS8353,
ADS7853, and ADS7253 ......................................... 27
8
Detailed Description ............................................ 28
8.1
8.2
8.3
8.4
8.5
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Register Maps and Serial Interface.........................
28
28
29
35
35
Application and Implementation ........................ 49
9.1 Application Information............................................ 49
9.2 Typical Applications ................................................ 51
10 Power-Supply Recommendations ..................... 59
11 Layout................................................................... 60
11.1 Layout Guidelines ................................................. 60
11.2 Layout Example .................................................... 60
12 Device and Documentation Support ................. 61
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Related Documentation.........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
61
61
61
61
61
13 Mechanical, Packaging, and Orderable
Information ........................................................... 61
4 Revision History
Changes from Revision A (July 2014) to Revision B
Page
•
Made changes to the ADS8353 preview device and moved to Production Data status ........................................................ 1
•
Changed document status from Mixed Status to Production Data ........................................................................................ 1
•
Corrected cross-reference for Figure 99 .............................................................................................................................. 48
Changes from Original (October 2013) to Revision A
•
2
Page
Made changes to product preview data sheet........................................................................................................................ 1
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Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: ADS8353 ADS7853 ADS7253
ADS8353, ADS7853, ADS7253
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SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014
5 Device Comparison Table
PRODUCT
RESOLUTION
(Bits)
INPUT CONFIGURATION
NMC (Bits)
INL (LSB)
SNR (dB)
ADS8354
16
Fully-differential
16
±2.5
93 (typ)
ADS7854
14
Fully-differential
14
±1.5
88 (typ)
ADS7254
12
Fully-differential
12
±1
74 (typ)
ADS8353
16
Single-ended and
pseudo-differential
16
±2.5
89 (typ)
ADS7853
14
Single-ended and
pseudo-differential
14
±2
84 (typ)
ADS7253
12
Single-ended and
pseudo-differential
12
±1
73.5 (typ)
Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: ADS8353 ADS7853 ADS7253
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ADS8353, ADS7853, ADS7253
SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014
www.ti.com
6 Pin Configurations and Functions
RTE Package
WQFN-16
(Top View)
AINM_A
AINP_A
AVDD
GND
16
15
14
13
PW Package
TSSOP-16
(Top View)
REFIO_A
1
12
SDO_B
REFGND_A
2
11
SDO_A
REFGND_B
3
10
SCLK
REFIO_B
4
9
CS
AINP_A
1
16
AVDD
AINM_A
2
15
GND
REFIO_A
3
14
SDO_B
REFGND_A
4
13
SDO_A
REFGND_B
5
12
SCLK
REFIO_B
6
11
CS
AINM_B
7
10
SDI
AINP_B
8
9
DVDD
8
SDI
7
DVDD
6
AINP_B
AINM_B
5
Thermal Pad
Pin Functions
PIN
NO.
NAME
TSSOP
WQFN
I/O
AINM_A
2
16
Analog input
Negative analog input, channel A
AINM_B
7
5
Analog input
Negative analog input, channel B
AINP_A
1
15
Analog input
Positive analog input, channel A
Positive analog input, channel B
AINP_B
8
6
Analog input
AVDD
16
14
Supply
CS
11
9
Digital input
DESCRIPTION
Supply voltage for ADC operation
Chip-select signal; active low
DVDD
9
7
Digital I/O supply
GND
15
13
Supply
Digital ground
REFGND_A
4
2
Supply
Reference ground potential A
REFGND_B
5
3
Supply
Reference ground potential B
REFIO_A
3
1
Analog input/output
Reference voltage input/output, channel A
REFIO_B
6
4
Analog input/output
Reference voltage input/output, channel B
SCLK
12
10
Digital input
Clock for serial communication
SDI
10
8
Digital input
Data input for serial communication
SDO_A
13
11
Digital output
Data output for serial communication, channel A and channel B
SDO_B
14
12
Digital output
Data output for serial communication, channel B
Thermal pad
—
Thermal
pad
Supply
4
Submit Documentation Feedback
Digital I/O supply
Exposed thermal pad (only for WQFN). TI recommends
connecting this pin to the printed circuit board (PCB) ground.
Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: ADS8353 ADS7853 ADS7253
ADS8353, ADS7853, ADS7253
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SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
–0.3
6
V
REFGND_x – 0.3
AVDD + 0.3
V
GND – 0.3
DVDD + 0.3
V
AVDD to REFGND_x or DVDD to GND
Analog (AINP_x and AINM_x) and reference input (REFIO_x) voltage with
respect to REFGND_x
Digital input voltage with respect to GND
Ground voltage difference |REFGND_x-GND|
0.3
V
Input current to any pin except supply pins
±10
mA
Maximum virtual junction temperature, TJ
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
–2000
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
–500
500
Tstg
Storage temperature range
V(ESD)
Electrostatic discharge
(1)
(2)
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
AVDD
Analog supply voltage
DVDD
Digital supply voltage
NOM
MAX
UNIT
5
V
3.3
V
7.4 Thermal Information
ADS8353, ADS7853, ADS7253
THERMAL METRIC (1)
RTE (WQFN)
PW (TSSOP)
16 PINS
16 PINS
RθJA
Junction-to-ambient thermal resistance
33.3
86.9
RθJC(top)
Junction-to-case (top) thermal resistance
29.5
21
RθJB
Junction-to-board thermal resistance
7.3
39.1
ψJT
Junction-to-top characterization parameter
0.2
0.8
ψJB
Junction-to-board characterization parameter
7.4
38.4
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.9
N/A
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2013–2014, Texas Instruments Incorporated
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7.5 Electrical Characteristics: ADS8353
All minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF =
2.5 V (internal), and fDATA = 600 kSPS, unless otherwise noted.
Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
DC ACCURACY
16
Bits
(1)
NMC
No missing codes
32-clock mode
16
INL
Integral nonlinearity
32-clock mode
–2.5
±1
2.5
LSB
DNL
Differential nonlinearity
32-clock mode
–0.99
±0.6
2
LSB
EIO
Input offset error
–1
±0.5
1
mV
–1
±0.5
1
EIO match
ADC_A to ADC_B
Bits
Input offset thermal drift
EG
Gain error
Referenced to the voltage at REFIO_x
–0.1
±0.05
0.1
EG match
ADC_A to ADC_B
–0.1
±0.05
0.1
Gain error thermal drift
Referenced to the voltage at REFIO_x
dEG/dT
mV
μV/°C
dEIO/dT
1
%FS
%FS
1
ppm/°C
83
dB
VREF = 2.5 V,
2 × VREF input range, 32-clock mode
83.9
dB
VREF = 5 V (external),
VREF input range, 32-clock mode
88.7
dB
83
dB
VREF = 2.5 V,
2 × VREF input range, 32-clock mode
84
dB
VREF = 5 V (external),
VREF input range, 32-clock mode
89
dB
VREF = 2.5 V,
VREF input range, 32-clock mode
–100
dB
VREF = 2.5 V,
2 × VREF input range, 32-clock mode
–100
dB
VREF = 5 V (external),
VREF input range, 32-clock mode
–100
dB
VREF = 2.5 V,
VREF input range, 32-clock mode
105
dB
VREF = 2.5 V,
2 × VREF input range, 32-clock mode
105
dB
VREF = 5 V (external),
VREF input range, 32-clock mode
105
dB
AC ACCURACY (2)
VREF = 2.5 V,
VREF input range, 32-clock mode
SINAD
Signal-to-noise + distortion
80.2
VREF = 2.5 V,
VREF input range, 32-clock mode
SNR
THD
SFDR
(1)
(2)
6
Signal-to-noise ratio
Total harmonic distortion
Spurious-free dynamic range
80.5
LSB = least significant bit.
All ac parameters are tested at –0.5 dBFS and a 2-kHz input frequency.
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SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014
7.6 Electrical Characteristics: ADS7853
All minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF =
2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
DC ACCURACY
14
Bits
32-clock mode
14
Bits
16-clock mode
13
Bits
(1)
NMC
No missing codes
INL
Integral nonlinearity
DNL
Differential nonlinearity
EIO
Input offset error
EIO match
32-clock mode
–2
±0.7
2
LSB
16-clock mode
–2.5
±1
2.5
LSB
32-clock mode
–0.99
±0.5
1
LSB
16-clock mode
–1
±0.9
2
LSB
–1
±0.5
1
mV
–1
±0.5
1
ADC_A to ADC_B
Input offset thermal drift
EG
Gain error
Referenced to the voltage at REFIO_x
–0.1
±0.05
0.1
EG match
ADC_A to ADC_B
–0.1
±0.05
0.1
Gain error thermal drift
Referenced to the voltage at REFIO_x
dEG/dT
mV
μV/°C
dEIO/dT
±1
±1
%FS
%FS
ppm/°C
AC ACCURACY (2)
SINAD
Signal-to-noise + distortion
VREF = 2.5 V,
VREF input range
32-clock mode
80.9
dB
16-clock mode
80.3
dB
VREF = 2.5 V,
2 × VREF input range
32-clock mode
81.4
dB
16-clock mode
80.8
dB
= 5 V (external), 32-clock mode
input range
16-clock mode
83.9
dB
82.9
dB
VREF
VREF
SNR
THD
SFDR
Signal-to-noise ratio
Total harmonic distortion
Spurious-free dynamic range
VREF = 2.5 V,
VREF input range
32-clock mode
81
dB
16-clock mode
80.5
dB
VREF = 2.5 V,
2 × VREF input range
32-clock mode
81.5
dB
16-clock mode
81
dB
84
dB
83.5
dB
VREF = 2.5 V,
VREF input range
32-clock mode
–100
dB
16-clock mode
–93
dB
VREF = 2.5 V,
2 × VREF input range
32-clock mode
–98
dB
16-clock mode
–94
dB
VREF = 5 V (external), 32-clock mode
VREF input range
16-clock mode
–102
dB
–92
dB
VREF = 2.5 V,
VREF input range
32-clock mode
100
dB
16-clock mode
95
dB
VREF = 2.5 V,
2 × VREF input range
32-clock mode
100
dB
16-clock mode
95
dB
= 5 V (external), 32-clock mode
input range
16-clock mode
102
dB
95
dB
–100
dB
(1)
(2)
fIN = 15 kHz at 10 %FS,
fNOISE = 25 kHz at FS
ADC-to-ADC isolation
78.5
VREF = 5 V (external), 32-clock mode
VREF input range
16-clock mode
VREF
VREF
ISOXT
78.4
LSB = least significant bit.
All ac parameters are tested at –0.5 dBFS and a 2-kHz input frequency.
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7.7 Electrical Characteristics: ADS7253
All minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF =
2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
DC ACCURACY
12
Bits
(1)
NMC
No missing codes
12
INL
Integral nonlinearity
–1
±0.3
1
LSB
DNL
Differential nonlinearity
–0.99
±0.3
1
LSB
EIO
Input offset error
–2
±0.5
2
mV
–2
±0.5
2
EIO match
ADC_A to ADC_B
Bits
Input offset thermal drift
EG
Gain error
Referenced to the voltage at REFIO_x
–0.2
±0.05
0.2
EG match
ADC_A to ADC_B
–0.2
±0.05
0.2
Gain error thermal drift
Referenced to the voltage at REFIO_x
dEG/dT
±1
±1
mV
μV/°C
dEIO/dT
%FS
%FS
ppm/°C
AC ACCURACY (2)
VREF = 2.5 V,
VREF input range
SINAD
Signal-to-noise + distortion
71
72.9
dB
VREF = 2.5 V,
2 × VREF input range
72.9
dB
VREF = 5 V (external),
VREF input range
73.4
dB
73
dB
73
dB
VREF = 5 V (external),
VREF input range
73.5
dB
VREF = 2.5 V,
VREF input range
–90
dB
VREF = 2.5 V,
2 × VREF input range
–90
dB
VREF = 5 V (external),
VREF input range
–90
dB
VREF = 2.5 V,
VREF input range
93.5
dB
VREF = 2.5 V,
2 × VREF input range
93.5
dB
VREF = 5 V (external),
VREF input range
93.5
dB
fIN = 15 kHz at 10 %FS,
fNOISE = 25 kHz at FS
–80
dB
VREF = 2.5 V,
VREF input range
SNR
THD
SFDR
ISOXT
(1)
(2)
8
VREF = 2.5 V,
2 × VREF input range
Signal-to-noise ratio
Total harmonic distortion
Spurious-free dynamic range
ADC-to-ADC isolation
71.5
LSB = least significant bit.
All ac parameters are tested at –0.5 dBFS and a 2-kHz input frequency.
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SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014
7.8 Electrical Characteristics: All Devices
All minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF =
2.5 V, and fDATA = maximum, unless otherwise noted.
Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
VREF
V
–VREF / 2
VREF / 2
V
0
2 × VREF
V
–VREF
VREF
V
ANALOG INPUT
VREF
range
FSR
Full-scale input range
(AINP_x – AINM_x)
(1)
2 × VREF
range
VINP
Absolute input voltage
(AINP_x to REFGND)
VINM
Ci
Input capacitance
Ilkg(i)
Input leakage current
Pseudo-differential input,
AINM_x = +VREF / 2
Single-ended input,
AINM_x = GND,
AVDD ≥ 2 × VREF
Pseudo-differential input,
AINM_x = +VREF,
AVDD ≥ 2 × VREF
VREF range
0
VREF
V
2 × VREF range, AVDD ≥ 2 × VREF
0
2 × VREF
V
VREF
range
Absolute input voltage
(AINM_x to REFGND)
Single-ended input,
AINM_x = GND
2 × VREF
range
Single-ended input
Pseudo-differential input
–0.1
VREF / 2 – 0.1
Single-ended input,
AVDD ≥ 2 × VREF
Pseudo-differential input,
AVDD ≥ 2 × VREF
VREF / 2
–0.1
VREF – 0.1
In sample mode
VREF
0.1
V
VREF / 2 + 0.1
V
0.1
V
VREF + 0.1
V
40
In hold mode
pF
4
pF
0.1
µA
INTERNAL VOLTAGE REFERENCE
VREFOUT
Reference output voltage
REFDAC_x = 1FFh (default),
at 25°C
VREF-match
VREF_A to VREF_B matching
REFDAC_x = 1FFh (default),
at 25°C
2.495
REFDAC_x resolution (2)
2.500
2.505
V
±1
mV
1.1
mV
dVREFOUT/dT
Reference voltage
temperature drift
REFDAC_x = 1FFh (default)
±10
ppm/°C
dVREFOUT/dt
Long-term stability
1000 hours
150
ppm
RO
Internal reference output
impedance
1
Ω
IREFOUT
Reference output dc
current
2
mA
CREFOUT
Recommended output
capacitor
10
µF
tREFON
Reference output settling
time
8
ms
For CREF = 10 μF
VOLTAGE REFERENCE INPUT
VREF
Reference voltage (input)
IREF
Average Reference input
current
CREF
External ceramic
reference capacitance
Ilkg(dc)
DC leakage current
(1)
(2)
VREF range
2.4
2.5
AVDD
V
2 × VREF range
2.4
2.5
AVDD / 2
V
Per ADC
300
μA
10
μF
±0.1
μA
Ideal input span, does not include gain or offset error.
Refer to the Reference section for more details.
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Electrical Characteristics: All Devices (continued)
All minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF =
2.5 V, and fDATA = maximum, unless otherwise noted.
Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SAMPLING DYNAMICS
tA
Aperture delay
tA match
tAJIT
ADC_A to ADC_B
Aperture jitter
8
ns
40
ps
50
ps
DIGITAL INPUTS (3)
VIH
High-level input voltage
VIL
Low-level input voltage
DVDD > 2.3 V
0.7 DVDD
DVDD + 0.3
V
DVDD ≤ 2.3 V
0.8 DVDD
DVDD + 0.3
V
DVDD > 2.3 V
–0.3
0.3 DVDD
V
DVDD ≤ 2.3 V
–0.3
Input current
0.2 DVDD
±10
V
nA
DIGITAL OUTPUTS (3)
VOH
High-level output voltage
IOH = 500-µA source
VOL
Low-level output voltage
IOH = 500-µA sink
0.8 DVDD
DVDD
V
0
0.2 DVDD
V
POWER SUPPLY
AVDD
Analog supply voltage
(AVDD to AGND)
±VREF
range
±2 × VREF
range
DVDD
AIDD
DIDD
PD
(3)
(4)
10
Internal reference
4.5
5.0
5.5
V
External reference:
VEXT_REF < 4.5 V
4.5
5.0
5.5
V
External reference:
VEXT_REF > 4.5 V
VEXT_REF
5.0
5.5
V
5.0
5.0
5.5
V
2 × VREF_EXT
5.0
5.5
V
5.5
V
10
mA
Internal reference
External reference
Digital supply voltage
(DVDD to AGND)
Analog supply current
Digital supply current
Power dissipation
(normal operation)
1.65
AVDD = 5 V, fastest throughput
internal reference
8.5
AVDD = 5 V, fastest throughput
external reference (4)
7.5
AVDD = 5 V, no conversion
internal reference
5.5
AVDD = 5 V, no conversion
external reference (4)
4.5
mA
AVDD = 5 V, STANDBY mode
Internal Reference
2.5
mA
AVDD = 5 V, STANDBY mode
external reference (4)
1
mA
mA
7
μA
Power-down mode
10
DVDD = 3.3 V, CLOAD = 10 pF,
fastest throughput
0.5
mA
1
mA
DVDD = 5 V, CLOAD = 10 pF
fastest throughput
AVDD = 5V, fastest throughput,
internal reference
42.5
50
mA
50
mW
Specified by design; not production tested.
With internal reference powered down, CFR.B6 = 0.
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7.9 Timing Requirements: Interface Mode (1)
PARAMETER
ASSOCIATED FIGURES
tCLK
CLOCK period
Figure 1, Figure 91, Figure 92, Figure 93, Figure 94
tACQ
Acquisition time
Figure 91, Figure 92, Figure 93, Figure 94
tCONV
Conversion time
Figure 91, Figure 92, Figure 93, Figure 94
(1)
These parameters are specific to the interface mode of operation. Refer to the Conversion Data Read section for more details.
7.10 Timing Characteristics: Serial Interface
PARAMETER
TEST CONDITIONS
ASSOCIATED FIGURES
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
tPH_CK
CLOCK high time
tPL_CK
CLOCK low time
fCLK
CLOCK frequency
tPH_CS
CS high time
0.4
Figure 1
Figure 1
ADS8353
tPH_CS_SHRT
CS high time after frame abort
ADS7853
Figure 99
ADS7253
tSU_CSCK
Setup time: CS falling edge to
SCLK falling edge
tD_CKCS
Delay time: Last SCLK falling edge
to CS rising edge
tSU_CKDI
Setup time: DIN data valid to SCLK
falling edge
tHT_CKDI
Hold time: SCLK falling edge to
(previous) data valid on DIN
tPU_STDBY
Power-up time from STANDBY
mode
tPU_SPD
Power-up time from SPD mode
0.4
0.6
tCLK
0.6
tCLK
1 / tCLK
MHz
40
ns
150
ns
100
ns
70
ns
15
ns
15
ns
5
ns
5
ns
1
µs
3
ms
1
ms
1.666
µs
1
µs
Figure 1
Figure 96
With internal reference
With external reference
Figure 98
TIMING SPECIFICATIONS
ADS8353
tTHROUGHPUT
ADS7853
Throughput time
ADS7253
32-CLK mode
32-CLK mode
Figure 91, Figure 92
16-CLK mode
Figure 93, Figure 94
1
µs
32-CLK mode
Figure 91, Figure 92
1
µs
16-CLK mode
Figure 93, Figure 94
1
µs
Figure 91, Figure 92,
Figure 93, Figure 94
fTHROUGHPUT
Throughput
tDV_CSDO
Delay time: CS falling edge to data
enable
tDZ_CSDO
Delay time: CS rising edge to data
going to 3-state
tD_CKDO
Delay time: SCLK falling edge to
next data valid
Figure 1
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1 / tTHROUGHPUT
kSPS
12
ns
12
ns
20
ns
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Figure 1 shows the details of the serial interface between the device and the digital host controller.
CS
CS
tSU_CSCK
SCLK
1
2
1
SCLK
2
12
13
14
tSU_CKDI
tDV_CSDO
SDO
B14
B15
SDI
15
16
tHT_CKDI
B4
B3
B2
B1
Sample
N+1
Sample
N
tPH_CS
CS
SCLK
1
2
N9
tSCLK
tPL_CK
tPH_CK
N8
N7
N6
N5
N4
N3
N2
tD_CKDO
tD_CKCS
N1
N
tDZ_CSDO
SDOADS8353/4
V
V
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDOADS7853/4
V
V
D7
D6
D5
D4
D3
D2
D1
D0
0
0
SDOADS7253/4
V
V
D5
D4
D3
D2
D1
D0
0
0
0
0
Figure 1. Serial Interface Timing Diagram
12
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7.11 Typical Characteristics: ADS8353
0
0
±20
±20
±40
±40
Signal Power (dB)
Signal Power (dB)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS, unless otherwise noted.
±60
±80
±100
±120
±140
±60
±80
±100
±120
±140
±160
±160
±180
±180
±200
±200
0
60
120
180
240
300
Input Frequency (kHz)
fIN = 2 kHz
0
60
SNR = 84.2 dB
THD = -101.3 dB
fIN = 100 kHz
Signal-to-Noise and Distortion Ratio (dB)
Signal-to-Noise Ratio (dB)
85
84
83
82
81
80
26
59
92
85
84
83
82
81
80
±40
±7
26
59
Free-Air Temperature (oC)
92
125
C204
fIN = 2 kHz
Figure 4. SNR vs Temperature
Figure 5. SINAD vs Temperature
Signal-to-Noise and Distortion Ratio (dB)
90
89
Signal-to-Noise Ratio (dB)
C202
THD = -99.1 dB
86
C203
fIN = 2 kHz
88
87
86
85
84
83
82
2.5
300
87
125
Free-Air Temperature (oC)
2
240
Figure 3. Typical FFT
86
±7
180
SNR = 80.8 dB
Figure 2. Typical FFT
87
±40
120
Input Frequency (kHz)
C201
3
3.5
4
4.5
Reference Voltage (V)
fIN = 2 kHz
5
5.5
90
89
88
87
86
85
84
83
82
2
2.5
3
3.5
4
4.5
5
Reference Voltage (V)
C205
5.5
C206
fIN = 2 kHz
Figure 6. SNR vs Reference Voltage
Figure 7. SINAD vs Reference Voltage
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Typical Characteristics: ADS8353 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS, unless otherwise noted.
Signal-to-Noise and Distortion Ratio (dB)
85
Signal-to-Noise Ratio (dB)
84
83
82
81
80
79
78
77
76
75
0
60
120
180
240
Input Frequency (kHz)
85
83
81
79
77
75
300
0
180
240
300
C208
VREF = 5 V
Figure 8. SNR vs Input Frequency
Figure 9. SINAD vs Input Frequency
±70
Total Harmonic Distortion (dB)
±70
Total Harmonic Distortion (dB)
120
Input Frequency (kHz)
VREF = 5 V
±80
±90
±100
±110
±120
±130
±80
±90
±100
±110
±120
±130
±40
±7
26
59
92
Free-Air Temperature (oC)
125
2
2.5
3
3.5
4
4.5
5
Reference Voltage (V)
C209
fIN = 2 kHz
5.5
C211
fIN = 2 kHz
Figure 10. THD vs Temperature
Figure 11. THD vs Reference Voltage
±70
10
9.5
±80
IAVDD Dynamic (mA)
Total Harmonic Distortion (dB)
60
C207
±90
±100
±110
±120
9
8.5
8
7.5
7
6.5
±130
6
0
60
120
180
240
Input Frequency (kHz)
300
±40
±7
26
59
Free-Air Temperature (oC)
C213
92
125
C224
VREF = 5 V
Figure 12. THD vs Input Frequency
14
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Figure 13. Analog Supply Current vs Temperature
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Typical Characteristics: ADS8353 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS, unless otherwise noted.
40000
10
30000
8
Number of Hits
IAVDD Dynamnic (mA)
9
7
6
5
20000
10000
4
3
0
2
0
4
8
12
16
SCLK Frequency (MHz)
32771
20
32772
750
75
500
50
Gain Error (m%)
100
0
±250
32776
32777
C215
VIN-DIFF = 0 V
25
0
±25
±500
±50
±750
±75
±1000
32775
Figure 15. DC Histogram
Figure 14. Analog Supply Current vs SCLK Frequency
1000
250
32774
Code
65536 data points
Offset Error (uV)
32773
C225
±100
±40
±7
26
59
92
Free-Air Temperature (oC)
125
±40
26
±7
59
92
Free-Air Temperature (oC)
C216
Figure 16. Offset Error vs Temperature
125
C217
Figure 17. Gain Error vs Temperature
2
2.5
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
2
1.5
1
0.5
0
-0.5
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-1
-2.5
0
65535
Code
0
65535
Code
C218
Figure 18. Typical DNL
C219
Figure 19. Typical INL
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Typical Characteristics: ADS8353 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS, unless otherwise noted.
2
2.5
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
2
1.5
1
Maximum
0.5
0
-0.5
Minimum
1.5
Maximum
1
0.5
0
-0.5
-1
Minimum
-1.5
-2
-1
-2.5
±40
26
±7
59
92
125
Free-Air Temperature (oC)
±40
26
±7
59
92
125
Free-Air Temperature (oC)
C220
Figure 20. DNL vs Temperature
C221
Figure 21. INL vs Temperature
2
2.5
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
2
1.5
1
Maximum
0.5
0
-0.5
Minimum
Maximum
1
0.5
0
-0.5
Minimum
-1
-1.5
-2
-1
-2.5
2
2.5
3
3.5
4
4.5
5
Reference Voltage (V)
Figure 22. DNL vs Reference Voltage
16
1.5
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5.5
2
2.5
3
3.5
4
4.5
5
Reference Voltage (V)
C222
5.5
C223
Figure 23. INL vs Reference Voltage
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7.12 Typical Characteristics: ADS7853
0
0
±20
±20
±40
±40
Signal Power (dB)
Signal Power (dB)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
±60
±80
±100
±120
±140
±60
±80
±100
±120
±140
±160
±160
±180
±180
±200
±200
0
100
200
300
400
Input Frequency (kHz)
fIN = 2 kHz
16-CLK interface
SNR = 81.1 dB
500
0
100
THD = –94.2 dB
fIN = 250 kHz
16-CLK interface
400
500
C102
THD = –90.4 dB
Figure 25. Typical FFT
0
0
±20
±20
±40
±40
Signal Power (dB)
Signal Power (dB)
300
SNR = 80.2 dB
Figure 24. Typical FFT
±60
±80
±100
±120
±140
±60
±80
±100
±120
±140
±160
±160
±180
±180
±200
±200
0
100
200
300
400
Input Frequency (kHz)
fIN = 2 kHz
32-CLK interface
SNR = 81.9 dB
500
0
100
THD = –98.1 dB
fIN = 250 kHz
32-CLK interface
Signal-to-Noise and Distortion Ratio (dB)
32 CLK Mode
83.5
83
16 CLK Mode
82.5
82
81.5
81
±7
26
59
400
500
C152
THD = –92.1 dB
Figure 27. Typical FFT
84.5
±40
300
SNR = 80.8 dB
Figure 26. Typical FFT
84
200
Input Frequency (kHz)
C151
85
Signal-to-Noise Ratio (dB)
200
Input Frequency (kHz)
C101
92
Free-Air Temperature (oC)
fIN = 2 kHz
125
84
83.5
32 CLK Mode
83
82.5
82
81.5
16 CLK Mode
81
80.5
80
±40
±7
26
59
92
Free-Air Temperature (oC)
C103
125
C104
fIN = 2 kHz
Figure 28. SNR vs Temperature
Figure 29. SINAD vs Temperature
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Typical Characteristics: ADS7853 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
Signal-to-Noise and Distortion Ratio (dB)
85
Signal-to-Noise Ratio (dB)
84.5
84
83.5
83
82.5
82
81.5
81
80.5
80
2
2.5
3
3.5
4
4.5
5
Reference Voltage (V)
84
83.5
83
82.5
82
81.5
81
80.5
80
2
5.5
Figure 30. SNR vs Reference Voltage
Signal-to-Noise and Distortion Ratio (dB)
Signal-to-Noise Ratio (dB)
4
4.5
5
5.5
C106
Figure 31. SINAD vs Reference Voltage
84.5
84
83.5
83
82.5
82
81.5
81
50
100
150
200
250
Input Frequency (kHz)
85
84.5
84
83.5
83
82.5
82
81.5
81
0
300
50
100
150
200
250
Input Frequency (kHz)
C107
VREF = 5 V
300
C108
VREF = 5 V
Figure 32. SNR vs Input Frequency
Figure 33. SINAD vs Input Frequency
±60
Total Harmonic Distortion (dB)
±60
Total Harmonic Distortion (dB)
3.5
fIN = 2 kHz
85
±70
±80
16 CLK Mode
±90
32 CLK Mode
±100
±110
±120
±70
±80
16 CLK Mode
±90
32 CLK Mode
±100
±110
±120
±40
±7
26
59
92
Free-Air Temperature (oC)
fIN = 2 kHz
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125
2
2.5
3
3.5
4
4.5
5
Reference Voltage (V)
C109
5.5
C111
fIN = 2 kHz
Figure 34. THD vs Temperature
18
3
Reference Voltage (V)
fIN = 2 kHz
0
2.5
C105
Figure 35. THD vs Reference Voltage
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Typical Characteristics: ADS7853 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
10
9.5
±70
IAVDD Dynamic (mA)
Total Harmonic Distortion (dB)
±60
±80
±90
±100
±110
9
8.5
8
7.5
7
6.5
6
±120
0
50
100
150
200
250
Input Frequency (kHz)
300
±40
26
±7
59
92
Free-Air Temperature (oC)
C113
125
C124
VREF = 5 V
Figure 36. THD vs Input Frequency
Figure 37. Analog Supply Current vs Temperature
10
10
9
IAVDD Dynamic (mA)
IAVDD Dynamic (mA)
9
8
7
6
5
7
6
5
4
3
2
4
0
4
8
12
16
SCLK Frequency (MHz)
0
20
8
16
24
32
SCLK Frequency (MHz)
C030
40
C125
32-CLK interface
16-CLK interface
Figure 39. Analog Supply Current vs SCLK Frequency
Figure 38. Analog Supply Current vs SCLK Frequency
70000
70000
60000
60000
50000
50000
Number of Hits
Number of Hits
8
40000
30000
40000
30000
20000
20000
10000
10000
0
0
8098
8099
8100
16-CLK interface
8099
8100
C115
Code
65536 data points
Figure 40. DC Histogram
VIN-DIFF = 0 V
8101
Code
32-CLK interface
65536 data points
C155
VIN-DIFF = 0 V
Figure 41. DC Histogram
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Typical Characteristics: ADS7853 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
100
1000
750
75
32 CLK Mode
50
Gain Error (m%)
Offset Error (uV)
500
16 CLK Mode
250
0
±250
16 CLK Mode
25
0
32 CLK Mode
±25
±500
±50
±750
±75
±100
±1000
±40
±7
26
59
92
Free-Air Temperature (oC)
±40
125
1
2
0.75
1.5
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
92
125
C11
Figure 43. Gain Error vs Temperature
0.5
0.25
0
-0.25
-0.5
-0.75
1
0.5
0
-0.5
-1
-1.5
-1
-2
0
16384
Code
0
16384
Code
C118
16-CLK interface
C119
16-CLK interface
Figure 44. Typical DNL
Figure 45. Typical INL
2
2
1.5
1.5
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
59
Free-Air Temperature (oC)
Figure 42. Offset Error vs Temperature
1
0.5
0
-0.5
1
0.5
0
-0.5
-1
-1.5
-1
-2
0
16384
Code
0
16384
Code
C153
32-CLK interface
C154
32-CLK interface
Figure 46. Typical DNL
20
26
±7
C116
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Figure 47. Typical INL
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Typical Characteristics: ADS7853 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
2
1.5
1.5
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
2
Maximum 16 CLK Mode
1
0.5
Maximum 32 CLK Mode
0
Minimum 32 CLK Mode
-0.5
Maximum 16 CLK Mode
1
0.5
Maximum 32 CLK Mode
0
Minimum 32 CLK Mode
-0.5
-1
Minimum 16 CLK Mode
-1.5
Minimum 16 CLK Mode
-1
-2
±40
26
±7
59
92
125
Free-Air Temperature (oC)
±40
92
125
C121
Figure 49. INL vs Temperature
2
1.5
1.5
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
Figure 48. DNL vs Temperature
Maximum 16 CLK Mode
Maximum 32 CLK Mode
0.5
59
Free-Air Temperature (oC)
2
1
26
±7
C120
0
Minimum 32 CLK Mode
-0.5
Maximum 16 CLK Mode
1
0.5
Maximum 32 CLK Mode
0
Minimum 32 CLK Mode
-0.5
Minimum 16 CLK Mode
Minimum 16 CLK Mode
-1
-1
2
2.5
3
3.5
4
4.5
5
Reference Voltage (V)
Figure 50. DNL vs Reference Voltage
5.5
2
2.5
3
3.5
4
4.5
5
Reference Voltage (V)
C122
5.5
C123
Figure 51. INL vs Reference Voltage
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7.13 Typical Characteristics: ADS7253
0
0
±20
±20
±40
±40
±60
Signal Power (dB)
Signal Power (dB)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
±80
±100
±120
±140
±60
±80
±100
±120
±140
±160
±160
±180
±180
±200
0
100
200
300
400
Input Frequency (kHz)
fIN = 2 kHz
16-CLK interface
SNR = 73.2 dB
±200
500
0
100
THD = –90.5 dB
fIN = 250 kHz
16-CLK interface
0
0
±20
±20
±40
±40
Signal Power (dB)
Signal Power (dB)
400
500
C002
THD = –90.1 dB
Figure 53. Typical FFT
±60
±80
±100
±120
±140
±60
±80
±100
±120
±140
±160
±160
±180
±180
±200
±200
0
100
200
300
400
Input Frequency (kHz)
fIN = 2 kHz
32-CLK interface
SNR = 73.6 dB
500
0
100
THD = –91.6 dB
fIN = 250 kHz
32-CLK interface
Signal-to-Noise and Distortion Ratio (dB)
16 CLK Mode
72.5
72
71.5
71
70.5
70
±40
±7
26
59
92
Free-Air Temperature (oC)
fIN = 2 kHz
500
C052
THD = –90.6 dB
125
74
73.5
73
72.5
72
71.5
71
70.5
70
±40
±7
26
59
92
Free-Air Temperature (oC)
C003
125
C004
fIN = 2 kHz
Figure 56. SNR vs Temperature
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400
Figure 55. Typical FFT
32 CLK Mode
73
300
SNR = 73.4 dB
Figure 54. Typical FFT
73.5
200
Input Frequency (kHz)
C051
74
Signal-to-Noise Ratio (dB)
300
SNR = 73.1 dB
Figure 52. Typical FFT
22
200
Input Frequency (kHz)
C001
Figure 57. SINAD vs Temperature
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Typical Characteristics: ADS7253 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
32 CLK Mode
73.5
Signal-to-Noise Ratio (dB)
Signal-to-Noise and Distiortion Ratio (dB)
74
73
16 CLK Mode
72.5
72
71.5
71
70.5
70
2
2.5
3
3.5
4
4.5
5
Reference Voltage (V)
74
32 CLK Mode
73
16 CLK Mode
72
71
70
5.5
2
4
4.5
5
5.5
C00
Figure 59. SINAD vs Reference Voltage
Signal-to-Noise and Distortion Ratio (dB)
75
74.5
Signal-to-Noise Ratio (dB)
3.5
fIN = 2 kHz
Figure 58. SNR vs Reference Voltage
16 CLK Mode
74
73.5
32 CLK Mode
73
72.5
72
71.5
71
50
100
150
200
250
Input Frequency (kHz)
75
74.5
16 CLK Mode
74
73.5
73
72.5
72
71.5
71
300
0
50
100
150
200
250
Input Frequency (kHz)
C007
VREF = 5 V
300
C008
VREF = 5 V
Figure 60. SNR vs Input Frequency
Figure 61. SINAD vs Input Frequency
±60
Total Harmonic Distortion (dB)
±60
Total Harmonic Distortion (dB)
3
Reference Voltage (V)
fIN = 2 kHz
0
2.5
C005
±70
±80
±90
±100
±110
±70
±80
32 CLK Mode
±90
16 CLK Mode
±100
±110
±120
±120
±40
±7
26
59
92
Free-Air Temperature (oC)
fIN = 2 kHz
125
2
2.5
C009
3
3.5
4
4.5
5
Reference Voltage (V)
5.5
C011
fIN = 2 kHz
Figure 62. THD vs Temperature
Figure 63. THD vs Reference Voltage
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Typical Characteristics: ADS7253 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
8
7.5
±70
±80
IAVDD Dynamiv (mA)
Total Harmonic Distortion (dB)
±60
16 CLK Mode
±90
32 CLK Mode
±100
±110
7
6.5
6
5.5
5
4.5
4
±120
0
50
100
150
200
250
Input Frequency (kHz)
300
±40
±7
26
59
92
Free-Air Temperature (oC)
C013
125
C024
VREF = 5 V
Figure 64. THD vs Input Frequency
Figure 65. Analog Supply Current vs Temperature
10
10
9
IAVDD Dynamic (mA)
IAVDD Dynamic (mA)
9
8
7
6
5
6
5
4
2
0
4
8
12
16
SCLK Frequency (MHz)
0
20
8
16
24
32
SCLK Frequency (MHz)
C030
40
C125
32-CLK interface
16-CLK interface
Figure 67. Analog Supply Current vs SCLK Frequency
Figure 66. Analog Supply Current vs SCLK Frequency
60000
60000
50000
50000
40000
40000
Number of Hits
Number of Hits
7
3
4
30000
20000
10000
30000
20000
10000
0
0
2024
2025
2026
Code
16-CLK interface
65536 data points
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2024
2025
Code
C015
Figure 68. DC Histogram
24
8
VIN-DIFF = 0 V
32-CLK interface
65536 data points
2026
C015
VIN-DIFF = 0 V
Figure 69. DC Histogram
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Typical Characteristics: ADS7253 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
100
2000
32 CLK Mode
1500
75
16 CLK Mode
50
500
Gain Error (m%)
Offset Error (uV)
1000
32 CLK Mode
0
±500
16 CLK Mode
25
0
±25
±1000
±50
±1500
±75
±100
±2000
±40
±7
26
59
92
Free-Air Temperature (oC)
125
±40
92
125
C01
Figure 71. Gain Error vs Temperature
1
1
0.75
0.75
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
59
Free-Air Temperature
Figure 70. Offset Error vs Temperature
0.5
0.25
0
-0.25
-0.5
-0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-1
0
4096
Code
0
4096
Code
C018
16-CLK interface
C019
16-CLK interface
Figure 72. Typical DNL
Figure 73. Typical INL
1
1
0.75
0.75
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
26
±7
C016
0.5
0.25
0
-0.25
-0.5
-0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-1
0
4096
Code
0
4096
Code
C053
32-CLK interface
C054
32-CLK interface
Figure 74. Typical DNL
Figure 75. Typical INL
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Typical Characteristics: ADS7253 (continued)
1
1
0.75
0.75
0.5
Differential Nonlinearity (LSB)
Differential Nonlinearity (LSB)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
Maximum 16 CLK Mode
0.25
Maximum 32 CLK Mode
0
Minimum 32 CLK Mode
-0.25
-0.5
Minimum 16 CLK Mode
-0.75
-1
0.5
Maximum 16 CLK Mode
0.25
Maximum 32 CLK Mode
0
Minimum 32 CLK Mode
-0.25
Minimum 16 CLK Mode
-0.5
-0.75
-1
±40
26
±7
59
92
125
Free-Air Temperature (oC)
±40
0.75
0.75
Maximum 16 CLK Mode
0.25
Maximum 32 CLK Mode
Minimum 32 CLK Mode
-0.25
Minimum 16 CLK Mode
-0.5
-0.75
125
C021
0.5
Maximum 16 CLK Mode
0.25
Maximum 32 CLK Mode
0
Minimum 32 CLK Mode
-0.25
Minimum 16 CLK Mode
-0.5
-0.75
-1
-1
2
2.5
3
3.5
4
4.5
5
Reference Voltage (V)
Figure 78. DNL vs Reference Voltage
26
92
Figure 77. DNL vs Temperature
1
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
Figure 76. DNL vs Temperature
0
59
Free-Air Temperature (oC)
1
0.5
26
±7
C020
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5.5
2
2.5
C022
3
3.5
4
4.5
5
Reference Voltage (V)
5.5
C023
Figure 79. INL vs Reference Voltage
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7.14 Typical Characteristics: Common to ADS8353, ADS7853, and ADS7253
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = maximum, unless otherwise noted.
200
3
IAVDD Power Down (mA)
IAVDD STANDBY (mA)
2.5
16 CLK Mode
2
1.5
32 CLK Mode
1
0.5
160
120
80
40
16 CLK Mode
-40
-7
26
59
92
Free-Air Temperature (oC)
-40
125
-7
26
59
92
Free- AirTemperature (oC)
C027
Figure 80. STANDBY Current vs Temperature
125
C028
Figure 81. Power-Down Current vs Temperature
2.55
2.6
Internal Reference Output (V)
Internal Reference Output (V)
32 CLK Mode
0
0
2.53
2.51
2.49
2.47
2.45
-40
-7
26
59
Free-Air Temperature (oC)
92
125
2.55
2.5
2.45
2.4
2.35
2.3
-5
0
C016
5
10
15
Load Current (mA)
20
25
30
C017
ROUT = 0.67 Ω
Figure 82. Internal Reference Output vs Temperature
Figure 83. Internal Reference Output Impedance
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8 Detailed Description
8.1 Overview
These devices belong to a family of pin-compatible, dual, high-speed, simultaneous-sampling, analog-to-digital
converters (ADCs). The ADS8353, ADS7853, and ADS7253 support single-ended and pseudo-differential input
signals. The devices provide a simple, serial interface to the host controller and operate over a wide range of
analog and digital power supplies.
These devices have two independently programmable internal references to achieve system-level gain error
correction. The Functional Block Diagram section provides a functional block diagram of the device.
8.2 Functional Block Diagram
REF_A
Comparator
S/H
CDAC
SAR
ADC_A
ADC_B
S/H
Serial
Interface
SAR
CDAC
Comparator
REF_B
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8.3 Feature Description
8.3.1 Reference
The device has two simultaneous sampling ADCs (ADC_A and ADC_B). ADC_A and ADC_B operate with
reference voltages VREF_A and VREF_B present on the REFIO_A and REFIO_B pins, respectively. The REFIO_A
and REFIO_B pins should be decoupled with the REFGND_A and REFGND_B pins, respectively, with 10-µF
decoupling capacitors.
The device supports operation either with an internal or external reference source, as shown in Figure 84. The
reference voltage source is determined by setting bit 6 of the configuration register (CFR.B6). Note that this bit is
common to ADC_A and ADC_B.
AINP_A
AINM_A
ADC_A
REFGND_A
REFDAC_A
DAC_A
10 PF
REFIO_A
CFR.B6
Enable
INTREF
REFIO_B
REFDAC_B
10 PF
DAC_B
REFGND_B
AINP_B
AINM_B
ADC_B
Figure 84. Reference Configurations and Connections
When CFR.B6 is 0, the device shuts down the internal reference source (INTREF) and ADC_A and ADC_B
operate on external reference voltages provided by the user on the REFIO_A and REFIO_B pins, respectively.
When CFR.B6 is 1, the device operates with the internal reference source (INTREF) connected to REFIO_A and
REFIO_B via DAC_A and DAC_B, respectively. In this configuration, VREF_A and VREF_B can be changed
independently by writing to the respective user-programmable registers, REFDAC_A and REFDAC_B,
respectively. Refer to the REFDAC Registers (REFDAC_A and REFDAC_B) section for more details.
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Feature Description (continued)
8.3.2 Analog Inputs
The ADS8353, ADS7853, and ADS7253 support single-ended or pseudo-differential analog inputs on both ADC
channels. These inputs are sampled and converted simultaneously by the two ADCs, ADC_A and ADC_B.
ADC_A samples and converts (VAINP_A – VAINM_A), and ADC_B samples and converts (VAINP_B – VAINM_B).
Figure 85a and Figure 85b show equivalent circuits for the ADC_A and ADC_B analog input pins, respectively.
Series resistance, RS, represents the on-state sampling switch resistance (typically 50 Ω) and CSAMPLE is the
device sampling capacitor (typically 40 pF).
AVDD
AVDD
RS
CSAMPLE
AINP_A
RS
CSAMPLE
RS
CSAMPLE
AINP_B
GND
GND
AVDD
AVDD
RS
CSAMPLE
AINM_A
AINM_B
GND
GND
a) ADC_A
b) ADC_B
Figure 85. Equivalent Circuit for the Analog Input Pins
8.3.2.1 Analog Input: Full-Scale Range Selection
The full-scale range (FSR) supported at the analog inputs of the device is programmable with bit B9 of the
configuration register (CFR.B9). This bit is common for both ADCs (ADC_A and ADC_B). The FSR is given by
Equation 1 and Equation 2 :
For CFR.B9 = 0, FSR_ADC_A = 0 to VREF_A and FSR_ADC_B = 0 to VREF_B
For CFR.B9 = 1, FSR_ADC_A = 0 to 2 × VREF_A and FSR_ADC_B = 0 to 2 × VREF_B
(1)
where:
•
VREF_A and VREF_B are the reference voltages going to ADC_A and ADC_B, respectively (as described in the
Reference section).
(2)
Therefore, with appropriate settings of the REFDAC_A and REFDAC_B registers, CFR.B7, and CFR.B9, the
maximum dynamic range of the ADC can be used.
Note that while using CFR.B9 set to 1, care must be taken so that the ADC analog supply (AVDD) is as in
Equation 3 and Equation 4:
2 × VREF_A ≤ AVDD ≤ AVDD(max)
2 × VREF_B ≤ AVDD ≤ AVDD(max)
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(3)
(4)
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Feature Description (continued)
8.3.2.2 Analog Input: Single-Ended and Pseudo-Differential Configurations
The ADS8353, ADS7853, and ADS7253 can support single-ended or pseudo-differential input configurations.
For supporting single-ended inputs, B7 in the configuration register (CFR.B7) must be set to 0 (CFR.B7 = 0) and
AINM_A and AINM_B must be externally connected to GND.
For supporting pseudo-differential inputs, CFR.B7 must be set to 1 (CFR.B7 = 1) and AINM_A and AINM_B must
be externally connected to FSR_ADC_A / 2 and FSR_ADC_B / 2, respectively. Note that CFR.B7 is common to
both ADCs.
The CFR.B9 and CFR.B7 settings can be combined to select the desired input configuration, as shown in
Table 1.
Table 1. Input Configurations
INPUT RANGE SELECTION
AINM SELECTION
CONNECTION DIAGRAM
VREF_x
VREF_x
REFIO_x
AINP_x
CFR.B9 = 0
(FSR_ADC_A = 0 to VREF_A)
(FSR_ADC_B = 0 to VREF_B)
CFR.B7 = 0
(AINM_A = GND)
(AINM_B = GND)
0V
Device
AINM_x
2 u VREF_x
VREF_x
REFIO_x
AINP_x
CFR.B9 = 1
(FSR_ADC_A = 0 to 2 x VREF_A)
(FSR_ADC_B = 0 to 2 x VREF_B)
CFR.B7 = 0
(AINM_A = GND)
(AINM_B = GND)
0V
Device
AINM_x
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Feature Description (continued)
Table 1. Input Configurations (continued)
INPUT RANGE SELECTION
AINM SELECTION
CONNECTION DIAGRAM
VREF_x
VREF_x
REFIO_x
AINP_x
0V
CFR.B9 = 0
(FSR_ADC_A = VREF_A)
(FSR_ADC_B = VREF_B)
CFR.B7 = 1
(AINM_A = VREF_A/2)
(AINM_B = VREF_B/2)
Device
AINM_x
VREF_x / 2
2 u VREF_x
VREF_x
REFIO_x
AINP_x
0V
CFR.B9 = 1
(FSR_ADC_A = 2 x VREF_A)
(FSR_ADC_B = 2 x VREF_B)
CFR.B7 = 1
(AINM_A = VREF_A)
(AINM_B = VREF_B)
Device
AINM_x
VREF_x
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8.3.3 Transfer Function
The device supports two input configurations:
1. Single-ended inputs, CFR.B7 = 0 (default), or
2. Pseudo-differential inputs, CFR.B7 = 1.
The device also supports two output data formats:
1. Straight binary output, CFR.B4 = 0 (default), or
2. Twos compliment output, CFR.B4 = 1.
Device resolution is calculated by Equation 5:
1 LSB = (FSR_ADC_x) / (2N)
where:
•
•
N = 16 (ADS8353), 14 (ADS7853), or 12 (ADS7253) and
FSR_ADC_x is the full-scale input range of the ADC (refer to the Analog Input section for more details)
(5)
Table 2 and Table 3 show the different input voltages and the corresponding output codes from the device.
Table 2. Transfer Characteristics for Straight Binary Output (CFR.B4 = 0, Default)
AINP_x
Single-ended
(CFR.B7 = 0,
default)
Pseudo-differential
(CFR.B7 = 1)
OUTPUT CODE (Hex)
INPUT VOLTAGE
INPUT
CONFIGURATION
AINM_x
STRAIGHT BINARY (CFR.B4 = 0, Default)
AINP_x - AINM_x
CODE
ADS8353
ADS7853
≤ 1 LSB
ZC
0000
0000
000
FSR_ADC_x / 2
MC
7FFF
1FFF
7FF
≥ FSR_ADC_x – 1 LSB
≥ FSR_ADC_x – 1 LSB
FSC
FFFF
3FFF
FFF
≤ 1 LSB
≤ –FSR_ADC_x / 2 + 1 LSB
ZC
0000
0000
000
0
MC
7FFF
1FFF
7FF
≥ FSR_ADC_x / 2 – 1 LSB
FSC
FFFF
3FFF
FFF
≤ 1 LSB
FSR_ADC_x / 2
FSR_ADC_x / 2
0
FSR_ADC_x / 2
≥ FSR_ADC_x – 1 LSB
ADS7253
Table 3. Transfer Characteristics for Twos Compliment Output (CFR.B4 = 1)
AINP_x
Single-ended
(CFR.B7 = 0,
default)
AINM_x
≤ 1 LSB
FSR_ADC_x / 2
0
≥ FSR_ADC_x – 1 LSB
≤ 1 LSB
Pseudo-differential
(CFR.B7 = 1)
OUTPUT CODE (Hex)
INPUT VOLTAGE
INPUT
CONFIGURATION
FSR_ADC_x / 2
FSR_ADC_x / 2
≥ FSR_ADC_x – 1 LSB
TWOS COMPLIMENT (CFR.B4 = 1)
AINP_x - AINM_x
CODE
ADS8353
ADS7853
ADS7253
≤ 1 LSB
NFSC
8000
2000
800
FSR_ADC_x / 2
MC
0000
0000
000
≥ FSR_ADC_x – 1 LSB
PFSC
7FFF
1FFF
7FF
≤ –FSR_ADC_x / 2 + 1 LSB
NFSC
8000
2000
800
0
MC
0000
0000
000
≥ FSR_ADC_x / 2 – 1 LSB
PFSC
7FFF
1FFF
7FF
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Figure 86 shows the ideal device transfer characteristics for the single-ended analog input.
PFSC
MC
MC
ZC
NFSC
1 LSB
FSR_ADC_x / 2
VIN
ADC Code (Hex)
Twos Compliment Output Format
ADC Code (Hex)
Straight Binary Output Format
FSC
FSR_ADC_x ± 1 LSB
Single-Ended Analog Input
(AINP_x ± AINM_x)
Figure 86. Ideal Transfer Characteristics for a Single-Ended Analog Input
Figure 87 shows the ideal device transfer characteristics for the pseudo-differential analog input.
PFSC
-FSR_ADC_x/2
+ 1 LSB
MC
0
FSR_ADC_x/2
± 1 LSB
ZC
MC
ADC Code (Hex)
Twos Compliment Output Format
ADC Code (Hex)
Straight Binary Output Format
FSC
NFSC
Pseudo-Differential Analog Input
(AINP_x ± AINM_x)
Figure 87. Ideal Transfer Characteristics for a Pseudo-Differential Analog Input
34
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8.4 Device Functional Modes
The device provides three user-programmable registers: the configuration register (CFR), the REFDAC_A
register, and the REFDAC_B register. These registers support write (refer to the Write to User Programmable
Registers section) and readback (refer to the Reading User-Programmable Registers section) operations and
allow the user to customize ADC behavior for specific application requirements.
The device supports four interface modes (refer to the Conversion Data Read section), two low-power modes
(refer to the Low-Power Modes section), and short-cycling/reconversion feature (refer to the Frame Abort,
Reconversion, or Short-Cycling section).
8.5 Register Maps and Serial Interface
8.5.1 Serial Interface
The device uses the serial clock (SCLK) for synchronizing data transfers in and out of the device.
The CS signal defines one conversion and serial transfer frame. A frame starts with a CS falling edge and ends
with a CS rising edge. Between the start and end of the frame, a minimum of N SCLK falling edges must be
provided to validate the read or write operation. As shown in Table 4, N depends upon the interface mode used
to read the conversion result. When N SCLK falling edges are provided, the write operation attempted in the
frame is validated and the internal user-programmable registers are updated on the subsequent CS rising edge.
This CS rising edge also ends the frame.
Table 4. SCLK Falling Edges for a Valid Write Operation
INTERFACE MODE
MINIMUM SCLK FALLING EDGES REQUIRED TO
VALIDATE WRITE OPERATION N
32-CLK, dual-SDO mode (default). See the 32-CLK, Dual-SDO Mode section.
32
32-CLK, single-SDO mode. See the 32-CLK, Single-SDO Mode section.
48
16-CLK, dual-SDO mode. See the 16-CLK, Dual-SDO Mode section.
16
16-CLK, single SDO mode. See the 16-CLK, Single SDO Mode section.
32
If CS is brought high before providing N SCLK falling edges, the write operation attempted in the frame is not
valid. Refer to the Frame Abort, Reconversion, or Short-Cycling section for more details.
8.5.2 Write to User Programmable Registers
The device features three user-programmable registers: the configuration register (CFR), the REFDAC_A
register, and the REFDAC_B register. These registers can be written with the device SDI pin. The first 16 bits of
data on SDI are latched into the device on the first 16 SCLK falling edges. However, the new configuration takes
effect only when the read or write operation is validated. If these registers are not required to update, SDI must
remain low during the respective frames.
The first four SDI data bits (B[15:12]) determine what operation is performed (that is, either a read or write
operation or no operation), which register address the operation uses, and the function of the next 12 SDI data
bits (B[11:0]). Table 5 lists the various combinations supported for B[15:12].
Table 5. Data Write Operation
B15
B14
B13
B12
OPERATION
FUNCTION OF BITS B[11:0]
0
0
0
0
No operation is performed
These bits are ignored
0
0
0
1
REFDAC_A read
000h; see the Reading User-Programmable Registers section
0
0
1
0
REFDAC_B read
000h; see the Reading User-Programmable Registers section
0
0
1
1
CFR read
000h; see the Reading User-Programmable Registers section
1
0
0
0
CFR write
See the Configuration Register (CFR) section
1
0
0
1
REFDAC_A write
See the REFDAC_A section
1
0
1
0
REFDAC_B write
See the REFDAC_B section
1
0
1
1
No operation is performed
These bits are ignored
X
1
X
X
No operation is performed
These bits are ignored
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8.5.2.1 Configuration Register (CFR)
The device operation configuration is controlled by the configuration register (CFR) status. Data written into the
CFR in a valid frame (F) determine the device configuration for frame (F+1). The bit functions are outlined in
Figure 88. On power-up, all bits in the CFR default to 0.
Figure 88. CFR Bit Functions
15
14
13
12
WRITE/READ
0
ADDR1
ADDR0
7
6
5
INM_SEL
REF_SEL
STANDBY
4
RD_DATA_
FORMAT
11
RD_CLK_
MODE
3
10
RD_DATA_
LINES
2
9
8
INPUT_RANGE
0
1
0
0
0
0
0
Table 6. Configuration Register (CFR) Field Descriptions
Bit
Field
Type
Reset
15
WRITE/READ
W
0h
14
0
R/W
0h
13
ADDR1
R/W
0h
12
ADDR0
R/W
0h
11
10
RD_DATA_LINES
R/W
R/W
These bits select the user-programmable register.
1000 = Select this combination to write to the CFR register and
to enable bits 11:0
0h
This bit provides clock mode selection for the serial interface.
0 = Selects 32-CLK mode (default)
1 = Selects 16-CLK mode
(Note that the ADS8353 only supports 32-CLK mode. This bit is
ignored for the ADS8353.)
0h
This bit provides data line selection for the serial interface.
0 = Use SDO_A to output ADC_A data and SDO_B to output of
ADC_B data (default)
1 = Use only SDO_A to output of ADC_A data followed by
ADC_B data
9
INPUT_RANGE
R/W
0h
This bit selects the maximum input range for the ADC as a
function of the reference voltage provided to the ADC. See the
Analog Inputs section for more details.
0 = FSR equals VREF
1 = FSR equals 2 × VREF
8
0
R/W
0h
This bit must be set to 0 (default)
7
INM_SEL
R/W
0h
This bit selects the voltage to be externally connected to the
INM pin.
0 = INM must be externally connected to the GND potential
(default)
1 = INM must be externally connected to the FSR_ADC_x / 2
potential
6
REF_SEL
R/W
0h
This bit selects the ADC reference voltage source. Refer to the
Reference section for more details.
0 = Use external reference (default)
1 = Use internal reference
5
STANDBY
W
0h
This bit is used by the device to enter or exit STANDBY mode.
Refer to the STANDBY Mode section for more details.
4
RD_DATA_FORMAT
R/W
0h
This bit selects the output data format.
0 = Output is in straight binary format (default)
1 = Output is in twos compliment format
0
R/W
0h
These bits must be set to 0 (default)
3:0
36
RD_CLK_MODE
Description
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8.5.2.2 REFDAC Registers (REFDAC_A and REFDAC_B)
The REFDAC registers, bit functions, and resolution information are described in this section.
Figure 89. REFDAC_X Bit Functions
15
WRITE/READ
7
D4
14
0
6
D3
13
ADDR1
5
D2
12
ADDR0
4
D1
11
D8
3
D0
10
D7
2
0
9
D6
1
0
8
D5
0
0
Table 7. REFDAC Registers Field Descriptions
Bit
Field
Type
Reset
Description
15
WRITE/READ
W
0h
14
0
R/W
0h
13
ADDR1
R/W
0h
12
ADDR0
R/W
0h
These bits select the configurable register address.
1001 = Select this combination to write to the REFDAC_A
register
1010 = Select this combination to write to the REFDAC_B
register
11:3
D[8:0]
R/W
0h
Data to program the individual DAC output voltage.
Note: These bits are valid only for bits 15:12 = 1001 or bits
15:12 = 1010.
Table 8 shows the relationship between the REFDAC_x
programmed value and the DAC_x output voltage.
2:0
0
R/W
0h
This bit must be set to 0 (default)
Table 8. REFDAC Settings
REFDAC_x VALUE (Bits 11:3 in Hex)
B[2:0]
Typical DAC_x OUPTUT VOLTAGE (V) (1)
1FF (default)
000
2.5000
1FE
000
2.4989
1FD
000
2.4978
—
—
—
1D7
000
2.45
—
—
—
1AE
000
2.40
—
—
—
186
000
2.35
(1)
—
—
—
15D
000
2.30
—
—
—
134
000
2.25
—
—
—
10C
000
2.20
—
—
—
0E3
000
2.15
—
—
—
0BA
000
2.10
—
—
—
091
000
2.05
—
—
—
069
000
2.00
—
—
—
064 to 000
000
Do not use
Actual output voltage may vary by a few millivolts from the specified value. To obtain the desired output voltage, TI recommends starting
with the specified register setting and then experimenting with five codes on either side of the specified register setting.
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8.5.3 Data Read Operation
The device supports two types of read operations: reading user-programmable registers and reading conversion
results.
8.5.3.1 Reading User-Programmable Registers
The device supports a readback option for all user-programmable registers: CFR, REFDAC_A, and REFDAC_B.
Figure 90 shows a detailed timing diagram for this operation.
Frame (F)
Frame (F+1)
Frame (F+2)
Frame (F+3)
CS
SCLK
1
2
N
1
2
4
3
5
16
48
SDO-A
Valid Data
Valid data as per device configuration.
SDO-B
Valid Data
Valid data as per device configuration.
SDI
No change in device
configuration
B14 B13 B12
B15
X
X
X
1
2
R15 R14
15
16
47
R1
R0
1
48
2
N
Valid Data
Valid Data
X
No change in device
configuration
Device configuration for frame (F+3)
Note that N is a function of the device configuration, as described in Table 4.
Figure 90. Register Readback Timing
To readback the user-programmable register settings, the appropriate control word should be transmitted to the
device during frame (F+1), as shown in Table 9. Frame (F+1) must have at least 48 SCLK falling edges.
Table 9. Control Word to Readback User-Programmable Registers
CONTROL WORD TO BE PROGRAMMED IN FRAME (F+1)
USER-PROGRAMMABLE REGISTER
B[15:12] (Binary)
B[11:0] (Hex)
CFR
0011b
000h
REFDAC_A
0001b
000h
REFDAC_B
0010b
000h
Frame (F+2) must have at least 48 SCLK falling edges. During frame (F+2), SDO_A outputs the contents of the
selected user-programmable register on the first 16 SCLK falling edges (as shown in Table 10) and then outputs
0s for any subsequent SCLK falling edges. The SDO_B pin outputs 0s for all the SCLK falling edges.
Table 10. Register Data Read Back
USERPROGRAMMABLE
REGISTER
DATA READ ON SDO-A IN FRAME (F+2)
R15
R14
R13
R12
CFR
0
0
1
REFDAC_A
0
0
REFDAC_B
0
0
R11
—
R3
R2
R1
R0
1
CFG.B11
—
CFG.B3
CFG.B2
CFG.B1
CFG.B0
0
1
REFDAC_A.D8
—
1
0
REFDAC_B.D8
—
REFDAC_A.D0
0
0
0
REFDAC_B.D0
0
0
0
Register settings programmed during frame (F+2) determine the device configuration in frame (F+3).
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8.5.3.2 Conversion Data Read
The device provides four different interface modes to the user for reading the conversion result. These modes
offer flexible hardware connections and firmware programming. Table 11 shows how to select one of the four
interface modes.
Table 11. Interface Mode Selection
CFR.B11
CFR.B10
INTERFACE MODE
MINIMUM SCLK FALLING EDGES
REQUIRED TO VALIDATE WRITE
OPERATION N
0
0
32-CLK, dual-SDO mode (default)
32
0
1
32-CLK, single-SDO mode
48
1
0
16-CLK, dual-SDO mode
16
1
1
16-CLK, single SDO mode
32
In the 32-CLK interface modes, the device uses an internal clock to convert the sampled analog signal. The
conversion is completed during the first 16 periods of SCLK and the conversion result can be read on the
subsequent SCLK falling edges. All devices in the family (that is, ADS8353, ADS7853, and ADS7253) support
the 32-CLK interface modes.
In addition to the 32-CLK interface modes, the ADS7853 and ADS7253 also support the 16-CLK interface
modes. By using the 16-CLK interface modes, the same throughput can be achieved at much lower SCLK
speeds.
The following sections detail the various interface modes supported by the device.
8.5.3.2.1 32-CLK, Dual-SDO Mode (CFR.B11 = 0, CFR.B10 = 0, Default)
The 32-CLK, dual-SDO mode is the default mode supported by all devices. This mode can also be selected by
writing CFR.B11 = 0 and CFR.B10 = 0.
In this mode, the SDO_A pin outputs the ADC_A conversion result and the SDO_B pin outputs the ADC_B
conversion result. Figure 91 shows a detailed timing diagram for this mode.
Sample
N
Sample
N+1
tTHROUGHPUT
tCONV
tACQ
CS
tSCLK
SCLK
1
2
14
15
16
ADS8353, ADS8354
SDO_A and SDO_B
17
18
25
26
27
D15
D14
D7
D6
D5
28
29
D4
30
31
32
D3
D2
D1
D0
D1
D0
0
0
0
0
0
0
Data From Sample N
ADS7853, ADS7854
SDO_A and SDO_B
D13
D12
D5
D4
D3
D2
Data From Sample N
ADS7253, ADS7254
SDO_A and SDO_B
D11
D10
D3
D2
D1
D0
Data From Sample N
SDI
B15
B14
B2
B1
B0
X
X
X
X
X
X
X
X
X
X
Figure 91. 32-CLK, Dual-SDO Mode Timing Diagram
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A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A and SDO_B pins.
The device converts the sampled analog input during the conversion time (tCONV). SDO_A and SDO_B read 0
during this period. After completing the conversion process, the sample-and-hold circuit returns to sample mode.
The device outputs the MSBs of ADC_A and ADC_B on SDO_A and SDO_B pins, respectively, on the 16th
SCLK falling edge. The subsequent SCLK falling edges are used to shift out the rest of the bits of the conversion
result, as shown in Table 12.
Table 12. Data Launch Edge
LAUNCH EDGE
DEVICE
ADS8353
ADS7853
ADS7253
PINS
CS
SCLK
↓
↓1
—
—
↓27
↓28
↓29
↓30
↓31
↓32 ...
↑
SDO-A
0
0
—
0 D15_A
—
D4_A
D3_A
D2_A
D1_A
D0_A
0 ...
Hi-Z
SDO-B
0
0
—
0 D15_B
—
D4_B
D3_B
D2_B
D1_B
D0_B
0 ...
Hi-Z
SDO-A
0
0
—
0 D13_A
—
D2_A
D1_A
D0_A
0
0
0 ...
Hi-Z
SDO-B
0
0
—
0 D13_B
—
D2_B
D1_B
D0_B
0
0
0 ...
Hi-Z
SDO-A
0
0
—
0 D11_A
—
D0_A
0
0
0
0
0 ...
Hi-Z
SDO-B
0
0
—
0 D11_B
—
D0_B
0
0
0
0
0 ...
Hi-Z
↓15 ↓16
CS
In this mode, at least 32 SCLK falling edges must be given to validate the read or write frame. A CS rising edge
ends the frame and puts the serial bus into 3-state.
Refer to Table 13 for timing specifications specific to this serial interface mode.
Table 13. 32-CLK, Dual-SDO Interface Specific Timing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
tCLK
CLOCK period
tACQ
Acquisition time
ADS8353
50
ns
ADS7853
29.4
ns
ADS7253
29.4
ns
33 × tCLK – tCONV
ns
TIMING SPECIFICATIONS
tCONV
40
Conversion time
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ADS8353
730
ns
ADS7853
450
ns
ADS7253
450
ns
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8.5.3.2.2 32-CLK, Single-SDO Mode (CFR.B11 = 0, CFR.B10 = 1)
The 32-CLK, single-SDO mode provides the option of using only one SDO pin (SDO_A) to read conversion
results from both ADCs (ADC_A and ADC_B). SDO_B remains in 3-state and can be treated as a no connect
(NC) pin.
This mode can be selected by writing CFR.B11 = 0 and CFR.B10 = 1. Figure 92 shows a detailed timing diagram
for this mode.
Sample
N
Sample
N+1
tTHROUGHPUT
tCONV
tACQ
CS
SCLK
1
2
14
15
16
17
28
18
ADS8353, ADS8354
SDO_A
D1
5-A
D1
4-A
ADS7853, ADS7854
SDO_A
D1
3-A
D1
2-A
ADS7253, ADS7254
SDO_A
D1
1-A
D1
0-A
29
D4A
31
30
D3A
D2A
33
32
34
45
44
47
46
48
D1A
D0A
D1
5-B
D4B
D3B
D2B
D1B
D0B
0
0
D1
3-B
D2B
D1B
D0B
0
0
0
0
D1
1-B
D0B
0
0
0
0
X
X
X
X
X
X
Data From Sample N
D2A
D1A
D0A
Data From Sample N
D0A
0
0
Data From Sample N
All Devices
SDO_B
SDI
B15
B14
B3
B2
B1
B0
X
X
X
X
X
X
X
Figure 92. 32-CLK, Single-SDO Mode Timing Diagram
A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A pin. The device
converts the sampled analog input during the conversion time (tCONV). SDO_A reads 0 during this period. After
competing the conversion process, the sample-and-hold circuit goes back into sample mode. The device outputs
the MSB of ADC_A on the SDO_A pin on the 16th SCLK falling edge. The subsequent SCLK falling edges are
used to shift out the conversion result of ADC_A followed by the conversion result of ADC_B on the SDO_A pin,
as shown in Table 14.
Table 14. Data Launch Edge
LAUNCH EDGE
DEVICE
PIN
CS
SCLK
↓
↓1
—
↓15
↓16
—
↓27
↓28
↓29
↓30
↓31
CS
↓32
—
↓43
↓44
↓45
↓46
↓47
↓48 ...
D15_B
—
↑
D4_B
D3_B
D2_B
D1_B
D0_B
0 ...
Hi-Z
ADS8353
SDO-A
0
0
—
0
D15_A
—
D4_A
D3_A
D2_A
D1_A
D0_A
ADS7853
SDO-A
0
0
—
0
D13_A
—
D2_A
D1_A
D0_A
0
0
0
—
D2_B
D1_B
D0_B
0
0
0 ...
Hi-Z
ADS7253
SDO-A
0
0
—
0
D11_A
—
D0_A
0
0
0
0
0
—
D0_B
0
0
0
0
0 ...
Hi-Z
In this mode, at least 48 SCLK falling edges must be given to validate the read or write frame. A CS rising edge
ends the frame and puts the serial bus into 3-state.
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Refer to Table 15 for timing specifications specific to this serial interface mode.
Table 15. 32-CLK, Single-SDO Interface Specific Timing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
tCLK
tACQ
CLOCK period
ADS8353
50
ns
ADS7853
29.4
ns
ADS7253
29.4
ns
Acquisition time
49 × tCLK – tCONV
ns
TIMING SPECIFICATIONS
tCONV
Conversion time
ADS8353
730
ns
ADS7853
450
ns
ADS7253
450
ns
8.5.3.2.3 16-CLK, Dual-SDO Mode (CFR.B11 = 1, CFR.B10 = 0)
The 16-CLK, dual-SDO mode is designed to support the maximum throughput at lower SCLK frequencies. This
interface mode is not supported by the ADS8353.
For the ADS7853 and ADS7253, this interface mode can be selected by writing CFR.B11 = 1 and CFR.B10 = 0.
In this mode, the SDO_A pin outputs the ADC_A conversion result and the SDO_B pin outputs the ADC_B
conversion result. Figure 93 shows a detailed timing diagram for this mode.
Sample
N
Sample
N+1
tTHROUGHPUT
tPH_CS
CS
tSCLK
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
tCONV
ADS7853, ADS7854
SDO_A and SDO_B
0
0
D13
D12
D11
D10
D9
D8
tACQ
D7
D6
D5
D4
D3
D2
D1
tCONV
ADS7253, ADS7254
SDO_A and SDO_B
0
0
D11
D10
D9
D8
D7
D0
tACQ
D6
D5
D4
D3
D2
D1
D0
0
0
Data From Sample N
SDI
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 93. 16-CLK, Dual-SDO Mode Timing Diagram
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A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A and SDO_B pins.
The subsequent SCLK falling edges are used for conversion and for data transfer using the serial interface, as
shown in Table 16.
The sample-and-hold circuit goes back into sample mode as soon as the conversion process is over.
Table 16. Data Launch Edge
LAUNCH EDGE
DEVICE
ADS7853
ADS7253
PINS
CS
SCLK
CS
↓
↓1
↓2
—
↓13
↓14
↓15
↓16 ...
↑
SDO-A
0
0
D13_A
—
D2_A
D1_A
D0_A
0 ...
Hi-Z
SDO-B
0
0
D13_B
—
D2_B
D1_B
D0_B
0 ...
Hi-Z
SDO-A
0
0
D11_A
—
D0_A
0
0
0 ...
Hi-Z
SDO-B
0
0
D11_B
—
D0_B
0
0
0 ...
Hi-Z
In this mode, at least 16 SCLK falling edges must be given to validate the read or write frame. A CS rising edge
ends the frame and puts the serial bus into 3-state.
Refer to Table 17 for timing specifications specific to this serial interface mode.
Table 17. 16-CLK, Dual-SDO Interface Specific Timing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
tCLK
tACQ
CLOCK period
Acquisition time
ADS7853
55.5
ADS7253
55.5
ns
ns
ADS7853
4 × tCLK
ns
ADS7253
6 × tCLK
ns
ADS7853
14 × tCLK
ns
ADS7253
12 × tCLK
ns
TIMING SPECIFICATIONS
tCONV
Conversion time
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8.5.3.2.4 16-CLK, Single-SDO Mode (CFR.B11 = 1, CFR.B10 = 1)
The 16-CLK, single-SDO mode provides the option of using only one SDO pin (SDO_A) and a lower-speed clock
to read the conversion results of both ADCs. This interface mode is not supported by the ADS8353.
For the ADS7853 and ADS7253, this mode can be selected by writing CFR.B11 = 1 and CFR.B10 = 1. The
SDO_A pin is used to output the conversion results of both ADCs (ADC_A and ADC_B). SDO_B remains in 3state and can be treated as a no connect (NC) pin. Figure 94 shows a detailed timing diagram for this mode.
Sample
N
Sample
N+1
tTHROUGHPUT
tPH_CS
CS
tSCLK
SCLK
1
2
3
4
5
14
13
15
16
17
18
19
20
21
D13B
D12B
tCONV
ADS7853, ADS7854
SDO_A
0
0
D13A
D12A
0
0
D11A
31
32
tACQ
D11A
D2-A
D3-A
D1-A
D0-A
0
0
tCONV
ADS7253, ADS7254
SDO_A
30
D11D2-B
B
D1-B
D0-B
D9-B D0-B
0
0
tACQ
D10A
D9-A
D0-A
D1-A
0
0
0
D11B
0
D10B
Data From Sample N
All Devices
SDO_B
SDI
B15
B14
B13
B3
B12
B2
B1
B0
X
X
X
X
X
X
X
X
Figure 94. 16-CLK, Single-SDO Mode Timing Diagram
A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A pin. The
subsequent SCLK falling edges are used for conversion and for data transfer using the serial interface, as shown
in Table 18.
The sample-and-hold circuit goes back into sample mode as soon as the conversion process is over.
Table 18. Data Launch Edge
LAUNCH EDGE
DEVICE
PIN
CS
SCLK
↓
↓1
↓2
—
↓13
↓14
↓15
↓16
↓17
CS
↓18
—
↓29
↓30
↓31
↓32 ...
↑
ADS7853
SDO-A
0
0
D13_A
—
D2_A
D1_A
D0_A
0
0
D13_B
—
D2_B
D1_B
D0_B
0 ...
Hi-Z
ADS7253
SDO-A
0
0
D11_A
—
D0_A
0
0
0
0
D11_B
—
D0_B
0
0
0 ...
Hi-Z
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In this mode, at least 32 SCLK falling edges must be given to validate the read/write frame. A CS rising edge
ends the frame and puts the serial bus into 3-state.
Refer to Table 19 for timing specifications specific to this serial interface mode.
Table 19. 16-CLK, Single-SDO Interface Specific Timing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
tCLK
CLOCK period
tACQ
Acquisition time
ADS7853
55.5
ADS7253
55.5
ns
ns
ADS7853
19 × tCLK
ns
ADS7253
21 × tCLK
ns
ADS7853
14 × tCLK
ns
ADS7253
12 × tCLK
ns
TIMING SPECIFICATIONS
tCONV
Conversion time
8.5.4 Low-Power Modes
In normal mode of operation, all internal circuits of the device are always powered up and the device is always
ready to commence a new conversion. This mode enables the device to support the rated throughput. The
device also supports two low-power modes to optimize the power consumption at lower throughputs: STANDBY
mode and software power-down (SPD) mode.
8.5.4.1 STANDBY Mode
The device supports a STANDBY mode of operation where some of the internal circuits of the device are
powered down. However, if bit 6 in configuration register is set to 1 (CFR.B6 = 1), then the internal reference is
not powered down and the contents of the REFDAC_A and REFDAC_B registers are retained to enable faster
power-up to a normal mode of operation.
As shown in Figure 95, a valid write operation in frame (F) to program the configuration register with B5 set to 1
(CFR.B5 = 1) places the device into a STANDBY mode of operation on the following CS rising edge. While in
STANDBY mode, SDO_A and SDO_B output all 1s when CS is low and remain in 3-state when CS is high.
To remain in STANDBY mode, SDI must remain low in the subsequent frames.
Device enters
STANDBY mode
Frame (F)
Frame (F+1)
Device in
STANDBY mode
CS
SCLK
1
2
3
4
SDO-A and
SDO-B
5
6
7
8
9
10
11
12
13
14
15
16
N
1
2
Valid Data as per device configuration
CFG.B[5] = 1
SDI
CFG.B[15:12] = 1000b
CFG.B[11:6]
CFG.B[4:0] = 00000b
Note that N is a function of the device configuration, as described in Table 4.
Figure 95. Enter STANDBY Mode
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As shown in Figure 96, a valid write operation in frame (F+3) by writing the configuration register with B5 set to 0
(CFR.B5 = 0) brings the device out of STANDBY mode on the following CS rising edge. Frame (F+3) must have
at least 48 SCLK falling edges.
After exiting the STANDBY mode, a delay of tPU_STDBY must elapse for the internal circuits to fully power-up and
resume normal operation in frame (F+4). Device configuration for frame (F+4) is determined by the status of the
CFR.B[11:6] bits programmed during frame (F+3).
Frame (F+2)
CS
SCLK
Frame (F+3)
Device in
STANDBY
mode
tPU_STDBY
1
2
3
4
5
SDO-A
and
SDO-B
SDI
Frame (F+4)
Device exits
STANDBY mode
6
7
8
9
10
11
12
13
14
15
16
48
CFG.B[11:6]
2
15
16
N
Valid Data as per device configuration
These bits set device
configuration for Frame (F+4)
CFG.B[5] = 0
CFG.B[15:12] = 1000b
1
CFG.B[4:0] = 00000b
CFG settings for Frame (F+5)
Note that N is a function of the device configuration, as described in Table 4.
Figure 96. Exit STANDBY Mode
Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.
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8.5.4.2 Software Power-Down (SPD) Mode
In software power-down (SPD) mode, all internal circuits (including the internal references) are powered down.
However, the contents of the REFDAC_A and REFDAC_B registers are retained.
As shown in Figure 97, to enter SPD mode, the device must be selected (by bringing CS low) and SDI must be
kept high for a minimum of 48 SCLK cycles during frame (F). The device goes to SPD on the CS rising edge
following frame (F). While in SPD mode, SDO_A and SDO_B go to 3-state irrespective of the status of the CS
signal.
To remain in SPD mode, SDI must remain high in subsequent frames.
Device enters SPD
mode
Frame (F)
Frame (F+1)
Device in SPD
mode
CS
SCLK
1
2
SDO-A and
SDO-B
3
47
1
48
2
Valid Data as per device configuration
SDI
Figure 97. Enter SPD Mode
As shown in Figure 98, to exit SPD mode, the device must be selected (by bringing CS low) and SDI must be
kept low for a minimum of 48 SCLK cycles during frame (F+3). The device starts powering-up on a CS rising
edge following frame (F+3). After frame (F+3), a delay of tPU_SPD must elapse before programming the
configuration register.
A valid write operation in frame (F+4) sets the device configuration for frame (F+5). Frame (F+4) must have at
least 48 SCLK falling edges. The output data in frame (F+4) should be discarded.
Frame (F+2)
Frame (F+3)
Frame (F+4)
Device exits
SPD
Frame (F+5)
tPU_SPD
CS
SCLK
Device in
SPD
1
2
47
48
1
2
SDO-A
and
SDO-B
15
16
48
Invalid Data
SDI
CFG settings for Frame (F+5)
1
2
15
16
N
Valid Data as per device configuration
CFG settings for Frame (F+6)
Note that N is a function of the device configuration, as described in Table 4.
Figure 98. Exit SPD Mode
Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.
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8.5.5 Frame Abort, Reconversion, or Short-Cycling
As discussed in Figure 99, the minimum number of SCLK falling edges (N) that must be provided between the
beginning and end of the frame depends on the serial interface mode. The SCLK falling edges (N) program the
device and retrieve the conversion result. If CS is brought high before the expected number of SCLK falling
edges are provided, the current frame is aborted and the device starts sampling the new analog input signal.
If frame (F) is aborted, then the register write operation attempted in frame (F) is considered invalid and the
internal registers are not updated. The device continues to have the same configuration in frame (F+1) from
frame (F).
The output data bits latched before the CS rising edge are still valid data that correspond to sample N.
tPL_CS
tPH_CS_SHRT
CS
1
SCLK
2
SDO
Sample
N
Sample
N+1
tCONV
tACQ
tPH_CS_SHRT
CS
SCLK
1
2
SDO
13
14
15
16
17
22
23
24
V
V
V
V
V
Data From Sample N
Figure 99. Frame Abort, Reconversion, or Short-Cycling Feature
Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.
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9 Application and Implementation
9.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section details some general principles for designing these circuits, and some application circuits designed using
these devices.
The device supports operation either with an internal or external reference source. Refer to the Reference
section for details about the decoupling requirements.
The reference source to the ADC must provide low-drift and very accurate dc voltage and support the dynamic
charge requirements without affecting the noise and linearity performance of the device. The output broadband
noise (typically in the order of a few 100 μVRMS) of the reference source must be appropriately filtered by using a
low-pass filter with a cutoff frequency of a few hundred hertz. After band-limiting the noise from the reference
source, the next important step is to design a reference buffer that can drive the dynamic load posed by the
reference input of the ADC. At the start of each conversion, the reference buffer must regulate the voltage of the
reference pin within 1 LSB of the intended value. This condition necessitates the use of a large filter capacitor at
the reference pin of the ADC. The amplifier selected to drive the reference input pin must be stable while driving
this large capacitor and should have low output impedance, low offset, and temperature drift specifications. To
reduce the dynamic current requirements and crosstalk between the channels, a separate reference buffer is
recommended for driving the reference input of each ADC channel.
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a fly-wheel
RC filter. The amplifier is used for signal conditioning of the input voltage and its low output impedance provides
a buffer between the signal source and the switched capacitor inputs of the ADC. The RC filter helps attenuate
the sampling charge injection from the switched-capacitor input stage of the ADC and functions as an antialiasing
filter to band-limit the wideband noise contributed by the front-end circuit. Careful design of the front-end circuit is
critical to meet the linearity and noise performance of a high-precision ADC.
9.1.1 Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type and the performance goals
of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate
amplifier to drive the inputs of the ADC are:
• Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible
after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance
of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter at the ADC
inputs. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. In order to
maintain the overall stability of the input driver circuit, the amplifier bandwidth should be selected as
described in Equation 6:
§
1
Unity Gain Bandwidth t 4 u ¨¨
© 2S u ( RFLT RFLT ) u C FLT
•
·
¸¸
¹
(6)
Noise. Noise contribution of the front-end amplifiers should be as low as possible to prevent any degradation
in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data
acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit
should be kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is bandlimited by designing a low cutoff frequency RC filter and is calculated by Equation 7:
2
§ V 1 _ AM P_ PP ·
S
¨
¸
NG u 2 u ¨ f
en2 _ RM S u u f3dB
¸
6.6
2
¨
¸
©
¹
d
§ SNR dB ·
¸
20
¹
¨
1 VREF
u
u 10 ©
5
2
where:
•
•
•
•
V1 / f_AMP_PP is the peak-to-peak flicker noise in µV,
en_RMS is the amplifier broadband noise density in nV/√Hz,
f–3dB is the 3-dB bandwidth of the RC filter, and
NG is the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration.
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Application Information (continued)
•
Distortion. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. As a rule of
thumb, to ensure that the distortion performance of the data acquisition system is not limited by the front-end
circuit, the distortion of the input driver should be at least 10 dB lower than the distortion of the ADC, as
shown in Equation 8.
THD AMP d THD ADC 10 dB
•
(8)
Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal
must settle to the desired accuracy at the inputs of the ADC during the acquisition time window. This
condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data
sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the
desired accuracy. Therefore, the settling behavior of the input driver should always be verified by TINA™SPICE simulations before selecting the amplifier.
9.1.2 Antialiasing Filter
Converting analog-to-digital signals requires sampling an input signal at a constant rate. Any higher frequency
content in the input signal beyond half the sampling frequency is digitized and folded back into the low-frequency
spectrum. This process is called aliasing. Therefore, an analog, antialiasing filter must be used to remove the
harmonic content from the input signal before being sampled by the ADC. An antialiasing filter is designed as a
low-pass, RC filter, for which the 3-dB bandwidth is optimized based on specific application requirements. For dc
signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow
accurately settling the signal at the ADC inputs during the small acquisition time window. For ac signals, the filter
bandwidth should be kept low to band-limit the noise fed into the ADC input, thereby increasing the signal-tonoise ratio (SNR) of the system.
A filter capacitor, CFLT, connected across the ADC inputs (as shown in Figure 100), filters the noise from the
front-end drive circuitry, reduces the sampling charge injection and provides a charge bucket to quickly charge
the internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this
capacitor should be at least 10 times the specified value of the ADC sampling capacitance. For these devices,
the input sampling capacitance is equal to 40 pF. Thus, the value of CFLT should be greater than 400 pF. The
capacitor should be a COG- or NPO-type because these capacitor types have a high-Q, low-temperature
coefficient, and stable electrical characteristics under varying voltages, frequency, and time.
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design. For these devices, TI recommends limiting the value of RFLT to a maximum of 22 Ω
in order to avoid any significant degradation in linearity performance. The tolerance of the selected resistors can
be chosen as 1% because the use of a differential capacitor at the input balances the effects resulting from any
resistor mismatch.
RFLT ”22
f 3 dB
2S u R FLT
1
R FLT u C FLT
V
+
AINP
CFLT •400 pF
ADS8353
ADS7853
ADS7253
AINM
GND
RFLT ”22
Figure 100. Antialiasing Filter
The input amplifier bandwidth should be much higher than the cutoff frequency of the antialiasing filter. TI
strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase
margin with the selected filter. If an amplifier has less than a 40° phase margin with 22-Ω resistors, using a
different amplifier with higher bandwidth or reducing the filter cutoff frequency with a larger differential capacitor
is advisable.
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9.2 Typical Applications
9.2.1 DAQ Circuit to Achieve Maximum SINAD for a 10-kHz Input Signal at Full Throughput
AVDD
VCM
AVDD
OPA836
+
+
1k 10
+
AVDD
-
8.2 nF
COG
(NPO)
VIN+
1k AINP
ADSxx53
AINM
GND
10
VDC
Where;
VDC = 0 V for CFR.B7 = 0
VDC = FSR_ADC_x/2 for CFR.B7 = 1
VCM = FSR_ADC_x/2
ADS8353 : 16-bit, 600 kSPS
ADS7853 : 14-bit, 1 MSPS
ADS7253 : 12-bit, 1 MSPS
INPUT DRIVER
NOTE: Only one ADC channel is shown in this diagram. Replicate the same circuit for other ADC channels.
Figure 101. DAQ Circuit: Maximum SINAD for a 10-kHz Input Signal at Full Throughput, 32-CLK Interface
AVDD
VCM
AVDD
OPA836
+
+
1k 4
+
AVDD
-
1.8 nF
COG
(NPO)
VIN+
1k AINP
ADSxx53
AINM
GND
4
VDC
Where;
VDC = 0 V for CFR.B7 = 0
VDC = FSR_ADC_x/2 for CFR.B7 = 1
VCM = FSR_ADC_x/2
ADS7853 : 14-bit, 1 MSPS
ADS7253 : 12-bit, 1 MSPS
INPUT DRIVER
NOTE: Only one ADC channel is shown in this diagram. Replicate the same circuit for other ADC channels.
Figure 102. DAQ Circuit: Maximum SINAD for a 10-kHz Input Signal at Full Throughput, 16-CLK Interface
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Typical Applications (continued)
AVDD
10 µF
AVDD
REF5025,
REF5040,
REF5050(1)
REFGND-A
1k 0.1
+
ADC_A
AVDD
1 µF
REFIN-A
-
VOUT
Device
AVDD
TRIM
0.22
1k +
1 µF
REFIN-B
10 µF
1 µF
ADC_B
-
0.1
REFGND-B
OPA2350
10 µF
(1) When using the REF5050, AVDD must be set to 5.5 V.
Figure 103. Reference Drive Circuit
9.2.1.1 Design Requirements
To design an application circuit optimized to achieve target specifications listed in Table 20.
Table 20. Target Specifications
TARGET SPECIFICATIONS
TEST CONDITIONS
SNR
THD
DEVICE
INPUT SIGNAL
FREQUENCY
THROUGHPUT
INTERFACE MODE
> 83 dB
< -100 dB
ADS8353
10 kHz
Maximum supported
32-CLK, dual-SDO
> 81 dB
< –95 dB
ADS7853
10 kHz
Maximum supported
32-CLK, dual-SDO
> 77.5 dB
< –85 dB
ADS7853
10 kHz
Maximum supported
16-CLK, dual-SDO
> 71.5 dB
< –88 dB
ADS7253
10 kHz
Maximum supported
32-CLK, dual-SDO
> 70.5 dB
< –80 dB
ADS7253
10 kHz
Maximum supported
16-CLK, dual-SDO
9.2.1.2 Detailed Design Procedure
Best practice is for the distortion from the input driver to be at least 10 dB less than the ADC distortion. The
distortion resulting from variation in the common-mode signal is eliminated by using the amplifier in an inverting
gain configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates
the requirement of rail-to-rail swing at the amplifier input. The low-power OPA836, used as an input driver,
provides exceptional ac performance because of its extremely low-distortion and high-bandwidth specifications.
In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low
without adding distortion to the input signal.
The application circuit illustrated in Figure 101 is optimized to achieve the lowest distortion and lowest noise for a
10-kHz input signal fed to the ADS8353 or ADS7853 or ADS7253 operating at full throughput with the default 32CLK, dual-SDO interface mode. The input signal is processed through a high-bandwidth, low-distortion amplifier
in an inverting gain configuration and a low-pass RC filter before being fed into the device.
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The ADS7853 and the ADS7253 also support 16-CLK interface modes that achieve the rated throughput rate at
much lower SCLK frequencies. However, when using the 16-CLK interface modes, the device receives less
acquisition time when compared to the 32-CLK interface modes. The application circuit illustrated in Figure 102 is
optimized to achieve the lowest distortion and lowest noise for a 10-kHz input signal fed to the ADS7853 or
ADS7253 operating at full throughput with the 16-CLK, dual-SDO interface mode. The input signal is processed
through a high-bandwidth, low-distortion amplifier in an inverting gain configuration and a low-pass RC filter
before being fed into the device.
Figure 103 illustrates the reference driver circuit when operation with an external reference is desired. The
reference voltage is generated by the high-precision, low-noise REF50xx circuit. The output broadband noise of
the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz. The decoupling
capacitor on each reference pin is selected to be 10 µF. The low output impedance, low noise, and fast settling
time makes the OPA2350 a good choice for driving this high capacitive load.
9.2.1.3 Application Curves
To minimize external components and to maximize the dynamic range of the ADC, device is configured to
operate with internal reference (CFR.B6 = 1) and 2 x VREF_x input full scale range (CFR.B9 = 1).
Figure 104, Figure 105, and Figure 106, show the FFT plots and test results obtained with the ADS8353,
ADS7853, and ADS7253, respectively, operating at full throughput with a 32-CLK interface and the circuit
configuration of Figure 101.
0
0
±20
±30
±60
Power (dB)
Signal Power (dB)
±40
±80
±100
±120
±60
±90
±140
±160
±120
±180
±200
±150
0
60
120
180
240
300
Input Frequency (kHz)
SNR = 83.5 dB
THD = –101.2 dB
0
100
200
fIN = 10.1 kHz
300
400
500
Input Frequency (kHz)
C301
SNR = 82.1 dB
Figure 104. ADS8353 in 32-CLK Interface Mode
THD = –98.2 dB
C003
fIN = 10.1 kHz
Figure 105. ADS7853 in 32-CLK Interface Mode
0
Power (dB)
±30
±60
±90
±120
±150
0
100
200
300
400
500
Input Frequency (kHz)
SNR = 72.5 dB
THD = –94.2 dB
C001
fIN = 10.1 kHz
Figure 106. ADS7253 in 32-CLK Interface Mode
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0
0
±30
±30
Power (dB)
Power (dB)
Figure 107 and Figure 108 show the FFT plots and test results obtained with the ADS7853 and ADS7253,
respectively, operating at full throughput with 16-CLK interface and the circuit configuration of Figure 102.
±60
±90
±120
±90
±120
±150
0
100
200
300
400
Input Frequency (kHz)
SNR = 78.1 dB
THD = –89.8 dB
Submit Documentation Feedback
500
±150
0
100
fIN = 10.1 kHz
200
300
400
500
Input Frequency (kHz)
C004
Figure 107. ADS7853 in 16-CLK Interface Mode
54
±60
SNR = 71.2 dB
THD = –84.9 dB
C002
fIN = 10.1 kHz
Figure 108. ADS7253 in 16-CLK Interface Mode
Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: ADS8353 ADS7853 ADS7253
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9.2.2 DAQ Circuit to Achieve Maximum SINAD for a 100-kHz Input Signal at Full Throughput
+15 V
VCM
AVDD
THS4032
+
4.7
602
AVDD
+
-
VIN+
-15 V
V
+
AINP
1 nF
COG
(NPO)
602
ADSxx53
AINM
GND
10 pF
4.7
+15 V
VDC
+
THS4032
-15 V
ADS8353 : 16-bit, 600 kSPS
ADS7853 : 14-bit, 1 MSPS
ADS7253 : 12-bit, 1 MSPS
Where;
VDC = 0 V for CFR.B7 = 0
VDC = FSR_ADC_x/2 for CFR.B7 = 1
VCM = FSR_ADC_x/2
INPUT DRIVER
NOTE: Only one ADC channel is shown in this diagram. Replicate the same circuit for other ADC channels.
Figure 109. DAQ Circuit: Maximum SINAD for a 100-kHz Input Signal at Full Throughput
AVDD
AVDD
REF5025,
REF5040,
REF5050(1)
10 µF
REFGND-A
1k +
0.1
AVDD
1 µF
ADC_A
REFIN-A
-
VOUT
Device
AVDD
TRIM
0.22
1k +
1 µF
REFIN-B
10 µF
1 µF
-
ADC_B
0.1
REFGND-B
OPA2350
10 µF
(1) When using the REF5050, AVDD must be set to 5.5 V.
Figure 110. Reference Drive Circuit
Copyright © 2013–2014, Texas Instruments Incorporated
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9.2.2.1 Design Requirements
To design an application circuit optimized to achieve target specifications listed in Table 21.
Table 21. Target Specifications
TARGET SPECIFICATIONS
TEST CONDITIONS
SNR
THD
DEVICE
INPUT SIGNAL
FREQUENCY
> 83 dB
< -95 dB
ADS8353
100 kHz
Maximum supported
32-CLK, dual-SDO
> 78.5 dB
< –88 dB
ADS7853
100 kHz
Maximum supported
32-CLK, dual-SDO
> 77.5 dB
< –85 dB
ADS7853
100 kHz
Maximum supported
16-CLK, dual-SDO
> 71.5 dB
< –85 dB
ADS7253
100 kHz
Maximum supported
32-CLK, dual-SDO
> 71 dB
< –84 dB
ADS7253
100 kHz
Maximum supported
16-CLK, dual-SDO
THROUGHPUT
INTERFACE MODE
9.2.2.2 Detailed Design Procedure
Best practice is for the distortion from the input driver to be at least 10 dB less than the ADC distortion. The
distortion resulting from variation in the common-mode signal is eliminated by using the amplifier in an inverting
gain configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates
the requirement of rail-to-rail swing at the amplifier input. The low-power OPA836, used as an input driver,
provides exceptional ac performance because of its extremely low-distortion and high-bandwidth specifications.
In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low
without adding distortion to the input signal. To take full advantage of the pseudo-differential input structure of the
ADC, the AINM pin must be driven to the appropriate VDC with the same amplifier and matching source
impedance.
The application circuit illustrated in Figure 109 is optimized to achieve the lowest distortion and lowest noise for a
100-kHz input signal fed to the ADS8353 or ADS7853 or ADS7253 operating at full throughput. The THS4032,
used as an input driver, provides exceptional ac performance because of its extremely low-distortion, low-noise,
and high-bandwidth specifications. In addition, the components of the antialiasing filter are such that the noise
from the front-end circuit is kept low without adding distortion to the input signal. External clamp circuit may be
required to ensure that the inputs to the device do not exceed AVDD.
Figure 103 illustrates the reference driver circuit when operation with an external reference is desired. The
reference voltage is generated by the high-precision, low-noise REF50xx circuit. The output broadband noise of
the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz. The decoupling
capacitor on each reference pin is selected to be 10 µF. The low output impedance, low noise, and fast settling
time makes the OPA2350 a good choice for driving this high capacitive load.
56
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9.2.2.3 Application Curves
To minimize external components and to maximize the dynamic range of the ADC, device is configured to
operate with internal reference (CFR.B6 = 1) and 2 x VREF_x input full scale range (CFR.B9 = 1).
Figure 111, Figure 112, and Figure 113 show the FFT plots and test results obtained with the ADS8353,
ADS7853 and ADS7253, respectively, operating at full throughput with a 32-CLK interface and the circuit
configuration of Figure 109.
0
0
±20
±30
±60
±80
Power (dB)
Signal Power (dB)
±40
±100
±120
±60
±90
±140
±160
±120
±180
±200
0
60
120
180
240
Input Frequency (kHz)
SNR = 83.1 dB
THD = –95.5 dB
±150
300
0
100
C303
200
300
400
500
C007
Input Frequency (dB)
fIN = 100.2 kHz
SNR = 79.6 dB
Figure 111. ADS8353 in 32-CLK Interface Mode
THD = –90.9 dB
fIN = 100.2 kHz
Figure 112. ADS7853 in 32-CLK Interface Mode
0
Power (dB)
±30
±60
±90
±120
±150
0
100
200
300
400
Input Frequency (kHz)
SNR = 72.9 dB
THD = –85.8 dB
500
C005
fIN = 100.2 kHz
Figure 113. ADS7253 in 32-CLK Interface Mode
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0
0
±30
±30
Power (dB)
Power (dB)
Figure 114 and Figure 115 show the FFT plots and test results obtained with the ADS7853 and ADS7253,
respectively, operating with a 16-CLK interface and the circuit configuration of Figure 109.
±60
±90
±120
±90
±120
±150
±150
0
100
200
300
400
500
Input Frequency (kHz)
SNR = 78.2 dB
THD = –87.2 dB
Submit Documentation Feedback
0
100
fIN = 100.2 kHz
200
300
400
Input Frequency (kHz)
C008
Figure 114. ADS7853 in 16-CLK Interface Mode
58
±60
SNR = 72.3 dB
THD = –84.3 dB
500
C006
fIN = 100.2 kHz
Figure 115. ADS7253 in 16-CLK Interface Mode
Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: ADS8353 ADS7853 ADS7253
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SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014
10 Power-Supply Recommendations
The devices have two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is
used for the interface circuits. AVDD and DVDD can be independently set to any value within the permissible
ranges.
When using the device with 2 × VREF input range (CFR.B9 = 1), the AVDD supply voltage value defines the
permissible voltage swing on the analog input pins. To avoid saturation of output codes, and to use the full
dynamic range on the analog input pins, AVDD must be set as shown in Equation 9, Equation 10, and
Equation 11:
AVDD ≥ 2 × VREF_A
AVDD ≥ 2 × VREF_B
4.75 V ≤ AVDD ≤ 5.25 V
(9)
(10)
(11)
Decouple the AVDD and DVDD pins with the GND pin using individual 10-µF decoupling capacitors, as shown in
Figure 116.
AVDD
AVDD (pin 14)
10 PF
GND (pin 13)
10 PF
DVDD
DVDD (pin 7)
Figure 116. Power-Supply Decoupling
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11 Layout
11.1 Layout Guidelines
Figure 117 shows a board layout example for the ADS8353, ADS7853, and ADS7253 with the WQFN package.
Use a ground plane underneath the device and partition the PCB into analog and digital sections. Avoid crossing
digital lines with the analog signal path and keep the analog input signals and the reference input signals away
from noise sources. As shown in Figure 117, the analog input and reference signals are routed on the left side of
the board and the digital connections are routed on the right side of the device.
The power sources to the device must be clean and well-bypassed. Use 10-μF, ceramic bypass capacitors in
close proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the
AVDD and DVDD pins and the bypass capacitors. Connect all ground pins to the ground plane using short, low
impedance paths.
The REFIO-A and REFIO-B reference inputs and outputs are bypassed with 10-μF, X7R-grade, 0805-size, 16-V
rated ceramic capacitors (CREF-x). Place the reference bypass capacitors as close as possible to the reference
REFIO-x pins and connect the bypass capacitors using short, low-inductance connections. Avoid placing vias
between the REFIO-x pins and the bypass capacitors. Small 0.1-Ω to 0.2-Ω resistors (RREF-x) are used in series
with the reference bypass capacitors to improve stability.
The fly-wheel RC filters are placed immediately next to the input pins. Among ceramic surface-mount capacitors,
COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG
(NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature
changes. Figure 117 shows CIN-A and CIN-B filter capacitors placed across the analog input pins of the device.
11.2 Layout Example
CREF-A
AVDD
CIN-A
GND
GND
AVDD
AINP-A
AINM-A
RREF-A
CAVDD
GND
SDO-A
REFIO-A
CIN-B
/CS
SDI
AINM-B
RREF-B
CREF-B
SCLK
GND
REFIO-B
GND
SDO-B
REFGND-B
DVDD
GND
REFGND-A
AINP-B
GND
CDVDD
DVDD
GND
GND
Figure 117. Recommended Layout
60
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 22. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ADS8353
Click here
Click here
Click here
Click here
Click here
ADS7853
Click here
Click here
Click here
Click here
Click here
ADS7253
Click here
Click here
Click here
Click here
Click here
12.2 Related Documentation
•
•
•
•
•
TIPD117 Verified Design Reference Guide: 12 Bit 1 MSPS Single Supply Dual Channel Data Acquisition
System for Optical Encoders in Motor Control Application Reference Design, SLAU517.
REF5050 Data Sheet, SBOS410.
OPA2350 Data Sheet, SBOS099.
OPA836, OPA2836 Data Sheet, SLOS712.
THS4032 Data Sheet, SLOS224.
12.3 Trademarks
TINA is a trademark of Texas Instruments Inc..
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2013–2014, Texas Instruments Incorporated
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61
PACKAGE OPTION ADDENDUM
www.ti.com
7-Sep-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS7253IPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ADS7253
ADS7253IPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ADS7253
ADS7253IRTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7253
ADS7253IRTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7253
ADS7853IPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ADS7853
ADS7853IPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ADS7853
ADS7853IRTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7853
ADS7853IRTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7853
ADS8353IPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ADS8353
ADS8353IPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ADS8353
ADS8353IRTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
8353
ADS8353IRTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
8353
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Sep-2014
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS7253IPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
ADS7253IRTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS7253IRTET
WQFN
RTE
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS7853IPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
ADS7853IRTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS7853IRTET
WQFN
RTE
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS8353IPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
ADS8353IRTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS8353IRTET
WQFN
RTE
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS7253IPWR
ADS7253IRTER
TSSOP
PW
16
2000
367.0
367.0
35.0
WQFN
RTE
16
3000
367.0
367.0
35.0
ADS7253IRTET
WQFN
RTE
16
250
210.0
185.0
35.0
ADS7853IPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
ADS7853IRTER
WQFN
RTE
16
3000
367.0
367.0
35.0
ADS7853IRTET
WQFN
RTE
16
250
210.0
185.0
35.0
ADS8353IPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
ADS8353IRTER
WQFN
RTE
16
3000
367.0
367.0
35.0
ADS8353IRTET
WQFN
RTE
16
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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