Texas Instruments | QUAD CHANNEL, 12-BIT, 105/80 MSPS ADC WITH SERIAL LVDS INTERFACE (Rev. B) | Datasheet | Texas Instruments QUAD CHANNEL, 12-BIT, 105/80 MSPS ADC WITH SERIAL LVDS INTERFACE (Rev. B) Datasheet

Texas Instruments QUAD CHANNEL, 12-BIT, 105/80 MSPS ADC WITH SERIAL LVDS INTERFACE (Rev. B) Datasheet
ADS6424
ADS6423
ADS6422
www.ti.com
SLAS532B – MAY 2007 – REVISED DECEMBER 2013
QUAD CHANNEL, 12-BIT, 105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE
Check for Samples: ADS6424, ADS6423, ADS6422
FEATURES
•
•
•
•
APPLICATIONS
1
•
•
•
•
•
•
•
12-Bit Resolution With No Missing Codes
Simultaneous Sample and Hold
3.5dB Coarse Gain and upto 6dB
Programmable Fine Gain for SFDR/SNR TradeOff
Serialized LVDS Outputs With Programmable
Internal Termination Option
Supports Sine, LVCMOS, LVPECL, LVDS Clock
Inputs and Amplitude down to 400 mVPP
Internal Reference With External Reference
Support
No External Decoupling Required for
References
3.3-V Analog and Digital Supply
64 QFN Package (9 mm × 9 mm)
Pin Compatible 14-Bit Family (ADS644X SLAS531A)
Feature Compatible Dual Channel Family
(ADS624X - SLAS542A, ADS622X - SLAS543A)
•
•
•
•
Base-station IF Receivers
Diversity Receivers
Medical Imaging
Test Equipment
Table 1. ADS64XX Quad Channel Family
125 MSPS
105 MSPS
80 MSPS
65 MSPS
ADS644X
14 Bit
ADS6445
ADS6444
ADS6443
ADS6442
ADS642X
12 Bit
ADS6425
(SLWS197)
ADS6424
ADS6423
ADS6422
Table 2. Performance Summary
SFDR, dBc
SINAD, dBFS
Fin = 10MHz (0 dB gain)
Fin = 170MHz (3.5 dB gain)
ADS6425
ADS6424
ADS6423
ADS6422
90
91
91
93
79
81
82
83
Fin = 10MHz (0 dB gain)
70.7
71.1
71.3
71.3
Fin = 170MHz (3.5 dB gain)
67.4
68.1
68.2
68.7
420
340
300
265
Power per channel, mW
DESCRIPTION
The ADS6424/ADS6423/ADS6422 (ADS642X) is a family of high performance 12-bit 105/80/65 MSPS quad
channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact
64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5dB
coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to
the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it
possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing
receiver design. The ADS642X also includes the traditional 1-wire interface that can be used at lower sampling
frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit
clock is used to serialize the 12-bit data from each channel. In addition to the serial data streams, the frame and
bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable
LVDS currents, current doubling modes and internal termination options. These can be used to widen eyeopenings and improve signal integrity, easing capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
ADS6424
ADS6423
ADS6422
SLAS532B – MAY 2007 – REVISED DECEMBER 2013
www.ti.com
LVDD
LGND
CAP
AVDD
AGND
ADS642X has internal references, but can also support an external reference mode. The device is specified over
the industrial temperature range (–40°C to 85°C).
CLKP
CLKM
BIT Clock
DCLKP
DCLKM
FRAME Clock
FCLKP
FCLKM
PLL
12-Bit
ADC
Digital
Encoder
and
Serializer
12-Bit
ADC
Digital
Encoder
and
Serializer
SHA
12-Bit
ADC
Digital
Encoder
and
Serializer
SHA
12-Bit
ADC
Digital
Encoder
and
Serializer
INA_P
SHA
INA_M
INB_P
SHA
INB_M
INC_P
INC_M
IND_P
VCM
DA1_P
DA1_M
DB0_P
DB0_M
DB1_P
DB1_M
DC0_P
DC0_M
DC1_P
DC1_M
DD0_P
DD0_M
DD1_P
DD1_M
REFM
REFP
IND_M
DA0_P
DA0_M
Reference
Parallel
Interface
Serial
Interface
2
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SCLK
RESET
SEN
SDATA
CFG4
CFG3
CFG1
CFG2
PDN
ADS642x
B0199-04
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADS6424 ADS6423 ADS6422
ADS6424
ADS6423
ADS6422
www.ti.com
SLAS532B – MAY 2007 – REVISED DECEMBER 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS6424
QFN-64 (2)
RGC
–40°C to 85°C
AZ6424
ADS6423
QFN-64 (2)
RGC
–40°C to 85°C
AZ6423
ADS6422
QFN-64 (2)
RGC
–40°C to 85°C
AZ6422
(1)
(2)
ORDERING NUMBER
TRANSPORT
MEDIA,
QUANTITY
ADS6424IRGCT
250, Tape/reel
ADS6424IRGCR
2000, Tape/reel
ADS6423IRGCT
250, Tape/reel
ADS6423IRGCR
2000, Tape/reel
ADS6422IRGCT
250, Tape/reel
ADS6422IRGCR
2000, Tape/reel
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 23.17 °C/W (0 LFM air flow), θJC
= 22.1 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in. x 3 in. PCB.
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
AVDD
Supply voltage range
–0.3 to 3.9
V
LVDD
Supply voltage range
–0.3 to 3.9
V
Voltage between AGND and DGND
–0.3 to 0.3
V
Voltage between AVDD to LVDD
–0.3 to 3.3
V
Voltage applied to external pin, VCM
–0.3 to 2.0
V
Voltage applied to analog input pins
–0.3V to minimum ( 3.6, AVDD + 0.3V)
V
TA
Operating free-air temperature range
–40 to 85
°C
TJ
Operating junction temperature range
125
°C
Tstg
Storage temperature range
–65 to 150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2007–2013, Texas Instruments Incorporated
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ADS6424
ADS6423
ADS6422
SLAS532B – MAY 2007 – REVISED DECEMBER 2013
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
AVDD Analog supply voltage
3.0
3.3
3.6
V
LVDD
3.0
3.3
3.6
V
SUPPLIES
LVDS Buffer supply voltage
ANALOG INPUTS
Differential input voltage range
2
Vpp
1.5
±0.1
Input common-mode voltage
Voltage applied on VCM in external reference mode
1.45
1.50
V
1.55
V
CLOCK INPUT
Input clock sample rate, Fs
ADS6424
5
105
ADS6423
5
80
ADS6422
5
Sine wave, ac-coupled
Input clock amplitude differential (VCLKP – VCLKM)
0.4
LVPECL, ac-coupled
65
1.5
±0.8
LVDS, ac-coupled
VPP
±0.35
LVCMOS, ac-coupled
Input clock duty cycle
MSPS
3.3
35%
50%
65%
DIGITAL OUTPUTS
CLOAD
Maximum external load capacitance from each output pin to
DGND
RLOAD
Differential load resistance (external) between the LVDS
output pairs
TA
Operating free-air temperature
4
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Without internal termination
5
With internal termination
pF
10
100
–40
Ω
85
°C
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADS6424 ADS6423 ADS6422
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ADS6423
ADS6422
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SLAS532B – MAY 2007 – REVISED DECEMBER 2013
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference
mode (unless otherwise noted).
ADS6424
Fs = 105 MSPS
PARAMETER
MIN
RESOLUTION
TYP
ADS6423
Fs = 80 MSPS
MAX
MIN
TYP
ADS6422
Fs = 65 MSPS
MAX
MIN
TYP
UNIT
MAX
12
12
12
Bits
2.0
2.0
2.0
VPP
7
7
7
pF
Analog input bandwidth
500
500
500
MHz
Analog input common
mode current (per input pin
of each ADC)
130
100
81
μA
ANALOG INPUT
Differential input voltage
range
Differential input
capacitance
REFERENCE VOLTAGES
VREFB
Internal reference bottom
voltage
1.0
1.0
1.0
V
VREFT
Internal reference top
voltage
2.0
2.0
2.0
V
ΔVREF
Internal reference error,
(VREFT–VREFB)
VCM
Common mode output
voltage
1.5
1.5
1.5
V
VCM output current
capability
±4
±4
±4
mA
-15
±2
15
-15
±2
15
-15
±2
15
mV
DC ACCURACY
No missing codes
EO
Offset error, across devices
and across channels within
a device
Specified
–15
Offset error temperature
coefficient, across devices
and across channels within
a device
±2
Specified
15
–15
0.05
±2
Specified
15
–15
0.05
±2
15
0.05
mV
mV/°C
There are two sources of gain error - internal reference inaccuracy and channel gain error
EGREF
Gain error due to internal
reference inaccuracy alone,
(ΔVREF /2.0) %
-0.75
Reference gain error
temperature coefficient
EGCHAN
±0.1
0.75
-0.75
0.0125
Gain error of channel
alone, across devices and
across channels within a
device (1)
–1
Channel gain error
temperature coefficient,
across devices and across
channels within a device
±0.3
±0.1
0.75
-0.75
0.0125
1
–1
0.005
±0.3
±0.1
0.75
Δ%/°C
0.0125
1
–1
0.005
±0.3
% FS
1
% FS
Δ%/°C
0.005
DNL
Differential nonlinearity
–0.9
±0.5
2.0
–0.9
±0.4
1.8
–0.9
±0.4
1.8
INL
Integral nonlinearity
–2.2
±1.25
2.2
–2.0
±1.25
2.0
–2.0
±1.0
2.0
PSRR
DC power supply rejection
ratio
LSB
LSB
0.5
0.5
0.5
mV/V
410
360
320
mA
POWER SUPPLY
ICC
(1)
Total supply current
This is specified by design and characterization; it is not tested in production.
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ADS6424
ADS6423
ADS6422
SLAS532B – MAY 2007 – REVISED DECEMBER 2013
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ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference
mode (unless otherwise noted).
PARAMETER
ADS6424
Fs = 105 MSPS
MIN
TYP
ADS6423
Fs = 80 MSPS
MAX
MIN
TYP
ADS6422
Fs = 65 MSPS
MAX
MIN
TYP
IAVDD
Analog supply current
322
280
245
ILVDD
LVDS supply current
88
80
75
Total power
Power down (with input
clock stopped)
6
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UNIT
MAX
mA
mA
1.35
1.55
1.18
1.35
1.05
1.25
W
77
150
77
150
77
150
mW
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: ADS6424 ADS6423 ADS6422
ADS6424
ADS6423
ADS6422
www.ti.com
SLAS532B – MAY 2007 – REVISED DECEMBER 2013
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference
mode (unless otherwise noted).
PARAMETER
TEST CONDITIONS
ADS6424
Fs = 105 MSPS
MIN
TYP
MAX
ADS6423
Fs = 80 MSPS
MIN
TYP
ADS6422
Fs = 65 MSPS
MAX
MIN
UNIT
TYP MAX
DYNAMIC AC CHARACTERISTICS
Fin = 10 MHz
71.2
Fin = 50 MHz
70.8
Fin = 70 MHz
67.5
Fin = 100 MHz
SNR
Signal to noise ratio
Fin = 170 MHz
Fin = 230 MHz
71
70.5
69
69.1
3.5 dB
Coarse
gain
68.4
68.4
68.8
0 dB gain
67.8
66.9
68.1
3.5 dB
Coarse
gain
67.3
67.3
67.8
71.1
71.3
71.3
69.8
67
67.5
70.9
70
70.6
67.5
71
70
70.1
70
68.5
68.6
68.9
3.5 dB
Coarse
gain
68.1
68.2
68.7
0 dB gain
66.8
66.5
67.3
3.5 dB
Coarse
gain
66.8
67.2
67.4
Inputs tied to common-mode
0.407
0.407
0.407
Fin = 10 MHz
91
91
93
Fin = 50 MHz
80
73
Fin = 230 MHz
87
76
86
86
85
85
83
0 dB gain
78
79
80
3.5 dB
Coarse
gain
81
82
83
0 dB gain
76
77
78
3.5 dB
Coarse
gain
79
80
81
Copyright © 2007–2013, Texas Instruments Incorporated
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dBFS
LSB
88
81
Fin = 100 MHz
Fin = 170 MHz
76
dBFS
70.7
0 dB gain
Fin = 70 MHz
SFDR
Spurious free
dynamic range
70.9
70.5
Fin = 100 MHz
RMS Output noise
71.2
70.6
68.8
Fin = 70 MHz
Fin = 230 MHz
71.4
68
70.1
Fin = 50 MHz
Fin = 170 MHz
71.1
0 dB gain
Fin = 10 MHz
SINAD
Signal to noise and
distortion ratio
71.4
68
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dBc
7
ADS6424
ADS6423
ADS6422
SLAS532B – MAY 2007 – REVISED DECEMBER 2013
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference
mode (unless otherwise noted).
PARAMETER
TEST CONDITIONS
ADS6424
Fs = 105 MSPS
MIN
Fin = 10 MHz
94
Fin = 50 MHz
88
Fin = 70 MHz
73
Fin = 170 MHz
Fin = 230 MHz
MAX
MIN
96
76
90
97
76
92
92
87
0 dB gain
84
86
86
3.5 dB
Coarse
gain
86
88
88
0 dB gain
81
82
83
3.5 dB
Coarse
gain
83
84
85
91
Fin = 50 MHz
80
73
91
76
87
88
86
86
85
85
83
0 dB gain
78
79
80
3.5 dB
Coarse
gain
82
82
83
0 dB gain
76
77
78
3.5 dB
Coarse
gain
79
80
81
Fin = 10 MHz
95
96
98
Fin = 50 MHz
94
95
95
Fin = 70 MHz
94
95
95
Fin = 100 MHz
92
93
93
Fin = 170 MHz
89
90
90
Fin = 230 MHz
86
87
87
Fin = 10 MHz
89.5
89.5
Fin = 50 MHz
78.5
Fin = 70 MHz
74
85.5
84
83
80.5
Fin = 170 MHz
76
77.5
78.5
Fin = 230 MHz
74
75.5
Fin = 50 MHz
IMD
2-Tone
intermodulation
distortion
F1= 46.09 MHz, F2 = 50.09
MHz
90
94
97.5
F1= 185.09 MHz, F2 =
190.09 MHz
88
92
96
8
Fin = 70 MHz
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dBc
76.5
ENOB
Effective number of
bits
10.8
dBc
86
70
11.5
dBc
91
74
Fin = 100 MHz
10.9
dBc
93
76
81
Fin = 170 MHz
UNIT
TYP MAX
87
Fin = 10 MHz
Fin = 230 MHz
THD
Total harmonic
distortion
TYP
90
Fin = 100 MHz
Worst harmonic
(other than HD2,
HD3)
MIN
90
Fin = 70 MHz
HD3
Third harmonic
MAX
ADS6422
Fs = 65 MSPS
88
Fin = 100 MHz
HD2
Second harmonic
TYP
ADS6423
Fs = 80 MSPS
10.9
11.5
Bits
11.4
dBFS
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ADS6423
ADS6422
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SLAS532B – MAY 2007 – REVISED DECEMBER 2013
ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1dBFS differential analog input, internal reference
mode (unless otherwise noted).
PARAMETER
TEST CONDITIONS
ADS6424
Fs = 105 MSPS
MIN
Cross-talk
TYP
MAX
ADS6423
Fs = 80 MSPS
MIN
TYP
ADS6422
Fs = 65 MSPS
MAX
MIN
Near channel
Cross-talk signal frequency
= 10 MHz
92
94
100
Far channel
Cross-talk signal frequency
= 10 MHz
105
106
108
1
1
1
35
35
35
Input overload
recovery
Recovery to within 1% (of
final value) for 6-dB overload
with sine wave input
AC PSRR
Power Supply
Rejection Ratio
< 100 MHz signal, 100 mVPP
on AVDD supply
UNIT
TYP MAX
dBc
Clock
cycles
dBc
DIGITAL CHARACTERISTICS
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 AVDD = LVDD = 3.3V, IO = 3.5mA, RLOAD = 100 Ω (1).
All LVDS specifications are characterized, but not tested at production.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS
High-level input voltage
2.4
V
Low-level input voltage
0.8
V
High-level input current
10
μA
Low-level input current
10
μA
4
pF
1375
mV
Input capacitance
DIGITAL OUTPUTS
High-level output voltage
Low-level output voltage
1025
|VOD|
Output differential voltage
VOS
Output offset voltage
Common-mode voltage of OUTP and OUTM
Output capacitance
Output capacitance inside the device, from either output to ground
(1)
250
350
mV
450
mV
1200
mV
2
pF
IO refers to the LVDS buffer current setting, RLOAD is the external differential load resistance between the LVDS output pair.
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ADS6424
ADS6423
ADS6422
SLAS532B – MAY 2007 – REVISED DECEMBER 2013
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TIMING SPECIFICATIONS (1)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA,
RL = 100 Ω (3), no internal termination, unless otherwise noted.
TEST
CONDITIONS
PARAMETER
tJ
Aperture jitter
ADS6424
Fs = 105 MSPS
MIN
Uncertainty in the
sampling instant
TYP
ADS6423
Fs = 80 MSPS
MAX
MIN
250
ADS6422
Fs = 65 MSPS
TYP MAX
MIN
250
TYP
UNIT
MAX
250
fs rms
Interface: 2-wire, DDR bit clock, 14x
serialization
Data setup time (4)
From data crossover to bit clock
cross-over
0.45
0.65
0.65
0.85
0.8
1.1
ns
Data hold time (4)
(5) (6)
From bit clock
cross-over to data
cross-over
0.5
0.7
0.7
0.9
0.8
1.1
ns
Frame setup time
From frame clock
rising edge crossover to bit clock
rising edge crossover
0.45
0.65
0.65
0.85
0.8
1.1
ns
th
Frame hold time
From bit clock
falling edge crossover to frame clock
falling edge crossover
0.5
0.7
0.7
0.9
0.8
1.1
ns
tpd_clk
Input clock rising
Clock
edge cross-over to
propagation delay
frame clock rising
(6)
edge cross-over
3.4
4.4
3.4
4.4
3.4
4.4
tsu
(5) (6)
th
tsu
Bit clock cyclecycle jitter (5)
Frame clock
cycle-cycle jitter
(5)
5.4
5.4
5.4
ns
350
350
350
ps pp
75
75
75
ps pp
Below specifications apply for 5 MSPS ≤ Sampling freq ≤ 105 MSPS and all interface options
tA
Aperture delay
Delay from input
clock rising edge to
the actual sampling
instant
1
2
3
1
2
3
1
2
3
ns
Aperture delay
variation
Channel-channel
within same device
–250
±80
250
–250
±80
250
–250
±80
250
ps
ADC Latency
(1)
(2)
(3)
(4)
(5)
(6)
(7)
10
(7)
Time for a sample
to propagate to
ADC outputs, see
Figure 1
12
12
12
Clock
cycles
Timing parameters are ensured by design and characterization and not tested in production.
CL is the external single-ended load capacitance between each output pin and ground.
Io refers to the LVDS buffer current setting; RL is the external differential load resistance between the LVDS output pair.
Timing parameters are measured at the end of a 2 inch pcb trace (100-Ω characteristic impedance) terminated by RLand CL.
Setup and hold time specifications take into account the effect of jitter on the output data and clock.
Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options.
Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as
listed in Table 27.
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TIMING SPECIFICATIONS(1) (continued)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA,
RL = 100 Ω (3), no internal termination, unless otherwise noted.
PARAMETER
Wake up time
TEST
CONDITIONS
ADS6424
Fs = 105 MSPS
MIN
TYP
ADS6423
Fs = 80 MSPS
MAX
MIN
ADS6422
Fs = 65 MSPS
TYP MAX
MIN
TYP
UNIT
MAX
Time to valid data
after coming out of
global power down
100
100
100
μs
Time to valid data
after input clock is
re-started
100
100
100
μs
Time to valid data
after coming out of
channel standby
200
200
200 clock cycles
tRISE
Data rise time
From –100 mV to
+100 mV
50
100
200
50
100
200
50
100
200
ps
tFALL
Data fall time
From +100 mV to
–100 mV
50
100
200
50
100
200
50
100
200
ps
tRISE
Bit clock and
Frame clock rise
time
From –100 mV to
+100 mV
50
100
200
50
100
200
50
100
200
ps
tFALL
Bit clock and
Frame clock fall
time
From +100 mV to
–100 mV
50
100
200
50
100
200
50
100
200
ps
Bit clock duty
cycle
45%
50%
55%
45%
50%
55%
45%
50%
55%
Frame clock duty
cycle
47%
50%
53%
47%
50%
53%
47%
50%
53%
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Sample
N+13
Sample
N+12
Sample
N+11
Sample
N
Input
Signal
tA
Input
Clock
CLKM
CLKP
tPD_CLK
Latency 12 Clocks
Bit
Clock
Output
Data
DCLKP
DCLKM
DOP
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 D11 D10 D9
Sample N–1
Frame
Clock
D8
D7
D6
D5
D4
D3
D2
D1
D0
DOM
Sample N
FCLKM
FCLKP
T0105-03
Figure 1. Latency
12
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DCLKP
Bit clock
DCLKM
tsu
th
tsu
th
P
Output data
(differential)
DA, DB, DC, DD
Dn+1
Dn
M
tsu
th
FCLKP
Frame clock
FCLKM
Figure 2. LVDS Timings
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DEVICE PROGRAMMING MODES
ADS642X offers flexibility with several programmable features that are easily configured.
The device can be configured independently using either parallel interface control or serial interface
programming.
In addition, the device supports a third configuration mode, where both the parallel interface and the serial control
registers are used. In this mode, the priority between the parallel and serial interfaces is determined by a priority
table (refer to Table 4). If this additional level of flexibility is not required, the user can select either the serial
interface programming or the parallel interface control.
USING PARALLEL INTERFACE CONTROL ONLY
To control the device using parallel interface, keep RESET tied to high (LVDD). Pins CFG1, CFG2, CFG3,
CFG4, PDN, SEN, SCLK, and SDATA are used to directly control certain functions of the ADC. After power-up,
the device will automatically get configured as per the parallel pin voltage settings (refer to Table 5 to Table 8)
and no reset is required. In this mode, SEN, SCLK, and SDATA function as parallel interface control pins.
Frequently used functions are controlled in this mode—output data interface and format, power down modes,
coarse gain and internal/external reference. The parallel pins can be configured using a simple resistor string
(with 10% tolerance resistors) as illustrated in Figure 3.
Table 3 lists descriptions of the modes controlled by the parallel pins.
Table 3. Parallel Pin Definition
PIN
SEN
SCLK, SDATA
CONTROL FUNCTIONS
Coarse gain and internal/external reference.
Sync, deskew patterns and global power down.
PDN
Dedicated pin for global power down
CFG1
1-Wire/2-wire and DDR/SDR bit clock
CFG2
12x/14x Serialization and SDR bit clock capture edge
CFG3
Reserved function. Tie CFG3 to Ground.
CFG4
MSB/LSB First and data format.
USING SERIAL INTERFACE PROGRAMMING ONLY
In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal
registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET
pin or by a high setting on the <RST> bit (in register ). After reset, the RESET pin must be kept low.
The serial interface section describes the register programming and register reset in more detail.
Since the parallel pins (CFG1-4 and PDN) are not used in this mode, they must be tied to ground. The register
override bit <OVRD> - D10 in register 0x0D has to be set high to disable the control of parallel interface pins in
this serial interface control ONLY mode.
USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (CFG1-4 and PDN)
can also be used to configure the device.
The parallel interface control pins CFG1 to CFG4 and PDN are available. After power-up, the device will
automatically get configured as per the parallel pin voltage settings (refer to Table 5 to Table 11) and no reset is
required. A simple resistor string can be used as illustrated in Figure 3.
SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC.
The registers must first be reset to their default values either by applying a pulse on RESET pin or by a high
setting on the <RST> bit (in register ). After reset, the RESET pin must be kept low.
The serial interface section describes the register programming and register reset in more detail.
Since some functions are controlled using both the parallel pins and serial registers, the priority between the two
is determined by a priority table (refer to Table 4).
14
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Table 4. Priority Between Parallel Pins and Serial Registers
FUNCTIONS
SUPPORTED
PIN
PRIORITY
As described in Table 8
to Table 11
Register bits can control the modes only if the register bit <OVRD> is high. If <OVRD> is
low, then the control voltage on these parallel pins determines the function.
PDN
Global Power Down
Register bit <PDN GLOBAL> controls global power down only if PDN pin is low. If PDN is
high, device is in global power down mode.
SEN
Serial Interface Enable
CFG1 to CFG4
Coarse gain setting is controlled by bit <COARSE GAIN> only if the <OVRD> bit is high.
Else, it is in default setting of 0 dB gain.
Internal/External reference setting is determined by bit <REF>.
SCLK, SDATA
Serial Interface Clock
Register bits <PATTERN> control the sync and deskew output patterns.
and Serial Interface Data
Power down is determined by bit <PDN GLOBAL>.
pins
LVDD
LVDD
(5/6) LVDD
R
(5/8) LVDD
GND
2R
(5/8) LVDD
3R
(5/6) LVDD
LVDD
GND
2R
LVDD
(3/8) LVDD
(3/6) LVDD
(3/8) LVDD
(3/6) LVDD
3R
3R
To SEN Pin
To CFGx Pins
GND
GND
Figure 3. Simple Scheme to Configure Parallel Pins
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DESCRIPTION OF PARALLEL PINS
Table 5. SCLK, SDATA Control Pins
SCLK
SDATA
DESCRIPTION
LOW
LOW
NORMAL conversion.
LOW
HIGH
SYNC - ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the
deserialized data to the frame boundary. See Capture Test Patterns for details.
HIGH
LOW
POWER DOWN –Global power down, all channels of the ADC are powered down, including internal references,
PLL and output buffers.
HIGH
HIGH
DESKEW - ADC outputs deskew pattern on all channels. This pattern can be used by the receiver to ensure
deserializer uses the right clock edge. See Capture Test Patterns for details.
Table 6. SEN Control Pin
SEN
0
DESCRIPTION
External reference and 0 dB coarse gain (full-scale = 2 VPP)
(3/8)LVDD
External reference and 3.5 dB coarse gain (full-scale = 1.34 VPP)
(5/8)LVDD
Internal reference and 3.5 dB coarse gain (full-scale = 1.34 VPP)
LVDD
Internal reference and 0 dB coarse gain (full-scale = 2 VPP)
Independent of the programming mode used, after power-up the parallel pins PDN, CFG1 to CFG4 will
automatically configure the device as per the voltage applied (refer to Table 7 to Table 11).
Table 7. PDN Control Pin
PDN
0
AVDD
DESCRIPTION
Normal operation
Power down global
Table 8. CFG1 Control Pin
CFG1
DESCRIPTION
0 (default) +
200mV
DDR Bit clock and 1-wire interface
(3/6) LVDD ±
200mV
Not used
(5/6) LVDD ±
200mV
SDR Bit clock and 2-wire interface
LVDD - 200mV
DDR Bit clock and 2-wire interface
Table 9. CFG2 Control Pin
CFG2
DESCRIPTION
0 (default) +
200mV
12x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode)
(3/6) LVDD ±
200mV
14x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode)
(5/6) LVDD ±
200mV
14x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode)
LVDD - 200mV
12x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode)
Table 10. CFG3 Control Pin
CFG3
16
RESERVED - TIE TO GROUND
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Table 11. CFG4 Control Pin
CFG4
DESCRIPTION
0 (default) +
200mV
MSB First and 2s complement
(3/6) LVDD ±
200mV
MSB First and offset binary
(5/6) LVDD ±
200mV
LSB First and offset binary
LVDD - 200mV
LSB First and 2s complement
SERIAL INTERFACE
The ADC has a serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock),
SDATA (serial interface data) and RESET. Serial shift of bits into the device is enabled when SEN is low. Serial
data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the
register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits,
the excess bits are ignored. Data can be loaded in multiple of 16-bit words within a single active SEN pulse. The
interface can work with SCLK frequency from 20 MHz down to very low speeds (few hertz) and even with non50% duty cycle SCLK.
The first 5-bits of the 16-bit word are the address of the register while the next 11 bits are the register data.
Register Reset
After power-up, the internal registers must be reset to their default values. This can be done in one of two ways:
1. Either by applying a high-going pulse on RESET (of width greater than 10 ns) OR
2. By applying software reset. Using the serial interface, set the <RST> bit in register 0x00 to high – this resets
the registers to their default values and then self-resets the <RST> bit to LOW.
When RESET pin is not used, it must be tied to LOW.
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Register Address
SDATA
A4
A3
A2
A1
Register Data
A0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t(DH)
t(SCLK)
t(DSU)
SCLK
t(SLOADH)
t(SLOADS)
SEN
RESET
T0109-03
Figure 4. Serial Interface Timing
18
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SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD =
3.3 V, unless otherwise noted.
PARAMETER
MIN
TYP
> DC
MAX
UNIT
20
MHz
fSCLK
SCLK Frequency, fSCLK = 1/tSCLK
tSLOADS
SEN to SCLK Setup time
25
ns
tSLOADH
SCLK to SEN Hold time
25
ns
tDSU
SDATA Setup time
25
ns
tDH
SDATA Hold time
25
ns
100
ns
Time taken for register write to take effect after 16th SCLK falling edge
RESET TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD =
3.3 V, unless otherwise noted.
PARMATER
CONDITIONS
MIN
t1
Power-on delay time
Delay from power-up of AVDD and LVDD to RESET pulse active
t2
Reset pulse width
t3
tPO
TYP
MAX
UNIT
5
ms
Pulse width of active RESET signal
10
ns
Register write delay time
Delay from RESET disable to SEN active
25
Power-up delay time
Delay from power-up of AVDD and LVDD to output stable
ns
6.5
ms
Power Supply
AVDD, LVDD
t1
RESET
t2
t3
SEN
T0108-03
Figure 5. Reset Timing
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SERIAL REGISTER MAP
Table 12. Summary of Functions Supported By Serial Interface
REGISTER
ADDRESS
A4 - A0
REGISTER FUNCTIONS (1)
D10
D9
D8
D7
00
<RST>
S/W RESET
0
0
0
04
0
0
0
0
0
<DF>
DATA
FORMAT 2S
COMP OR
STRAIGHT
BINARY
0
0A
0D
10
11
(1)
(2)
(3)
20
0
D5
<REF>
INTERNAL
OR
EXTERNAL
D4
D3
<PDN CHD>
POWER
DOWN CH D
<PDN CHC>
POWER
DOWN CHC
D2
<PDN CHB>
POWER
DOWN CH B
<CLKIN GAIN>
INPUT CLOCK BUFFER GAIN CONTROL
<PATTERNS>
TEST PATTERNS
0
0
0
D1
D0
<PDN CHA>
POWER
DOWN CH A
<PDN
GLOBAL>
GLOBAL
POWER
DOWN
0
0
0
0
<CUSTOM A>
CUSTOM PATTERN (LOWER 11 BITS)
0B
0C
D6
(2) (3)
<FINE GAIN>
FINE GAIN CONTROL (1dB to 6 dB)
<OVRD>
OVERRIDE
BIT
0
0
0
0
0
0
0
0
0
<CUSTOM
B>
CUSTOM
PATTERN
(MSB BIT)
BYTE-WISE
OR BITWISE
MSB OR
LSB FIRST
<COARSE
GAIN>
COURSE
GAIN
ENABLE
FALLING OR
RISING BIT
CLOCK
CAPTURE
EDGE
0
12-BIT OR
14-BIT
SERIALIZE
DDR OR
SDR BIT
CLOCK
1-WIRE OR
2-WIRE
INTERFACE
<TERM CLK>
LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS
WORD-WISE CONTROL
0
0
<LVDS CURR>
LVDS CURRENT SETTINGS
0
0
<CURR DOUBLE>
LVDS CURRENT DOUBLE
<TERM DATA>
LVDS INTERNAL TERMINATION - DATA OUTPUTS
The unused bits in each register (shown by blank cells in above table) must be programmed as 0.
Multiple functions in a register can be programmed in a single write operation.
After a hardware or software reset, all register bits are cleared to ‘0’.
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DESCRIPTION OF SERIAL REGISTERS
Note: After a hardware or software reset, all register bits are cleared to ‘0’.
Table 13. Serial Register A
REGISTER
ADDRESS
A4 - A0
00
BITS
D10
<RST>
S/W RESET
D9
0
D8
D7
0
0
D6
D5
0
<REF>
INTERNAL
OR
EXTERNAL
D4
<PDN CHD>
POWER
DOWN CH D
D3
<PDN CHC>
POWER
DOWN CHC
D2
<PDN CHB>
POWER
DOWN CH B
D1
D0
<PDN CHA>
POWER
DOWN CH A
<PDN>
GLOBAL
POWER
DOWN
D0 - D4
Power down modes
D0
<PDN GLOBAL>
0
Normal operation
1
Global power down, including all channels ADCs, internal references, internal PLL and output
buffers
D1
<PDN CHA>
0
CH A Powered up
1
CH A ADC Powered down
D2
<PDN CHB>
0
CH B Powered up
1
CH B ADC Powered down
D3
<PDN CHC>
0
CH C Powered up
1
CH C ADC Powered down
D4
<PDN CHD>
0
CH D Powered up
1
CH D ADC Powered down
D5
<REF> Reference
0
Internal reference enabled
1
External reference enabled
D10
<RST>
1
Software reset applied – resets all internal registers and self-clears to 0
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Table 14. Serial Register B
REGISTER
ADDRESS
A4 - A0
04
BITS
D10
0
D9
0
D8
D7
0
D6
D5
D4
D3
D2
<CLKIN GAIN>
INPUT CLOCK BUFFER GAIN CONTROL
0
D6 - D2
<CLKIN GAIN> Input clock buffer gain control
11000
Gain 0, minimum gain
00000
Gain 1, default gain after reset
01100
Gain 2
01010
Gain 3
01001
Gain 4
01000
Gain 5, maximum gain
D1
D0
0
0
Table 15. Serial Register C
REGISTER
ADDRESS
A4 - A0
0A
BITS
D10
D9
D8
0
<DF>
DATA
DORMAT 2S
COMP OR
STRAIGHT
BINARY
0
D7
D6
D5
<PATTERNS>
TEST PATTERNS
D4
D3
D2
D1
D0
0
0
0
0
0
D7 - D5
<PATTERNS> Capture test patterns
000
Normal ADC operation
001
Output all zeros
010
Output all ones
011
Output toggle pattern
100
Unused
101
Output custom pattern (contents of CUSTOM pattern registers 0x0B and 0x0C)
110
Output DESKEW pattern (serial stream of 1010..)
111
Output SYNC pattern
D9
<DF> Data format selection
0
2s Complement format
1
Straight binary format
22
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Table 16. Serial Register D
REGISTER
ADDRESS
A4 - A0
BITS
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D2
D1
D0
<CUSTOM A>
CUSTOM PATTERN (LOWER 11 BITS)
0B
D10 - D0
<CUSTOM A> Lower 11 bits of custom pattern <D10>…<D0>
Table 17. Serial Register E
REGISTER
ADDRESS
A4 - A0
0C
BITS
D10
D9
D8
D7
<FINE GAIN>
FINE GAIN CONTROL (1 dB to 6 dB)
D6
0
D5
0
D4
0
0
D4 - D0
<CUSTOM B> MSB bit of custom pattern <D11>
D10-D8
<FINE GAIN> Fine gain control
000
0 dB Gain (full-scale range = 2.00 VPP)
001
1 dB Gain (full-scale range = 1.78 VPP)
010
2 dB Gain (full-scale range = 1.59 VPP)
011
3 dB Gain (full-scale range = 1.42 VPP)
100
4 dB Gain (full-scale range = 1.26 VPP)
101
5 dB Gain (full-scale range = 1.12 VPP)
110
6 dB Gain (full-scale range = 1.00 VPP)
D3
0
0
0
<CUSTOM
B>
CUSTOM
PATTERN
(MSB BIT)
Table 18. Serial Register F
REGISTER
ADDRESS
A4 - A0
0D
BITS
D10
<OVRD>
OVER-RIDE
BITE
D9
D8
0
D7
BYTE-WISE
OR BITWISE
0
D6
MSB OR
LSB FIRST
D5
D4
D3
D2
D1
D0
<COARSE
GAIN>
COARSE
GAIN
ENABLE
FALLING OR
RISING BIT
CLOCK
CAPTURE
EDGE
0
14-BIT OR
16-BIT
SERIALIZE
DDR OR
SDR BIT
CLOCK
1-WIRE OR
2-WIRE
INTERFACE
D0
Interface selection
0
1 Wire interface
1
2 Wire interface
D1
Bit clock selection (only in 2-wire interface)
0
DDR Bit clock
1
SDR Bit clock
D2
Serialization selection
0
12x Serialization
1
14x Serialization
D4
Bit clock capture edge (only when SDR bit clock is selected, D1 = 1)
0
Capture data with falling edge of bit clock
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1
Capture data with rising edge of bit clock
D5
<COARSE GAIN> Coarse gain control
0
0 dB coarse gain
1
3.5dB coarse gain (full-scale range = 1.34 VPP)
D6
MSB or LSB first selection
0
MSB First
1
LSB First
D7
Byte/bit wise outputs (only when 2-wire is selected)
0
Byte wise
1
Bit wise
D10
<OVRD> Over-ride bit. All the functions in register 0x0D can also be controlled using the
parallel control pins. By setting bit <OVRD> = 1, the contents of register 0x0D will over-ride
the settings of the parallel pins.
0
Disable over-ride
1
Enable over-ride
Table 19. Serial Register G
REGISTER
ADDRESS
A4 - A0
BITS
D10
D9
D8
D7
D6
D5
<TERM CLK>
LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS
10
D4
D3
D2
<LVDS CURR>
LVDS CURRENT SETTINGS
D0
<CURR DOUBLE> LVDS current double for data outputs
0
Nominal LVDS current, as set by <D5…D2>
1
Double the nominal value
D1
<CURR DOUBLE> LVDS current double for bit and word clock outputs
0
Nominal LVDS current, as set by <D5…D2>
1
Double the nominal value
D3-D2
<LVDS CURR> LVDS current setting for data outputs
00
3.5 mA
01
4 mA
10
2.5 mA
11
3 mA
D5-D4
<LVDS CURR> LVDS current setting for bit and word clock outputs
00
3.5 mA
01
4 mA
10
2.5 mA
11
3 mA
D10-D6
<TERM CLK> LVDS internal termination for bit and word clock outputs
00000
No internal termination
00001
166 Ω
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D1
D0
<LVDS DOUBLE>
LVDS CURRENT DOUBLE
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00010
200 Ω
00100
250 Ω
01000
333 Ω
10000
500 Ω
Any combination of above bits can also be programmed, resulting in a parallel combination of
the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω
100 Ω
00101
Table 20. Serial Register H
REGISTER
ADDRESS
A4 - A0
11
BITS
D10
D9
WORD-WISE CONTROL
D8
D7
D6
D5
0
0
0
0
D4
D3
D2
D1
D0
<TERM DATA>
LVDS INTERNAL TERMINATION - DATA OUTPUTS
D4-D0
<TERM DATA> LVDS internal termination for data outputs
00000
No internal termination
00001
166 Ω
00010
200 Ω
00100
250 Ω
01000
333 Ω
10000
500 Ω
Any combination of above bits can also be programmed, resulting in a parallel combination
of the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω
00101
100 Ω
D10-D9
Only when 2-wire interface is selected
00
Byte-wise or bit-wise output, 1x frame clock
11
Word-wise output enabled, 0.5x frame clock
01,10
Do not use
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PIN CONFIGURATION (2-WIRE INTERFACE)
LVDD
DC1_P
DC1_M
DC0_P
DC0_M
LGND
FCLKP
FCLKM
DCLKP
DCLKM
LGND
DB1_P
DB1_M
DB0_P
DB0_M
LVDD
ADS642x
RGC PACKAGE
(TOP VIEW)
DA1_P
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
DD0_M
DA1_M
2
47
DD0_P
DA0_P
3
46
DD1_M
DA0_M
4
45
DD1_P
CAP
5
44
SCLK
RESET
6
43
SDATA
LVDD
7
42
SEN
AGND
8
41
PDN
PAD
IND_P
AGND
13
36
AGND
INB_M
14
35
INC_M
INB_P
15
34
INC_P
AGND
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AGND
AVDD
AVDD
37
AGND
12
CFG1
INA_P
CFG2
IND_M
CFG3
38
AVDD
11
AGND
INA_M
CLKM
AGND
CLKP
39
AGND
10
VCM
AGND
CFG4
AVDD
NC
40
AGND
9
AVDD
AVDD
P0056-06
PIN ASSIGNMENTS (2-WIRE INTERFACE)
PINS
NAME
NO.
I/O
NO. OF
PINS
DESCRIPTION
SUPPLY AND GROUND PINS
AVDD
9,17,19,27,32
,40
6
Analog power supply
AGND
8,10,13,16,
18, 23, 26,
31,33,36,39
11
Analog ground
LVDD
7,49,64
3
Digital power supply
LGND
54,59
2
Digital ground
INPUT PINS
CLKP, CLKM
24,25
I
2
Differential input clock pair
INA_P, INA_M
12,11
I
2
Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do not float.
INB_P, INB_M
15,14
I
2
Differential input signal pair, channel B. If unused, the pins should be tied to VCM. Do not float.
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PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued)
PINS
NAME
NO.
I/O
NO. OF
PINS
DESCRIPTION
INC_P, INC_M
34,35
I
2
Differential input signal pair, channel C. If unused, the pins should be tied to VCM. Do not float.
IND_P, IND_M
37,38
I
2
Differential input signal pair, channel D. If unused, the pins should be tied to VCM. Do not float.
1
Connect 2-nF capacitor from pin to ground
CAP
5
SCLK
44
I
1
This pin functions as serial interface clock input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along with
SDATA). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
SDATA
43
I
1
This pin functions as serial interface data input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along with
SCLK). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
SEN
42
I
1
This pin functions as serial interface enable input when RESET is low.
When RESET is high, it controls coarse gain and internal/external reference modes. Refer to Table 6 for
description.
This pin has an internal pull-up resistor.
Serial interface reset input.
When using the serial interface mode, the user MUST initialize internal registers through hardware
RESET by applying a high-going pulse on this pin or by using software reset option. Refer to the Serial
Interface section. In parallel interface mode, tie RESET permanently high. (SCLK, SDATA and SEN
function as parallel control pins in this mode).
RESET
6
I
1
PDN
41
I
1
Global power down control pin.
CFG1
30
I
1
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock selection. Refer to
Table 8 for description.
Tie to AVDD for 2-wire interface with DDR bit clock.
CFG2
29
I
1
Parallel input pin. It controls 12x or 14x serialization and SDR bit clock capture edge. Refer to Table 9
for description.
For 12x serialization with DDR bit clock, tie to ground or AVDD.
CFG3
28
I
1
RESERVED pin - TIE to ground.
CFG4
21
I
1
Parallel input pin. It controls data format and MSB or LSB first modes. Refer to Table 11 for description.
VCM
22
I/O
1
Internal reference mode – common-mode voltage output
External reference mode – reference input. The voltage forced on this pin sets the internal reference.
DA0_P,DA0_M
3,4
O
2
Channel A differential LVDS data output pair, wire 0
DA1_P,DA1_M
1,2
O
2
Channel A differential LVDS data output pair, wire 1
DB0_P,DB0_M
62,63
O
2
Channel B differential LVDS data output pair, wire 0
DB1_P,DB1_M
60,61
O
2
Channel B differential LVDS data output pair, wire 1
DC0_P,DC0_M
52,53
O
2
Channel C differential LVDS data output pair, wire 0
DC1_P,DC1_M
50,51
O
2
Channel C differential LVDS data output pair, wire 1
DD0_P,DD0_M
47,48
O
2
Channel D differential LVDS data output pair, wire 0
DD1_P,DD1_M
45,46
O
2
Channel D differential LVDS data output pair, wire 1
DCLKP,DCLKM
57,58
O
2
Differential bit clock output pair
FCLKP,FCLKM
55,56
O
2
Differential frame clock output pair
The pin has an internal pull-down resistor to ground.
OUTPUT PINS
NC
20
1
Do Not Connect
PAD
0
1
Connect to ground plane using multiple vias. See Board Design Considerations in application section.
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PIN CONFIGURATION (1-WIRE INTERFACE)
LVDD
DD_P
DD_M
DC_P
DC_M
LGND
FCLKP
FCLKM
DCLKP
DCLKM
LGND
DB_P
DB_M
DA_P
LVDD
DA_M
ADS642x
RGC PACKAGE
(TOP VIEW)
UNUSED
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
UNUSED
UNUSED
2
47
UNUSED
UNUSED
3
46
UNUSED
UNUSED
4
45
UNUSED
CAP
5
44
SCLK
RESET
6
43
SDATA
LVDD
7
42
SEN
AGND
8
41
PDN
PAD
IND_P
AGND
13
36
AGND
INB_M
14
35
INC_M
INB_P
15
34
INC_P
AGND
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AGND
AVDD
AVDD
37
AGND
12
CFG1
INA_P
CFG2
IND_M
CFG3
38
AVDD
11
AGND
INA_M
CLKM
AGND
CLKP
39
AGND
10
VCM
AGND
CFG4
AVDD
NC
40
AVDD
9
AGND
AVDD
P0056-07
PIN ASSIGNMENTS (1-WIRE INTERFACE)
PINS
NAME
NO.
I/O
NO. OF
PINS
DESCRIPTION
SUPPLY AND GROUND PINS
AVDD
9,17,19,27,32,40,
6
Analog power supply
AGND
8,10,13,16,18,23,
26,31,33,36,39,
11
Analog ground
LVDD
7,49,64
3
Digital power supply
LGND
54,59
2
Digital ground
INPUT PINS
CLKP, CLKM
24,25
I
2
Differential input clock pair
INA_P, INA_M
12,11
I
2
Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do not float.
INB_P, INB_M
15,14
I
2
Differential input signal pair, channel B. If unused, the pins should be tied to VCM. Do not float.
INC_P, INC_M
34,35
I
2
Differential input signal pair, channel C. If unused, the pins should be tied to VCM. Do not float.
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SLAS532B – MAY 2007 – REVISED DECEMBER 2013
PIN ASSIGNMENTS (1-WIRE INTERFACE) (continued)
PINS
NAME
IND_P, IND_M
NO.
37,38
I/O
NO. OF
PINS
I
2
Differential input signal pair, channel D. If unused, the pins should be tied to VCM. Do not float.
1
Connect 2-nF capacitance from pin to ground
DESCRIPTION
CAP
5
SCLK
44
I
1
This pin functions as serial interface clock input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along with
SDATA). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
SDATA
43
I
1
This pin functions as serial interface data input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along with
SCLK). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
SEN
42
I
1
This pin functions as serial interface enable input when RESET is low.
When RESET is high, it controls coarse gain and internal/external reference modes. Refer to
Table 6 for description.
This pin has an internal pull-up resistor.
Serial interface reset input.
When using the serial interface mode, the user MUST initialize internal registers through hardware
RESET by applying a high-going pulse on this pin or by using software reset option. Refer to the
Serial Interface section. In parallel interface mode, tie RESET permanently high. (SCLK, SDATA
and SEN function as parallel control pins in this mode).
RESET
6
I
1
PDN
41
I
1
Global power down control pin.
CFG1
30
I
1
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock selection. Refer to
Table 8 for description.
Tie to ground for 1-wire interface with DDR bit clock.
CFG2
29
I
1
Parallel input pin. It controls 12x or 14x serialization and SDR bit clock capture edge. Refer to
Table 9 for description.
For 12x serialization with DDR bit clock, tie to ground or AVDD.
CFG3
28
I
1
RESERVED pin - TIE to ground.
CFG4
21
I
1
Parallel input pin. It controls data format and MSB or LSB first modes. Refer to Table 11 for
description.
VCM
22
I/O
1
Internal reference mode – common-mode voltage output
External reference mode – reference input. The voltage forced on this pin sets the internal
reference.
DA_P,DA_M
62,63
O
2
Channel A differential LVDS data output pair
DB_P,DB_M
60,61
O
2
Channel B differential LVDS data output pair
DC_P,DC_M
52,53
O
2
Channel C differential LVDS data output pair
DD_P,DD_M
50,51
O
2
Channel D differential LVDS data output pair
DCLKP,DCLKM
57,58
O
2
Differential bit clock output pair
FCLKP,FCLKM
55,56
O
2
Differential frame clock output pair
1-4,45-48
8
These pins are unused in the 1-wire interface. Do not connect
NC
20
1
Do Not Connect
PAD
0
1
Connect to ground plane using multiple vias. See Board Design Considerations in application
section.
The pin has an internal pull-down resistor to ground.
OUTPUT PINS
UNUSED
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TYPICAL CHARACTERISTICS
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain 32K point FFT
(unless otherwise noted)
ADS6424 (Fsrated = 105 MSPS)
FFT for 10 MHz INPUT SIGNAL
FFT for 100 MHz INPUT SIGNAL
0
SFDR = 91.7 dBc
SINAD = 71.2 dBFS
SNR = 71.2 dBFS
THD = 89.8 dBc
−20
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
50
f − Frequency − MHz
0
10
20
30
40
50
f − Frequency − MHz
G001
G002
Figure 6.
Figure 7.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
0
SFDR = 80 dBc
SINAD = 67.5 dBFS
SNR = 67.8 dBFS
THD = 79.5 dBc
−20
fIN1 = 185.1 MHz, –7 dBFS
fIN2 = 190.1 MHz, –7 dBFS
2-Tone IMD = –88 dBFS
SFDR = –88 dBFS
−20
−40
Amplitude − dB
−40
Amplitude − dB
SFDR = 81.1 dBc
SINAD = 69.7 dBFS
SNR = 70.4 dBFS
THD = 79.8 dBc
−20
Amplitude − dB
−40
Amplitude − dB
0
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
f − Frequency − MHz
50
0
10
20
30
40
f − Frequency − MHz
G003
Figure 8.
50
G004
Figure 9.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
72
92
90
71
Gain = 0 dB
86
SNR − dBFS
SFDR − dBc
88
Gain = 3.5 dB
84
82
70
69
Gain = 3.5 dB
68
80
78
Gain = 0 dB
67
76
74
66
0
50
100
150
200
fIN − Input Frequency − MHz
250
G005
0
50
100
Figure 10.
30
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150
fIN − Input Frequency − MHz
200
250
G006
Figure 11.
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SLAS532B – MAY 2007 – REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain 32K point FFT
(unless otherwise noted)
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
72
92
Input adjusted to get −1dBFS input
90
88
2 dB
70
3 dB
84
82
6 dB
80
69
68
67
2 dB
66
78
4 dB
1 dB
0 dB
76
65
74
64
10
30
50
70
90
5 dB
6 dB
20
110 130 150 170 190 210 230
fIN − Input Frequency − MHz
40
60
80
G007
PERFORMANCE vs AVDD
PERFORMANCE vs LVDD
fIN = 70.1 MHz
LVDD = 3.3 V
77
94
73
fIN = 70.1 MHz
AVDD = 3.3 V
72
75
80
74
78
73
76
72
SNR
3.1
3.2
3.3
86
70
SFDR
82
3.4
78
3.0
70
3.6
3.5
3.1
3.2
PERFORMANCE vs TEMPERATURE
100
74
82
73
80
72
SNR
71
76
SNR − dBFS
SFDR
SFDR − dBc
68
3.6
G010
110
70
85
90
80
80
75
SNR (dBFS)
70
70
60
65
SFDR (dBc)
50
30
−40
69
T − Temperature − °C
90
SFDR (dBFS)
60
40
fIN = 70.1 MHz
60
SFDR − dBc, dBFS
84
40
3.5
PERFORMANCE vs INPUT AMPLITUDE
75
20
3.4
Figure 15.
86
0
3.3
LVDD − Supply Voltage − V
G009
Figure 14.
−20
69
71
AVDD − Supply Voltage − V
78
71
SNR
80
G011
SNR − dBFS
74
90
SNR − dBFS
SFDR
82
SFDR − dBc
76
SNR − dBFS
SFDR − dBc
98
78
84
74
−40
G008
Figure 13.
88
72
3.0
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
Figure 12.
86
1 dB
3 dB
SINAD − dBFS
5 dB
86
SFDR − dBc
3.5 dB
0 dB
71
4 dB
55
fIN = 20.1 MHz
−30
−20
−10
50
0
Input Amplitude − dBFS
Figure 16.
G012
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain 32K point FFT
(unless otherwise noted)
PERFORMANCE vs CLOCK AMPLITUDE
PERFORMANCE vs CLOCK DUTY CYCLE
82
74
90
74
fIN = 20.1 MHz
73
fIN = 70.1 MHz
80
71
84
70
82
69
80
78
72
76
68
SFDR
78
1.0
1.5
2.0
74
66
3.0
2.5
Input Clock Amplitude − VPP
70
72
69
35
40
45
50
60
65
Input Clock Duty Cycle − %
G013
G014
Figure 19.
POWER DISSIPATION vs SAMPLING FREQUENCY
OUTPUT NOISE HISTOGRAM WITH
INPUTS TIED TO COMMON-MODE
2.0
45
1.8
40
1.6
35
RMS (LSB) = 0.407
Occurence − %
1.4
1.2
1.0
AVDD
0.8
0.6
30
25
20
15
10
LVDD
0.4
5
0
0.0
0
20
40
60
80
fS − Sampling Frequency − MSPS
2035 2036 2037 2038 2039 2040 2041 2042 2043 2044
100
G033
Output Code
Figure 20.
CMRR vs FREQUENCY
74
fIN = 70.1 MHz
External Reference Mode
72
SNR
82
70
68
SFDR
81
SNR − dBFS
84
66
80
1.30
1.35
1.40
1.45
1.50
1.55
1.60
VVCM − VCM Voltage − V
1.65
64
1.70
CMRR − Common-Mode Rejection Ratio − dBc
PERFORMANCE IN EXTERNAL REFERENCE MODE
83
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
50
100
150
200
f − Frequency − MHz
G017
Figure 22.
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G016
Figure 21.
85
SFDR − dBc
55
Figure 18.
0.2
32
71
SNR
67
76
0.5
PD − Power Dissipation − W
SFDR − dBc
SNR
86
73
SFDR
72
SNR − dBFS
SFDR − dBc
88
SNR − dBFS
92
250
300
G018
Figure 23.
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ADS6423
ADS6422
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SLAS532B – MAY 2007 – REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain 32K point FFT
(unless otherwise noted)
ADS6423 (Fsrated = 80 MSPS)
FFT for 10 MHz INPUT SIGNAL
FFT for 100 MHz INPUT SIGNAL
0
SFDR = 91.2 dBc
SINAD = 71.2 dBFS
SNR = 71.3 dBFS
THD = 88.3 dBc
−20
SFDR = 85.8 dBc
SINAD = 70.6 dBFS
SNR = 70.9 dBFS
THD = 83.9 dBc
−20
−40
Amplitude − dB
−40
Amplitude − dB
0
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
f − Frequency − MHz
40
0
10
20
G020
Figure 25.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
0
SFDR = 81 dBc
SINAD = 68.3 dBFS
SNR = 68.4 dBFS
THD = 79.5 dBc
−20
fIN1 = 185.1 MHz, –7 dBFS
fIN2 = 190.1 MHz, –7 dBFS
2-Tone IMD = –92 dBFS
SFDR = –93 dBFS
−20
−40
Amplitude − dB
−40
Amplitude − dB
40
f − Frequency − MHz
G019
Figure 24.
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
f − Frequency − MHz
40
0
10
20
30
40
f − Frequency − MHz
G021
Figure 26.
G022
Figure 27.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
94
74
92
73
90
72
Gain = 3.5 dB
88
SNR − dBFS
SFDR − dBc
30
86
84
82
Gain = 0 dB
70
69
Gain = 3.5 dB
68
80
67
78
66
76
65
74
Gain = 0 dB
71
64
0
50
100
150
200
fIN − Input Frequency − MHz
250
G023
0
50
100
150
200
250
fIN − Input Frequency − MHz
Figure 28.
G024
Figure 29.
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ADS6424
ADS6423
ADS6422
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain 32K point FFT
(unless otherwise noted)
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
74
94
Input adjusted to get −1dBFS input
92
72
5 dB
88
86
3 dB
84
6 dB
82
2 dB
71
SINAD − dBFS
90
SFDR − dBc
73
4 dB
3.5 dB
3 dB
0 dB
70
69
68
2 dB
67
80
66
1 dB
78
4 dB
5 dB
65
0 dB
76
6 dB
64
10
30
50
70
90
20
110 130 150 170 190 210 230
fIN − Input Frequency − MHz
40
60
80
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
G025
Figure 30.
G026
Figure 31.
PERFORMANCE vs AVDD
PERFORMANCE vs LVDD
94
92
76
fIN = 50.1 MHz
LVDD = 3.3 V
92
1 dB
91
75
73
fIN = 50.1 MHz
AVDD = 3.3 V
72
88
73
86
72
90
71
89
70
88
69
SFDR
SNR
84
87
71
82
3.0
3.1
3.2
3.3
3.4
86
3.0
70
3.6
3.5
AVDD − Supply Voltage − V
68
3.1
3.2
3.4
3.5
67
3.6
G028
Figure 33.
PERFORMANCE vs TEMPERATURE
92
PERFORMANCE vs INPUT AMPLITUDE
75
fIN = 50.1 MHz
110
90
100
85
88
73
86
72
SNR
84
71
90
80
SFDR (dBFS)
80
75
70
70
SNR (dBFS)
60
65
SFDR (dBc)
50
60
40
82
−40
70
−20
0
20
40
T − Temperature − °C
60
30
−40
80
G029
55
fIN = 20.1 MHz
50
−30
−20
Input Amplitude − dBFS
Figure 34.
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SNR − dBFS
SFDR
SNR − dBFS
74
SFDR − dBc, dBFS
90
SFDR − dBc
3.3
LVDD − Supply Voltage − V
G027
Figure 32.
34
SNR − dBFS
74
SFDR
SFDR − dBc
90
SNR − dBFS
SFDR − dBc
SNR
−10
0
G030
Figure 35.
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ADS6423
ADS6422
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SLAS532B – MAY 2007 – REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain 32K point FFT
(unless otherwise noted)
PERFORMANCE vs CLOCK AMPLITUDE
PERFORMANCE vs CLOCK DUTY CYCLE
75
88
73
SFDR
86
SFDR
72
84
71
SNR
82
70
80
69
78
68
73
80
72
78
76
71
SNR
74
76
0.5
fIN = 50.1 MHz
1.0
1.5
2.0
67
3.0
2.5
70
72
35
40
45
50
G032
Figure 37.
POWER DISSIPATION vs SAMPLING FREQUENCY
OUTPUT NOISE HISTOGRAM WITH
INPUTS TIED TO COMMON-MODE
40
1.8
35
RMS (LSB) = 0.407
1.6
30
1.4
1.2
1.0
AVDD
0.8
0.6
25
20
15
10
0.4
LVDD
5
0.2
0
0.0
0
20
40
60
2036 2037 2038 2039 2040 2041 2042 2043 2044
80
fS − Sampling Frequency − MSPS
G051
Output Code
Figure 38.
CMRR vs FREQUENCY
75
fIN = 50.1 MHz
External Reference Mode
73
SNR
92
71
SFDR
69
88
SNR − dBFS
94
67
1.35
1.40
1.45
1.50
1.55
1.60
VVCM − VCM Voltage − V
1.65
65
1.70
CMRR − Common-Mode Rejection Ratio − dBc
PERFORMANCE IN EXTERNAL REFERENCE MODE
90
G034
Figure 39.
96
SFDR − dBc
69
65
60
Input Clock Duty Cycle − %
G031
2.0
86
1.30
55
Figure 36.
Occurence − %
PD − Power Dissipation − W
Input Clock Amplitude − VPP
SNR − dBFS
74
fIN = 20.1 MHz
SNR − dBFS
90
74
82
SFDR − dBc
SFDR − dBc
92
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
50
G035
Figure 40.
100
150
200
250
300
f − Frequency − MHz
G018
Figure 41.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain 32K point FFT
(unless otherwise noted)
ADS6422 (Fsrated = 65 MSPS)
FFT for 10 MHz INPUT SIGNAL
FFT for 100 MHz INPUT SIGNAL
0
SFDR = 92.5 dBc
SINAD = 71.3 dBFS
SNR = 71.4 dBFS
THD = 90.1 dBc
−20
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
f − Frequency − MHz
0
10
G038
Figure 43.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
fIN1 = 185.1 MHz, –7 dBFS
fIN2 = 190.1 MHz, –7 dBFS
2-Tone IMD = –96 dBFS
SFDR = –87 dBFS
−20
−40
Amplitude − dB
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
f − Frequency − MHz
0
10
20
30
f − Frequency − MHz
G039
Figure 44.
G040
Figure 45.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
96
74
94
73
92
72
90
88
SNR − dBFS
SFDR − dBc
30
f − Frequency − MHz
G037
SFDR = 81.5 dBc
SINAD = 68.1 dBFS
SNR = 68.4 dBFS
THD = 80.3 dBc
−20
Gain = 3.5 dB
86
84
82
Gain = 0 dB
71
70
Gain = 3.5 dB
69
68
80
Gain = 0 dB
67
78
76
66
0
50
100
150
200
fIN − Input Frequency − MHz
250
G041
0
50
100
Submit Documentation Feedback
150
fIN − Input Frequency − MHz
Figure 46.
36
20
Figure 42.
0
Amplitude − dB
SFDR = 86.7 dBc
SINAD = 71 dBFS
SNR = 71.3 dBFS
THD = 83.7 dBc
−20
Amplitude − dB
−40
Amplitude − dB
0
200
250
G042
Figure 47.
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ADS6422
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SLAS532B – MAY 2007 – REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain 32K point FFT
(unless otherwise noted)
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
96
74
Input adjusted to get −1dBFS input
94
92
3 dB
4 dB
88
86
84
6 dB
82
3.5 dB
1 dB
72
2 dB
71
SINAD − dBFS
90
SFDR − dBc
73
5 dB
3 dB
70
69
68
67
2 dB
80
66
1 dB
78
4 dB
5 dB
65
0 dB
76
6 dB
64
10
30
50
70
90
110 130 150 170 190 210 230
fIN − Input Frequency − MHz
20
40
60
80
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
G043
Figure 48.
G044
Figure 49.
PERFORMANCE vs AVDD
PERFORMANCE vs LVDD
94
92
0 dB
92
76
fIN = 50.1 MHz
LVDD = 3.3 V
91
75
73
fIN = 50.1 MHz
AVDD = 3.3 V
72
88
73
86
72
90
71
89
70
SFDR
88
69
87
68
SNR − dBFS
74
SFDR
SFDR − dBc
90
SNR − dBFS
SFDR − dBc
SNR
SNR
84
3.1
3.2
3.3
3.4
86
3.0
70
3.6
3.5
AVDD − Supply Voltage − V
3.1
3.2
3.4
PERFORMANCE vs TEMPERATURE
94
110
90
73
88
72
SNR − dBFS
74
SNR
86
71
SFDR − dBc, dBFS
92
90
100
75
SFDR
90
80
85
SFDR (dBFS)
80
75
SNR (dBFS)
70
60
70
65
SFDR (dBc)
50
60
40
55
fIN = 50.1 MHz
30
−40
70
0
20
40
G046
PERFORMANCE vs INPUT AMPLITUDE
76
−20
67
3.6
Figure 51.
96
84
−40
3.5
LVDD − Supply Voltage − V
G045
Figure 50.
SFDR − dBc
3.3
60
T − Temperature − °C
80
G047
SNR − dBFS
82
3.0
71
fIN = 20.1 MHz
−30
−20
−10
50
0
Input Amplitude − dBFS
Figure 52.
G048
Figure 53.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain 32K point FFT
(unless otherwise noted)
PERFORMANCE vs CLOCK AMPLITUDE
96
PERFORMANCE vs CLOCK DUTY CYCLE
83
78
fIN = 50.1 MHz
94
74
fIN = 20.1 MHz
77
81
88
74
86
73
84
SFDR
79
82
72
77
72
SNR
1.0
1.5
75
70
2.5
2.0
Input Clock Amplitude − VPP
70
73
69
35
40
45
50
60
65
Input Clock Duty Cycle − %
G049
G050
Figure 55.
POWER DISSIPATION vs SAMPLING FREQUENCY
OUTPUT NOISE HISTOGRAM WITH
INPUTS TIED TO COMMON-MODE
2.0
40
1.8
35
RMS (LSB) = 0.407
1.6
30
Occurence − %
1.4
1.2
1.0
0.8
AVDD
0.6
25
20
15
10
0.4
LVDD
5
0
0.0
0
10
20
30
40
50
fS − Sampling Frequency − MSPS
2045 2046 2047 2048 2049 2050 2051 2052 2053 2054
60
G069
Output Code
Figure 56.
CMRR vs FREQUENCY
74
fIN = 50.1 MHz
External Reference Mode
72
SNR
90
70
68
SFDR
88
SNR − dBFS
94
66
1.35
1.40
1.45
1.50
1.55
1.60
VVCM − VCM Voltage − V
1.65
64
1.70
CMRR − Common-Mode Rejection Ratio − dBc
PERFORMANCE IN EXTERNAL REFERENCE MODE
92
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
50
100
150
200
f − Frequency − MHz
G053
Figure 58.
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G052
Figure 57.
96
86
1.30
55
Figure 54.
0.2
SFDR − dBc
71
SNR
71
80
0.5
38
SNR − dBFS
75
SFDR
SFDR − dBc
90
PD − Power Dissipation − W
73
76
SNR − dBFS
SFDR − dBc
92
250
300
G018
Figure 59.
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ADS6424
ADS6423
ADS6422
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SLAS532B – MAY 2007 – REVISED DECEMBER 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain 32K point FFT
(unless otherwise noted)
Contour Plots Across Input and Sampling Frequencies
105
fS - Sampling Frequency - MSPS
100
90
84
87
90
69
81
66
84
75
81
80
72
78
69
84
84
70
63
75
87
90
66
72
78
60
84
84
50
69
78
93
40
87
75
84
96
72
66
84
30
10
50
150
100
200
250
300
400
350
450
500
fIN - Input Frequency - MHz
60
70
65
75
90
85
80
95
SFDR - dBc
M0049-10
Figure 60. SFDR Contour (no gain)
105
95
100
fS - Sampling Frequency - MSPS
89
90
83
86
83
68
83
89
92
71
74
77
80
74
80
80
95
70
92
83
86
89
71
77
68
95
60
74
77
50
95
40
92
98
95
30
10
86
89
83
80
80
68
80
92
50
100
71
150
200
250
77
300
74
400
350
450
500
fIN - Input Frequency - MHz
65
70
75
80
85
SFDR - dBc
90
95
M0049-11
Figure 61. SFDR Contour (3.5 dB coarse gain)
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain 32K point FFT
(unless otherwise noted)
105
100
69
70
71
64
65
fS - Sampling Frequency - MSPS
66
90
67
68
80
70
70
71
65
69
64
66
60
67
68
50
71
66
68
30
10
50
100
200
63
64
67
150
64
65
69
70
40
250
300
62
400
350
450
500
fIN - Input Frequency - MHz
60
66
64
62
68
70
72
SNR - dBFS
M0048-10
Figure 62. SNR Contour (no gain)
105
100
fS - Sampling Frequency - MSPS
68
69
70
65
67
90
66
64
80
68
69
70
65
70
60
67
64
66
50
68
40
70
30
10
50
100
65
69
150
67
200
64
66
250
300
63
63
62
62
61
61
400
350
450
500
fIN - Input Frequency - MHz
60
62
64
68
66
SNR - dBFS
70
M0048-11
Figure 63. SNR Contour (3.5 dB coarse gain)
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SLAS532B – MAY 2007 – REVISED DECEMBER 2013
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS6425/ADS6424/ADS6423/ADS6422 (ADS642X) is a family of quad channel, 12-bit pipeline ADC up to
125 MSPS sampling frequency.
The conversion is initiated simultaneously by all the four channels at the rising edge of the external input clock.
After the input signals are captured by the sample and hold circuit of each channel, the samples are sequentially
converted by a series of low resolution stages. The stage outputs are combined in a digital correction logic block
to form the final 12-bit word with a latency of 12 clock cycles. The 12-bit word of each channel is serialized and
output as LVDS levels. In addition to the data streams, a bit clock and frame clock are also output. The frame
clock is aligned with the 12-bit word boundary.
ANALOG INPUT
The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in
Figure 64. This differential topology results in very good AC performance even for high input frequencies. The
INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V, available on VCM pin
13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5 V
and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The maximum swing is determined by the internal
reference voltages REFP (2.0V nominal) and REFM (1.0 V, nominal). The sampling circuit has a 3 dB bandwidth
that extends up to 500 MHz (see Figure 65, shown by the transfer function from the analog input pins to the
voltage across the sampling capacitors).
Sampling
Switch
Lpkg
3 nH
25 W
Sampling
Capacitor
RCR Filter
INP
Cbond
2 pF
50 W
Resr
200 W
Lpkg
3 nH
3.2 pF
Cpar2 Ron
1 pF 15 W
Cpar1
0.8 pF
Ron
10 W
50 W
Ron
15 W
25 W
INM
Cpar2
1 pF
Cbond
2 pF
Resr
200 W
Csamp
4.0 pF
Csamp
4.0 pF
Sampling
Capacitor
Sampling
Switch
S0237-01
Figure 64. Input Sampling Circuit
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1
Magnitude − dB
0
−1
−2
−3
−4
−5
−6
0
100
200
300
400
500
600
fIN − Input Frequency − MHz
700
G073
Figure 65. Analog Input Bandwidth (represented by magnitude of TF_ADC, see Figure 67 )
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection.
A 5-Ω resistor in series with each input pin is recommended to damp out ringing caused by the package
parasitics. It is also necessary to present low impedance (< 50 Ω) for the common mode switching currents. For
example, this is achieved by using two resistors from each input terminated to the common mode voltage (VCM).
In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the
desired frequency range and matched impedance to the source. While doing this, the ADC input impedance has
to be taken into account. Figure 66 shows that the impedance (Zin, looking into the ADC input pins) decreases at
high input frequencies. The smith chart shows that the input impedance is capacitive and can be approximated
by a series R-C upto 500 MHz.
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SLAS532B – MAY 2007 – REVISED DECEMBER 2013
F1
Freq = 50 MHz
S(1, 1) = 0.967 / –13.241
Impedance = 62.211 – j421.739
1000
F1
Frequency = 50 MHz
Mag(Zin1) = 426.302
900
700
F2
Frequency = 400 MHz
Mag(Zin1) = 65.193
600
F1
500
S(1, 1)
Magnitude of Zin -- W
800
400
F2
300
200
F1
F2
100
0
0
50
100
150
200
250
300
350
400
450
500
fI -- Input Frequency -- MHz
Frequency (100 kHz to 500 MHz)
F2
Freq = 400 MHz
S(1, 1) = 0.273 / –59.329
Impedance = 58.132 – j29.510
M0087-01
Figure 66. ADC Input Impedance, Zin
Using RF-Transformer Based Drive Circuits
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection. An example of input drive using RF transformers is shown in
Figure 67 and Figure 68.
The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated on the
secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by the
sampling circuit from the RF transformer’s leakage inductances. The termination is accomplished by two resistors
connected in series, with the center point connected to the 1.5 V common mode (VCM pin). The value of the
termination resistors (connected to common mode) has to be low (< 100 Ω) to provide a low-impedance path for
the ADC common-mode switching current.
Figure 67 shows a configuration using a single 1:1 turns ratio transformer (for example, WBC1-1) that can be
used for low input frequencies up to 100 MHz.
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TF_ADC
0.1 mF
ADS6xxx
5W
INP
0.1 mF
25 W
25 W
INM
5W
1:1
VCM
S0256-01
Figure 67. Single Transformer Drive Circuit
At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results
in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps
minimize this mismatch, and good performance is obtained for high frequency input signals. Figure 68 shows an
example using two transformers (Coilcraft WBC1-1). An additional termination resistor pair (enclosed within the
shaded box) may be required between the two transformers to improve the balance between the P and M sides.
The center point of this termination must be connected to ground.
ADS6xxx
0.1 mF
5W
INP
50 W
0.1 mF
50 W
50 W
50 W
INM
1:1
5W
1:1
VCM
S0164-04
Figure 68. Two Transformer Drive Circuit
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Using Differential Amplifier Drive Circuits
Figure 69 shows a drive ciruit using a differential amplifier (TI's THS4509) to convert a single-ended input to
differential output that can be interfaced to the ADC input pins. In addition to the single-ended to differential
conversion, the amplifier also provides gain (10dB in Figure 69). As shown in the figure, RFIL helps to isolate the
amplifier output from the switching inputs of the ADC. Together with CFIL, it also forms a low-pass filter that
bandlimits the noise (and signal) at the ADC input. As the amplifier outputs are ac-coupled, the common-mode of
the ADC input pins is set using two resistors connected to VCM.
The amplifier outputs can also be dc-coupled. Using the output common-mode control of the THS4509, the ADC
input pins can be biased to 1.5 V. In this case, use +4-V and –1-V supplies for the THS4509 to ensure it's output
common-mode voltage (1.5 V) is at mid-supply.
RF
+VS
500 W
0.1 mF
RS
0.1 mF 10 mF
RFIL
0.1 mF
5W
INP
RG
0.1 mF
RT
CFIL
200 W
CFIL
200 W
CM THS4509
RG
RFIL
INM
RS || RT
0.1 mF
5W
0.1 mF
500 W
VCM
–VS
ADS6xxx
0.1 mF 10 mF
0.1 mF
RF
S0259-01
Figure 69. Drive Circuit using THS4509
Refer to the EVM User Guide (SLAU196) for more information.
INPUT COMMON MODE
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-μF low-inductance capacitor
connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC
sinks a common-mode current in the order of 155 μA at 125 MSPS (per input pin). Equation 1 describes the
dependency of the common-mode current and the sampling frequency.
155 mAxFs
125 MSPS
(1)
This equation helps to design the output capability and impedance of the CM driving circuit accordingly.
REFERENCE
The ADS642X has built-in internal references REFP and REFM, requiring no external components. Design
schemes are used to linearize the converter load seen by the references; this and the on-chip integration of the
requisite reference capacitors eliminates the need for external decoupling. The full-scale input range of the
converter can be controlled in the external reference mode as explained below. The internal or external reference
modes can be selected by programming the register bit <REF> (refer to Table 13).
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INTREF
Internal
Reference
VCM
1 kW
INTREF
4 kW
EXTREF
REFM
REFP
ADS6xxx
S0165-04
Figure 70. Reference Section
Internal Reference
When the device is in internal reference mode, the REFP and REFM voltages are generated internally. Commonmode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog input pins.
External Reference
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the
VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential
input voltage corresponding to full-scale is given by Equation 2.
Full−scale differential input pp + (Voltage forced on VCM) 1.33
(2)
In this mode, the range of voltage applied on VCM should be 1.45 V to 1.55 V. The 1.5-V common-mode voltage
to bias the input pins has to be generated externally.
COARSE GAIN AND PROGRAMMABLE FINE GAIN
ADS642X includes gain settings that can be used to get improved SFDR performance (compared to 0 dB gain
mode). The gain settings are 3.5 dB coarse gain and programmable fine gain from 0 dB to 6 dB. For each gain
setting, the analog input full-scale range scales proportionally, as listed in Table 21.
The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR. The
fine gain is programmable in 1 dB steps from 0 to 6 dB. With fine gain also, SFDR improvement is achieved, but
at the expense of SNR (there is about 1dB SNR degradation for every 1dB of fine gain).
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So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get
best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the
SFDR improvement is significant with marginal degradation in SINAD.
The gains can be programmed using the register bits <COARSE GAIN> (refer to Table 18) and <FINE GAIN>
(refer to Table 17). Note that the default gain after reset is 0 dB.
Table 21. Full-Scale Range Across Gains
GAIN, dB
TYPE
FULL-SCALE, VPP
0
Default (after reset)
2
3.5
Coarse setting (fixed)
1.34
1
1.78
2
1.59
3
1.42
Fine setting (programmable)
4
1.26
5
1.12
6
1.00
CLOCK INPUT
The ADS642X clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
VCM using internal 5-kΩ resistors as shown in Figure 71. This allows using transformer-coupled drive circuits for
sine wave clock or ac-coupling for LVPECL, LVDS clock sources (see Figure 72 and Figure 74).
VCM
VCM
5 kW
5 kW
CLKP
CLKM
ADS6xxx
S0166-04
Figure 71. Internal Clock Buffer
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0.1 mF
CLKP
Differential Sine-Wave
or PECL or LVDS Clock Input
0.1 mF
CLKM
ADS6xxx
S0167-05
Figure 72. Differential Clock Driving Circuit
Figure 73 shows a typical scheme using PECL clock drive from a CDCM7005 clock driver. SNR performance
with this scheme is comparable with that of a low jitter sine wave clock source.
VCC
Reference Clock
REF_IN
VCC
Y0
CLKP
Y0B
CLKM
CDCM7005
VCXO_INP
OUTM
VCXO_INM
CP_OUT
ADS6xxx
VCXO
OUTP
CTRL
S0238-02
Figure 73. PECL Clock Drive Using CDCM7005
Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin) connected to ground with a
0.1-μF capacitor, as shown in Figure 74.
0.1 mF
CMOS Clock Input
CLKP
0.1 mF
CLKM
ADS6xxx
S0168-07
Figure 74. Single-Ended Clock Driving Circuit
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For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode
noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a non50% duty cycle clock input.
CLOCK BUFFER GAIN
When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is
increased. Hence, it is recommended to use large clock amplitude. Use clock amplitude greater than 1 VPP to
avoid performance degradation.
In addition, the clock buffer has programmable gain to amplify the input clock to support very low clock
amplitude. The gain can be set by programming the register bits <CLKIN GAIN> (refer to Table 14) and
increases monotonically from Gain 0 to Gain 5 settings. Table 22 lists the minimum clock amplitude supported for
each gain setting.
Table 22. Minimum Clock Amplitude Across Gains
CLOCK BUFFER GAIN
MINIMUM CLOCK AMPLITUDE SUPPORTED,
mVPP differential
Gain 0 (minimum gain)
800
Gain 1 (default gain)
400
Gain 2
300
Gain 3
200
Gain 4
150
Gain 5 (highest gain)
100
POWER DOWN MODES
The ADS642X has three power down modes – global power down, channel standby and input clock stop.
Global Power Down
This is a global power down mode in which almost the entire chip is powered down, including the four ADCs,
internal references, PLL and LVDS buffers. As a result, the total power dissipation falls to about 77 mW typical
(with input clock running). This mode can be initiated by setting the register bit <PDN GLOBAL> (refer to
Table 13). The output data and clock buffers are in high impedance state.
The wake-up time from this mode to data becoming valid in normal mode is 100 μs.
Channel Standby
In this mode, only the ADC of each channel is powered down and this helps to get very fast wake-up times. Each
of the four ADCs can be powered down independently using the register bits <PDN CH> (refer to Table 13). The
output LVDS buffers remain powered up.
The wake-up time from this mode to data becoming valid in normal mode is 200 clock cycles.
Input Clock Stop
The converter enters this mode:
• If the input clock frequency falls below 1 MSPS or
• If the input clock amplitude is less than 400 mV (pp, differential with default clock buffer gain setting) at any
sampling frequency.
All ADCs and LVDS buffers are powered down and the power dissipation is about 235 mW. The wake-up time
from this mode to data becoming valid in normal mode is 100 μs.
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Table 23. Power Down Modes Summary
POWER DOWN MODE
AVDD POWER
(mW)
LVDD POWER
(mW)
WAKE UP TIME
In power-up
1360
297
–
Global power down
100 μs
12
(1)
1115
2 Channels in standby
825
(1)
3 Channels in standby
532
(1)
4 Channels in standby
245
(1)
Input clock stop
(1)
65
1 Channel in standby
200
297
(1)
200 Clocks
297
(1)
200 Clocks
297
(1)
200 Clocks
297
(1)
200 Clocks
35
100 μs
Sampling frequency = 125 MSPS.
POWER SUPPLY SEQUENCING
During power-up, the AVDD and LVDD supplies can come up in any sequence. The two supplies are separated
inside the device. Externally, they can be driven from separate supplies or from a single supply.
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DIGITAL OUTPUT INTERFACE
The ADS642X offers several flexible output options making it easy to interface to an ASIC or an FPGA. Each of
these options can be easily programmed using either parallel pins or the serial interface.
The output interface options are:
• 1-Wire, 1× frame clock, 12× and 14× serialization with DDR bit clock
• 2-Wire, 1× frame clock, 12× serialization, with DDR and SDR bit clock, byte wise/bit wise/word wise
• 2-Wire, 1× frame clock, 14× serialization, with SDR bit clock, byte wise/bit wise/word wise
• 2-Wire, (0.5 x) frame clock, 14× serialization, with DDR bit clock, byte wise/bit wise/word wise.
The maximum sampling frequency, bit clock frequency and output data rate will vary depending on the interface
options selected (refer to Table 12).
Table 24. Maximum Recommended Sampling Frequency for Different Output Interface Options
INTERFACE OPTIONS
MAXIMUM
RECOMMENDED
SAMPLING
FREQUENCY,
MSPS
BIT CLOCK
FREQUENCY,
MHZ
FRAME CLOCK
FREQUENCY, MHZ
SERIAL DATA RATE,
Mbps
DDR Bit
clock
12× Serialization
65
390
65
780
14× Serialization
65
455
65
910
2-Wire
DDR Bit
clock
12× Serialization
125
375
125
750
14× Serialization
125
437.5
62.5
875
2-Wire
SDR Bit
clock
12× Serialization
65
390
65
390
14× Serialization
65
455
65
455
1-Wire
Each interface option is described in detail below.
1-WIRE INTERFACE - 12× AND 14× SERIALIZATION WITH DDR BIT CLOCK
Here the device outputs the data of each ADC serially on a single LVDS pair (1-wire). The data is available at the
rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at the rising edge of every
frame clock, starting with the MSB. Optionally, it can also be programmed to output the LSB first. The data rate is
12 × sample frequency (12× serialization) and 14 × sample frequency (14× serialization).
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Input Clock,
CLK
Freq = Fs
14-Bit Serialization
(1)
12-Bit Serialization
Frame Clock,
FCLK
Freq = 1 ´ Fs
Bit Clock,
DCLK
Freq = 6 ´ Fs
Output Data
DA, DB, DC, DD
Data Rate = 12 ´ Fs
D11
(D0)
D10
(D1)
D9
(D2)
D8
(D3)
D7
(D4)
D6
(D5)
D5
(D6)
D7
(D6)
D6
(D7)
D3
(D8)
D4
(D7)
D2
(D9)
D1
(D10)
D0
(D11)
D11
(D0)
D0
(0)
0
(D0)
D10
(D1)
Bit Clock,
DCLK
Freq = 7 ´ Fs
Output Data
DA, DB, DC, DD
Data Rate = 14 ´ Fs
0
(D0)
0
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D5
(D8)
D4
(D9)
D3
D2
(D10) (D11)
D1
(0)
Sample N
0
(D1)
Sample N + 1
Data Bit in MSB First Mode
D13
(D2)
Data Bit in LSB First Mode
(1)
In 14-Bit serialization, two zero bits are padded to the 12-bit ADC data on the MSB side.
T0225-01
Figure 75. 1-Wire Interface
2-WIRE INTERFACE - 12× SERIALIZATION WITH DDR/SDR BIT CLOCK
The 2-wire interface is recommended for sampling frequencies above 65 MSPS. The device outputs the data of
each ADC serially on two LVDS pairs (2-wire). The data rate is 6 × sample frequency since 6 bits are sent on
each wire every clock cycle. The data is available along with DDR bit clock or optionally with SDR bit clock. Each
ADC sample is sent over the 2 wires as byte-wise or bit-wise or word-wise.
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Input Clock,
CLK
Freq = Fs
Frame Clock,
FCLK
Freq = 1 ´ Fs
Bit Clock – SDR,
DCLK
Freq = 6 ´ Fs
In Byte-Wise Mode
Bit Clock – DDR,
DCLK
Freq = 3 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D5
(D0)
D4
(D1)
D3
(D2)
D2
(D3)
D1
(D4)
D0
(D5)
D5
(D0)
D4
(D1)
D3
(D2)
D2
(D3)
D1
(D4)
D0
(D5)
Output Data
DA1, DB1, DC1, DD1
D11
(D6)
D10
(D7)
D9
(D8)
D8
(D9)
D7
D6
D11
(D6)
D10
(D7)
D9
(D8)
D8
(D9)
D7
D6
(D10) (D11)
(D10) (D11)
D10
(D0)
D8
(D2)
D6
(D4)
D4
(D6)
D2
(D8)
(D10)
In Word-Wise Mode
In Bit-Wise Mode
Data Rate = 6 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D10
(D0)
D8
(D2)
D6
(D4)
D4
(D6)
D2
(D8)
(D10)
Output Data
DA1, DB1, DC1, DD1
D11
(D1)
D9
(D3)
D7
(D5)
D5
(D7)
D3
(D9)
(D11)
D11
(D1)
D9
(D3)
D7
(D5)
D5
(D7)
D3
(D9)
(D11)
Output Data
DA0, DB0, DC0, DD0
D11
(D0)
D10
(D1)
D9
(D2)
D8
(D3)
D7
(D4)
D6
(D5)
D5
(D6)
D4
(D7)
D3
(D8)
D2
(D9)
D1
D0
(D10) (D11)
Output Data
DA1, DB1, DC1, DD1
D11
(D0)
D10
(D1)
D9
(D2)
D8
(D3)
D7
(D4)
D6
(D5)
D5
(D6)
D4
(D7)
D3
(D8)
D2
(D9)
(D10) (D11)
D0
D1
Data Bit in MSB First Mode
D1
D0
D1
D0
White Cells – Sample N
D5
(D0)
Data Bit in LSB First Mode
Grey Cells – Sample N + 1
T0226-01
Figure 76. 2-Wire Interface 12× Serialization
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2-WIRE INTERFACE - 14× SERIALIZATION
In 14× serialization, two zero bits are padded to the 14-bit ADC data on the MSB side and the combined 14-bit
data is serialized and output over two LVDS pairs. A frame clock at 1× sample frequency is also available with an
SDR bit clock. With DDR bit clock option, the frame clock frequency is 0.5× sample frequency. The output data
rate will be 7 × sample frequency as 7 data bits are output every clock cycle on each wire. Each ADC sample is
sent over the 2 wires as byte-wise or bit-wise or word-wise.
Using the 14× serialization makes it possible to upgrade to a 14-bit ADC in the 64xx family in the future
seamlessly, without requiring any modification to the receiver capture logic design.
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Input Clock,
CLK
Freq = Fs
Frame Clock,
FCLK
Freq = 1 ´ Fs
In Byte-Wise Mode
Bit Clock – SDR,
DCLK
Freq = 7 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D6
(D0)
D5
(D1)
D4
(D2)
D3
(D3)
D2
(D4)
D1
(D5)
D0
(D6)
D6
(D0)
D5
(D1)
D4
(D2)
D3
(D3)
D2
(D4)
D1
(D5)
D0
(D6)
D6
(D0)
D5
(D1)
Output Data
DA1, DB1, DC1, DD1
0
(D7)
0
(D8)
D11
(D9)
D10
D9
D8
(0)
D7
(0)
0
(D7)
0
(D8)
D11
(D9)
D10
D9
(D10) (D11)
(D10) (D11)
D8
(0)
D7
(0)
0
(D7)
0
(D8)
D2
D0
(0)
0
(D0)
D10
(D2)
D8
(D4)
D6
(D6)
D4
(D8)
D2
(D10)
D0
(0)
0
(D0)
D10
(D2)
(D11)
D1
(0)
0
(D1)
D11
(D3)
D1
(0)
D0
(0)
0
(D0)
0
(D1)
D1
(0)
D0
(0)
0
(D0)
0
(D1)
In Word-Wise Mode
In Bit-Wise Mode
Data Rate = 7 ´ Fs
Output Data
DA0, DB0, DC0, DD0
0
(D0)
D10
(D2)
D8
(D4)
D6
(D6)
D4
(D8)
(D10)
Output Data
DA1, DB1, DC1, DD1
0
(D1)
D11
(D3)
D9
(D5)
D7
(D7)
D5
(D9)
(D11)
D1
(0)
0
(D1)
D11
(D3)
D9
(D5)
D7
(D7)
D5
(D9)
Output Data
DA0, DB0, DC0, DD0
0
(D0)
0
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D5
(D8)
D4
(D9)
D3
D2
(D10) (D11)
Output Data
DA1, DB1, DC1, DD1
0
(D0)
0
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D5
(D8)
D4
(D9)
(D10) (D11)
D3
Data Bit in MSB First Mode
D3
D2
D3
White Cells – Sample N
D6
(D0)
Data Bit in LSB First Mode
Grey Cells – Sample N + 1
T0227-01
Figure 77. 2-Wire Interface 14× Serialization - SDR Bit Clock
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Input Clock,
CLK
Freq = Fs
Frame Clock,
FCLK
Freq = 0.5 ´ Fs
In Byte-Wise Mode
Bit Clock – DDR,
DCLK
Freq = 3.5 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D6
(D0)
D5
(D1)
D4
(D2)
D3
(D3)
D2
(D4)
D1
(D5)
D0
(D6)
D6
(D0)
D5
(D1)
D4
(D2)
D3
(D3)
D2
(D4)
D1
(D5)
D0
(D6)
D6
(D0)
D5
(D1)
Output Data
DA1, DB1, DC1, DD1
0
(D7)
0
(D8)
D11
(D9)
D10
D9
D8
(0)
D7
(0)
0
(D7)
0
(D8)
D11
(D9)
D10
D9
(D10) (D11)
(D10) (D11)
D8
(0)
D7
(0)
0
(D7)
0
(D8)
D2
D0
(0)
0
(D0)
D10
(D2)
D8
(D4)
D6
(D6)
D4
(D8)
D2
(D10)
D0
(0)
0
(D0)
D10
(D2)
(D11)
D1
(0)
0
(D1)
D11
(D3)
D1
(0)
D0
(0)
0
(D0)
0
(D1)
D1
(0)
D0
(0)
0
(D0)
0
(D1)
In Word-Wise Mode
In Bit-Wise Mode
Data Rate = 7 ´ Fs
Output Data
DA0, DB0, DC0, DD0
0
(D0)
D10
(D2)
D8
(D4)
D6
(D6)
D4
(D8)
(D10)
Output Data
DA1, DB1, DC1, DD1
0
(D1)
D11
(D3)
D9
(D5)
D7
(D7)
D5
(D9)
(D11)
D1
(0)
0
(D1)
D11
(D3)
D9
(D5)
D7
(D7)
D5
(D9)
Output Data
DA0, DB0, DC0, DD0
0
(D0)
0
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D5
(D8)
D4
(D9)
D3
D2
(D10) (D11)
Output Data
DA1, DB1, DC1, DD1
0
(D0)
0
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D5
(D8)
D4
(D9)
(D10) (D11)
D3
D3
D2
D3
White Cells – Sample N
Data Bit in MSB First Mode
D6
(D0)
Data Bit in LSB First Mode
Grey Cells – Sample N + 1
T0228-01
A.
In the byte-wise and bit-wise modes, the frame clock frequency is 1 x Fs. In the word-wise mode, the frame clock
frequency is 0.5 x Fs
Figure 78. 2-Wire interface 14× Serialization - DDR Bit Clock
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OUTPUT BIT ORDER
In the 2-wire interface, three types of bit order are supported - byte-wise, bit-wise and word-wise.
Byte-wise: Each 14-bit sample is split across the 2 wires. Wires DA0, DB0, DC0 and DD0 carry the 6 LSB bits
D5-D0 and wires DA1, DB1, DC1 and DD1 carry the 6 MSB bits.
Bit-wise: Each 14-bit sample is split across the 2 wires. Wires DA0, DB0, DC0 and DD0 carry the 6 even bits
(D0,D2,D4..) and wires DA1, DB1, DC1 and DD1 carry the 6 odd bits (D1,D3,D5...).
Word-wise: In this case, all 14-bits of a sample are sent over a single wire. Successive samples are sent over
the 2 wires. For example sample N is sent on wires DA0, DB0, DC0 and DD0, while sample N+1 is sent over
wires DA1, DB1, DC1 and DD1. The frame clock frequency is 0.5x sampling frequency, with the rising edge
aligned with the start of each word.
MSB/LSB FIRST
By default after reset, the 14-bit ADC data is output serially with the MSB first (D11,D10,...D1,D0). The data can
be output LSB first also by programming the register bit <MSB_LSB_First>. In the 2-wire mode, the bit order in
each wire is flipped in the LSB first mode.
OUTPUT DATA FORMATS
Two output data formats are supported – 2s complement (default after reset) and offset binary. They can be
selected using the serial interface register bit <DF>. In the event of an input voltage overdrive, the digital outputs
go to the appropriate full-scale level. For a positive overdrive, the output code is 0xFFF in offset binary output
format, and 0x7FF in 2s complement output format. For a negative input overdrive, the output code is 0x000 in
offset binary output format and 0x800 in 2s complement output format.
LVDS CURRENT CONTROL
The default LVDS buffer current is 3.5 mA. With an external 100-Ω termination resistance, this develops ±350mV logic levels at the receiver. The LVDS buffer currents can also be programmed to 2.5 mA, 3.0 mA, and 4.5
mA using the register bits <LVDS CURR>. In addition, there exists a current double mode, where the LVDS
nominal current is doubled (register bits <CURR DOUBLE>, refer to Table 19).
LVDS INTERNAL TERMINATION
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. Five termination resistances are available – 166, 200, 250, 333, and 500 Ω
(nominal with ±20% variation). Any combination of these terminations can be programmed; the effective
termination will be the parallel combination of the selected resistances. The terminations can be programmed
separately for the clock and data buffers (bits <TERM CLK> and <TERM DATA>, refer to Table 20).
The internal termination helps to absorb any reflections from the receiver end, improving the signal integrity. This
makes it possible to drive up to 10 pF of load capacitance, compared to only 5 pF without the internal
termination.Figure 79 and Figure 80 show the eye diagram with 5-pF and 10-pF load capacitors (connected from
each output pin to ground).
With 100-Ω internal and 100-Ω external termination, the voltage swing at the receiver end will be halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode (bits <CURR DOUBLE>, refer to Table 19).
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C001
Figure 79. LVDS Data Eye Diagram with 5-pF Load Capacitance (No Internal Termination)
C002
Figure 80. LVDS Data Eye Diagram with 10-pF Load Capacitance (100 Ω Internal Termination)
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CAPTURE TEST PATTERNS
ADS642X outputs the bit clock (DCLK), positioned nearly at the center of the data transitions. It is recommended
to route the bit clock, frame clock and output data lines with minimum relative skew on the PCB. This ensures
sufficient setup/hold times for a reliable capture by the receiver.
The DESKEW is a 1010... or 0101... pattern output on the serial data lines that can be used to verify if the
receiver capture clock edge is positioned correctly. This may be useful in case there is some skew between
DCLK and serial data inside the receiver. Once deserialized, it is required to ensure that the parallel data is
aligned to the frame boundary. The SYNC test pattern can be used for this. For example, in the 1-wire interface,
the SYNC pattern is 6 '1's followed by 6 '0's (from MSB to LSB). This information can be used by the receiver
logic to shift the deserialized data until it matches the SYNC pattern.
In addition to DESKEW and SYNC, the ADS642X includes other test patterns to verify correctness of the capture
by the receiver such as all zeros, all ones and toggle. These patterns are output on all four channel data lines
simultaneously. Some patterns like custom and sync are affected by the type of interface selected, serialization
and bit order.
Table 25. Test Patterns
PATTERN
DESCRIPTION
All zeros
Outputs logic low.
All ones
Outputs logic high.
Toggle
Outputs toggle pattern – <D11 – D0> alternates between 101010101010 and 010101010101 every clock cycle.
Custom
Outputs a 12-bit custom pattern. The 12-bit custom pattern can be specified into two serial interface registers. In the 2wire interface, each code is sent over the 2 wires depending on the serialization and bit order.
Sync
Deskew
Outputs a sync pattern.
Outputs deskew pattern. Either <D11 – D0> = 101010101010 or <D11-D0> = 010101010101 every clock cycle.
Table 26. SYNC Pattern
INTERFACE OPTION
SERIALIZATION
1-Wire
2-Wire
SYNC PATTERN ON EACH WIRE
12 X
MSB-111111000000-LSB
14 X
MSB-11111110000000-LSB
12 X
MSB-111000-LSB
14 X
MSB-1111000-LSB
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OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES
Setup, hold and other timing parameters are specified across sampling frequencies and for each type of output
interface in the following tables.
Table 28 to Table 31: Typical values are at 25°C, min and max values are across the full temperature range TMIN
= –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, CL = 5 pF , IO = 3.5 mA, RL = 100 Ω , no internal termination,
unless otherwise noted.
Timing parameters are ensured by design and characterization and not tested in production.
Ts = 1/ Sampling frequency = 1/Fs
Table 27. Clock Propagation Delay and Serializer Latency for different interface options
INTERFACE
SERIALIZATION
CLOCK PROPAGATION DELAY, tpd_clk
12X
tpd_clk = 0.5xTs + tdelay
14X
tpd_clk = 0.428xTs + tdelay
1-Wire with DDR bit clock
2-Wire with DDR bit clock
2-Wire with SDR bit clock
2-Wire with DDR bit clock
12X
(1)
0
tpd_clk = tdelay
1
tpd_clk = 0.5xTs + tdelay
0
2
(when tpd_clk ≥ Ts)
tpd_clk = 0.857xTs + tdelay
14X
2-Wire with SDR bit clock
(1)
SERIALIZER LATENCY
clock cycles
1
(when tpd_clk < Ts)
tpd_clk = 0.428xTs + tdelay
0
Note that the total latency = ADC latency + serializer latency. The ADC latency is 12 clocks.
Table 28. Timings for 1-Wire Interface
SERIALIZATION
12×
14×
DATA SETUP TIME, tsu
ns
DATA HOLD TIME, th
ns
SAMPLING
FREQUENCY
MSPS
MIN
TYP
MIN
TYP
65
0.4
0.6
0.5
0.7
40
0.8
1.0
0.9
1.1
20
1.6
2.0
1.8
2.2
10
3.5
4.0
3.5
4.2
MAX
65
0.3
0.5
0.4
0.6
40
0.65
0.85
0.7
0.9
20
1.3
1.65
1.6
1.9
10
3.2
3.5
3.2
3.6
tdelay
ns
MAX
MIN
TYP
MAX
Fs ≥ 40 MSPS
3
4
5
Fs < 40 MSPS
3
4.5
6
Fs ≥ 40 MSPS
3
4
5
Fs < 40 MSPS
3
4.5
6
Table 29. Timings for 2-Wire Interface, DDR Bit Clock
SERIALIZATION
12×
14×
60
DATA SETUP TIME, tsu
ns
DATA HOLD TIME, th
ns
SAMPLING
FREQUENCY
MSPS
MIN
TYP
MIN
TYP
105
0.55
0.75
0.6
0.8
92
0.65
0.85
0.7
0.9
80
0.8
1.0
0.8
1.05
65
0.9
1.2
1.0
1.3
40
1.7
2.0
1.1
2.1
105
0.45
0.65
0.5
0.7
92
0.55
0.75
0.6
0.8
80
0.65
0.85
0.7
0.9
65
0.8
1.1
0.8
1.1
40
1.4
1.7
1.5
1.9
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MAX
tdelay
ns
MAX
MIN
TYP
MAX
Fs ≥ 45 MSPS
3.4
4.4
5.4
Fs < 45 MSPS
3.7
5.2
6.7
Fs ≥ 45 MSPS
3
4
5
Fs < 45 MSPS
3
4.5
6
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Table 30. Timings for 2-Wire Interface, SDR Bit Clock
SERIALIZATION
DATA SETUP TIME, tsu
ns
DATA HOLD TIME, th
ns
SAMPLING
FREQUENCY
MSPS
MIN
TYP
MIN
TYP
65
1.0
1.2
1.1
1.3
40
1.8
2.0
1.9
2.1
20
3.9
4.1
3.8
4.1
10
8.2
8.4
7.8
8.2
65
0.8
1.0
1.0
1.2
40
1.5
1.7
1.6
1.8
20
3.4
3.6
3.3
3.5
10
6.9
7.2
6.6
6.9
12×
14×
MAX
tdelay
ns
MAX
MIN
TYP
MAX
Fs ≥ 40 MSPS
3.4
4.4
5.4
Fs < 40 MSPS
3.7
5.2
6.7
Fs ≥ 40 MSPS
3.4
4.4
5.4
Fs < 40 MSPS
3.7
5.2
6.7
Table 31. Output Jitter (applies to all interface options)
SAMPLING FREQUENCY
MSPS
BIT CLOCK JITTER, CYCLE-CYCLE
ps, peak-peak
MIN
≥ 65
TYP
MAX
FRAME CLOCK JITTER, CYCLE-CYCLE
ps, peak-peak
MIN
350
TYP
MAX
75
BOARD DESIGN CONSIDERATIONS
Grounding
A single ground plane is sufficient to give optimum performance, provided the analog, digital and clock sections
of the board are cleanly partitioned. Refer to the EVM User Guide (SLAU196) for more layout details.
Supply Decoupling
As the ADS644X already includes internal decoupling, minimal external decoupling can be used without loss in
performance. Note that the decoupling capacitors can help to filter external power supply noise, so the optimum
number of decoupling capacitors would depend on actual application.
It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching
noise from sensitive analog circuitry. In case only a single 3.3-V supply is available, it should be routed first to
AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being
routed to LVDD.
Exposed Thermal Pad
It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal
performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122A) and
QFN/SON PCB Attachment (SLUA271A).
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay will be different across channels. The maximum variation is specified as
aperture delay variation (channel-channel).
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate – The maximum sampling rate at which certified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly
1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – The INL is the deviation of the ADC's transfer function from a best fit line
determined by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – The gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The
gain error is given as a percentage of the ideal input full-scale range. The gain error does not include the error
caused by the internal reference deviation from ideal value. This is specifed separately as internal reference
error. The maximum variation of the gain error across devices and across channels within a device is specified
separately.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC's actual average
idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation
of the parameter across the TMIN to TMAX range by the difference TMAX–TMIN.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),
excluding the power at DC and the first nine harmonics.
P
SNR + 10Log10 S
PN
(3)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s fullscale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
PS
SINAD + 10Log10
PN ) PD
(4)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's fullscale range.
Effective Number of Bits (ENOB) – The ENOB is a measure of a converter’s performance as compared to the
theoretical limit based on quantization noise.
ENOB + SINAD * 1.76
6.02
(5)
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Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the
first nine harmonics (PD).
P
THD + 10Log10 S
PD
(6)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1
and f2) to the power of the worst spectral component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in
units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to
full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range.
DC Power Supply Rejection Ratio (DC PSRR) – The DC PSSR is the ratio of the change in offset error to a
change in analog supply voltage. The DC PSRR is typically given in units of mV/V.
AC Power Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the
supply voltage by the ADC. If ΔVsup is the change in supply voltage and ΔVout is the resultant change of the
ADC output code (referred to the input), then
PSRR + 20Log10 DVout , expressed in dBc
DVsup
(7)
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and
negative overload. The deviation of the first few samples after the overload (from their expected values) is noted.
Common Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variations in the analog input
common-mode by the ADC. If ΔVcm_in is the change in the common-mode voltage of the input pins and ΔVout
is the resultant change of the ADC output code (referred to the input), then
CMRR + 20Log10 DVout , expressed in dBc
DVcm_in
(8)
Cross-Talk (only for multi-channel ADC)– This is a measure of the internal coupling of a signal from adjacent
channel into the channel of interest. It is specified separately for coupling from the immediate neighboring
channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured
by applying a full-scale signal in the adjacent channel. Cross-talk is the ratio of the power of the coupling signal
(as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel
input. It is typically expressed in dBc.
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REVISION HISTORY
Changes from Revision A (June 2007) to Revision B
Page
•
Added Frame setup time and Frame hold time to the TIMING SPECIFICATIONS table .................................................. 10
•
Changed Figure 2 ............................................................................................................................................................... 13
•
Changed text in the USING PARALLEL INTERFACE CONTROL ONLY section From: "The parallel pins can be
configured using a simple resistor string" To: "The parallel pins can be configured using a simple resistor string (with
10% tolerance resistors)" .................................................................................................................................................... 14
•
Changed Figure 3 ............................................................................................................................................................... 15
•
Changed Table 8 ................................................................................................................................................................ 16
•
Changed Table 9 ................................................................................................................................................................ 16
•
Changed Table 11 .............................................................................................................................................................. 17
•
Added Note 3 to Table 12 ................................................................................................................................................... 20
•
Added note to the DESCRIPTION OF SERIAL REGISTERS - “After a hardware or software reset, all register bits
are cleared to ‘0’" ................................................................................................................................................................ 21
•
Added 32K point FFT to TYPICAL CHARACTERISTICS test conditions .......................................................................... 30
•
Added Gain 5 setting to CLOCK BUFFER GAIN section ................................................................................................... 49
•
Added Note A to Figure 78 ................................................................................................................................................. 56
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS6422IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ6422
ADS6422IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ6422
ADS6423IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ6423
ADS6424IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ6424
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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14-Sep-2018
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS6422IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS6422IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS6423IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS6424IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS6422IRGCR
VQFN
RGC
64
2000
350.0
350.0
43.0
ADS6422IRGCT
VQFN
RGC
64
250
213.0
191.0
55.0
ADS6423IRGCT
VQFN
RGC
64
250
213.0
191.0
55.0
ADS6424IRGCT
VQFN
RGC
64
250
213.0
191.0
55.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGC 64
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
9 x 9, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGC0064A
PLASTIC QUADFLAT PACK- NO LEAD
9.15
8.85
B
A
9.15
8.85
PIN 1 INDEX AREA
(0.1)TYP
DETAIL 'A'
OPTION1
1 MAX
(0.2)TYP
DETAIL 'A'
OPTION2
C
SEATING PLANE
0.05
0.00
EXPOSED
THERMAL PAD
0.08 C
2X
7.5
7.25±0.1
32
17
16
33
SEE DETAIL 'A'
60X
0.5
2X
7.5
SYMM
65
64X0.3
0.18
48
1
PIN1 ID
(OPTIONAL)
64
0.1
0.05
C A B
C
49
SYMM
64X0.5
0.3
4219009/A 10/2018
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGC0064A
PLASTIC QUADFLAT PACK- NO LEAD
2X(8.8)
2X(7.5)
64X(0.6)
(
SEE SOLDER MASK
DETAIL
7.25)
64
49
1
48
64X(0.24)
60X(0.5)
SYMM
65
2X(7.5)
4X
(1.14)
2X
(8.8)
2X
(1.1)
(0.05)
(TYP)
33
16
45X (Ø0.2)
(TYP) VIA
4X
(1.14)
17
SYMM
32
2X
(1.1)
LAND PATTERN EXAMPLE
SCALE: 10X
0.07 MAX
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
METAL UNDER
SOLDER MASK
4219009/A 10/2018
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGC0064A
PLASTIC QUADFLAT PACK- NO LEAD
2X (8.8)
2X(7.5)
36X
(0.94)
SYMM
64x(0.6)
64
49
1
48
65
64X(0.24)
60X(0.5)
2X(0.57)
SYMM
2X(7.5)
2X(8.8)
4X(1.14)
(R0.05)
TYP
33
16
EXPOSED METAL
32
17
2X(0.57)
4X(1.14)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
60% PRINTED COVERAGE BY AREA
SCALE: 12X
4219009/A 10/2018
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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