Texas Instruments | 16-Bit, 100-kSPS, Serial Interface, microPower, Miniature, True-Differential Inp (Rev. A) | Datasheet | Texas Instruments 16-Bit, 100-kSPS, Serial Interface, microPower, Miniature, True-Differential Inp (Rev. A) Datasheet

Texas Instruments 16-Bit, 100-kSPS, Serial Interface, microPower, Miniature, True-Differential Inp (Rev. A) Datasheet
ADS8867
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SBAS615A – MAY 2013 – REVISED DECEMBER 2013
16-Bit, 100-kSPS, Serial Interface, microPower, Miniature,
True-Differential Input, SAR Analog-to-Digital Converter
Check for Samples: ADS8867
FEATURES
APPLICATIONS
• Sample Rate: 100 kHz
• No Latency Output
• Unipolar, True-Differential Input Range:
–VREF to +VREF
• Wide Common-Mode Voltage Range:
0 V to VREF with 90-dB CMRR (min)
• SPI™-Compatible Serial Interface with
Daisy-Chain Option
• Excellent AC and DC Performance:
– SNR: 96 dB, THD: –115 dB
– INL: ±1.0 LSB (max)
– DNL: ±1.0 LSB (max), 16-Bit NMC
• Wide Operating Range:
– AVDD: 2.7 V to 3.6 V
– DVDD: 1.65 V to 3.6 V
(Independent of AVDD)
– REF: 2.5 V to 5 V (Independent of AVDD)
– Operating Temperature: –40°C to +85°C
• Low-Power Dissipation:
– 0.7 mW at 100 kSPS
– 70 µW at 10 kSPS
• Power-Down Current (AVDD): 50 nA
• Full-Scale Step Settling to 16 Bits: 1200 ns
• Packages: MSOP-10 and SON-10
•
•
•
•
1
234
Traditional Input Range
ADS8867 Input Range
VDIFF
Automatic Test Equipment (ATE)
Instrumentation and Process Controls
Precision Medical Equipment
Low-Power, Battery-Operated Instruments
DESCRIPTION
The ADS8867 is a 16-bit, 100-kSPS, true-differential
input, analog-to-digital converter (ADC). The device
operates with a 2.5-V to 5-V external reference,
offering a wide selection of signal ranges without
additional input signal scaling. The reference voltage
setting is independent of, and can exceed, the analog
supply voltage (AVDD).
The device offers an SPI-compatible serial interface
that also supports daisy-chain operation for
cascading multiple devices.
The device supports unipolar, true-differential analog
input signals with a differential input swing of –VREF to
+VREF. This true-differential analog input structure
allows for a common-mode voltage of any value in
the range of 0 V to +VREF (when both inputs are
within the operating input range of –0.1 V to VREF
+ 0.1 V).
Device operation is optimized for very low-power
operation. Power consumption directly scales with
speed. This feature makes the ADS8867 excellent for
lower-speed applications.
True-Differential Input Range
+VREF
2.5 V to 5 V
2.7 V to 3.6 V
REF
AVDD
1.65 V to 3.6 V
VREF
VCM
0V
0 V - VREF
DVDD
AINP
VCM
DIN
ADS8867
VREF
SCLK
DOUT
0V
AINM
CONVST
0 V - VREF
VREF/2
GND
-VREF
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TINA is a trademark of Texas Instruments Inc..
SPI is a trademark of Motorola Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
ADS8867
SBAS615A – MAY 2013 – REVISED DECEMBER 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FAMILY INFORMATION (1)
(1)
(2)
THROUGHPUT
18-BIT, TRUE-DIFFERENTIAL
16-BIT, SINGLE-ENDED
16-BIT, TRUE-DIFFERENTIAL
100 kSPS
ADS8887
ADS8866
ADS8867
250 kSPS
—
—
—
400 kSPS
ADS8885
ADS8864
ADS8865
500 kSPS
—
ADS8319 (2)
ADS8318 (2)
680 kSPS
ADS8883
ADS8862
ADS8863
1 MSPS
ADS8881
ADS8860
ADS8861
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
Pin-to-pin compatible device with AVDD = 5 V.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
MIN
MAX
AINP to GND or AINN to GND
–0.3
REF + 0.3
V
AVDD to GND or DVDD to GND
–0.3
4
V
REF to GND
–0.3
5.7
V
Digital input voltage to GND
–0.3
DVDD + 0.3
V
Digital output to GND
–0.3
DVDD + 0.3
V
Operating temperature range, TA
–40
+85
°C
Storage temperature range, Tstg
–65
+150
°C
(1)
UNIT
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under electrical characteristics is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
ADS8867
THERMAL METRIC
(1)
DGS
DRC
10 PINS
10 PINS
θJA
Junction-to-ambient thermal resistance
151.9
111.1
θJCtop
Junction-to-case (top) thermal resistance
45.4
46.4
θJB
Junction-to-board thermal resistance
72.2
45.9
ψJT
Junction-to-top characterization parameter
3.3
3.5
ψJB
Junction-to-board characterization parameter
70.9
45.5
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
N/A
(1)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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ELECTRICAL CHARACTERISTICS
All minimum and maximum specifications are at TA = –40°C to +85°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V,
VCM = VREF / 2 V, and fSAMPLE = 100 kSPS, unless otherwise noted.
Typical specifications are at TA = +25°C, AVDD = 3 V, and DVDD = 3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input span (1) (2)
Operating input range
(1) (2)
AINP – AINN
–VREF
VREF
V
AINP
–0.1
VREF + 0.1
V
AINN
–0.1
VREF + 0.1
V
VCM
Input common-mode range
0
CI
Input capacitance
AINP and AINN terminal to GND
Input leakage current
During acquisition for dc input
VREF / 2
VREF
V
59
pF
5
nA
16
Bits
SYSTEM PERFORMANCE
Resolution
NMC
No missing codes
DNL
Differential linearity
INL
Integral linearity (4)
EO
Offset error
16
(5)
±0.5
1
LSB (3)
–1
±0.5
1
LSB (3)
±1
4
–4
Offset error drift with temperature
EG
Bits
–0.99
mV
±1.5
Gain error
–0.01
Gain error drift with temperature
±0.005
µV/°C
0.01
±0.15
CMRR
Common-mode rejection ratio
With common-mode input signal = 5 VPP at dc
PSRR
Power-supply rejection ratio
At mid-code
90
%FSR
ppm/°C
100
dB
80
Transition noise
dB
0.35
LSB
SAMPLING DYNAMICS
tconv
Conversion time
500
tACQ
Acquisition time
1200
8800
ns
Maximum throughput rate
with or without latency
(1)
(2)
(3)
(4)
(5)
ns
100
kHz
Aperture delay
4
ns
Aperture jitter, RMS
5
ps
Step response
Settling to 16-bit accuracy
1200
ns
Overvoltage recovery
Settling to 16-bit accuracy
1200
ns
Ideal input span, does not include gain or offset error.
Specified for VCM = VREF / 2. Refer to the Analog Input section for the effect of VCM on the full-scale input range.
LSB = least significant bit.
This parameter is the endpoint INL, not best-fit.
Measured relative to actual measured reference.
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ELECTRICAL CHARACTERISTICS (continued)
All minimum and maximum specifications are at TA = –40°C to +85°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V,
VCM = VREF / 2 V, and fSAMPLE = 100 kSPS, unless otherwise noted.
Typical specifications are at TA = +25°C, AVDD = 3 V, and DVDD = 3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
95
MAX
UNIT
DYNAMIC CHARACTERISTICS
At 1 kHz, VREF = 5 V
SINAD
Signal-to-noise + distortion (6)
96.4
dB
At 10 kHz, VREF = 5 V
95.4
dB
At 49 kHz, VREF = 5 V
91.6
dB
96.5
dB
At 10 kHz, VREF = 5 V
95.5
dB
At 49 kHz, VREF = 5 V
92
dB
At 1 kHz, VREF = 5 V
–112
dB
At 10 kHz, VREF = 5 V
–112
dB
At 49 kHz, VREF = 5 V
-102
dB
At 1 kHz, VREF = 5 V
112
dB
At 10 kHz, VREF = 5 V
112
dB
At 49 kHz, VREF = 5 V
102
dB
30
MHz
At 1 kHz, VREF = 5 V
Signal-to-noise ratio (6)
SNR
Total harmonic distortion (6) (7)
THD
SFDR
BW–3dB
Spurious-free dynamic range (6)
95.1
–3-dB small-signal bandwidth
EXTERNAL REFERENCE INPUT
VREF
Input range
2.5
Reference input current
During conversion, 100-kHz sample rate, mid-code
Reference leakage current
CREF
Decoupling capacitor at the REF
input
10
5
V
35
μA
250
nA
22
µF
POWER-SUPPLY REQUIREMENTS
Power-supply
voltage
AVDD
Analog supply
DVDD
Digital supply range
Supply current
AVDD
PVA
Power dissipation
IAPD
Device power-down current (8)
2.7
3
3.6
1.65
1.8
3.6
V
V
100-kHz sample rate, AVDD = 3 V
0.23
0.4
mA
100-kHz sample rate, AVDD = 3 V
0.7
1.2
mW
10-kHz sample rate, AVDD = 3 V
70
μW
50
nA
DIGITAL INPUTS: LOGIC FAMILY (CMOS)
VIH
High-level input voltage
VIL
Low-level input voltage
ILK
Digital input leakage current
1.65 V < DVDD < 2.3 V
0.8 × DVDD
DVDD + 0.3
V
2.3 V < DVDD < 3.6 V
0.7 × DVDD
DVDD + 0.3
V
1.65 V < DVDD < 2.3 V
–0.3
0.2 × DVDD
V
2.3 V < DVDD < 3.6 V
–0.3
0.3 × DVDD
V
±100
nA
0.8 × DVDD
DVDD
V
0
0.2 × DVDD
V
–40
+85
°C
±10
DIGITAL OUTPUTS: LOGIC FAMILY (CMOS)
VOH
High-level output voltage
IO = 500-μA source, CLOAD = 20 pF
VOL
Low-level output voltage
IO = 500-μA sink, CLOAD = 20 pF
TEMPERATURE RANGE
TA
(6)
(7)
(8)
4
Operating free-air temperature
All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale,
unless otherwise specified.
Calculated on the first nine harmonics of the input frequency.
The device automatically enters a power-down state at the end of every conversion, and remains in power-down during the acquisition
phase.
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TIMING CHARACTERISTICS
3-WIRE OPERATION
1/fsample
DIN = HIGH
tconv-max
tACQ
tclkh
th-CK-DO
CONVST
tclkl
tquiet
œœ
SCLK
1
2
td-CNV-DO
D15
DOUT
3
14
15
16
D1
D0
tSCLK
œœ
D14
D13
D2
œœ
twh-CNV-min
td-CK-DO
td-CK-DOhz
Figure 1. 3-Wire Operation: CONVST Functions as Chip Select
Table 1. TIMING REQUIREMENTS: 3-Wire Operation (1)
PARAMETER
MIN
TYP
MAX
UNIT
tACQ
Acquisition time
1200
tconv
Conversion time
500
1/fsample
Time between conversions
twh-CNV
Pulse duration: CONVST high
fSCLK
SCLK frequency
tSCLK
SCLK period
62.5
tclkl
SCLK low time
tclkh
SCLK high time
th-CK-DO
SCLK falling edge to current data invalid
td-CK-DO
SCLK falling edge to next data valid delay
13.4
ns
td-CNV-DO
Enable time: CONVST low to MSB valid
12.3
ns
td-CNV-DOhz
Disable time: CONVST high or last SCLK falling edge to DOUT 3-state (CS mode)
13.2
ns
tquiet
Quiet time
(1)
ns
8800
ns
10000
ns
10
ns
16
MHz
0.45
0.55
tSCLK
0.45
0.55
tSCLK
ns
3
ns
20
ns
All specifications are at TA = –40°C to +85°C, AVDD = 3 V, and DVDD = 3 V, unless otherwise noted.
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4-WIRE OPERATION
1/fsample
tACQ
tconv-max
CONVST
tsu-DI-CNV
twl-CNV
DIN
œœ
SCLK
1
DOUT
D15
2
3
D14
D13
14
15
16
D1
D0
œœ
twh-DI-min
td-DI-DO
D2
œœ
td-DI-DOhz
Figure 2. 4-Wire Operation: DIN Functions as Chip Select
Table 2. TIMING REQUIREMENTS: 4-Wire Operation (1)
PARAMETER
tACQ
Acquisition time
tconv
Conversion time
1/fsample
Time between conversions
twh-DI
MIN
TYP
MAX
1200
500
UNIT
ns
8800
ns
10000
ns
Pulse duration: DIN high
10
ns
twl-CNV
Pulse width: CONVST low
20
td-DI-DO
Delay time: DIN low to MSB valid
12.3
ns
td-DI-DOhz
Delay time: DIN high or last SCLK falling edge to DOUT 3-state
13.2
ns
tsu-DI-CNV
Setup time: DIN high to CONVST rising edge
th-DI-CNV
Hold time: DIN high from CONVST rising edge
(1)
6
ns
7.5
ns
0
ns
All specifications are at TA = –40°C to +85°C, AVDD = 3 V, and DVDD = 3 V, unless otherwise noted.
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DAISY-CHAIN OPERATION
1/fsample
tconv-
tACQ
max
CONVST
th-CK-CNV
SCLK
DIN 1 = LOW
1
2
15
16
17
18
31
32
D15
D14
D1
D0
tsu-DI-CK
tsu-CK-CNV
DOUT 1,
DIN 2
D15
D14
D1
D0
DOUT 2
D15
D15
D1
D0
Device 2 Data
Device 1 Data
Figure 3. Daisy-Chain Operation: Two Devices
Table 3. TIMING REQUIREMENTS: Daisy-Chain (1)
PARAMETER
MIN
TYP
MAX
UNIT
tACQ
Acquisition time
1200
tconv
Conversion time
500
1/fsample
Time between conversions
10000
ns
tsu-CK-CNV
Setup time: SCLK valid to CONVST rising edge
5
ns
th-CK-CNV
Hold time: SCLK valid from CONVST rising edge
5
ns
tsu-DI-CNV
Setup time: DIN low to CONVST rising edge (see )
7.5
ns
th-DI-CNV
Hold time: DIN low from CONVST rising edge
0
ns
tsu-DI-CK
Setup time: DIN valid to SCLK falling edge
1.5
ns
(1)
ns
8800
ns
All specifications are at TA = –40°C to +85°C, AVDD = 3 V, and DVDD = 3 V, unless otherwise noted.
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EQUIVALENT CIRCUITS
500 µA
IOL
1.4 V
DOUT
20 pF
500 µA
IOH
Figure 4. Load Circuit for Digital Interface Timing
DIN
CONVST
SCLK
VIH
VIL
VOH
VOH
VOL
VOL
SDO
Figure 5. Voltage Levels for Timing
8
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PIN CONFIGURATIONS
DGS PACKAGE
VSSOP-10
(TOP VIEW, Not to Scale)
DRC PACKAGE
SON-10
(TOP VIEW, Not to Scale)
REF
1
10
DVDD
AVDD
2
9
DIN
AINP
3
8
SCLK
AINN
4
7
DOUT
GND
5
6
CONVST
REF
1
10
DVDD
AVDD
2
9
DIN
AINP
3
8
SCLK
AINN
4
7
DOUT
GND
5
6
CONVST
Thermal
PAD
PIN ASSIGNMENTS
PIN NAME
PIN
NUMBER
FUNCTION
AINN
4
Analog input
Inverting analog signal input
AINP
3
Analog input
Noninverting analog signal input
AVDD
2
Analog
CONVST
6
Digital input
Convert input.
This pin also functions as the CS input in 3-wire interface mode. Refer to the
Description and Timing Characteristics sections for more details.
Serial data input.
The DIN level at the start of a conversion selects the mode of operation (such as CS
or daisy-chain mode). This pin also serves as the CS input in 4-wire interface mode.
Refer to the Description and Timing Characteristics sections for more details.
DESCRIPTION
Analog power supply.
This pin must be decoupled to GND with a 1-μF capacitor.
DIN
9
Digital input
DOUT
7
Digital output
Serial data output
DVDD
10
Power supply
Digital interface power supply.
This pin must be decoupled to GND with a 1-μF capacitor.
Device ground.
Note that this pin is a common ground pin for both the analog power supply (AVDD)
and digital I/O supply (DVDD). The reference return line is also internally connected to
this pin.
GND
5
Analog, digital
REF
1
Analog
SCLK
8
Digital input
Clock input for serial interface.
Data output (on DOUT) are synchronized with this clock.
Thermal pad
—
Thermal pad
Exposed thermal pad.
Texas Instruments recommends connecting the thermal pad to the printed circuit
board (PCB) ground.
Positive reference input.
This pin must be decoupled with a 10-μF or larger capacitor.
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TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 100 kSPS, unless otherwise noted.
1
Typical Differential Nonlinearity (LSB)
Typical Integral Nonlinearity (LSB)
1
AVDD = 3 V
REF = 2.5 V
TA = 25ƒC
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
±32768
±19661
6553
±6554
ADC Output Code
19660
AVDD = 3 V
REF = 2.5 V
TA = 25ƒC
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
±32768
32767
Figure 6. TYPICAL INL (VREF = 2.5 V)
Typical Differential Nonlinearity (LSB)
Typical Integral Non Linearity (LSB)
19660
32767
C002
1
AVDD = 3 V
REF = 5 V
TA = 25ƒC
0.75
0.50
0.25
0.00
±0.25
±0.50
±0.75
±1.00
±32768
±19661
±6554
6553
19660
ADC Output Code
AVDD = 3 V
REF = 5 V
TA = 25ƒC
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
±32768
32767
±19661
C003
Figure 8. TYPICAL INL (VREF = 5 V)
6553
±6554
ADC Output Code
19660
32767
C004
Figure 9. TYPICAL DNL (VREF = 5 V)
1
1
Maximum INL
AVDD = 3 V
REF = 5 V
Differential Nonlinearity (LSB)
0.75
Integral Nonlinearity (LSB)
6553
±6554
ADC Output Code
Figure 7. TYPICAL DNL (VREF = 2.5 V)
1.00
0.5
0.25
0
-0.25
Minimum INL
-0.5
-0.75
-1
AVDD = 3 V
REF = 5 V
0.75
Maximum DNL
0.5
0.25
0
Minimum DNL
-0.25
-0.5
-0.75
-1
-40
-15
10
35
60
Free-Air Temperature (oC)
85
-40
C00
Figure 10. INL vs TEMPERATURE
10
±19661
C001
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-15
10
35
60
Free-Air Temperature (oC)
85
C00
Figure 11. DNL vs TEMPERATURE
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 100 kSPS, unless otherwise noted.
1
1
Maximum INL
Differential Nonlinearity (LSB)
Integral Nonlinearity (LSB)
0.75
AVDD = 3 V
TA = 25oC
0.5
0.25
0
-0.25
Minimum INL
-0.5
-0.75
Maximum DNL
0.5
0.25
0
-0.25
Minimum DNL
-0.5
-0.75
-1
-1
2.5
3
3.5
4
Reference Voltage (V)
4.5
5
2.5
3.5
4
Reference Voltage (V)
4.5
5
C00
Figure 13. DNL vs REFERENCE VOLTAGE
80
80
AVDD = 3 V
REF = 2.5 V
TA = 25oC
70
AVDD = 3 V
REF = 5 V
TA = 25oC
70
60
Hits per Code (%)
60
Hits per Code (%)
3
C00
Figure 12. INL vs REFERENCE VOLTAGE
50
40
30
50
40
30
20
20
10
10
0
0
-1
0
1
2
ADC Output Code
-1
3
0
1
ADC Output Code
C00
Figure 14. DC INPUT HISTOGRAM (VREF = 2.5 V)
2
C01
Figure 15. DC INPUT HISTOGRAM (VREF = 5 V)
0
0
AVDD = 3 V
REF = 2.5 V
TA = 25ƒC
fIN = 1 kHz
SNR = 93.5 dB
THD = ±118 dB
±40
±60
±80
AVDD = 3 V
REF = 5 V
TA = 25ƒC
fIN = 1 kHz
SNR = 96.1 dB
THD = 112 dB
±20
±40
±60
Power (dB)
±20
Power (dB)
AVDD = 3 V
TA = 25oC
0.75
±100
±120
±80
±100
±120
±140
±140
±160
±160
±180
±180
±200
±200
0
10
20
30
40
Input Frequency (kHz)
50
0
C001
Figure 16. TYPICAL FFT (VREF = 2.5 V)
10
20
30
Input Frequency (kHz)
40
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C002
Figure 17. TYPICAL FFT (VREF = 5 V)
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 100 kSPS, unless otherwise noted.
98
Signal-to-Noise and Distortion (dBFS)
Signal-to-Noise Ratio (dBFS)
98
97
96
95
94
93
92
91
fIN = 1 kHz
90
2.5
3
3.5
4
Reference Voltage (V)
4.5
97
96
95
94
93
92
91
fIN = 1 kHz
90
5
2.5
Figure 18. SNR vs REFERENCE VOLTAGE
Total Harmonic Distortion (dBFS)
Effective Number of Bits
4.5
5
C01
-109
17.5
17
16.5
16
15.5
15
14.5
fIN = 1 kHz
14
fIN = 1 kHz
-111
-113
-115
-117
-119
-121
-123
-125
2.5
3
3.5
4
Reference Voltage (V)
4.5
5
2.5
3
C01
Figure 20. ENOB vs REFERENCE VOLTAGE
3.5
4
Reference Voltage (V)
4.5
5
C01
Figure 21. THD vs REFERENCE VOLTAGE
126
98
fIN = 1 kHz
124
Signal-to-Noise Ratio (dBFS)
Spurious-Free Dynamic Range (dBFS)
3.5
4
Reference Voltage (V)
Figure 19. SINAD vs REFERENCE VOLTAGE
18
122
120
118
116
114
112
110
97
96
95
94
93
92
91
fIN = 1 kHz
90
2.5
3
3.5
4
Reference Voltage (V)
4.5
5
-40
C01
Figure 22. SFDR vs REFERENCE VOLTAGE
12
3
C01
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-15
10
35
60
Free-Air Temperature (oC)
85
C01
Figure 23. SNR vs TEMPERATURE
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TYPICAL CHARACTERISTICS (continued)
98
18
97
17.5
Effective Number of Bits
Signal-to-Noise and Distortion (dBFS)
At TA = +25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 100 kSPS, unless otherwise noted.
96
95
94
93
92
fIN = 1 kHz
17
16.5
16
15.5
15
14.5
91
fIN = 1 kHz
14
90
-40
-15
10
35
60
Free-Air Temperature (oC )
-40
85
Figure 24. SINAD vs TEMPERATURE
Spurious-Free Dynamic Range (dBFS)
Total Harmonic Distortion (dBFS)
-111
-113
-115
-117
-119
-121
fIN = 1 kHz
-125
-40
-15
10
35
60
Free-Air Temperature (oC)
85
C02
126
fIN = 1 kHz
124
122
120
118
116
114
112
110
85
-40
-15
C02
Figure 26. THD vs TEMPERATURE
10
35
60
Free- Air Temperature (oC)
85
C02
Figure 27. SFDR vs TEMPERATURE
1
2.5
Power Consumption (mW)
Analog Supply Current (mA)
10
35
60
Free-Air Temperature (oC)
Figure 25. ENOB vs TEMPERATURE
-109
-123
-15
C01
0.75
0.5
0.25
0
2
1.5
1
0.5
0
-40
-15
10
35
60
Free-Air Temperature (oC)
85
Figure 28. SUPPLY CURRENT vs TEMPERATURE
-40
C00
-15
10
35
60
Free-Air Temperature (oC)
85
C00
Figure 29. POWER CONSUMPTION vs TEMPERATURE
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 100 kSPS, unless otherwise noted.
1
Power Consumption (mW)
Analog Supply Current (mA)
0.4
0.3
0.2
0.1
0.8
0.6
0.4
0.2
0
0
0
20
40
60
Throughput (kSPS)
80
0
100
20
C00
Figure 30. SUPPLY CURRENT vs THROUGHPUT
40
60
Throughput (kSPS)
80
100
C00
Figure 31. POWER CONSUMPTION vs THROUGHPUT
4
200
2
150
Offset (mV)
Power-Down Current (mA)
175
125
100
75
0
-2
50
25
-4
0
-40
-15
10
35
Free-Air Temperature (oC)
60
-40
85
35
60
85
C03
Figure 33. OFFSET vs TEMPERATURE
0.01
Common-Mode Rejection Ratio (dB)
105
0.005
Gain Error (%FS)
10
Free-Air Temperature (oC)
Figure 32. POWER-DOWN CURRENT vs TEMPERATURE
0
-0.005
-0.01
-40
-15
10
35
60
Free-Air Temperature (oC)
85
103
101
99
97
95
93
91
89
87
85
0.001
C03
Figure 34. GAIN ERROR vs TEMPERATURE
14
-15
C03
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0.01
0.1
1
10
Input Frequency (kHz)
100
C03
Figure 35. CMRR vs INPUT FREQUENCY
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = 3 V, DVDD = 3 V, VREF = 5 V, and fSAMPLE = 100 kSPS, unless otherwise noted.
4000
3500
3000
AVDD = 3 V
REF = 5 V
TA = 25oC
5000 Devices
1200
2500
Frequency
Frequency
1500
AVDD = 3 V
REF = 5 V
TA = 25oC
5000 Devices
2000
1500
900
600
1000
300
500
0
-0.01
-0.005
0
0.005
Gain Error (% FS)
0
0.01
-4
Figure 36. TYPICAL DISTRIBUTION OF GAIN ERROR
-2
-1
0
1
Offset (mV)
2
3
4
C03
Figure 37. TYPICAL DISTRIBUTION OF OFFSET ERROR
5000
3500
AVDD = 3 V
REF = 5 V
TA = 25oC
5000 Devices
AVDD = 3 V
REF = 5 V
TA = 25oC
5000 Devices
3000
2500
Frequency
4000
Frequency
-3
C03
3000
2000
2000
1500
1000
1000
500
0
0
-1
-0.5
0
0.5
Differential Nonlinearity Min and Max (LSB)
-1
1
C038
Figure 38. TYPICAL DISTRIBUTION OF DIFFERENTIAL
NONLINEARITY (Minimum and Maximum)
-0.5
0
0.5
Integral Nonlinearity Min and Max (LSB)
1
C039
Figure 39. TYPICAL DISTRIBUTION OF INTEGRAL
NONLINEARITY (Minimum and Maximum)
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OVERVIEW
The ADS8867 is a high-speed, successive approximation register (SAR), analog-to-digital converter (ADC) from
a 16- and 18-bit product family. This compact device features high performance. Power consumption is
inherently low and scales linearly with sampling speed. The architecture is based on charge redistribution, which
inherently includes a sample-and-hold (S/H) function.
The ADS8867 supports a true-differential analog input across two pins (INP and INN). When a conversion is
initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in
progress, both the INP and INN inputs are disconnected from the internal circuit.
The ADS8867 uses an internal clock to perform conversions. The device reconnects the sampling capacitors to
the INP and INN pins after conversion and then enters an acquisition phase. During the acquisition phase, the
device is powered down and the conversion result can be read.
The device digital output is available in SPI-compatible format, which makes interfacing with microprocessors,
digital signal processors (DSPs), or field-programmable gate arrays (FPGAs) easy.
ANALOG INPUT
As shown in Figure 40, the device features a differential analog input. Both positive and negative inputs are
individually sampled on 55-pF sampling capacitors and the device converts for the voltage difference between
the two sampled values: VINP – VINN.
AVDD
REF
DVDD
REF
CONVST
AINP
Sample
and
Hold
AINN
SCLK
SAR
ADC
ADC
SPI
DOUT
DIN
AGND
REFM
DGND
GND
GND
Figure 40. Detailed Block Diagram
16
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Most differential input SAR ADCs prohibit the input common-mode voltage, VCM (that is, the average voltage
between the inputs), at AINP or AINM from varying more than approximately 10% beyond the mid-scale input
value. As shown in Figure 41, the device has a unique common-mode voltage detection and rejection block that
does not have this restriction and thus allows VCM to be set to any value between 0 V and VREF without
degrading device performance.
REF
AINP
+
±
2
Binary
Search
Algorithm
(SAR)
+
±
I
N
T
E
R
F
A
C
E
AINM
Common Mode Voltage
Detection and Rejection
Block
Figure 41. Conceptual Diagram: True Differential Input Structure
Table 4 shows the full-scale input range of the device as a function of input common-mode voltage. The device
offers a maximum dynamic range for VCM = VREF / 2. The differential input with wide common-mode range allows
connecting differential signals from sensors without any signal conditioning.
Table 4. Full-Scale Input Range
ABSOLUTE INPUT RANGE
VCM
VCM < VREF / 2
VAINP
VAINN
0 to 2 × VCM
0 to 2 x VCM
FULL SCALE INPUT RANGE (VFS)
(–2 x VCM) to (2 x VCM)
VCM = VREF / 2
0 to VREF
0 to VREF
(–VREF) to (VREF)
VCM > VREF / 2
(2 × VCM – VREF) to VREF
(2 × VCM – VREF) to VREF
(–2 × (VCM – VREF)) to (2 × (VCM – VREF))
Figure 42 shows an equivalent circuit of the input sampling stage. The sampling switch is represented by a 96-Ω
resistance in series with the ideal switch. Refer to the ADC Input Driver section for more details on the
recommended driving circuits.
Device in Hold Mode
96
AINP
4 pF
55 pF
REF
4 pF
55 pF
96
GND
GND
AINN
Figure 42. Input Sampling Stage Equivalent Circuit
Figure 40 and Figure 42 illustrate electrostatic discharge (ESD) protection diodes to REF and GND from both
analog inputs. Make sure that these diodes do not turn on by keeping the analog inputs within the specified
range.
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REFERENCE
The device operates with an external reference voltage and switches binary-weighted capacitors onto the
reference terminal (REF pin) during the conversion process. The switching frequency is proportional to the
internal conversion clock frequency but the dynamic charge requirements are a function of the absolute value of
the input voltage and reference voltage. This dynamic load must be supported by a reference driver circuit
without degrading the noise and linearity performance of the device. During the acquisition process, the device
automatically powers down and does not take any dynamic current from the external reference source. The basic
circuit diagram for such a reference driver circuit for precision ADCs is shown in Figure 43. Refer to the ADC
Reference Driver section for more details on the application circuits.
RREF_FLT
Buffer
CREF_FLT
RBUF_FLT
Voltage
Reference
REF
CBUF_FLT
ADC
Figure 43. Reference Driver Schematic
CLOCK
The device uses an internal clock for conversion. Conversion duration may vary but is bounded by the minimum
and maximum value of tconv, as specified in the Timing Characteristics section. An external SCLK is only used for
a serial data read operation. Data are read after a conversion completes and when the device is in acquisition
phase for the next sample.
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ADC TRANSFER FUNCTION
The ADS8867 is a unipolar, differential input device. The device output is in twos compliment format.
Figure 44 shows ideal characteristics for the device. The full-scale range for the ADC input (AINP – AINN) is
equal to twice the reference input voltage to the ADC (2 × VREF). The LSB for the ADC is given by Equation 1.
1 LSB = [2 × (VREF / 216)]
(1)
ADC Code (Hex)
7FFF
0000
FFFF
8001
8000
±VREF
+ 1 LSB
±1 LSB
0
VREF
± 1 LSB
VIN
Differential Analog Input
(AINP AINN)
Figure 44. Transfer Characteristics
DIGITAL INTERFACE
The ADS8867 is a low pin-count device. However, the device offers three different options for interfacing with the
digital host.
These options can be broadly classified as being either CS mode (in either a 3- or 4-wire interface) or daisychain mode. The device operates in CS mode if DIN is high at the CONVST rising edge. If DIN is low at the
CONVST rising edge, or if DIN and CONVST are connected together, the device operates in daisy-chain mode.
The 3-wire interface in CS mode is useful for applications that need galvanic isolation on-board. The 4-wire
interface in CS mode allows the user to sample the analog input independent of the serial interface timing and,
therefore, allows easier control of an individual device while having multiple, similar devices on-board. The daisychain mode is provided to hook multiple devices in a chain similar to a shift register and is useful in reducing
component count and the number of signal traces on the board.
CS Mode
CS mode is selected if DIN is high at the CONVST rising edge. There are two different interface options available
in this mode: 3-wire CS mode, and 4-wire CS mode. The following sections discuss these interface options in
detail.
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3-Wire CS Mode
This interface option is most useful when a single ADC is connected to an SPI-compatible digital host. In this
interface option, DIN can be connected to DVDD and CONVST functions as CS (as shown in Figure 45). As
shown in Figure 46, a CONVST rising edge forces DOUT to 3-state, samples the input signal, and causes the
device to enter a conversion phase. Conversion is done with the internal clock and continues regardless of the
state of CONVST. As a result, CONVST (functioning as CS) can be pulled low after the start of the conversion to
select other devices on the board. However, CONVST must return high before the minimum conversion time
(tconv-min) elapses and is held high until the maximum possible conversion time (tconv-max) elapses.
DVDD
DIN
CONVST
CNV
SCLK
CLK
DOUT
SDI
ADC
Digital Host
Figure 45. Connection Diagram: 3-Wire CS Mode (DIN = 1)
1/fsample
DIN = HIGH
CONVST = 1
CONVST
SCLK
1
DOUT
D15
2
3
D14
D13
œœ
14
15
16
D1
D0
œœ
tACQ
tconv-max
tconv-min
ADC
STATE
D2
œœ
Acquiring
Sample N
Conversion Result of Sample N Clocked-out
while Acquiring Sample N+1
Converting
Sample N
End-of-Conversion
Figure 46. Interface Timing Diagram: 3-Wire CS Mode (DIN = 1)
When conversion is complete, the device enters an acquisition phase and powers down. CONVST (functioning
as CS) can be brought low after the maximum conversion time (tconv-max) elapses. On the CONVST falling edge,
DOUT comes out of 3-state and the device outputs the MSB of the data. The lower data bits are output on
subsequent SCLK falling edges. Data are valid on both SCLK edges. Data are valid on both edges of SCLK and
can be captured on either edge. However, a digital host capturing data on the SCLK falling edge can achieve a
faster reading rate (provided th_CK_DO is acceptable). DOUT goes to 3-state after the 16th SCLK falling edge or
when CONVST goes high, whichever occurs first.
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4-Wire CS Mode
This interface option is useful when one or more ADCs are connected to an SPI-compatible digital host.
Figure 47 shows the connection diagram for single ADC, Figure 49 shows the connection diagram for two ADCs.
CS
CNV
DIN
CONVST
DOUT
SDI
SCLK
CLK
ADC
Digital Host
Figure 47. Connection Diagram: Single ADC with 4-Wire CS Mode
In this interface option, DIN is controlled by the digital host and functions as CS. As shown in Figure 48, with DIN
high, a CONVST rising edge selects CS mode, forces DOUT to 3-state, samples the input signal, and causes the
device to enter a conversion phase. In this interface option, CONVST must be held at a high level from the start
of the conversion until all data bits are read. Conversion is done with the internal clock and continues regardless
of the state of DIN. As a result, DIN (functioning as CS) can be pulled low to select other devices on the board.
However, DIN must be pulled high before the minimum conversion time (tconv-min) elapses and remains high until
the maximum possible conversion time (tconv-max) elapses.
1/fsample
tconv-max
tACQ
tconv-min
CONVST
DIN = 1
DIN
SCLK
1
2
DOUT
D15
D14
œœ
15
16
œœ
ADC
STATE
End-ofConversion
Acquiring
Sample N
D1
D0
œœ
Read Sample N
Converting
Sample N
Acquiring Sample N+1
Figure 48. Interface Timing Diagram: Single ADC with 4-Wire CS Mode
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When conversion is complete, the device enters acquisition phase and powers down. DIN (functioning as CS)
can be brought low after the maximum conversion time (tconv-max) elapses. On the DIN falling edge, DOUT comes
out of 3-state and the device outputs the MSB of the data. The lower data bits are output on subsequent SCLK
falling edges. Data are valid on both SCLK edges. Data are valid on both edges of SCLK and can be captured
on either edge. However, a digital host capturing data on the SCLK falling edge can achieve a faster reading rate
(provided th_CK_DO is acceptable). DOUT goes to 3-state after the 16th SCLK falling edge or when DIN goes high,
whichever occurs first.
As shown in Figure 49, multiple devices can be hooked together on the same data bus. In this case, as shown in
Figure 50, the DIN of the second device (functioning as CS for the second device) can go low after the first
device data are read and the DOUT of the first device is in 3-state.
Care must be taken so that CONVST and DIN are not both low together at any time during the cycle.
CS1
CS2
CNV
CONVST
DIN
CONVST
DIN
DOUT
DOUT
SCLK
SDI
SCLK
CLK
ADC #1
ADC #2
Digital Host
Figure 49. Connection Diagram: Two ADCs with 4-Wire CS Mode
1/fsample
tconv-max
tACQ
tconv-min
CONVST
DIN = 1
DIN
(ADC 1)
DIN = 1
DIN
(ADC 2)
SCLK
1
2
DOUT
D15
D14
œœ
15
16
17
18
D0
D15
D14
ADC
STATE
Acquiring
Sample N
Converting
Sample N
32
œœ
œœ
End-ofConversion
œœ
31
D1
D1
D0
œœ
œœ
Read Sample N
ADC 1
Read Sample N
ADC 2
Acquiring Sample N+1
Figure 50. Interface Timing Diagram: Two ADCs with 4-Wire CS Mode
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DAISY-CHAIN MODE
Daisy-chain mode is selected if DIN is low at the time of a CONVST rising edge or if DIN and CONVST are
connected together. The following section discusses this interface option in detail.
Daisy-Chain Mode
This interface option is most useful in applications where multiple ADC devices are used but the digital host has
limited interfacing capability. Figure 51 shows a connection diagram with N ADCs connected in the daisy-chain.
The CONVST pins of all ADCs in the chain are connected together and are controlled by a single pin of the
digital host. Similarly, the SCLK pins of all ADCs in the chain are connected together and are controlled by a
single pin of the digital host. The DIN pin for ADC 1 is connected to GND. The DOUT pin of ADC 1 is connected
to the DIN pin of ADC 2, and so on. The DOUT pin of the last ADC in the chain (ADC N) is connected to the SDI
pin of the digital host.
CNV
CONVST
DIN
DOUT
SCLK
CONVST
DIN
CONVST
DOUT
}
DIN
SCLK
CONVST
DOUT
DIN
SCLK
SDI
DOUT
SCLK
CLK
ADC 1
ADC 2
}
ADC N
ADC N1
Digital Host
Figure 51. Connection Diagram: Daisy-Chain Mode (DIN = 0)
As shown in Figure 52, the device DOUT pin is driven low when DIN and CONVST are low together. With DIN
low, a CONVST rising edge selects daisy-chain mode, samples the analog input, and causes the device to enter
a conversion phase. In this interface option, CONVST must remain high from the start of the conversion until all
data bits are read. When started, the conversion continues regardless of the state of SCLK, however SCLK must
be low at the CONVST rising edge.
tconv-min
1/fsample
tconv-max
tACQ
CONVST
SCLK
1
2
œœ
15
16
17
18
D15
D14
œœ
31
32
DIN 1 = LOW
œœ
DOUT 1
DIN 2
D15
D14
D1
D0
D1
D0
œœ
œœ
D15
DOUT 2
œœ
œœ
End-ofConversion
ADC
STATE
D14
Acquiring
Sample N
Converting
Sample N
D1
D0
œœ
Read Sample N
ADC 2
Read Sample N
ADC 1
Acquiring Sample N+1
Figure 52. Interface Timing Diagram: For Two Devices in Daisy-Chain Mode
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At the end of conversion, every ADC in the chain loads its own conversion result into the internal, 16-bit, shift
register and also outputs the MSB bit of this conversion result on its own DOUT pin. All ADCs enter an
acquisition phase and power-down. On every subsequent SCLK falling edge, the internal shift register of each
ADC latches the data available on its DIN pin and shifts out the next bit of data on its DOUT pin. Therefore, the
digital host receives the data of ADC N, followed by the data of ADC N–1, and so on (in MSB-first fashion). A
total of 16 x N SCLK falling edges are required to capture the outputs of all N devices in the chain. Data are valid
on both SCLK edges. Data are valid on both edges of SCLK and can be captured on either edge. However, a
digital host capturing data on the SCLK falling edge can achieve a faster reading rate (provided th_CK_DO is
acceptable).
POWER SUPPLY
The device has two separate power supplies: AVDD and DVDD. The internal circuits of the device operate on
AVDD; DVDD is used for the digital interface. AVDD and DVDD can be independently set to any value within the
permissible range.
Decouple the AVDD and DVDD pins with GND, using individual 1-µF decoupling capacitors placed in close
proximity to the pin, as shown in Figure 53.
Digital
Supply
REF
Analog
Supply
AVDD
1 µF
DVDD
DIN
AINP
SCLK
AINN
DOUT
GND
CONVST
1 µF
Figure 53. Supply Decoupling
POWER SAVING
The device has an auto power-down feature that powers down the internal circuitry at the end of every
conversion. Referring to Figure 54, the input signal is acquired on the sampling capacitors when the device is in
a power-down state (tacq); at the same time, the result for the previous conversion is available for reading. The
device powers up on the start of the next conversion. During conversion phase (tconv), the device also consumes
current from the reference source (connected to pin REF).
24
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tTHROUGHPUT
Device Phase
tCONV
tACQ
œœ
IREF
tACQ
~50000X
~50000X
œœ
IAVDD
tCONV
2 * tTHROUGHPUT
~1200X
~1200X
~2X
IAVG(AVDD+REF)
Figure 54. Power Scaling with Throughput
The conversion time, tconv, is independent of the SCLK frequency. When operating the device at speeds lower
than the maximum rated throughput, the conversion time, tconv, does not change; the device spends more time in
power-down state. Therefore, as shown in Figure 55, the device power consumption from the AVDD supply and
the external reference source is directly proportional to the speed of operation. Extremely low AVDD power-down
current (50 nA, typical) and extremely low external reference leakage current (250 nA, typical), make this device
ideal for very low throughput applications (such as pulsed measurements).
Analog Supply Current (mA)
0.4
0.3
0.2
0.1
0
0
20
40
60
Throughput (kSPS)
80
100
C00
Figure 55. Power Scaling with Throughput
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ADS8867
SBAS615A – MAY 2013 – REVISED DECEMBER 2013
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APPLICATION INFORMATION
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section details some general principles for designing these circuits, followed by some application circuits
designed using the ADS8867.
ADC REFERENCE DRIVER
The external reference source to the ADS8867 must provide low-drift and very accurate voltage for the ADC
reference input and support the dynamic charge requirements without affecting the noise and linearity
performance of the device. The output broadband noise of most references can be in the order of a few 100
μVRMS. Therefore, to prevent any degradation in the noise performance of the ADC, the output of the voltage
reference must be appropriately filtered by using a low-pass filter with a cutoff frequency of a few hundred Hertz.
After band-limiting the noise of the reference circuit, the next important step is to design a reference buffer that
can drive the dynamic load posed by the reference input of the ADC. The reference buffer must regulate the
voltage at the reference pin such that the value of VREF stays within the 1-LSB error at the start of each
conversion. This condition necessitates the use of a large capacitor, CBUF_FLT (refer to Figure 43) for regulating
the voltage at the reference input of the ADC. The amplifier selected to drive the reference pin should have an
extremely low offset and temperature drift with a low output impedance to drive the capacitor at the ADC
reference pin without any stability issues.
Reference Driver Circuit for VREF = 4.5 V
The application circuit in Figure 56 shows the schematic of a complete reference driver circuit that generates a
voltage of 4.5 V dc using a single 5-V supply. This circuit is suitable to drive the reference of the ADS8867 at
higher sampling rates up to 100 kSPS. The 4.5-V reference voltage in this design is generated by the highprecision, low-noise REF5045 circuit. The output broadband noise of the reference is heavily filtered by a lowpass filter with a 3-dB cutoff frequency of 160 Hz.
20 k
1 µF
-
AVDD
REF5045
Vin
+
Vout
1k
+
1k
+
OPA333
AVDD
+
THS4281
1 µF
0.2
AVDD
Temp
Gnd
1 µF
AVDD
REF AVDD
V
+
AINP
10 µF
Trim
CONVST
ADS8867
AINM
GND
1 µF
Figure 56. Schematic of Reference Driver Circuit with VREF = 4.5 V
The reference buffer is designed with the THS4281 and OPA333 in a composite architecture to achieve superior
dc and ac performance at a reduced power consumption, compared to using a single high-performance amplifier.
The THS4281 is a high-bandwidth amplifier with a very low output impedance of 1 Ω at a frequency of 1 MHz.
The low output impedance makes the THS4281 a good choice for driving a high capacitive load to regulate the
voltage at the reference input of the ADC. The high offset and drift specifications of the THS4281 are corrected
by using a dc-correcting amplifier (OPA333) inside the feedback loop. The composite scheme inherits the
extremely low offset and temperature drift specifications of the OPA333.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, using a similar device, refer to 18-Bit Data Acquisition (DAQ) Block Optimized for 1-μs Full-Scale Step
Response (SLAU512).
26
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SBAS615A – MAY 2013 – REVISED DECEMBER 2013
Reference Driver Circuit for VREF = 2.5 V in Ultralow Power, Lower Throughput Applications
The application circuit in Figure 57Figure 58 shows the schematic of a complete reference driver circuit that
generates a voltage of 2.5 V dc using a single 3.3-V supply. This ultralow power reference block is suitable to
drive the ADS8867 for power-sensitive applications at a relatively lower throughput. This design uses the highprecision REF3325 circuit that provides an accurate 2.5-V reference voltage at an extremely low quiescent
current of 5 µA. The output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB
cutoff frequency of 16 Hz.
1k 1 µF
AVDD
REF3325
IN
AVDD
10 k OUT
+ +
4.7
OPA333
REF AVDD
AINP
V+
GND
1 µF
22 µF
CONVST
ADS8887
AVDD
AINM
GND
Figure 57. Schematic of Reference Driver Circuit with VREF = 2.5 V DC
1k 1 µF
AVDD
REF3325
IN
AVDD
10 k OUT
+ +
4.7
OPA333
REF AVDD
AINP
V+
GND
1 µF
22 µF
CONVST
ADS8867
AVDD
AINM
GND
Figure 58. Schematic of Reference Driver Circuit with VREF = 2.5 V DC
The reference buffer is designed using the low-power OPA333 that can operate from a 3.3-V supply at an
extremely low quiescent current of 28 µA. The wideband noise contribution from the amplifier is limited by a lowpass filter of a cutoff frequency equal to 1.5 kHz, formed by a 4.7-Ω resistor in combination with a 22-µF
capacitor. The 4.7-Ω series resistor creates an additional drop in the reference voltage, which is corrected by a
dual-feedback configuration.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, using a similar device, refer to 18-Bit, 10kSPS Data Acquisition (DAQ) Block Optimized for Ultra Low
Power < 1mW (SLAU514).
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ADC INPUT DRIVER
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a fly-wheel
RC filter. The amplifier is used for signal conditioning of the input voltage and its low output impedance provides
a buffer between the signal source and the switched capacitor inputs of the ADC. The RC filter helps attenuate
the sampling charge injection from the switched-capacitor input stage of the ADC and functions as an antialiasing
filter to band-limit the wideband noise contributed by the front-end circuit. Careful design of the front-end circuit is
critical to meet the linearity and noise performance of a high-precision, 16-bit ADC such as the ADS8867.
Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type as well as the performance
goals of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate
amplifier to drive the inputs of the ADC are:
• Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible
after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance
of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter (refer to the
Antialiasing Filter section) at the inputs of the ADC. Higher bandwidth also minimizes the harmonic distortion
at higher input frequencies. In order to maintain the overall stability of the input driver circuit, the amplifier
bandwidth should be selected as described in Equation 2:
•
§
·
1
¸¸
Unity Gain Bandwidth t 4 u ¨¨
© 2S u RFLT u CFLT ¹
(2)
Noise. Noise contribution of the front-end amplifiers should be as low as possible to prevent any degradation
in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data
acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit
should be kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is bandlimited by designing a low cutoff frequency RC filter, as explained in Equation 3.
2
§ V 1 _ AM P_ PP ·
S
¨
¸
NG u 2 u ¨ f
en2 _ RM S u u f3dB
¸
6
.
6
2
¨
¸
©
¹
d
§ SNR dB ·
¸
20
¹
¨
1 VREF
u
u 10 ©
5
2
where:
•
•
•
•
•
V1 / f_AMP_PP is the peak-to-peak flicker noise in µVRMS,
en_RMS is the amplifier broadband noise density in nV/√Hz,
f–3dB is the 3-dB bandwidth of the RC filter, and
NG is the noise gain of the front-end circuit, which is equal to '1' in a buffer configuration.
THD AMP d THD ADC 10 dB
•
28
(3)
Distortion. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. As a rule of
thumb, to ensure that the distortion performance of the data acquisition system is not limited by the front-end
circuit, the distortion of the input driver should be at least 10 dB lower than the distortion of the ADC, as
shown in Equation 4.
(4)
Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal
must settle within a 16-bit accuracy at the device inputs during the acquisition time window. This condition is
critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data sheets specify
the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the desired 16-bit
accuracy. Therefore, the settling behavior of the input driver should always be verified by TINA™-SPICE
simulations before selecting the amplifier.
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Antialiasing Filter
Converting analog-to-digital signals requires sampling an input signal at a constant rate. Any higher frequency
content in the input signal beyond half the sampling frequency is digitized and folded back into the low-frequency
spectrum. This process is called aliasing. Therefore, an analog, antialiasing filter must be used to remove the
harmonic content from the input signal before being sampled by the ADC. An antialiasing filter is designed as a
low-pass, RC filter, for which the 3-dB bandwidth is optimized based on specific application requirements. For dc
signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow
accurately settling the signal at the inputs of the ADC during the small acquisition time window. For ac signals,
the filter bandwidth should be kept low to band-limit the noise fed into the input of the ADC, thereby increasing
the signal-to-noise ratio (SNR) of the system.
Besides filtering the noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling
charge injection from the switched-capacitor input stage of the ADC. A differential capacitor, CFLT, is connected
across the inputs of the ADC (as shown in Figure 59). This capacitor helps reduce the sampling charge injection
and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition
process. As a rule of thumb, the value of this capacitor should be at least 10 times the specified value of the
ADC sampling capacitance. For the ADS8867, the input sampling capacitance is equal to 59 pF, thus the value
of CFLT should be greater than 590 pF. The capacitor should be a COG- or NPO-type because these capacitor
types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying voltages,
frequency, and time.
RFLT ”22
f 3 dB
2S u R FLT
1
R FLT u C FLT
CFLT •590 pF
V
AINP
+
ADS8867
AINM
GND
RFLT ”22
Figure 59. Antialiasing Filter
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design. For the ADS8867, TI recommends limiting the value of RFLT to a maximum of 22 Ω
in order to avoid any significant degradation in linearity performance. The tolerance of the selected resistors can
be chosen as 1% because the use of a differential capacitor at the input balances the effects resulting from any
resistor mismatch.
The input amplifier bandwidth should be much higher than the cutoff frequency of the antialiasing filter. TI
strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase
margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers
might require more bandwidth than others to drive similar filters. If an amplifier has less than a 40° phase margin
with 22-Ω resistors, using a different amplifier with higher bandwidth or reducing the filter cutoff frequency with a
larger differential capacitor is advisable.
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APPLICATION CIRCUIT EXAMPLES
This section describes some common application circuits using the ADS8867. These data acquisition (DAQ)
blocks are optimized for specific input types and performance requirements of the system. For simplicity, powersupply decoupling capacitors are not shown in these circuit diagrams; refer to the Power Supply section for
suggested guidelines.
DAQ Circuit for a 10-µs, Full-Scale Step Response
The application circuit shown in Figure 60 is optimized for using the ADS8867 at the maximum-specified
throughput of 100 kSPS for a full-scale step input voltage. Such step input signals are common in multiplexed
applications when switching between different channels. In a worst-case scenario, one channel is at the negative
full-scale (NFS) and the other channel is at the positive full-scale (PFS) voltage, in which case the step size is
the full-scale range (FSR) of the ADC when the MUX channel is switched.
In such applications, the primary design requirement is to ensure that the full-scale step input signal settles to 16bit accuracy at the ADC inputs. This condition is critical to achieve the excellent linearity specifications of the
ADC. Therefore, the bandwidth of the antialiasing RC filter should be large enough to allow optimal settling of the
input signal during the ADC acquisition time. The filter capacitor helps reduce the sampling charge injection at
the ADC inputs, but degrades the phase margin of the driving amplifier, thereby leading to stability issues.
Amplifier stability is maintained by the series isolation resistor. Therefore, the component values of the
antialiasing filter should be carefully selected to meet the settling requirements of the system as well as to
maintain the stability of the input driving amplifiers.
REFERENCE DRIVE CIRCUIT
20 k
1 µF
THS4281
+
-
1k
+
AVDD
OPA333
0.2
1 µF
+
1k
+
REF5045
Vout
Vin
AVDD
AVDD
10 µF
Temp
1 µF
Trim
Gnd
1 µF
+
AVDD
VIN+
+
AVDD
+
OPA364
22
REF AVDD
VCM
V
+
AINP
470 pF
CONVST
ADS8867
AINM
GND
+
VIN-
-
CONVST
22
OPA364
+
+
AVDD
INPUT DRIVER
16-Bit 100-kSPS SAR
ADC
Figure 60. DAQ Circuit for 10-µs, Full-Scale Step Response
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, using a similar device, refer to 18-Bit Data Acquisition (DAQ) Block Optimized for 1-μs Full-Scale Step
Response (SLAU512).
30
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Low-Power DAQ Circuit for Excellent Dynamic Performance at 100 kSPS
The application circuit shown in Figure 61 is optimized for using the ADS8867 at the maximum specified
throughput of 100 kSPS for a full-scale sinusoidal signal of 1-kHz frequency. This circuit achieves excellent
dynamic performance for the lowest power consumption. The differential ac input signal is processed through
low-noise and low-power amplifiers configured as unity-gain buffers and a low-pass, RC filter before being fed
into the ADC.
In such applications, the input driver must be low in power and noise as well as able to support rail-to-rail input
and output swing with a single supply. A high amplifier bandwidth is also preferred to help attenuate highfrequency distortion. However, oftentimes bandwidth and noise are traded off with the power consumption of the
amplifier. This circuit uses the OPA313 as the front-end driving amplifier because this device offers relatively low
noise density at ultra-low quiescent currents of 50 µA per channel.
The noise contribution from the front-end amplifier is band-limited by the 3-dB bandwidth of the RC filter, which is
designed to be 30 kHz in this application. To maintain good phase margin, RFLT is selected as 47 Ω instead of
the 22-Ω recommended maximum. The result is a slight degradation in linearity, which is a common tradeoff for
very low-power applications.
REFERENCE DRIVE CIRCUIT
20 k
1 µF
THS4281
+
-
1k
+
AVDD
OPA333
0.2
1 µF
+
1k
+
REF5045
Vout
Vin
AVDD
AVDD
10 µF
Temp
1 µF
Trim
Gnd
1 µF
+
AVDD
VIN+
+
AVDD
+
OPA313
47
REF AVDD
VCM
V
+
AINP
56 nF
CONVST
ADS8867
AINM
GND
+
VIN-
-
CONVST
47
OPA313
+
+
AVDD
INPUT DRIVER
16-Bit 100-kSPS SAR
ADC
Figure 61. DAQ Circuit for Lowest Power and Excellent Dynamic Performance at 100 kSPS
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, using a similar device, refer to 18-Bit, 1-MSPS Data Acquisition (DAQ) Block Optimized for Lowest
Power (SLAU513).
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DAQ Circuit for Lowest Distortion and Noise Performance at 100 kSPS
This section describes two application circuits (Figure 62 and Figure 63) that are optimized for using the
ADS8867 with lowest distortion and noise performance at a throughput of 100 kSPS. In both applications, the
input signal is processed through a high-bandwidth, low-distortion, fully-differential amplifier (FDA) designed in an
inverting gain configuration and a low-pass RC filter before being fed into the ADC.
As a rule of thumb, the distortion from the input driver should be at least 10 dB less than the ADC distortion. The
distortion resulting from variation in the common-mode signal is eliminated by using the FDA in an inverting gain
configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates the
requirement of a rail-to-rail swing at the amplifier input. Therefore, these circuits use the low-power THS4521 as
an input driver, which provides exceptional ac performance because of its extremely low-distortion and highbandwidth specifications.
In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low
without adding distortion to the input signal.
Differential Input Configuration
The circuit in Figure 62 shows a fully-differential DAQ block optimized for low distortion and noise using the
THS4521 and ADS8867. This front-end circuit configuration requires a differential signal at the input of the FDA
and provides a differential output to drive the ADC inputs. The common-mode voltage of the input signal provided
to the ADC is set by the VOCM pin of the THS4521 (not shown in Figure 62). To use the complete dynamic range
of the ADC, VOCM can be set to VREF / 2 by using a simple resistive divider. However, note that the ADS8867
allows the common-mode input voltage (VCM) to be set to any value in the range of 0 V to VREF.
REFERENCE DRIVE CIRCUIT
20 k 1 µF
THS4281
+
0.2
-
1k +
AVDD
OPA333
1 µF
+
1k +
REF5045
Vout
Vin
AVDD
AVDD
10 µF
Temp
1 µF
Trim
Gnd
1 µF
1K 1K AVDD
AVDD
VIN+
VCM
+
10
+
10 nF
REF AVDD
V
+
CONVST
ADS8867
AINM
10
GND
CONVST
+
VIN-
AINP
THS4521
+
-
1K 1K INPUT DRIVER
16-Bit 100-kSPS
SAR ADC
Figure 62. Differential Input DAQ Circuit for Lowest Distortion and Noise at 100 kSPS
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, using a similar device, refer to 18-Bit, 1-MSPS Data Acquisition (DAQ) Block Optimized for Lowest
Distortion and Noise (SLAU515).
32
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SBAS615A – MAY 2013 – REVISED DECEMBER 2013
Single-Ended to Differential Configuration
The circuit in Figure 63 shows a single-ended to differential DAQ block optimized for low distortion and noise
using the THS4521 and the ADS8867. This front-end circuit configuration requires a single-ended ac signal at
the input of the FDA and provides a fully-differential output to drive the ADC inputs. The common-mode voltage
of the input signal provided to the ADC is set by the VOCM pin of the THS4521 (not shown in Figure 63). To use
the complete dynamic range of the ADC, VOCM can be set to VREF / 2 by using a simple resistive divider.
However, note that the ADS8867 allows the common-mode input voltage (VCM) to be set to any value in the
range of 0 V to VREF.
REFERENCE DRIVE CIRCUIT
20 k
1 µF
THS4281
+
-
1k
+
AVDD
OPA333
0.2
1 µF
+
1k
+
REF5045
Vout
Vin
AVDD
AVDD
10 µF
Temp
1 µF
Trim
Gnd
1 µF
1K
1K
AVDD
AVDD
VIN+
+
10
+
REF AVDD
10 nF
CONVST
ADS8867
AINM
10
1K
V
+
AINP
THS4521
+
-
GND
1K
INPUT DRIVER
CONVST
16-Bit 100-kSPS
SAR ADC
Figure 63. Single-Ended to Differential DAQ Circuit for Lowest Distortion and Noise at 100 kSPS
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ADS8867
SBAS615A – MAY 2013 – REVISED DECEMBER 2013
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Ultralow-Power DAQ Circuit at 10 kSPS
The data acquisition circuit shown in Figure 64 is optimized for using the ADS8867 at a reduced throughput of 10
kSPS with ultralow-power consumption (< 1 mW) targeted at portable and battery-powered applications.
In order to save power, this circuit is operated on a single 3.3-V supply. The circuit uses extremely low-power,
dual amplifiers (such as the OPA2333) with a maximum quiescent current of 28 µA per channel to drive the ADC
inputs. The input amplifiers are configured in a modified unity-gain buffer configuration. The filter capacitor at the
ADC inputs attenuates the sampling charge-injection noise from the ADC but effects the stability of the input
amplifiers by degrading the phase margin. This attenuation requires a series isolation resistor to maintain
amplifier stability. The value of the series resistor is directly proportional to the open-loop output impedance of
the driving amplifier to maintain stability, which is high (in the order of kΩ) in the case of low-power amplifiers
such as the OPA333. Therefore, a high value of 1 kΩ is selected for the series resistor at the ADC inputs.
However, this series resistor creates an additional voltage drop in the signal path, thereby leading to linearity and
distortion issues. The dual-feedback configuration used in Figure 64 corrects for this additional voltage drop and
maintains system performance at ultralow-power consumption.
1k REFERENCE DRIVE CIRCUIT
1 µF
REF3325
IN
AVDD
4.7
OPA333
10 k + +
OUT
GND
22 µF
1 µF
AVDD
10 k AVDD
10 nF
REF AVDD
AINP
CONVST
ADS8867
AINM
-
1k GND
CONVST
+
OPA333
+ +
VIN+
VCM
AVDD
4.7 nF
VIN+
+ +
1k OPA333
ADS8867 running at 10 kSPS
-
10 nF
10 k INPUT DRIVER
Figure 64. Ultralow-Power DAQ Circuit at 10 kSPS
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, using a similar device, refer to 18-Bit, 10kSPS Data Acquisition (DAQ) Block Optimized for Ultra Low
Power < 1mW (SLAU514).
34
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SBAS615A – MAY 2013 – REVISED DECEMBER 2013
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (May 2013) to Revision A
Page
•
Changed Wide Common-Mode Voltage Range Features bullet .......................................................................................... 1
•
Changed sub-bullets of AC and DC Performance Features bullet ....................................................................................... 1
•
Changed Full-Scale Step Settling Features bullet ................................................................................................................ 1
•
Deleted last two Applications bullets .................................................................................................................................... 1
•
Changed Description section ................................................................................................................................................ 1
•
Changed front page graphic ................................................................................................................................................. 1
•
Added Family Information, Absolute Maximum Ratings, and Thermal Information tables ................................................... 2
•
Added Electrical Characteristics table .................................................................................................................................. 3
•
Added Timing Characteristics section .................................................................................................................................. 5
•
Added Pin Configurations section ......................................................................................................................................... 9
•
Added Typical Characteristics section ................................................................................................................................ 10
•
Added Overview section ..................................................................................................................................................... 16
•
Added Application Information section ............................................................................................................................... 26
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35
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS8867IDGS
ACTIVE
VSSOP
DGS
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
8867
ADS8867IDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
8867
ADS8867IDRCR
ACTIVE
VSON
DRC
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
8867
ADS8867IDRCT
ACTIVE
VSON
DRC
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
8867
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS8867IDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
ADS8867IDRCR
VSON
DRC
10
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
ADS8867IDRCT
VSON
DRC
10
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS8867IDGSR
VSSOP
DGS
10
2500
367.0
367.0
35.0
ADS8867IDRCR
VSON
DRC
10
3000
367.0
367.0
35.0
ADS8867IDRCT
VSON
DRC
10
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
SCALE 3.200
SMALL OUTLINE PACKAGE
C
5.05
TYP
4.75
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
10
1
3.1
2.9
NOTE 3
8X 0.5
2X
2
5
6
B
10X
3.1
2.9
NOTE 4
SEE DETAIL A
0.27
0.17
0.1
C A
1.1 MAX
B
0.23
TYP
0.13
0.25
GAGE PLANE
0 -8
0.15
0.05
0.7
0.4
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (0.3)
10X (1.45)
(R0.05)
TYP
SYMM
1
10
SYMM
8X (0.5)
6
5
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
10X (0.3)
SYMM
1
(R0.05) TYP
10
SYMM
8X (0.5)
6
5
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DRC 10
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204102-3/M
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