Texas Instruments | ADC121S051 Single Channel, 200 to 500 ksps, 12-Bit A/D Converter (Rev. I) | Datasheet | Texas Instruments ADC121S051 Single Channel, 200 to 500 ksps, 12-Bit A/D Converter (Rev. I) Datasheet

Texas Instruments ADC121S051 Single Channel, 200 to 500 ksps, 12-Bit A/D Converter (Rev. I) Datasheet
ADC121S051
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ADC121S051 Single Channel, 200 to 500 ksps, 12-Bit A/D Converter
Check for Samples: ADC121S051
FEATURES
DESCRIPTION
•
•
•
•
•
The ADC121S051 is a low-power, single channel
CMOS 12-bit analog-to-digital converter with a highspeed serial interface. Unlike the conventional
practice of specifying performance at a single sample
rate only, the ADC121S051 is fully specified over a
sample rate range of 200 ksps to 500 ksps. The
converter is based upon a successive-approximation
register architecture with an internal track-and-hold
circuit.
1
2
Specified Over a Range of Sample Rates.
6-lead WSON and SOT-23 Packages
Variable Power Management
Single Power Supply with 2.7V - 5.25V Range
SPI™/QSPI™/MICROWIRE/DSP Compatible
APPLICATIONS
•
•
•
Portable Systems
Remote Data Acquisition
Instrumentation and Control Systems
The output serial data is straight binary, and is
compatible with several standards, such as SPI™,
QSPI™, MICROWIRE, and many common DSP
serial interfaces.
KEY SPECIFICATIONS
•
•
•
•
The ADC121S051 operates with a single supply that
can range from +2.7V to +5.25V. Normal power
consumption using a +3.6V or +5.25V supply is 1.7
mW and 8.7 mW, respectively. The power-down
feature reduces the power consumption to as low as
2.6 µW using a +5.25V supply.
DNL +0.5/-0.25 LSB (typ)
INL +0.45/-0.40 LSB (typ)
SNR 72.0 dB (typ)
Power Consumption
– 3.6V Supply 1.7 mW (typ)
– 5.25V Supply 8.7 mW (typ)
The ADC121S051 is packaged in 6-lead WSON and
SOT-23 packages. Operation over the industrial
temperature range of −40°C to +85°C is ensured.
PIN COMPATIBLE ALTERNATIVES BY RESOLUTION AND SPEED (1)
Resolution
(1)
Specified for Sample Rate Range of:
50 to 200 ksps
200 to 500 ksps
500 ksps to 1 Msps
12-bit
ADC121S021
ADC121S051
ADC121S101
10-bit
ADC101S021
ADC101S051
ADC101S101
8-bit
ADC081S021
ADC081S051
ADC081S101
All devices are fully pin and function compatible.
Connection Diagram
VA
1
GND
2
VIN
3
ADC121S051
6
CS
5
SDATA
4
SCLK
Figure 1. 6-Lead SOT-23 or WSON
See DBV or NGF Package
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Block Diagram
VIN
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
SCLK
CONTROL
LOGIC
CS
SDATA
Figure 2.
Table 1. PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Pin No.
Symbol
Description
ANALOG I/O
3
VIN
Analog input. This signal can range from 0V to VA
DIGITAL I/O
4
SCLK
Digital clock input. This clock directly controls the conversion and readout processes.
5
SDATA
Digital data output. This clock directly controls the conversion and readout processes.
6
CS
Chip select. On the falling edge of CS, a conversion process begins.
1
VA
Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and
bypassed to GND with a 1 μF capacitor and a 0.1 μF monolithic capacitor located within 1
cm of the power pin.
2
GND
The ground return for the supply and signals.
PAD
GND
For package suffix CISD(X) only, it is recommended that the center pad should be
connected to ground.
POWER SUPPLY
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings (1) (2) (3)
−0.3V to 6.5V
Analog Supply Voltage VA
−0.3V to 6.5V
Voltage on Any Digital Pin to GND
−0.3V to (VA +0.3V)
Voltage on Any Analog Pin to GND
Input Current at Any Pin
Package Input Current
(4)
±10 mA
(4)
±20 mA
(5)
Power Consumption at TA = 25°C
See
ESD Susceptibility (6)
Human Body Model
Machine Model
3500V
300V
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
(1)
(2)
(3)
(4)
(5)
(6)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
All voltages are measured with respect to GND = 0V, unless otherwise specified.
When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to
10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an
input current of 10 mA to two. The Absolute Maximum Rating specification does not apply to the VA pin. The current into the VA pin is
limited by the Analog Supply Voltage specification.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDmax = (TJmax − TA) / θJA. The values for maximum power dissipation listed above will be reached only when the device is operated
in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is
reversed). Obviously, such conditions should always be avoided.
Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms.
Operating Ratings (1) (2)
−40°C ≤ TA ≤ +85°C
Operating Temperature Range
VA Supply Voltage
+2.7V to +5.25V
Digital Input Pins Voltage Range
(regardless of supply voltage)
−0.3V to +5.25V
Analog Input Pins Voltage Range
0V to VA
Clock Frequency
25 kHz to 20 MHz
Sample Rate
(1)
(2)
up to 1Msps
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to GND = 0V, unless otherwise specified.
Package Thermal Resistance (1)
θJA
Package
6-lead WSON
94°C / W
6-lead SOT-23
265°C / W
Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com and http://www.ti.com/lit/SNOA549.
(1)
Reflow temperature profiles are different for lead-free and non-lead-free packages.
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ADC121S051 Converter Electrical Characteristics (1) (2)
The following specifications apply for VA = +2.7V to 5.25V, fSCLK = 4 MHz to 10 MHz, fSAMPLE = 200 ksps to 500 ksps, CL = 15
pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
Symbol
Parameter
Conditions
Typical
Limits
(2)
Units
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
12
+0.45
VA = +2.7V to +3.6V
INL
−0.40
Integral Non-Linearity
+0.75
VA = +4.75 to +5.25V
Differential Non-Linearity
VA = +4.75 to +5.25V
VOFF
Offset Error
GE
Gain Error
LSB (min)
LSB (max)
−0.45
VA = +2.7V to +3.6V
DNL
±1.0
Bits
LSB (max)
LSB (min)
+0.50
+1.0
−0.25
−0.9
LSB (max)
LSB (min)
+0.80
LSB (max)
−0.50
LSB (min)
VA = +2.7V to +3.6V
−0.18
VA = +4.75 to +5.25V
+1.9
VA = +2.7V to +3.6V
−0.62
VA = +4.75 to +5.25V
−1.50
±1.2
±1.5
LSB (max)
LSB (max)
DYNAMIC CONVERTER CHARACTERISTICS
SINAD
Signal-to-Noise Plus Distortion Ratio
VA = +2.7V to 5.25V
fIN = 100 kHz, −0.02 dBFS
72
70
dB (min)
SNR
Signal-to-Noise Ratio
VA = +2.7V to 5.25V
fIN = 100 kHz, −0.02 dBFS
72
70.8
dB (min)
THD
Total Harmonic Distortion
VA = +2.7V to 5.25V
fIN = 100 kHz, −0.02 dBFS
−83
dB
SFDR
Spurious-Free Dynamic Range
VA = +2.7V to 5.25V
fIN = 100 kHz, −0.02 dBFS
84
dB
ENOB
Effective Number of Bits
VA = +2.7V to 5.25V
fIN = 100 kHz, −0.02 dBFS
11.7
Intermodulation Distortion, Second
Order Terms
VA = +5.25V
fa = 103.5 kHz, fb = 113.5 kHz
−83
dB
Intermodulation Distortion, Third Order
Terms
VA = +5.25V
fa = 103.5 kHz, fb = 113.5 kHz
−82
dB
VA = +5V
11
MHz
VA = +3V
8
MHz
IMD
FPBW
-3 dB Full Power Bandwidth
11.3
Bits (min)
ANALOG INPUT CHARACTERISTICS
VIN
Input Range
IDCL
DC Leakage Current
CINA
Input Capacitance
0 to VA
V
±1
µA (max)
Track Mode
30
pF
Hold Mode
4
pF
DIGITAL INPUT CHARACTERISTICS
VIH
Input High Voltage
VIL
Input Low Voltage
IIN
Input Current
CIND
Digital Input Capacitance
(1)
(2)
4
VA = +5.25V
2.4
VA = +3.6V
2.1
V (min)
VA = +5V
0.8
V (max)
VA = +3V
VIN = 0V or VA
V (min)
0.4
V (max)
±0.1
±1
µA (max)
2
4
pF (max)
Tested limits are specified to National's AOQL (Average Outgoing Quality Level).
Data sheet min/max specification limits are ensured by design, test, or statistical analysis.
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ADC121S051 Converter Electrical Characteristics(1)(2) (continued)
The following specifications apply for VA = +2.7V to 5.25V, fSCLK = 4 MHz to 10 MHz, fSAMPLE = 200 ksps to 500 ksps, CL = 15
pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
Symbol
Parameter
Conditions
Limits
Typical
(2)
Units
VA − 0.2
V (min)
0.4
V (max)
±0.1
±10
µA (max)
2
4
pF (max)
DIGITAL OUTPUT CHARACTERISTICS
VOH
Output High Voltage
VOL
Output Low Voltage
ISOURCE = 200 µA
VA − 0.07
ISOURCE = 1 mA
VA − 0.1
ISINK = 200 µA
0.03
ISINK = 1 mA
IOZH, IOZL TRI-STATE® Leakage Current
COUT
TRI-STATE® Output Capacitance
V
0.1
Output Coding
V
Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS
VA
Supply Voltage
Supply Current, Normal Mode
(Operational, CS low)
IA
Supply Current, Shutdown (CS high)
Power Consumption, Normal Mode
(Operational, CS low)
PD
Power Consumption, Shutdown (CS
high)
2.7
V (min)
5.25
V (max)
VA = +5.25V,
fSAMPLE = 200 ksps
1.66
3.0
mA (max)
VA = +3.6V,
fSAMPLE = 200 ksps
0.46
1.3
mA (max)
VA = +5.25V, fSCLK = 0 MHz,
fSAMPLE = 0 ksps
500
nA
VA = +5.25V, fSCLK = 10 MHz,
fSAMPLE = 0 ksps
60
µA
VA = +5.25V
8.7
15.8
mW (max)
VA = +3.6V
1.7
4.7
mW (max)
VA = +5.25V, fSCLK = 0 MHz,
fSAMPLE = 0 ksps
2.6
µW
VA = +5.25V, fSCLK = 10 MHz,
fSAMPLE = 0 ksps
315
µW
AC ELECTRICAL CHARACTERISTICS
4
MHz (min)
10
MHz (max)
Clock Frequency
fS
Sample Rate
DC
SCLK Duty Cycle
tACQ
Minimum Time Required for Acquisition
tQUIET
See
tAD
Aperture Delay
3
ns
tAJ
Aperture Jitter
30
ps
(3)
(4)
See
(3)
fSCLK
See
(3)
fSCLK = 10 MHz
50
(4)
200
ksps (min)
500
ksps (max)
40
% (min)
60
% (max)
350
ns (max)
50
ns (min)
This is the frequency range over which the electrical performance is ensured. The device is functional over a wider range which is
specified under Operating Ratings.
Minimum Quiet Time required by bus relinquish and the start of the next conversion.
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ADC121S051 Timing Specifications
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 4.0 MHz to 10.0 MHz, CL = 25 pF, fSAMPLE = 200
ksps to 500 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
Symbol
Parameter
Conditions
tCS
Minimum CS Pulse Width
tSU
CS to SCLK Setup Time
tEN
Delay from CS Until SDATA TRI-STATE Disabled
tACC
Data Access Time after SCLK Falling Edge
(2)
Typical
Limits
Units
10
ns (min)
10
ns (min)
20
ns (max)
VA = +2.7V to +3.6V
40
ns (max)
VA = +4.75V to +5.25V
20
ns (max)
(1)
tCL
SCLK Low Pulse Width
0.4 x tSCLK
ns (min)
tCH
SCLK High Pulse Width
0.4 x tSCLK
ns (min)
7
ns (min)
tH
VA = +2.7V to +3.6V
SCLK to Data Valid Hold Time
VA = +4.75V to +5.25V
VA = +2.7V to +3.6V
tDIS
SCLK Falling Edge to SDATA High Impedance
(3)
VA = +4.75V to +5.25V
tPOWER-
Power-Up Time from Full Power-Down
1
5
ns (min)
25
ns (max)
6
ns (min)
25
ns (max)
5
ns (min)
µs
UP
(1)
(2)
(3)
Measured with the timing test circuit shown in Figure 3 and defined as the time taken by the output signal to cross 1.0V.
Measured with the timing test circuit shown in Figure 3 and defined as the time taken by the output signal to cross 1.0V or 2.0V.
tDIS is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in Figure 3. The measured number
is then adjusted to remove the effects of charging or discharging the output capacitance. This means that tDIS is the true bus relinquish
time, independent of the bus loading.
Timing Diagrams
IOL
200 PA
To Output Pin
1.6 V
CL
25 pF
IOH
200 PA
Figure 3. Timing Test Circuit
6
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Hold
Track
|
CS
tCS
tSU
tACQ
tCL
1
2
3
4
12
13
14
15
16
Z1
Z0
DB11
3 leading zero bits
17
18
19
20
tQUIET
tCH
|
Z2
5
tACC
tEN
SDATA
|
SCLK
tH
tDIS
TRI-STATE
DB3
DB2
DB1
DB0
12 data bits
Figure 4. ADC121S051 Serial Timing Diagram
Specification Definitions
ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold
capacitor to charge up to the input voltage. Acquisition time is measured backwards from the falling edge
of CS when the signal is sampled and the part moves from track to hold. The start of the time interval that
contains TACQ is the 13th rising edge of SCLK of the previous conversion when the part moves from hold
to track. The user must ensure that the time between the 13th rising edge of SCLK and the falling edge of
the next CS is not less than TACQ to meet performance specifications.
APERTURE DELAY is the time after the falling edge of CS to when the input signal is acquired or held for
conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.
Aperture jitter manifests itself as noise in the output.
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word. This is from the falling edge of CS when the input signal is sampled to the 16th
falling edge of SCLK when the SDATA output goes into TRI-STATE.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of
1LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF − 1.5
LSB), after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last
code transition). The deviation of any given code from this straight line is measured from the center of that
code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the
power in the second and third order intermodulation products to the sum of the power in both of the
original frequencies. IMD is usually expressed in dB.
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MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC121S051 is
ensured not to have any missing codes.
OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +
0.5 LSB).
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of
the input signal to the rms value of all of the other spectral components below half the clock frequency,
including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal
amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral
component is any signal present in the output spectrum that is not present at the input and may or may
not be a harmonic.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five
harmonic components at the output to the rms level of the input signal frequency as seen at the output.
THD is calculated as
THD = 20 ‡ log10
A f 22 + + A f 6 2
A f 12
(1)
where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the
RMS power in the first 5 harmonic frequencies.
THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the
acquisition time plus the conversion time.
8
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Typical Performance Characteristics
TA = +25°C, fSAMPLE = 200 ksps to 500 ksps,fSCLK = 4 MHz to 10 MHz, fIN = 100 kHz unless otherwise stated.
DNL
fSCLK = 4 MHz
INL
fSCLK = 4 MHz
Figure 5.
Figure 6.
DNL
fSCLK = 10 MHz
INL
fSCLK = 10 MHz
Figure 7.
Figure 8.
DNL vs. Clock Frequency
INL vs. Clock Frequency
Figure 9.
Figure 10.
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Typical Performance Characteristics (continued)
TA = +25°C, fSAMPLE = 200 ksps to 500 ksps,fSCLK = 4 MHz to 10 MHz, fIN = 100 kHz unless otherwise stated.
10
SNR vs. Clock Frequency
SINAD vs. Clock Frequency
Figure 11.
Figure 12.
SFDR vs. Clock Frequency
THD vs. Clock Frequency
Figure 13.
Figure 14.
Spectral Response, VA = 5.25V
fSCLK = 4 MHz
Spectral Response, VA = 5.25V
fSCLK = 10 MHz
Figure 15.
Figure 16.
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Typical Performance Characteristics (continued)
TA = +25°C, fSAMPLE = 200 ksps to 500 ksps,fSCLK = 4 MHz to 10 MHz, fIN = 100 kHz unless otherwise stated.
Power Consumption vs. Throughput,
fSCLK = 10 MHz
Figure 17.
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APPLICATIONS INFORMATION
ADC121S051 OPERATION
The ADC121S051 is a successive-approximation analog-to-digital converters designed around a chargeredistribution digital-to-analog converter core. Simplified schematics of the ADC121S051 in both track and hold
modes are shown in Figure 18 and Figure 19, respectively. In Figure 18, the device is in track mode: switch SW1
connects the sampling capacitor to the input, and SW2 balances the comparator inputs. The device is in this
state until CS is brought low, at which point the device moves to the hold mode.
Figure 19 shows the device in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining
the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the chargeredistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is
balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of
the analog input voltage. The device moves from hold mode to track mode on the 13th rising edge of SCLK.
CHARGE
REDISTRIBUTION
DAC
VIN
SAMPLING
CAPACITOR
SW1
SW2
GND
+
-
CONTROL
LOGIC
VA
2
Figure 18. ADC121S051 in Track Mode
CHARGE
REDISTRIBUTION
DAC
VIN
SAMPLING
CAPACITOR
SW1
SW2
GND
+
-
CONTROL
LOGIC
VA
2
Figure 19. ADC121S051 in Hold Mode
USING THE ADC121S051
The serial interface timing diagram for the ADC is shown in Figure 4. CS is chip select, which initiates
conversions on the ADC and frames the serial data transfers. SCLK (serial clock) controls both the conversion
process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is found as a
serial data stream.
Basic operation of the ADC begins with CS going low, which initiates a conversion process and data transfer.
Subsequent rising and falling edges of SCLK will be labelled with reference to the falling edge of CS; for
example, "the third falling edge of SCLK" shall refer to the third falling edge of SCLK after CS goes low.
At the fall of CS, the SDATA pin comes out of TRI-STATE, and the converter moves from track mode to hold
mode. The input signal is sampled and held for conversion on the falling edge of CS. The converter moves from
hold mode to track mode on the 13th rising edge of SCLK (see Figure 4). It is at this point that the interval for the
TACQ specification begins. At least 350ns must pass between the 13th rising edge of SLCK and the next falling
edge of CS. The SDATA pin will be placed back into TRI-STATE after the 16th falling edge of SCLK, or at the
rising edge of CS, whichever occurs first. After a conversion is completed, the quiet time (tQUIET) must be
satisfied before bringing CS low again to begin another conversion.
12
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Sixteen SCLK cycles are required to read a complete sample from the ADC. The sample bits (including leading
zeroes) are clocked out on falling edges of SCLK, and are intended to be clocked in by a receiver on subsequent
falling edges of SCLK. The ADC will produce three leading zero bits on SDATA, followed by twelve data bits,
most significant first.
If CS goes low before the rising edge of SCLK, an additional (fourth) zero bit may be captured by the next falling
edge of SCLK.
Determining Throughput
Throughput depends on the frequency of SCLK and how much time is allowed to elapse between the end of one
conversion and the start of another. At the maximum specified SCLK frequency, the maximum ensured
throughput is obtained by using a 20 SCLK frame. As shown in Figure 4, the minimum allowed time between CS
falling edges is determined by 1) 12.5 SCLKs for Hold mode, 2) the larger of two quantities: either the minimum
required time for Track mode (tACQ) or 2.5 SCLKs to finish reading the result and 3) 0, 1/2 or 1 SCLK padding to
ensure an even number of SCLK cycles so there is a falling SCLK edge when CS next falls. For example, at the
fastest rate for this family of parts, SCLK is 20 MHz and 2.5 SCLKs are 125 ns, so the minimum time between
CS falling edges is calculated by:
12.5*50ns + 350ns + 0.5*50ns = 1000ns
(2)
(12.5 SCLKs + tACQ + 1/2 SCLK) which corresponds to a maximum throughput of 1MSPS. At the slowest rate for
this family, SCLK is 1MHz. Using a 20 cycle conversion frame as shown in Figure 4 yields a 20 µs time between
CS falling edges for a throughput of 50 KSPS. It is possible, however, to use fewer than 20 clock cycles provided
the timing parameters are met. With a 1MHz SCLK, there are 2500 ns in 2.5 SCLK cycles, which is greater than
tACQ. After the last data bit has come out, the clock will need one full cycle to return to a falling edge. Thus the
total time between falling edges of CS is 12.5*1µs +2.5*1µs +1*1µs=16 μs which is a throughput of 62.5 KSPS.
ADC121S051 TRANSFER FUNCTION
The output format of the ADC is straight binary. Code transitions occur midway between successive integer LSB
values. The LSB width for the ADC is VA/4096. The ideal transfer characteristic is shown in Figure 20. The
transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a voltage of
VA/8192. Other code transitions occur at steps of one LSB.
111...111
111...000
|
|
ADC CODE
111...110
1 LSB = VA/4096
011...111
000...010
|
000...001
000...000
0V
0.5 LSB
ANALOG INPUT
+VA-1.5 LSB
Figure 20. Ideal Transfer Characteristic
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TYPICAL APPLICATION CIRCUIT
A typical application of the ADC is shown in Figure 21. Power is provided in this example by the National
Semiconductor LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output
voltages. The power supply pin is bypassed with a capacitor network located close to the ADC. Because the
reference for the ADC is the supply voltage, any noise on the supply will degrade device noise performance. To
keep noise off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from
other circuitry to keep noise off the ADC supply pin. Because of the ADC 's low power requirements, it is also
possible to use a precision reference as a power supply to maximize performance. The three-wire interface is
shown connected to a microprocessor or DSP.
LP2950
1 PF
5V
0.1 PF
1 PF
0.1 PF
VA
SCLK
ADC121S051
VIN
MICROPROCESSOR
DSP
CS
SDATA
GND
Figure 21. Typical Application Circuit
ANALOG INPUTS
An equivalent circuit for the ADC 's input is shown in Figure 22. Diodes D1 and D2 provide ESD protection for
the analog inputs. At no time should the analog input go beyond (VA + 300 mV) or (GND − 300 mV), as these
ESD diodes will begin conducting, which could result in erratic operation. For this reason, the ESD diodes should
not be used to clamp the input signal.
The capacitor C1 in Figure 22 has a typical value of 4pF, and is mainly the package pin capacitance. Resistor R1
is the on resistance of the track / hold switch, and is typically 500Ω. Capacitor C2 is the ADC sampling capacitor
and is typically 26 pF. The ADC will deliver best performance when driven by a low-impedance source to
eliminate distortion caused by the charging of the sampling capacitance. This is especially important when using
the ADC to sample AC signals. Also important when sampling dynamic signals is an anti-aliasing filter.
VA
D1
R1
C2
26 pF
VIN
C1
4 pF
D2
Conversion Phase - Switch Open
Track Phase - Switch Closed
Figure 22. Equivalent Input Circuit
DIGITAL INPUTS AND OUTPUTS
The ADC digital inputs (SCLK and CS) are not limited by the same maximum ratings as the analog inputs. The
digital input pins are instead limited to +5.25V with respect to GND, regardless of VA, the supply voltage. This
allows the ADC to be interfaced with a wide range of logic levels, independent of the supply voltage.
14
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MODES OF OPERATION
The ADC has two possible modes of operation: normal mode, and shutdown mode. The ADC enters normal
mode (and a conversion process is begun) when CS is pulled low. The device will enter shutdown mode if CS is
pulled high before the tenth falling edge of SCLK after CS is pulled low, or will stay in normal mode if CS remains
low. Once in shutdown mode, the device will stay there until CS is brought low again. By varying the ratio of time
spent in the normal and shutdown modes, a system may trade-off throughput for power consumption, with a
sample rate as low as zero.
Normal Mode
The fastest possible throughput is obtained by leaving the ADC in normal mode at all times, so there are no
power-up delays. To keep the device in normal mode continuously, CS must be kept low until after the 10th
falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low).
If CS is brought high after the 10th falling edge, but before the 16th falling edge, the device will remain in normal
mode, but the current conversion will be aborted, and SDATA will return to TRI-STATE (truncating the output
word).
Sixteen SCLK cycles are required to read all of a conversion word from the device. After sixteen SCLK cycles
have elapsed, CS may be idled either high or low until the next conversion. If CS is idled low, it must be brought
high again before the start of the next conversion, which begins when CS is again brought low.
After sixteen SCLK cycles, SDATA returns to TRI-STATE. Another conversion may be started, after tQUIET has
elapsed, by bringing CS low again.
Shutdown Mode
Shutdown mode is appropriate for applications that either do not sample continuously, or it is acceptable to trade
throughput for power consumption. When the ADC is in shutdown mode, all of the analog circuitry is turned off.
To enter shutdown mode, a conversion must be interrupted by bringing CS high anytime between the second
and tenth falling edges of SCLK, as shown in Figure 23. Once CS has been brought high in this manner, the
device will enter shutdown mode; the current conversion will be aborted and SDATA will enter TRI-STATE. If CS
is brought high before the second falling edge of SCLK, the device will not change mode; this is to avoid
accidentally changing mode as a result of noise on the CS line.
Figure 23. Entering Shutdown Mode
Figure 24. Entering Normal Mode
To exit shutdown mode, bring CS back low. Upon bringing CS low, the ADC will begin powering up (power-up
time is specified in the Timing Specifications table). This power-up delay results in the first conversion result
being unusable. The second conversion performed after power-up, however, is valid, as shown in Figure 24.
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If CS is brought back high before the 10th falling edge of SCLK, the device will return to shutdown mode. This is
done to avoid accidentally entering normal mode as a result of noise on the CS line. To exit shutdown mode and
remain in normal mode, CS must be kept low until after the 10th falling edge of SCLK. The ADC will be fully
powered-up after 16 SCLK cycles.
POWER MANAGEMENT
The ADC takes time to power-up, either after first applying VA, or after returning to normal mode from shutdown
mode. This corresponds to one "dummy" conversion for any SCLK frequency within the specifications in this
document. After this first dummy conversion, the ADC will perform conversions properly. Note that the tQUIET time
must still be included between the first dummy conversion and the second valid conversion.
When the VA supply is first applied, the ADC may power up in either of the two modes: normal or shutdown. As
such, one dummy conversion should be performed after start-up, as described in the previous paragraph. The
part may then be placed into either normal mode or the shutdown mode, as described in Normal Mode and
Shutdown Mode.
When the ADC is operated continuously in normal mode, the maximum ensured throughput is FSCLK/20 at the
maximum specified FSCLK. Throughput may be traded for power consumption by running fSCLK at its maximum
specified rate and performing fewer conversions per unit time, raising the ADC CS line after the 10th and before
the 15th fall of SCLK of each conversion. A plot of typical power consumption versus throughput is shown in the
Typical Performance Characteristics section. To calculate the power consumption for a given throughput, multiply
the fraction of time spent in the normal mode by the normal mode power consumption and add the fraction of
time spent in shutdown mode multiplied by the shutdown mode power consumption. Note that the curve of power
consumption vs. throughput is essentially linear. This is because the power consumption in the shutdown mode
is so small that it can be ignored for all practical purposes.
POWER SUPPLY NOISE CONSIDERATIONS
The charging of any output load capacitance requires current from the power supply, VA. The current pulses
required from the supply to charge the output capacitance will cause voltage variations on the supply. If these
variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore,
discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current
into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the
substrate that will degrade noise performance if that current is large enough. The larger the output capacitance,
the more current flows through the die substrate and the greater is the noise coupled into the analog channel,
degrading noise performance.
To keep noise out of the power supply, keep the output load capacitance as small as practical. It is good practice
to use a 100 Ω series resistor at the ADC output, located as close to the ADC output pin as practical. This will
limit the charge and discharge current of the output capacitance and improve noise performance.
16
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REVISION HISTORY
Changes from Revision H (March 2013) to Revision I
•
Page
Changed sentence in the "Using the ADC121S051" section ............................................................................................. 12
Changes from Revision G (March 2013) to Revision H
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 16
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADC121S051CIMF/NOPB
ACTIVE
SOT-23
DBV
6
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
X13C
ADC121S051CIMFX/NOPB
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
X13C
ADC121S051CISD/NOPB
ACTIVE
WSON
NGF
6
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
X4C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADC121S051CIMF/NOPB SOT-23
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DBV
6
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT-23
DBV
6
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
ADC121S051CISD/NOPB WSON
NGF
6
1000
178.0
12.4
2.8
2.5
1.0
8.0
12.0
Q1
ADC121S051CIMFX/NOP
B
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADC121S051CIMF/NOPB
SOT-23
DBV
6
1000
210.0
185.0
35.0
SOT-23
DBV
6
3000
210.0
185.0
35.0
WSON
NGF
6
1000
210.0
185.0
35.0
ADC121S051CIMFX/NOP
B
ADC121S051CISD/NOPB
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
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EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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MECHANICAL DATA
NGF0006A
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