Texas Instruments | 24-Bit, Analog-to-Digital Converters (Rev. F) | Datasheet | Texas Instruments 24-Bit, Analog-to-Digital Converters (Rev. F) Datasheet

Texas Instruments 24-Bit, Analog-to-Digital Converters (Rev. F) Datasheet
ADS1240
ADS1241
ADS
124
0
ADS
124
1
SBAS173F – JUNE 2001 – REVISED OCTOBER 2013
24-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● 24 BITS NO MISSING CODES
● SIMULTANEOUS 50Hz AND 60Hz REJECTION
(–90dB MINIMUM)
● 0.0015% INL
● 21 BITS EFFECTIVE RESOLUTION
(PGA = 1), 19 BITS (PGA = 128)
● PGA GAINS FROM 1 TO 128
● SINGLE CYCLE SETTLING
● PROGRAMMABLE DATA OUTPUT RATES
● EXTERNAL DIFFERENTIAL REFERENCE
OF 0.1V TO 5V
● ON-CHIP CALIBRATION
● SPI™ COMPATIBLE
● 2.7V TO 5.25V SUPPLY RANGE
● 600µW POWER CONSUMPTION
● UP TO EIGHT INPUT CHANNELS
● UP TO EIGHT DATA I/O
The ADS1240 and ADS1241 are precision, wide dynamic range,
delta-sigma, Analog-to-Digital (A/D) converters with 24-bit resolution
operating from 2.7V to 5.25V power supplies. The delta-sigma A/D
converter provides up to 24 bits of no missing code performance and
effective resolution of 21 bits.
The input channels are multiplexed. Internal buffering can be
selected to provide very high input impedance for direct connection
to transducers or low-level voltage signals. Burnout current sources
are provided that allow for detection of an open or shorted sensor.
An 8-bit Digital-to-Analog (D/A) converter provides an offset correction with a range of 50% of the Full-Scale Range (FSR).
The Programmable Gain Amplifier (PGA) provides selectable gains of
1 to 128, with an effective resolution of 19 bits at a gain of 128. The
A/D conversion is accomplished with a 2nd-order delta-sigma modulator and programmable Finite-Impulse Response (FIR) filter that
provides a simultaneous 50Hz and 60Hz notch. The reference input
is differential and can be used for ratiometric conversion.
The serial interface is SPI compatible. Up to eight bits of data
I/O are also provided that can be used for input or output. The
ADS1240 and ADS1241 are designed for high-resolution measurement applications in smart transmitters, industrial process control,
weigh scales, chromatography, and portable instrumentation.
APPLICATIONS
●
●
●
●
●
●
INDUSTRIAL PROCESS CONTROL
WEIGH SCALES
LIQUID /GAS CHROMATOGRAPHY
BLOOD ANALYSIS
SMART TRANSMITTERS
PORTABLE INSTRUMENTATION
VREF+ VREF–
AVDD AGND
XIN
XOUT
AVDD
Clock Generator
2µA
Offset
DAC
AIN0/D0
A = 1:128
AIN1/D1
AIN2/D2
AIN3/D3
MUX
BUF
+
PGA
AIN4/D4
2nd-Order
Modulator
Digital
Filter
Controller
Registers
AIN5/D5
AIN6/D6
AIN7/D7
POL
AINCOM
SCLK
Serial Interface
ADS1241
Only
DIN
DOUT
2µA
CS
AGND
BUFEN
DVDD
DGND
PDWN
DSYNC
RESET
DRDY
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks property of their respective owners.
Copyright © 2001-2006, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
AVDD to DGND ...................................................................... –0.3V to +6V
DVDD to DGND ...................................................................... –0.3V to +6V
Input Current ............................................................... 100mA, Momentary
DGND to AGND .................................................................... –0.3V to 0.3V
Input Current ................................................................. 10mA, Continuous
AIN ................................................................. AGND –0.5V to AVDD + 0.5V
Digital Input Voltage to DGND ................................. –0.3V to DVDD + 0.3V
Digital Output Voltage to DGND .............................. –0.3V to DVDD + 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –60°C to +150°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see
the Package Option Addendum at the end of this document,
or see the TI website at www.ti.com.
DIGITAL CHARACTERISTICS: –40°C to +85°C, DVDD 2.7V to 5.25V
PARAMETER
Digital Input/Output
Logic Family
Logic Level: VIH
VIL
VOH
VOL
Input Leakage: IIH
IIL
Master Clock Rate: fOSC
Master Clock Period: tOSC
2
CONDITIONS
MIN
TYP
MAX
UNITS
DVDD
0.2 • DVDD
V
V
V
V
µA
µA
MHz
ns
CMOS
0.8 • DVDD
DGND
DVDD – 0.4
DGND
IOH = 1mA
IOL = 1mA
VI = DVDD
VI = 0
–10
1
200
1/fOSC
DGND + 0.4
10
5
1000
ADS1240, 1241
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SBAS173F
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, and VREF = +2.5V, unless otherwise specified.
ADS1240
ADS1241
PARAMETER
ANALOG INPUT (AIN0 – AIN7, AINCOM)
Analog Input Range
Full-Scale Input Range
Differential Input Impedance
Bandwidth
fDATA = 3.75Hz
fDATA = 7.50Hz
fDATA = 15.00Hz
Programmable Gain Amplifier
Input Capacitance
Input Leakage Current
Burnout Current Sources
CONDITIONS
MIN
Buffer OFF
Buffer ON
(In+) – (In–), See Block Diagram, RANGE = 0
RANGE = 1
Buffer OFF
Buffer ON
AGND – 0.1
AGND + 0.05
–3dB
–3dB
–3dB
User-Selectable Gain Ranges
Output Noise
Power-Supply Rejection
VOLTAGE REFERENCE INPUT
VREF
Reference Input Range
Common-Mode Rejection
Common-Mode Rejection
Bias Current(3)
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
Analog Current
Digital Current
Power Dissipation
UNITS
AVDD + 0.1
AVDD – 1.5
±VREF /PGA
±VREF /(2 • PGA)
5/PGA
5
V
V
V
V
MΩ
GΩ
1.65
3.44
14.6
Hz
Hz
Hz
1
128
Modulator OFF, T = 25°C
pF
pA
µA
RANGE = 0
RANGE = 1
±VREF /(2 • PGA)
±VREF /(4 • PGA)
V
V
±10
1
Bits
%
ppm/°C
Offset Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
Normal-Mode Rejection
MAX
9
5
2
OFFSET DAC
Offset DAC Range
SYSTEM PERFORMANCE
Resolution
Integral Nonlinearity
Offset Error (1)
Offset Drift(1)
Gain Error
Gain Error Drift(1)
Common-Mode Rejection
TYP
8
No Missing Codes
End Point Fit
24
±0.0015
7.5
0.02
0.005
0.5
fCM =
fCM =
fSIG =
fSIG =
at DC
60Hz, fDATA =
50Hz, fDATA =
50Hz, fDATA =
60Hz, fDATA =
100
15Hz
15Hz
15Hz
15Hz
at DC, dB = –20 log(∆VOUT /∆VDD)(2)
80
VREF ≡ (REF IN+) – (REF IN–), RANGE = 0
REF IN+, REF IN–
RANGE = 1
at DC
fVREFCM = 60Hz, fDATA = 15Hz
VREF = 2.5V
0.1
0
0.1
AVDD
PDWN = 0, or SLEEP
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
PGA = 128, Buffer ON
Normal Mode, DVDD = 5V
SLEEP Mode, DVDD = 5V
Read Data Continuous Mode, DVDD = 5V
PDWN
4.75
PGA = 1, Buffer OFF, DVDD = 5V
130
120
100
100
See Typical Characteristics
95
2.5
dB
2.6
AVDD
AVDD
V
V
V
dB
dB
µA
5.25
V
nA
µA
µA
µA
µA
µA
µA
µA
nA
120
120
1.3
1
120
400
160
760
80
60
230
0.5
1.1
Bits
% of FS
ppm of FS
ppm of FS/°C
%
ppm/°C
dB
dB
dB
dB
dB
250
675
300
1275
125
1.9
mW
NOTES: (1) Calibration can minimize these errors to the level of the noise.
(2) ∆VOUT is a change in digital result.
(3) 12pF switched capacitor at fSAMP clock frequency.
ADS1240, 1241
SBAS173F
www.ti.com
3
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications –40°C to +85°C, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, and VREF = +1.25V, unless otherwise specified.
ADS1240
ADS1241
PARAMETER
ANALOG INPUT (AIN0 – AIN7, AINCOM)
Analog Input Range
Full-Scale Input Voltage Range
Input Impedance
Differential
Bandwidth
fDATA = 3.75Hz
fDATA = 7.50Hz
fDATA = 15.00Hz
Programmable Gain Amplifier
Input Capacitance
Input Leakage Current
Burnout Current Sources
CONDITIONS
MIN
Buffer OFF
Buffer ON
(In+) – (In–) See Block Diagram, RANGE = 0
RANGE = 1
Buffer OFF
Buffer ON
AGND – 0.1
AGND + 0.05
–3dB
–3dB
–3dB
User-Selectable Gain Ranges
Output Noise
Power-Supply Rejection
VOLTAGE REFERENCE INPUT
VREF
Reference Input Range
Common-Mode Rejection
Common-Mode Rejection
Bias Current(3)
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
Analog Current
Digital Current
Power Dissipation
UNITS
AVDD + 0.1
AVDD – 1.5
±VREF /PGA
±VREF /(2 • PGA)
5/PGA
5
V
V
V
V
MΩ
GΩ
1.65
3.44
14.6
Hz
Hz
Hz
1
128
Modulator OFF, T = 25°C
pF
pA
µA
RANGE = 0
RANGE = 1
±VREF /(2 • PGA)
±VREF /(4 • PGA)
V
V
±10
2
Bits
%
ppm/°C
Offset DAC Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
Normal-Mode Rejection
MAX
9
5
2
OFFSET DAC
Offset DAC Range
SYSTEM PERFORMANCE
Resolution
Integral Nonlinearity
Offset Error(1)
Offset Drift(1)
Gain Error
Gain Error Drift(1)
Common-Mode Rejection
TYP
8
No Missing Codes
End Point Fit
24
±0.0015
15
0.04
0.01
1.0
fCM =
fCM =
fSIG =
fSIG =
at DC
60Hz, fDATA =
50Hz, fDATA =
50Hz, fDATA =
60Hz, fDATA =
100
15Hz
15Hz
15Hz
15Hz
at DC, dB = –20 log(∆VOUT /∆VDD)(2)
75
VREF ≡ (REF IN+) – (REF IN–), RANGE = 0
REF IN+, REF IN–
RANGE = 1
0.1
0
0.1
fVREFCM
at DC
= 60Hz, fDATA = 15Hz
VREF = 1.25
AVDD
PDWN = 0, or SLEEP
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
PGA = 128, Buffer ON
Normal Mode, DVDD = 3V
SLEEP Mode, DVDD = 3V
Read Data Continuous Mode, DVDD = 3V
PDWN = 0
PGA = 1, Buffer OFF, DVDD = 3V
130
120
100
100
See Typical Characteristics
90
1.25
2.5
dB
1.30
AVDD
2.6
120
120
0.65
2.7
V
V
V
dB
dB
µA
3.3
1
107
355
118
483
50
40
113
0.5
0.6
Bits
% of FS
ppm of FS
ppm of FS/°C
%
ppm/°C
dB
dB
dB
dB
dB
225
600
275
1225
100
1.2
V
nA
µA
µA
µA
µA
µA
µA
µA
nA
mW
NOTES: (1) Calibration can minimize these errors to the level of the noise.
(2) ∆VOUT is a change in digital result.
(3) 12pF switched capacitor at fSAMP clock frequency.
4
ADS1240, 1241
www.ti.com
SBAS173F
PIN CONFIGURATION (ADS1240)
PIN CONFIGURATION (ADS1241)
Top View
SSOP
Top View
SSOP
DVDD
1
28 BUFEN
DGND
2
27 DRDY
DVDD
1
24 BUFEN
DGND
2
23 DRDY
XIN
3
26 SCLK
XIN
3
22 SCLK
XOUT
4
25 DOUT
XOUT
4
21 DOUT
RESET
5
24 DIN
RESET
5
20 DIN
DSYNC
6
23 CS
DSYNC
6
19 CS
PDWN
7
ADS1240
22 POL
ADS1241
PDWN
7
18 POL
DGND
8
DGND
8
17 AVDD
VREF+
9
20 AGND
VREF+
9
16 AGND
VREF– 10
19 AINCOM
VREF– 10
15 AINCOM
AIN0/D0 11
18 AIN3/D3
AIN0/D0 11
14 AIN3/D3
AIN1/D1 12
17 AIN2/D2
AIN1/D1 12
13 AIN2/D2
AIN4/D4 13
16 AIN7/D7
AIN5/D5 14
15 AIN6/D6
PIN DESCRIPTIONS (ADS1241)
PIN DESCRIPTIONS (ADS1240)
PIN
NUMBER
NAME
DESCRIPTION
1
DVDD
Digital Power Supply
2
DGND
3
XIN
PIN
NUMBER
NAME
DESCRIPTION
1
2
3
4
5
6
7
DVDD
DGND
XIN
XOUT
RESET
DSYNC
PDWN
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DGND
VREF+
VREF–
AIN0/D0
AIN1/D1
AIN4/D4
AIN5/D5
AIN6/D6
AIN7/D7
AIN2/D2
AIN3/D3
AINCOM
AGND
AVDD
POL
CS
DIN
DOUT
SCLK
DRDY
BUFEN
Digital Power Supply
Digital Ground
Clock Input
Clock Output, used with external crystals.
Active LOW, resets the entire device.
Active LOW, Synchronization Control
Active LOW, Power Down. The power down function shuts down the analog and digital circuits.
Digital Ground
Positive Differential Reference Input
Negative Differential Reference Input
Analog Input 0 / Data I/O 0
Analog Input 1 / Data I/O 1
Analog Input 4 / Data I/O 4
Analog Input 5 / Data I/O 5
Analog Input 6 / Data I/O 6
Analog Input 7 / Data I/O 7
Analog Input 2 / Data I/O 2
Analog Input 3 / Data I/O 3
Analog Input Common, connect to AGND if unused.
Analog Ground
Analog Power Supply
Serial Clock Polarity
Active LOW, Chip Select
Serial Data Input, Schmitt Trigger
Serial Data Output
Serial Clock, Schmitt Trigger
Active LOW, Data Ready
Buffer Enable
Digital Ground
Clock Input
Clock Output, used with external crystals.
4
XOUT
5
RESET
6
DSYNC
Active LOW, Synchronization Control
7
PDWN
Active LOW, Power Down. The power down function shuts down the analog and digital circuits.
8
DGND
Digital Ground
9
VREF+
Positive Differential Reference Input
10
VREF–
Negative Differential Reference Input
11
AIN0/D0
Analog Input 0 / Data I/O 0
12
AIN1/D1
Analog Input 1 / Data I/O 1
13
AIN2/D2
Analog Input 2 / Data I/O 2
14
AIN3/D3
Analog Input 3 / Data I/O 3
15
AINCOM
Analog Input Common, connect to AGND if unused.
16
AGND
Analog Ground
17
AVDD
Analog Power Supply
18
POL
Serial Clock Polarity
19
CS
Active LOW, Chip Select
20
DIN
Serial Data Input, Schmitt Trigger
21
DOUT
Serial Data Output
22
SCLK
Serial Clock, Schmitt Trigger
23
DRDY
Active LOW, Data Ready
24
BUFEN
Buffer Enable
Active LOW, resets the entire device.
ADS1240, 1241
SBAS173F
21 AVDD
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5
TIMING DIAGRAMS
CS
t3
t1
t2
t10
SCLK
(POL = 0)
SCLK
(POL = 1)
t4
DIN
t2
t6
t5
MSB
t11
LSB
t7
(Command or Command and Data)
t8
DOUT
t9
MSB(1)
LSB(1)
NOTE: (1) Bit order = 0.
ADS1240 or ADS1241
Resets On
Falling Edge
300 • tOSC < t12 < 500 • tOSC
SCLK Reset Waveform
t13
t13
t13 : > 5 • tOSC
550 • tOSC < t14 < 750 • tOSC
SCLK
t12
t14
1050 • tOSC < t15 < 1250 • tOSC
t15
DIAGRAM 1.
t16
tDATA
DRDY
RESET, DSYNC, PDWN
t17
t18
SCLK
t19
DIAGRAM 2.
TIMING CHARACTERISTICS TABLE
SPEC
t1
DESCRIPTION
MIN
SCLK Period
MAX
UNITS
3
tOSC Periods
DRDY Periods
4
t2
SCLK Pulse Width, HIGH and LOW
200
ns
t3
CS low to first SCLK Edge; Setup Time(2)
0
ns
t4
DIN Valid to SCLK Edge; Setup Time
50
ns
t5
Valid DIN to SCLK Edge; Hold Time
50
ns
t6
Delay between last SCLK edge for DIN and first SCLK edge for DOUT:
t7(1)
RDATA, RDATAC, RREG, WREG
SCLK Edge to Valid New DOUT
t8(1)
SCLK Edge to DOUT, Hold Time
0
Last SCLK Edge to DOUT Tri-State
6
t9
50
tOSC Periods
ns
10
tOSC Periods
50
ns
NOTE: DOUT goes tri-state immediately when CS goes HIGH.
t10
t11
t16
t17
t18
t19
CS LOW time after final SCLK edge.
Read from the device
Write to the device
Final SCLK edge of one command until first edge SCLK
of next command:
RREG, WREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL
SELFCAL
RESET (also SCLK Reset or RESET Pin)
Pulse Width
Allowed analog input change for next valid conversion.
DOR update, DOR data not valid.
First SCLK after DRDY goes LOW:
RDATAC Mode
Any other mode
0
8
tOSC Periods
tOSC Periods
4
2
4
16
4
4
tOSC Periods
DRDY Periods
DRDY Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
10
0
tOSC Periods
tOSC Periods
5000
NOTES: (1) Load = 20pF 10kΩ to DGND.
(2) CS may be tied LOW.
6
ADS1240, 1241
www.ti.com
SBAS173F
TYPICAL CHARACTERISTICS
All specifications AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
EFFECTIVE NUMBER OF BITS vs PGA SETTING
EFFECTIVE NUMBER OF BITS vs PGA SETTING
22
21.5
DR = 10
21.0
21
DR = 10
DR = 01
20
20.0
ENOB (rms)
ENOB (rms)
20.5
19.5
19.0
DR = 00
18.5
19
DR = 01
18
DR = 00
17
18.0
Buffer ON
Buffer OFF
16
17.5
15
17.0
1
2
4
8
16
32
64
1
128
2
EFFECTIVE NUMBER OF BITS vs PGA SETTING
16
32
64
128
NOISE vs INPUT SIGNAL
2.0
20.5
1.8
20.0
DR = 10
19.0
Noise (rms, ppm of FS)
19.5
ENOB (rms)
8
PGA Setting
PGA Setting
DR = 01
18.5
18.0
DR = 00
17.5
17.0
Buffer OFF, VREF = 1.25V
16.5
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–2.5
16.0
1
2
4
8
16
32
64
128
–1.5
–0.5
0.5
1.5
PGA Setting
VIN (V)
COMMON-MODE REJECTION RATIO
vs FREQUENCY
POWER SUPPLY REJECTION RATIO
vs FREQUENCY
140
140
120
120
100
100
PSRR (dB)
CMRR (dB)
4
80
60
40
2.5
80
60
40
20
20
Buffer ON
Buffer ON
0
0
1
10
100
1k
10k
100k
ADS1240, 1241
SBAS173F
1
10
100
1k
10k
100k
Frequency of Power Supply (Hz)
Frequency of Power Supply (Hz)
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7
TYPICAL CHARACTERISTICS (Cont.)
All specifications AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
GAIN vs TEMPERATURE
(Cal at 25°C)
OFFSET vs TEMPERATURE
(Cal at 25°C)
1.00010
50
PGA16
PGA1
1.00006
Gain (Normalized)
Offset (ppm of FS)
0
–50
PGA64
–100
PGA128
–150
1.00002
0.99998
0.99994
0.99990
0.99986
–200
–50
–30
–10
10
30
50
70
–50
90
–30
–10
50
70
90
150
8
140
–40°C
6
AVDD = 5
130
120
+85°C
Current (µA)
INL (ppm of FS)
30
ANALOG CURRENT vs TEMPERATURE
INTEGRAL NONLINEARITY vs INPUT SIGNAL
10
4
10
Temperature (°C)
Temperature (°C)
2
0
–2
–4
100
AVDD = 3
90
80
+25°C
–6
110
70
–8
Buffer OFF
60
–10
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5
1.0
1.5
2.0
50
2.5
–50
–30
–10
VIN (V)
ANALOG CURRENT vs PGA
30
50
70
90
DIGITAL CURRENT vs SUPPLY
900
300
AVDD = 5V, Buffer = ON
800
10
Temperature (°C)
Buffer = OFF
250
600
500
IDIGITAL (µA)
IANALOG (µA)
700
AVDD = 3V, Buffer = ON
400
Buffer = OFF
200
SLEEP
4.91MHz
Normal
2.45MHz
Normal
4.91MHz
150
100
300
200
50
100
0
0
1
2
4
8
16
32
64
128
3.0
PGA Setting
8
SLEEP
2.45MHz
Power Down
3.5
4.0
4.5
5.0
VDD (V)
ADS1240, 1241
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SBAS173F
TYPICAL CHARACTERISTICS (Cont.)
All specifications AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
OFFSET DAC
OFFSET vs TEMPERATURE
(Cal at 25°C)
NOISE HISTOGRAM
Number of Occurrences
3000
200
10k Readings
VIN = 0V
170
140
Offset (ppm of FSR)
3500
2500
2000
1500
1000
110
80
50
20
–10
–40
500
–70
–100
0
–50
–30
–10
–3.5 –3.0 –2.5 –2.0 –1.5 –1 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
10
30
50
70
90
Temperature (°C)
ppm of FS
OFFSET DAC
GAIN vs TEMPERATURE
(Cal at 25°C)
OFFSET DAC
NOISE vs SETTING
1.00020
0.8
1.00016
0.7
Noise (rms, ppm of FS)
Gain (Normalized)
1.00012
1.00008
1.00004
1.00000
0.99996
0.99992
0.99988
0.99984
0.6
0.5
0.4
0.3
0.2
0.1
0.99980
0.99976
–50
–30
–10
10
30
50
70
0
–128
90
Temperature (°C)
–64
–32
0
32
64
96
128
Offset DAC Setting
ADS1240, 1241
SBAS173F
–96
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9
OVERVIEW
INPUT MULTIPLEXER
The input multiplexer provides for any combination of differential inputs to be selected on any of the input channels, as
shown in Figure 1. For example, if AIN0 is selected as the
positive differential input channel, any other channel can be
selected as the negative terminal for the differential input
AIN0/D0
AIN1/D1
AVDD
Burnout Current Source
AIN2/D2
The ADS1240 and ADS1241 feature a single-cycle settling
digital filter that provides valid data on the first conversion
after a new channel selection. In order to minimize the
settling error, synchronize MUX changes to the conversion
beginning, which is indicated by the falling edge of DRDY. In
other words, issuing a MUX change through the WREG
command immediately after DRDY goes LOW minimizes the
settling error. Increasing the time between the conversion
beginning (DRDY goes LOW) and the MUX change command (tDELAY) results in a settling error in the conversion
data, as shown in Figure 2.
BURNOUT CURRENT SOURCES
AIN3/D3
The Burnout Current Sources can be used to detect sensor
short-circuit or open-circuit conditions. Setting the Burnout
Current Sources (BOCS) bit in the SETUP register activates
two 2µA current sources called burnout current sources. One
of the current sources is connected to the converter’s negative input and the other is connected to the converter’s
positive input.
Input
Buffer
AIN4/D4
AIN5/D5
Burnout Current Source
AIN6/D6
AGND
Figure 3 shows the situation for an open-circuit sensor. This
is a potential failure mode for many kinds of remotely connected sensors. The current source on the positive input acts
as a pull-up, causing the positive input to go to the positive
analog supply, and the current source on the negative input
acts as a pull-down, causing the negative input to go to
ground. The ADS1240/41 therefore outputs full-scale (7FFFFF
Hex).
AIN7/D7
ADS1241
Only
channel. With this method, it is possible to have up to eight
single-ended input channels or four independent differential
input channels for the ADS1241, and four single-ended input
channels or two independent differential input channels for
the ADS1240. Note that AINCOM can be treated as an input
channel.
AINCOM
FIGURE 1. Input Multiplexer Configuration.
New Conversion Begins,
Previous Conversion Data
Complete Previous Conversion
New Conversion Complete
DRDY
tDELAY
SCLK
(POL = 0)
MSB
DIN
LSB
SETTLING ERROR vs DELAY TIME
fCLK = 2.4576MHz
10.000000
Settling Error (%)
1.000000
0.100000
0.010000
0.001000
0.000100
0.000010
0.000001
0
2
4
6
8
10
12
Delay Time, tDELAY (ms)
14
16
FIGURE 2. Input Multiplexer Configuration.
10
ADS1240, 1241
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SBAS173F
The buffer draws additional current when activated. The
current required by the buffer depends on the PGA setting.
When the PGA is set to 1, the buffer uses approximately
50µA; when the PGA is set to 128, the buffer uses approxi-
AVDD
2µA
mately 500µA.
AVDD
ADC
OPEN CIRCUIT
CODE = 0x7FFFFFH
0V
2µA
FIGURE 3. Burnout detection while sensor is open-circuited.
Figure 4 shows a short-circuited sensor. Since the inputs are
shorted and at the same potential, the ADS1240/41 signal
outputs are approximately zero. (Note that the code for
shorted inputs is not exactly zero due to internal series
resistance, low-level noise and other error sources.)
PGA
The Programmable Gain Amplifier (PGA) can be set to gains
of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can improve the
effective resolution of the A/D converter. For instance, with a
PGA of 1 on a 5V full-scale signal, the A/D converter can
resolve down to 1µV. With a PGA of 128 and a full-scale signal
of 39mV, the A/D converter can resolve down to 75nV. AVDD
current increases with PGA settings higher than 4.
OFFSET DAC
The input to the PGA can be shifted by half the full-scale input
range of the PGA using the Offset DAC (ODAC) register. The
ODAC register is an 8-bit value; the MSB is the sign and the
seven LSBs provide the magnitude of the offset. Using the
offset DAC does not reduce the performance of the A/D
converter. For more details on the ODAC, please refer to TI
application report SBAA077.
AVDD
MODULATOR
The modulator is a single-loop second-order system. The
modulator runs at a clock speed (fMOD) that is derived from
the external clock (fOSC). The frequency division is determined by the SPEED bit in the SETUP register, as shown in
Table I.
2µA
AVDD/2
SHORT
CIRCUIT
ADC
CODE ≅ 0
AVDD/2
2µA
fOSC
2.4576MHz
4.9152MHz
FIGURE 4. Burnout detection while sensor is short-circuited.
SPEED
BIT
fMOD
00
0
1
0
1
19,200Hz
9,600Hz
38,400Hz
19,200Hz
15Hz
7.5Hz
30Hz
15Hz
DR BITS
01
10
7.5Hz 3.75Hz
3.75Hz 1.875Hz
15Hz
7.5Hz
7.5Hz 3.75Hz
1st NOTCH
FREQ.
50/60Hz
25/30Hz
100/120Hz
50/60Hz
TABLE I. Output Configuration.
INPUT BUFFER
The input impedance of the ADS1240/41 without the buffer
enabled is approximately 5MΩ/PGA. For systems requiring
very high input impedance, the ADS1240/41 provides a
chopper-stabilized differential FET-input voltage buffer. When
activated, the buffer raises the ADS1240/41 input impedance
to approximately 5GΩ.
The buffer’s input range is approximately 50mV to AVDD –
1.5V. The buffer’s linearity will degrade beyond this range.
Differential signals should be adjusted so that both signals
are within the buffer’s input range.
The buffer can be enabled using the BUFEN pin or the
BUFEN bit in the ACR register. The buffer is on when the
BUFEN pin is high and the BUFEN bit is set to one. If the
BUFEN pin is low, the buffer is disabled. If the BUFEN bit is
set to zero, the buffer is also disabled.
CALIBRATION
The offset and gain errors can be minimized with calibration.
The ADS1240 and ADS1241 support both self and system
calibration.
Self-calibration of the ADS1240 and ADS1241 corrects internal offset and gain errors and is handled by three commands:
SELFCAL, SELFGAL, and SLEFOCAL. The SELFCAL command performs both an offset and gain calibration. SELFGCAL
performs a gain calibration and SELFOCAL performs an
offset calibration, each of which takes two tDATA periods to
complete. During self-calibration, the ADC inputs are disconnected internally from the input pins. The PGA must be set to
1 prior to issuing a SELFCAL or SELFGCAL command. Any
PGA is allowed when issuing a SELFOCAL command. For
example, if using PGA = 64, first set PGA = 1 and issue
ADS1240, 1241
SBAS173F
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11
SELFGCAL. Afterwards set PGA = 64 and issue SELFOCAL.
For operation with a reference voltage greater than (AVDD –
1.5) volts, the buffer must also be turned off during gain selfcalibration to avoid exceeding the buffer input range.
System calibration corrects both internal and external offset
and gain errors. While performing system calibration, the
appropriate signal must be applied to the inputs. The system
offset calibration command (SYSOCAL) requires a zero input
differential signal (see Table IV, page 18). It then computes
the offset that nullifies the offset in the system. The system
gain calibration command (SYSGCAL) requires a positive
full-scale input signal. It then computes a value to nullify the
gain error in the system. Each of these calibrations takes two
tDATA periods to complete. System gain calibration is recommended for the best gain calibration at higher PGAs.
Calibration should be performed after power on, a change in
temperature, or a change of the PGA. The RANGE bit (ACR bit
2) must be zero during calibration.
Calibration removes the effects of the ODAC; therefore, disable the ODAC during calibration, and enable again after
calibration is complete.
At the completion of calibration, the DRDY signal goes low,
indicating the calibration is finished. The first data after
calibration should be discarded since it may be corrupt from
calibration data remaining in the filter. The second data is
always valid.
EXTERNAL VOLTAGE REFERENCE
The ADS1240 and ADS1241 require an external voltage
reference. The selection for the voltage reference value is
made through the ACR register.
The external voltage reference is differential and is represented by the voltage difference between the pins: +VREF
and –VREF. The absolute voltage on either pin, +VREF or
–VREF, can range from AGND to AVDD. However, the following limitations apply:
For AVDD = 5.0V and RANGE = 0 in the ACR, the differential
VREF must not exceed 2.5V.
For AVDD = 5.0V and RANGE = 1 in the ACR, the differential
VREF must not exceed 5V.
For AVDD = 3.0V and RANGE = 0 in the ACR, the differential
VREF must not exceed 1.25V.
For AVDD = 3.0V and RANGE = 1 in the ACR, the differential
VREF must not exceed 2.5V.
CLOCK GENERATOR
The clock source for the ADS1240 and ADS1241 can be
provided from a crystal, oscillator, or external clock. When the
clock source is a crystal, external capacitors must be provided
to ensure start-up and stable clock frequency. This is shown in
both Figure 5 and Table II. XOUT is only for use with external
crystals and it should not be used as a clock driver for external
circuitry.
12
XIN
C1
Crystal
XOUT
C2
FIGURE 5. Crystal Connection.
CLOCK
SOURCE
FREQUENCY
C1
C2
PART
NUMBER
Crystal
2.4576
0-20pF
0-20pF
ECS, ECSD 2.45 - 32
Crystal
4.9152
0-20pF
0-20pF
ECS, ECSL 4.91
Crystal
4.9152
0-20pF
0-20pF
ECS, ECSD 4.91
Crystal
4.9152
0-20pF
0-20pF
CTS, MP 042 4M9182
TABLE II. Recommended Crystals.
DIGITAL FILTER
The ADS1240 and ADS1241 have a 1279 tap linear phase
Finite Impulse Response (FIR) digital filter that a user can
configure for various output data rates. When a 2.4576MHz
crystal is used, the device can be programmed for an output
data rate of 15Hz, 7.5Hz, or 3.75Hz. Under these conditions,
the digital filter rejects both 50Hz and 60Hz interference. Figure
6 shows the digital filter frequency response for data output
rates of 15Hz, 7.5Hz, and 3.75Hz.
If a different data output rate is desired, a different crystal
frequency can be used. However, the rejection frequencies
shift accordingly. For example, a 3.6864MHz master clock with
the default register condition has:
(3.6864MHz/2.4576MHz) • 15Hz = 22.5Hz data output rate
and the first and second notch is:
1.5 • (50Hz and 60Hz) = 75Hz and 90Hz
DATA I/O INTERFACE
The ADS1240 has four pins and the ADS1241 has eight pins
that serve a dual purpose as both analog inputs and data
I/O. These pins are powered from AVDD and are configured
through the IOCON, DIR, and DIO registers. These pins
can be individually configured as either analog inputs or data
I/O. See Figure 7 (page 14) for the equivalent schematic of
an Analog/Data I/O pin.
The IOCON register defines the pin as either an analog input
or data I/O. The power-up state is an analog input. If the pin
is configured as an analog input in the IOCON register, the
DIR and DIO registers have no effect on the state of the pin.
If the pin is configured as data I/O in the IOCON register,
then DIR and DIO are used to control the state of the pin.
The DIR register controls the direction of the data pin, either
as an input or output. If the pin is configured as an input in
the DIR register, then the corresponding DIO register bit
reflects the state of the pin. Make sure the pin is driven to a
ADS1240, 1241
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SBAS173F
ADS1240 AND ADS1241
FILTER RESPONSE WHEN fDATA = 15Hz
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN fDATA = 15Hz
0
–40
–20
–50
–40
–60
Magnitude (dB)
Gain (dB)
–60
–80
–100
–120
–140
–90
–100
–110
–130
–180
–140
0
20
40
60
80
100 120
140 160 180 200
45
50
55
60
Frequency (Hz)
Frequency (Hz)
ADS1240 AND ADS1241
FILTER RESPONSE WHEN fDATA = 7.5Hz
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN fDATA = 7.5Hz
0
–40
–20
–50
–40
–60
Magnitude (dB)
–60
Gain (dB)
–80
–120
–160
–80
–100
–120
65
–70
–80
–90
–100
–110
–140
–120
–160
–130
–180
–140
0
20
Frequency (Hz)
55
Frequency (Hz)
ADS1240 AND ADS1241
FILTER RESPONSE WHEN fDATA = 3.75Hz
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN fDATA = 3.75Hz
40
60
80
100 120
45
140 160 180 200
0
–40
–20
–50
–40
–60
–60
–70
Magnitude (dB)
Gain (dB)
–70
–80
–100
–120
–140
50
60
65
–80
–90
–100
–110
–120
–160
–130
–180
–140
0
20
40
60
80
100 120
140 160 180 200
45
50
Frequency (Hz)
55
60
65
Frequency (Hz)
fOSC = 2.4576MHz, SPEED = 0 or fOSC = 4.9152MHz, SPEED = 1
ATTENUATION
DATA
OUTPUT RATE
–3dB
BANDWIDTH
fIN = 50 ± 0.3Hz
fIN = 60 ± 0.3Hz
fIN = 50 ± 1Hz
15Hz
14.6Hz
–80.8dB
–87.3dB
–68.5dB
–76.1dB
7.5Hz
3.44Hz
–85.9dB
–87.4dB
–71.5dB
–76.2dB
3.75Hz
1.65Hz
–93.8dB
–88.6dB
–86.8dB
–77.3dB
fIN = 60 ± 1Hz
FIGURE 6. Filter Frequency Responses.
ADS1240, 1241
SBAS173F
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13
logic one or zero when configured as an input to prevent
excess current dissipation. If the pin is configured as an
output in the DIR register, then the corresponding DIO
register bit value determines the state of the output pin
(0 = AGND, 1 = AVDD).
Data Continuous Mode (RDATAC) command should not be
issued when DIN and DOUT are connected. While in RDATAC
mode, DIN looks for the STOPC or RESET command. If
either of these 8-bit bytes appear on DOUT (which is connected to DIN), the RDATAC mode ends.
It is still possible to perform A/D conversions on a pin
configured as data I/O. This may be useful as a test mode,
where the data I/O pin is driven and an A/D conversion is
done on the pin.
DATA READY DRDY PIN
IOCON
DIR
DIO WRITE
The status of DRDY can also be obtained by interrogating bit
7 of the ACR register (address 2H). The serial interface can
operate in 3-wire mode by tying the CS input LOW. In this
case, the SCLK, DIN, and DOUT lines are used to communicate with the ADS1240 and ADS1241. This scheme is
suitable for interfacing to microcontrollers. If CS is required
as a decoding signal, it can be generated from a port bit of
the microcontroller.
AINx/Dx
To Analog Mux
DIO READ
FIGURE 7. Analog/Data Interface Pin.
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) allows a controller to
communicate synchronously with the ADS1240 and ADS1241.
The ADS1240 and ADS1241 operate in slave-only mode.
The serial interface is a standard four-wire SPI (CS , SCLK,
DIN and DOUT) interface that supports both serial clock
polarities (POL pin).
Chip Select (CS )
The chip select (CS ) input must be externally asserted
before communicating with the ADS1240 or ADS1241. CS
must stay LOW for the duration of the communication.
Whenever CS goes HIGH, the serial interface is reset. CS
may be hard-wired LOW.
Serial Clock (SCLK)
The serial clock (SCLK) features a Schmitt-triggered input
and is used to clock DIN and DOUT data. Make sure to have
a clean SCLK to prevent accidental double-shifting of the
data. If SCLK is not toggled within 3 DRDY pulses, the serial
interface resets on the next SCLK pulse and starts a new
communication cycle. A special pattern on SCLK resets the
entire chip; see the RESET section for additional information.
Clock Polarity (POL)
The clock polarity input (POL) controls the polarity of SCLK.
When POL is LOW, data is clocked on the falling edge of
SCLK and SCLK should be idled LOW. Likewise, when POL
is HIGH, the data is clocked on the rising edge of SCLK and
SCLK should be idled HIGH.
Data Input (DIN) and Data Output (DOUT)
The data input (DIN) and data output (DOUT) receive and send
data from the ADS1240 and ADS1241. DOUT is high impedance when not in use to allow DIN and DOUT to be connected
together and driven by a bidirectional bus. Note: the Read
14
The DRDY line is used as a status signal to indicate when
data is ready to be read from the internal data register.
DRDY goes LOW when a new data word is available in the
DOR register. It is reset HIGH when a read operation from
the data register is complete. It also goes HIGH prior to the
updating of the output register to indicate when not to read
from the device to ensure that a data read is not attempted
while the register is being updated.
DSYNC OPERATION
Synchronization can be achieved either through the DSYNC
pin or the DSYNC command. When the DSYNC pin is used,
the digital circuitry is reset on the falling edge of DSYNC.
While DSYNC is LOW, the serial interface is deactivated.
Reset is released when DSYNC is taken HIGH. Synchronization occurs on the next rising edge of the system clock
after DSYNC is taken HIGH.
When the DSYNC command is sent, the digital filter is reset
on the edge of the last SCLK of the DSYNC command. The
modulator is held in RESET until the next edge of SCLK is
detected. Synchronization occurs on the next rising edge of
the system clock after the first SCLK following the DSYNC
command.
POWER-UP—SUPPLY VOLTAGE RAMP RATE
The power-on reset circuitry was designed to accommodate
digital supply ramp rates as slow as 1V/10ms. To ensure
proper operation, the power supply should ramp monotonically.
RESET
The user can reset the registers to their default values in
three different ways: by asserting the RESET pin; by issuing
the RESET command; or by applying a special waveform on
the SCLK (the SCLK Reset Waveform, as shown in the
Timing Diagram). Note: if both POL and SCLK pins are held
high, applying the SCLK Reset Waveform to the CS pin also
resets the part.
ADS1240, 1241
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SBAS173F
ADS1240 AND ADS1241
REGISTER
tion needed to configure the part, such as data format,
multiplexer settings, calibration settings, data rate, etc. The
set of the 16 registers are shown in Table III.
The operation of the device is set up through individual
registers. Collectively, the registers contain all the informa-
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00H
01H
SETUP
MUX
ID
PSEL3
ID
PSEL2
ID
PSEL1
ID
PSEL0
BOCS
NSEL3
PGA2
NSEL2
PGA1
NSEL1
PGA0
NSEL0
02H
03H
ACR
ODAC
DRDY
SIGN
U/B
OSET6
SPEED
OSET5
BUFEN
OSET4
BIT ORDER
OSET3
RANGE
OSET2
DR1
OSET1
DR0
OSET0
04H
05H
DIO
DIR
DIO_7
DIR_7
DIO_6
DIR_6
DIO_5
DIR_5
DIO_4
DIR_4
DIO_3
DIR_3
DIO_2
DIR_2
DIO_1
DIR_1
DIO_0
DIR_0
06H
07H
IOCON
OCR0
IO7
OCR07
IO6
OCR06
IO5
OCR05
IO4
OCR04
IO3
OCR03
IO2
OCR02
IO1
OCR01
IO0
OCR00
08H
09H
OCR1
OCR2
OCR15
OCR23
OCR14
OCR22
OCR13
OCR21
OCR12
OCR20
OCR11
OCR19
OCR10
OCR18
OCR09
OCR17
OCR08
OCR16
0AH
0BH
FSR0
FSR1
FSR07
FSR15
FSR06
FSR14
FSR05
FSR13
FSR04
FSR12
FSR03
FSR11
FSR02
FSR10
FSR01
FSR09
FSR00
FSR08
0CH
0DH
FSR2
DOR2
FSR23
DOR23
FSR22
DOR22
FSR21
DOR21
FSR20
DOR20
FSR19
DOR19
FSR18
DOR18
FSR17
DOR17
FSR16
DOR16
0EH
0FH
DOR1
DOR0
DOR15
DOR07
DOR14
DOR16
DOR13
FSR21
DOR12
DOR04
DOR11
DOR03
DOR10
DOR02
DOR09
DOR01
DOR08
DOR00
TABLE III. Registers.
DETAILED REGISTER DEFINITIONS
MUX (Address 01H) Multiplexer Control Register
Reset Value = 01H
SETUP (Address 00H) Setup Register
Reset Value = iiii0000
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ID
ID
ID
ID
BOCS
PGA2
PGA1
PGA0
bit 7-4
Factory Programmed Bits
bit 3
BOCS: Burnout Current Source
0 = Disabled (default)
1 = Enabled
bit 2-0
PGA2: PGA1: PGA0: Programmable Gain Amplifier
Gain Selection
000 = 1 (default)
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 128
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSEL3
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL1
NSEL0
bit 7-4
PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel
Select
0000 = AIN0 (default)
0001 = AIN1
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1xxx = AINCOM (except when xxx = 111)
1111 = Reserved
bit 3-0
NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel
Select
0000 = AIN0
0001 = AIN1 (default)
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1xxx = AINCOM (except when xxx = 111)
1111 = Reserved
ADS1240, 1241
SBAS173F
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15
ODAC (Address 03 ) Offset DAC
Reset Value = 00H
ACR (Address 02H) Analog Control Register
Reset Value = X0H
bit 7
bit 6
bit 5
bit 4
DRDY
U/B
SPEED
BUFEN
bit 3
bit 2
BIT ORDER RANGE
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DR1
DR0
SIGN
OSET6
OSET5
OSET4
OSET3
OSET2
OSET1
OSET0
bit 7
DRDY: Data Ready (Read Only)
This bit duplicates the state of the DRDY pin.
bit 6
U/B: Data Format
0 = Bipolar (default)
1 = Unipolar
U/B
0
1
ANALOG INPUT
DIGITAL OUTPUT (Hex)
+FSR
Zero
–FSR
+FSR
Zero
–FSR
0x7FFFFF
0x000000
0x800000
0xFFFFFF
0x000000
0x000000
bit 7
Sign
0 = Positive
1 = Negative
Offset =
VREF
 OSET [6 : 0] 
•


2 • PGA 
127
RANGE = 0
Offset =
VREF
4 • PGA
 OSET [6 : 0] 
•



127
RANGE = 1
NOTE: The offset DAC must be enabled after calibration or the calibration
nullifies the effects.
bit 5
SPEED: Modulator Clock Speed
0 = fMOD = fOSC/128 (default)
1 = fMOD = fOSC/256
bit 4
BUFEN: Buffer Enable
0 = Buffer Disabled (default)
1 = Buffer Enabled
bit 3
DIO (Address 04H) Data I/O
Reset Value = 00H
BIT ORDER: Data Output Bit Order
0 = Most Significant Bit Transmitted First (default)
1 = Least Significant Bit Transmitted First
This configuration bit controls only the bit order
within the byte of data that is shifted out. Data is
always shifted out of the part most significant byte
first. Data is always shifted into the part most
significant bit first.
bit 2
bit 1-0
RANGE: Range Select
0 = Full-Scale Input Range equal to ±V REF
(default).
1 = Full-Scale Input Range equal to ±1/2 VREF
NOTE: This allows reference voltages as high as
AVDD, but even with a 5V reference voltage the
calibration must be performed with this bit set to 0.
DR1: DR0: Data Rate
(fOSC = 2.4576MHz, SPEED = 0)
00 = 15Hz (default)
01 = 7.5Hz
10 = 3.75Hz
11 = Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIO 7
DIO 6
DIO 5
DIO 4
DIO 3
DIO 2
DIO 1
DIO 0
If the IOCON register is configured for data, a value written
to this register appears on the data I/O pins if the pin is
configured as an output in the DIR register. Reading this
register returns the value of the data I/O pins.
Bit 4 to bit 7 is not used in ADS1240.
DIR (Address 05H) Direction Control for Data I/O
Reset Value = FFH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
Each bit controls whether the corresponding data I/O pin is
an output (= 0) or input (= 1). The default power-up state is
as inputs.
Bit 4 to bit 7 is not used in ADS1240.
IOCON (Address 06H) I/O Configuration Register
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
bit 7-0
IO7: IO0: Data I/O Configuration
0 = Analog (default)
1 = Data
Configuring the pin as a data I/O pin allows it to be controlled
through the DIO and DIR registers.
Bit 4 to bit 7 is not used in ADS1240.
OCR0 (Address 07H) Offset Calibration Coefficient
(Least Significant Byte)
Reset Value = 00H
16
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
ADS1240, 1241
www.ti.com
SBAS173F
OCR1 (Address 08H) Offset Calibration Coefficient
(Middle Byte)
Reset Value = 00H
FSR2 (Address 0CH) Full-Scale Register
(Most Significant Byte)
Reset Value = 55H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR09
OCR08
FSR23
FSR22
FSR21
FSR20
FSR19
FSR18
FSR17
FSR16
OCR2 (Address 09H) Offset Calibration Coefficient
(Most Significant Byte)
Reset Value = 00H
DOR2 (Address 0DH) Data Output Register
(Most Significant Byte) (Read Only)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
DOR23
DOR22
DOR21
DOR20
DOR19
DOR18
DOR17
DOR16
FSR0 (Address 0AH) Full-Scale Register
(Least Significant Byte)
Reset Value = 59H
DOR1 (Address 0EH) Data Output Register
(Middle Byte) (Read Only)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR07
FSR06
FSR05
FSR04
FSR03
FSR02
FSR01
FSR00
DOR15
DOR14
DOR13
DOR12
DOR11
DOR10
DOR09
DOR08
FSR1 (Address 0BH) Full-Scale Register
(Middle Byte)
Reset Value = 55H
DOR0 (Address 0FH) Data Output Register
(Least Significant Byte) (Read Only)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR15
FSR14
FSR13
FSR12
FSR11
FSR10
FSR09
FSR08
DOR07
DOR06
DOR05
DOR04
DOR03
DOR02
DOR01
DOR00
ADS1240, 1241
SBAS173F
www.ti.com
17
ADS1240 AND ADS1241 CONTROL COMMAND DEFINITIONS
The commands listed in Table IV control the operations of
the ADS1240 and ADS1241. Some of the commands are
stand-alone commands (e.g., RESET) while others require
additional bytes (e.g., WREG requires the count and data
bytes).
COMMANDS
DESCRIPTION
RDATA
RDATAC
STOPC
RREG
WREG
SELFCAL
SELFOCAL
SELFGCAL
SYSOCAL
SYSGCAL
WAKEUP
DSYNC
SLEEP
RESET
Read Data
Read Data Continuously
Stop Read Data Continuously
Read from REG “rrrr”
Write to REG “rrrr”
Offset and Gain Self Cal
Self Offset Cal
Self Gain Cal
Sys Offset Cal
Sys GainCal
Wakup from SLEEP Mode
Sync DRDY
Put in SLEEP Mode
Reset to Power-Up Values
Operands:
n = count (0 to 127)
r = register (0 to 15)
x = don’t care
2nd COMMAND BYTE
OP CODE
0000
0000
0000
0001
0101
1111
1111
1111
1111
1111
1111
1111
1111
1111
0001 (01H)
0011 (03H)
1111 (0FH)
r r r r (1xH)
r r r r (5xH)
0000 (F0H)
0001 (F1H)
0010 (F2H)
0011 (F3H)
0100 (F4H)
1011 (FB H)
1100 (FCH)
1101 (FDH)
1110 (FEH)
—
—
—
xxxx_nnnn (# of regs-1)
xxxx_nnnn (# of regs-1)
—
—
—
—
—
—
—
—
—
NOTE: The received data format is always MSB First; the data out format is set by the BIT ORDER bit in the ACR register.
TABLE IV. Command Summary.
RDATA–Read Data
RDATAC–Read Data Continuous
Description: Read the most recent conversion result from the
Data Output Register (DOR). This is a 24-bit value.
Description: Read Data Continuous mode enables the continuous output of new data on each DRDY. This command
eliminates the need to send the Read Data Command on each
DRDY. This mode may be terminated by either the STOPC
command or the RESET command. Wait at least 10 fOSC after
Operands:
None
Bytes:
1
Encoding:
0000 0001
DRDY falls before reading.
Data Transfer Sequence:
DIN
DOUT
0000 0001
• • •(1)
xxxx xxxx
MSB
xxxx xxxx
Mid-Byte
NOTE: (1) For wait time, refer to timing specification.
xxxx xxxx
LSB
Operands:
None
Bytes:
1
Encoding:
0000 0011
Data Transfer Sequence:
Command terminated when “uuuu uuuu” equals STOPC or
RESET.
DRDY
DIN
0000 0011
• • •(1)
uuuu uuuu
uuuu uuuu
uuuu uuuu
MSB
Mid-Byte
LSB
Mid-Byte
LSB
•••
DOUT
DRDY
DOUT
•••
MSB
NOTE: (1) For wait time, refer to timing specification.
18
ADS1240, 1241
www.ti.com
SBAS173F
STOPC–Stop Continuous
SELFCAL–Offset and Gain Self Calibration
Description: Ends the continuous data output mode. Issue
after DRDY goes LOW.
Operands:
None
Description: Starts the process of self calibration. The Offset
Calibration Register (OCR) and the Full-Scale Register (FSR)
are updated with new values after this operation.
Bytes:
1
Operands:
None
Encoding:
0000 1111
Bytes:
1
Encoding:
1111 0000
Data Transfer Sequence:
Data Transfer Sequence:
DRDY
xxx
DIN
DIN
0000 1111
1111 0000
RREG–Read from Registers
SELFOCAL–Offset Self Calibration
Description: Output the data from up to 16 registers starting
with the register address specified as part of the instruction.
The number of registers read will be one plus the second byte
count. If the count exceeds the remaining registers, the addresses wrap back to the beginning.
Description: Starts the process of self-calibration for offset.
The Offset Calibration Register (OCR) is updated after this
operation.
Operands:
Bytes:
Encoding:
0001 rrrr xxxx nnnn
Operands:
None
Bytes:
1
r, n
Encoding:
1111 0001
2
Data Transfer Sequence:
Data Transfer Sequence:
Read Two Registers Starting from Register 01H (MUX)
0001 0001
DIN
0000 0001
• • •(1)
DOUT
xxxx xxxx
xxxx xxxx
MUX
ACR
DIN
SELFGCAL–Gain Self Calibration
Description: Starts the process of self-calibration for gain.
The Full-Scale Register (FSR) is updated with new values after
this operation.
NOTE: (1) For wait time, refer to timing specification.
Operands:
None
WREG–Write to Registers
Bytes:
1
Encoding:
1111 0010
Description: Write to the registers starting with the register
address specified as part of the instruction. The number of
registers that will be written is one plus the value of the second
byte.
Data Transfer Sequence:
Operands:
r, n
Bytes:
2
Encoding:
0101 rrrr xxxx nnnn
1111 0001
DIN
1111 0010
Data Transfer Sequence:
Write Two Registers Starting from 04H (DIO)
DIN
0101 0100
xxxx 0001
Data for DIO
Data for DIR
ADS1240, 1241
SBAS173F
www.ti.com
19
SYSOCAL–System Offset Calibration
DSYNC–Sync DRDY
Description: Initiates a system offset calibration. The input
should be set to 0V, and the ADS1240 and ADS1241 compute
the OCR value that compensates for offset errors. The Offset
Calibration Register (OCR) is updated after this operation. The
user must apply a zero input signal to the appropriate analog
inputs. The OCR register is automatically updated afterwards.
Description: Synchronizes the ADS1240 and ADS1241 to an
external event.
Operands:
None
Bytes:
1
Encoding:
1111 1100
Data Transfer Sequence:
Operands:
None
Bytes:
1
Encoding:
1111 0011
DIN
1111 1100
Data Transfer Sequence:
DIN
SLEEP–Sleep Mode
1111 0011
Description: Puts the ADS1240 and ADS1241 into a low
power sleep mode. To exit sleep mode, issue the WAKEUP
command.
SYSGCAL–System Gain Calibration
Description: Starts the system gain calibration process. For
a system gain calibration, the input should be set to the
reference voltage and the ADS1240 and ADS1241 compute
the FSR value that will compensate for gain errors. The FSR
is updated after this operation. To initiate a system gain
calibration, the user must apply a full-scale input signal to the
appropriate analog inputs. FCR register is updated automatically.
Operands:
None
Bytes:
1
Encoding:
1111 0100
None
Bytes:
1
Encoding:
1111 1101
Data Transfer Sequence:
DIN
1111 1101
RESET–Reset to Default Values
Description: Restore the registers to their power-up values.
This command stops the Read Continuous mode.
Data Transfer Sequence:
DIN
Operands:
1111 0100
Operands:
None
Bytes:
1
Encoding:
1111 1110
Data Transfer Sequence:
DIN
WAKEUP
1111 1110
Description: Wakes the ADS1240 and ADS1241 from SLEEP
mode.
Operands:
None
Bytes:
1
Encoding:
1111 1011
Data Transfer Sequence:
DIN
20
1111 1011
ADS1240, 1241
www.ti.com
SBAS173F
APPLICATION EXAMPLES
output can be directly applied to the differential inputs of
ADS1240.
GENERAL-PURPOSE WEIGH SCALE
HIGH PRECISION WEIGH SCALE
Figure 8 shows a typical schematic of a general-purpose
weigh scale application using the ADS1240. In this example,
the internal PGA is set to either 64 or 128 (depending on the
maximum output voltage of the load cell) so that the load cell
Figure 9 shows the typical schematic of a high-precision
weigh scale application using the ADS1240. The front-end
differential amplifier helps maximize the dynamic range.
2.7V ~ 5.25V
2.7V ~ 5.25V
EMI Filter
AVDD
VREF+
DVDD
VDD
EMI Filter
AIN0
DRDY
Load Cell
SCLK
DOUT
ADS1240
SPI
DOUT
MSP430x4xx
or other µP
CS
EMI Filter
AIN1
MCLK
XIN
XOUT
VREF–
AGND
DGND
GND
EMI Filter
FIGURE 8. Schematic of a General-Purpose Weigh Scale.
2.7V ~ 5.25V
2.7V ~ 5.25V
EMI Filter
AVDD
VREF+
DVDD
VDD
EMI Filter
RI
OPA2335
AIN0
Load Cell
RF
DRDY
SCLK
ADS1240
ADS1241
CI
RG
DOUT
DIN
RF
SPI
MSP430x4xx
or other µP
CS
RI
EMI Filter
OPA2335
AIN1
XIN
VREF–
AGND
MCLK
XOUT
DGND
GND
EMI Filter
G = 1 + 2 • RF/RG
FIGURE 9. Block Diagram for a High-Precision Weigh Scale.
ADS1240, 1241
SBAS173F
www.ti.com
21
fMOD =
DEFINITION OF TERMS
An attempt has been made to be consistent with the terminology used in this data sheet. In that regard, the definition
of each term is given as follows:
fSAMP—the frequency, or switching speed, of the input samPGA SETTING
Analog Input Voltage—the voltage at any one analog input
relative to AGND.
Analog Input Differential Voltage—given by the following
equation: (IN+) – (IN–). Thus, a positive digital output is
produced whenever the analog input differential voltage is
positive, while a negative digital output is produced whenever
the differential is negative.
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 1, the positive
full-scale output is produced when the analog input differential is 2.5V. The negative full-scale output is produced when
the differential is –2.5V. In each case, the actual input
voltages must remain within the AGND to AVDD range.
Conversion Cycle—the term conversion cycle usually refers
to a discrete A/D conversion operation, such as that performed by a successive approximation converter. As used
here, a conversion cycle refers to the tDATA time period.
Data Rate—The rate at which conversions are completed.
See definition for fDATA.
fDATA =
fOSC
128 • 2 SPEED • 1280 • 2DR
SPEED = 0, 1
DR = 0, 1, 2
fOSC—the frequency of the crystal oscillator or CMOS compatible input signal at the XIN input of the ADS1240 and
ADS1241.
fOSC
fOSC
=
mfactor 128 • 2 SPEED
SAMPLING FREQUENCY
1, 2, 4, 8
f SAMP =
fOSC
mfactor
16
f SAMP =
fOSC • 2
mfactor
32
f SAMP =
fOSC • 4
mfactor
64, 128
f SAMP =
fOSC • 8
mfactor
pling capacitor. The value is given by one of the following
equations:
fDATA—the frequency of the digital output data produced by
the ADS1240 and ADS1241, fDATA is also referred to as the
Data Rate.
Full-Scale Range (FSR)—as with most A/D converters, the
full-scale range of the ADS1240 and ADS1241 is defined as
the input, that produces the positive full-scale digital output
minus the input, that produces the negative full-scale digital
output.
For example, when the converter is configured with a 2.5V
reference and is placed in a gain setting of 2, the full-scale
range is: [1.25V (positive full-scale) minus –1.25V (negative
full-scale)] = 2.5V.
Least Significant Bit (LSB) Weight—this is the theoretical
amount of voltage that the differential voltage at the analog
input has to change in order to observe a change in the
output data of one least significant bit. It is computed as
follows:
fMOD—the frequency or speed at which the modulator of the
ADS1240 and ADS1241 is running. This depends on the
SPEED bit as given by the following equation:
LSB Weight =
Full− Scale Range
2N – 1
where N is the number of bits in the digital output.
mfactor
SPEED = 0
SPEED = 1
128
256
tDATA—the inverse of fDATA, or the period between each data
output.
5V SUPPLY ANALOG INPUT(1)
GENERAL EQUATIONS
GAIN SETTING
FULL-SCALE RANGE
DIFFERENTIAL
INPUT VOLTAGES(2)
PGA OFFSET
RANGE
FULL-SCALE
RANGE
DIFFERENTIAL
INPUT VOLTAGES(2)
1
2
4
8
16
32
64
128
5V
2.5V
1.25V
0.625V
312.5mV
156.25mV
78.125mV
39.0625mV
±2.5V
±1.25V
±0.625V
±312.5mV
±156.25mV
±78.125mV
±39.0625mV
±19.531mV
±1.25V
±0.625V
±312.5mV
±156.25mV
±78.125mV
±39.0625mV
±19.531mV
±9.766mV
2 • VREF
PGA
±VREF
PGA
PGA SHIFT
RANGE
± VREF
2 • PGA
RANGE = 0
VREF
PGA
± VREF
2 • PGA
± VREF
4 • PGA
RANGE = 1
NOTES: (1) With a 2.5V reference. (2) Refer to electrical specification for analog input voltage range.
TABLE VI. Full-Scale Range versus PGA Setting.
22
ADS1240, 1241
www.ti.com
SBAS173F
Revision History
DATE
REVISION
PAGE
SECTION
10/13
F
21
Application Examples
8/06
E
6
Timing Characteristics Table
DESCRIPTION
Changed Figure 9; switched plus and minus in upper op amp.
Clarified t10 specification.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
ADS1240, 1241
SBAS173F
www.ti.com
23
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS1240E
ACTIVE
SSOP
DB
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS1240E
ADS1240E/1K
ACTIVE
SSOP
DB
24
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS1240E
ADS1240E/1KG4
ACTIVE
SSOP
DB
24
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS1240E
ADS1240EG4
ACTIVE
SSOP
DB
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS1240E
ADS1241E
ACTIVE
SSOP
DB
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS1241E
ADS1241E/1K
ACTIVE
SSOP
DB
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS1241E
ADS1241E/1KG4
ACTIVE
SSOP
DB
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS1241E
ADS1241EG4
ACTIVE
SSOP
DB
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS1241E
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
30-Jun-2016
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS1240E/1K
SSOP
DB
24
1000
330.0
16.4
8.2
8.8
2.5
12.0
16.0
Q1
ADS1241E/1K
SSOP
DB
28
1000
330.0
16.4
8.1
10.4
2.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Oct-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS1240E/1K
SSOP
DB
24
1000
367.0
367.0
38.0
ADS1241E/1K
SSOP
DB
28
1000
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
DB0028A
SSOP - 2 mm max height
SCALE 1.500
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
26X 0.65
28
1
2X
10.5
9.9
NOTE 3
8.45
14
15
28X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.15
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214853/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
28X (1.85)
(R0.05) TYP
1
28X (0.45)
28
26X (0.65)
SYMM
15
14
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214853/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
28X (1.85)
SYMM
(R0.05) TYP
1
28X (0.45)
28
26X (0.65)
SYMM
14
15
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214853/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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