Texas Instruments | QUAD CHANNEL, 14 BIT, 125/105 MSPS ADC WITH SERIAL LVDS OUTPUTS (Rev. C) | Datasheet | Texas Instruments QUAD CHANNEL, 14 BIT, 125/105 MSPS ADC WITH SERIAL LVDS OUTPUTS (Rev. C) Datasheet

Texas Instruments QUAD CHANNEL, 14 BIT, 125/105 MSPS ADC WITH SERIAL LVDS OUTPUTS (Rev. C) Datasheet
ADS6445-EP
ADS6444-EP
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SLAS573C – FEBRUARY 2008 – REVISED MAY 2013
QUAD CHANNEL, 14 BIT, 125/105 MSPS ADC WITH SERIAL LVDS OUTPUTS
Check for Samples: ADS6445-EP, ADS6444-EP
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
Maximum Sample Rate: 125 MSPS
14-Bit Resolution with No Missing Codes
Simultaneous Sample and Hold
3.5-dB Coarse Gain and up to 6-dB
Programmable Fine Gain for SFDR/SNR TradeOff
Serialized LVDS Outputs with Programmable
Internal Termination Option
Supports Sine, LVCMOS, LVPECL, LVDS Clock
Inputs and Amplitude Down to 400 mVPP
Internal Reference with External Reference
Support
No External Decoupling Required for
References
3.3-V Analog and Digital Supply
64-pin QFN Package (9 mm × 9 mm)
Feature Compatible Dual Channel Family
Base-Station IF Receivers
Diversity Receivers
Medical Imaging
Test Equipment
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly and Test Site
One Fabrication Site
Available in Military (–55°C to 125°C)
Temperature Range
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Table 1. ADS644X Quad Channel Family (1)
ADS644X
14 Bit
(1)
125 MSPS
105 MSPS
ADS6445
ADS6444
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Table 2. Performance Summary
SFDR, dBc
SINAD, dBFS
Fin = 10 MHz (0 dB gain)
Fin = 170 MHz (3.5 dB gain)
ADS6445
ADS6444
87
91
79
83
Fin = 10 MHz (0 dB gain)
73.4
73.4
Fin = 170 MHz (3.5 dB gain)
68.3
69.3
Power, per channel, mW
420
340
DESCRIPTION
The ADS6445/ADS6444 is a high performance 14 bit 125/105 MSPS quad channel A-D converter. Serial LVDS
data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm)
that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to
improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also
exist, programmable in 1 dB steps up to 6 dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it
possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1 Gbps easing
receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling
frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit
clock is used to serialize the 14 bit data from each channel. In addition to the serial data streams, the frame and
bit clocks also are transmitted as LVDS outputs.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and
internal termination options. These can be used to widen eye openings and improve signal integrity, easing
capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.
The ADS644X has internal references, but also can support an external reference mode. The device is specified
over –55°C to 125°C operating junction temperature range.
2
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
LVDD
LGND
CAP
AVDD
AGND
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
CLKP
CLKM
BIT Clock
DCLKP
DCLKM
FRAME Clock
FCLKP
FCLKM
PLL
14 Bit
ADC
Digital
Encoder
and
Serializer
14 Bit
ADC
Digital
Encoder
and
Serializer
SHA
14 Bit
ADC
Digital
Encoder
and
Serializer
SHA
14 Bit
ADC
Digital
Encoder
and
Serializer
INA_P
SHA
INA_M
INB_P
SHA
INB_M
INC_P
INC_M
IND_P
VCM
DA1_P
DA1_M
DB0_P
DB0_M
DB1_P
DB1_M
DC0_P
DC0_M
DC1_P
DC1_M
DD0_P
DD0_M
DD1_P
DD1_M
REFM
REFP
IND_M
DA0_P
DA0_M
Reference
Parallel
Interface
Serial
Interface
SCLK
RESET
SEN
SDATA
CFG4
CFG3
CFG1
CFG2
PDN
ADS644x
B0199-03
ORDERING INFORMATION (1)
PRODUCT
ADS6445
ADS6444
(1)
(2)
(3)
PACKAGE-LEAD
PACKAGE
DESIGNATOR (2)
SPECIFIED
JUNCTION
TEMPERATURE
RANGE
QFN-64 (3)
RGC
–55°C to 125°C
PACKAGE
MARKING
ORDERING NUMBER
6445EP
ADS6445MRGCTEP
6444EP
ADS6444MRGCTEP
TRANSPORT
MEDIA,
QUANTITY
250, Tape/reel
VID NUMBER
V62/08628-01XE
V62/08628-02XE
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 23.17 °C/W (0 LFM air flow), θJC
= 22.1 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in. x 3 in. PCB.
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ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
AVDD
Supply voltage range
–0.3 to 3.9
V
LVDD
Supply voltage range
–0.3 to 3.9
V
Voltage between AGND and DGND
–0.3 to 0.3
V
Voltage between AVDD to LVDD
–0.3 to 3.3
V
Voltage applied to external pin, VCM
–0.3 to 2.0
V
Voltage applied to analog input pins
–0.3 V to minimum ( 3.6, AVDD + 0.3 V)
V
TJ
Operating junction temperature
Tstg
Storage temperature range
150
°C
–65 to 150
°C
220
°C
Lead temperature 1,6 mm (1/16") from the case for 10 seconds
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
xxx
Lifetime Expectancy (Years)
100.00
10.00
1.00
85
95
105
115
125
135
145
Junction Temperature, T J (°C)
(1)
See datasheet for absolute maximum and minimum recommended operating conditions.
(2)
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3)
Enhanced plastic product disclaimer applies.
Figure 1. Lifetime Expectancy Graph at Elevated Temperature
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THERMAL INFORMATION
ADS644x-EP
THERMAL METRIC (1)
RGC
UNITS
64 PINS
Junction-to-ambient thermal resistance (2)
θJA
23.6
(3)
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
ψJT
Junction-to-top characterization parameter (5)
ψJB
Junction-to-board characterization parameter (6)
3
θJCbot
Junction-to-case (bottom) thermal resistance (7)
0.3
(1)
(2)
(3)
(4)
(5)
(6)
(7)
7.7
3
°C/W
0.1
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
3.0
3.3
3.6
V
LVDD
LVDS Buffer supply voltage
3.0
3.3
3.6
V
ANALOG INPUTS
Differential input voltage range
2
Input common-mode voltage
Vpp
1.5±0.1
Voltage applied on VCM in external reference mode
1.45
1.50
V
1.55
V
CLOCK INPUT
Input clock sample rate, Fsrated
ADS6445
5
125
ADS6444
5
105
Sine wave, ac coupled
Input clock amplitude differential (VCLKP – VCLKM)
0.4
LVPECL, ac coupled
Vpp
± 0.35
LVCMOS, ac coupled
Input Clock duty cycle
1.5
± 0.8
LVDS, ac coupled
MSPS
3.3
35
50
65
%
DIGITAL OUTPUTS
Without internal termination
CLOAD
Maximum external load capacitance from each output pin
to DGND
RLOAD
Differential load resistance (external) between the LVDS output pairs
With internal termination
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5
10
100
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pF
Ω
5
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ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full junction temperature range TJ,MIN = –55°C to TJ,MAX =
125°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input,
internal reference mode (unless otherwise noted).
ADS6445
Fs = 125 MSPS
PARAMETER
MIN
RESOLUTION
TYP
ADS6444
Fs = 105 MSPS
MAX
MIN
TYP
UNIT
MAX
14
14
Bits
2.0
2.0
VPP
7
7
Analog input bandwidth
500
500
MHz
Analog input common mode current (per input pin
of each ADC)
155
130
μA
V
ANALOG INPUT
Differential input voltage range
Differential input capacitance
pF
REFERENCE VOLTAGES
VREFB
Internal reference bottom voltage
1.0
1.0
VREFT
Internal reference top voltage
2.0
2.0
ΔVREF
Internal reference error (VREFT–VREFB)
VCM
Common mode output voltage
1.5
1.5
V
VCM output current capability
±4
±4
mA
0.985
1
1.015
0.985
1
V
1.015
V
DC ACCURACY
No missing codes
EO
Assured
Offset error, across devices and across channels
within a device
–15
Offset error temperature coefficient, across
devices and across channels within a device
±2
Assured
15
–15
0.05
±2
15
0.05
mV
mV/°C
There are two sources of gain error - internal reference inaccuracy and channel gain error
EGREF
Gain error due to internal reference inaccuracy
alone, (ΔVREF /2.0) %
-0.75
Reference gain error temperature coefficient
EGCHAN
Gain error of channel alone, across devices and
across channels within a device
Channel gain error temperature coefficient, across
devices and across channels within a device
DNL
Differential nonlinearity, Fin = 50 MHz
INL
Integral nonlinearity, Fin = 50 MHz
PSRR
DC power supply rejection ratio
0.1
0.75
-0.75
0.1
0.75
% FS
0.0125
0.0125
Δ%/°C
±0.3
±0.3
% FS
0.005
0.005
Δ%/°C
–0.99
±0.6
2.0
–0.99
±0.6
2.0
-5
±3
5
-5
±3
5
LSB
LSB
0.5
0.5
mV/V
POWER SUPPLY
ICC
Total supply current
502
410
mA
IAVDD
Analog supply current
410
322
mA
ILVDD
LVDS supply current
92
88
Total power
Power down (with input clock stopped)
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mA
1.65
1.8
1.35
1.5
W
77
150
77
150
mW
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ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full junction temperature range TJ,MIN = –55°C to TJ,MAX =
125°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input,
internal reference mode (unless otherwise noted).
PARAMETER
TEST CONDITIONS
ADS6445
Fs = 125 MSPS
MIN
TYP
ADS6444
Fs = 105 MSPS
MAX
MIN
TYP
UNIT
MAX
DYNAMIC AC CHARACTERISTICS
Fin = 10 MHz
73.7
Fin = 50 MHz
SNR
Signal to noise
ratio
68.5
72.7
Fin = 100 MHz
72.1
72.2
0 dB gain
69.9
70.2
3.5 dB Coarse gain
69.4
69.7
0 dB gain
68.7
68.8
3.5 dB Coarse gain
68.1
68.2
73.4
73.4
Fin = 170 MHz
Fin = 10 MHz
Fin = 50 MHz
67.75
71.8
72
0 dB gain
67.9
69.8
3.5 dB Coarse gain
68.3
69.3
0 dB gain
67.8
67.7
3.5 dB Coarse gain
67.9
67.6
1.05
1.05
87
91
Fin = 170 MHz
Inputs tied to common-mode
69
81
72
Fin = 100 MHz
86
88
0 dB gain
76
79
3.5 dB Coarse gain
79
83
0 dB gain
77
77
3.5 dB Coarse gain
80
80
93
94
Fin = 10 MHz
Fin = 50 MHz
69
74
87
Fin = 100 MHz
89
90
0 dB gain
83
84
3.5 dB Coarse gain
85
86
0 dB gain
80
81
3.5 dB Coarse gain
82
83
87
91
Fin = 10 MHz
Fin = 50 MHz
69
74
81
88
78
Fin = 100 MHz
86
88
0 dB gain
76
79
3.5 dB Coarse gain
79
83
0 dB gain
77
77
3.5 dB Coarse gain
80
80
Fin = 230 MHz
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dBc
80
Fin = 70 MHz
Fin = 170 MHz
dBc
88
87
Fin = 230 MHz
LSB
81
Fin = 70 MHz
Fin = 170 MHz
dBFS
80
78
Fin = 230 MHz
HD3
Third harmonic
68.5
Fin = 70 MHz
Fin = 170 MHz
dBFS
71.7
Fin = 100 MHz
Fin = 50 MHz
HD2
Second harmonic
72.3
73
71.2
Fin = 10 MHz
SFDR
Spurious free
dynamic range
69
Fin = 70 MHz
Fin = 230 MHz
RMS
Output noise
73.2
Fin = 70 MHz
Fin = 230 MHz
SINAD
Signal to noise
and distortion
ratio
73.8
73.1
74
81
dBc
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ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25°C, min and max values are across the full junction temperature range TJ,MIN = –55°C to TJ,MAX =
125°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input,
internal reference mode (unless otherwise noted).
PARAMETER
TEST CONDITIONS
ADS6445
Fs = 125 MSPS
MIN
Worst harmonic
(other than HD2,
HD3)
THD
Total harmonic
distortion
TYP
ADS6444
Fs = 105 MSPS
MAX
MIN
TYP
Fin = 10 MHz
91
91
Fin = 50 MHz
87
87
Fin = 100 MHz
90
91
Fin = 170 MHz
88
88
Fin = 230 MHz
87
87
Fin = 10 MHz
86
89.5
Fin = 50 MHz
69
80
84.5
Fin = 170 MHz
73.5
86
74
77
72
79
dBc
ENOB
Effective number
of bits
Fin = 50 MHz
IMD
2-Tone intermodulation
distortion
F1= 46.09 MHz,
F2 = 50.09 MHz
88
90
F1= 185.09 MHz,
F2 = 190.09 MHz
86
88
Near channel
Cross-talk signal
frequency = 10 MHz
90
92
Far channel
Cross-talk signal
frequency = 10 MHz
103
105
1
1
Clock cycles
35
35
dBc
Cross-talk
10.95
dBc
80
Fin = 100 MHz
Fin = 230 MHz
UNIT
MAX
11.3
Fin = 70 MHz
Input overload
recovery
Recovery to within 1% (of final value) for 6dB overload with sine wave input
AC PSRR
Power supply
rejection ratio
< 100 MHz signal, 100 mVPP on AVDD
supply
8
11.7
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11.7
Bits
dBFS
dBc
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DIGITAL CHARACTERISTICS
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 AVDD = LVDD = 3.3 V, IO = 3.5 mA, RLOAD = 100 Ω (1).
All LVDS specifications are characterized, but not tested at production.
PARAMETER
TEST CONDITIONS
ASD6445/ADS6444
MIN
TYP
MAX
UNIT
DIGITAL INPUTS
High-level input voltage
2.4
V
Low-level input voltage
0.8
V
High-level input current
10
μA
Low-level input current
10
μA
4
pF
High-level output voltage
1375
mV
Low-level output voltage
1025
Input capacitance
DIGITAL OUTPUTS
Output differential voltage |VOD|
250
Output offset voltage VOS
Common-mode voltage of OUTP and OUTM
Output capacitance
Output capacitance inside the device, from either output to
ground
(1)
350
mV
450
mV
1200
mV
2
pF
IO refers to the LVDS buffer current setting, RLOAD is the external differential load resistance between the LVDS output pair.
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TIMING SPECIFICATIONS (1)
Typical values are at 25°C, min and max values are across the full junction temperature range TJ,MIN = –55°C to TJ,MAX =
125°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5
pF (2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted.
PARAMETER
TEST CONDITIONS
ADS6445
Fs = 125 MSPS
MIN
tJ
Aperture jitter
Uncertainty in the
sampling instant
TYP
ADS6444
Fs = 105 MSPS
MAX
MIN
TYP
UNIT
MAX
250
250
fs rms
From data cross-over to
bit clock cross-over
0.55
0.65
ns
From bit clock cross-over
to data cross-over
0.58
0.7
ns
Input clock rising edge
cross-over to frame clock
rising edge cross-over
4.4
4.4
ns
350
350
ps pp
75
75
ps pp
INTERFACE: 2-wire, DDR bit clock, 14x serialization
tsu
Data setup time (4)
th
Data hold time (4)
tpd_clk
(5) (6)
(5) (6)
Clock propagation delay
(6)
Bit clock cycle-cycle jitter
(5)
Frame clock cycle-cycle
jitter (5)
The following specifications apply for 5 MSPS ≤ Fs ≤ 125 MSPS and all interface options.
tA
Aperture delay
Delay from input clock
rising edge to the actual
sampling instant
2
2
ns
Aperture delay variation
Channel-channel within
same device
±80
±80
ps
12
12
Clock cycles
Time to valid data after
coming out of global
power down
100
100
μs
Time to valid data after
input clock is re-started
100
100
μs
Time to valid data after
coming out of channel
standby
200
200
Clock cycles
ADC Latency
(7)
Wake up time
Time for a sample to
propagate to ADC
outputs, see Figure 2
tRISE
Data rise time
From –100 mV to +100
mV
100
100
ps
tFALL
Data fall time
From +100 mV to –100
mV
100
100
ps
tRISE
Bit clock and frame
clock rise time
From –100 mV to +100
mV
100
100
ps
tFALL
Bit clock and frame
clock fall time
From +100 mV to –100
mV
100
100
ps
LVDS Bit clock duty
cycle
50%
50%
LVDS Frame clock duty
cycle
50%
50%
(1)
(2)
(3)
(4)
(5)
(6)
(7)
10
Timing parameters are ensured by design and characterization and not tested in production.
CL is the external single-ended load capacitance between each output pin and ground.
Io refers to the LVDS buffer current setting; RL is the external differential load resistance between the LVDS output pair.
Timing parameters are measured at the end of a 2 inch PCB trace (100 Ω characteristic impedance) terminated by RLand CL.
Setup and hold time specifications take into account the effect of jitter on the output data and clock.
Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options.
Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as
shown in Table 27.
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Sample
N+13
Sample
N+12
Sample
N+11
Sample
N
Input
Signal
tA
Input
Clock
CLKM
CLKP
tPD_CLK
Latency 12 Clocks
Bit
Clock
Output
Data
DCLKP
DCLKM
DOP
D13 D12 D11 D10
D6
D5
D4
D3
D2
D1 D0 D13 D12 D11 D10
Sample N–1
Frame
Clock
D6
D5
D4
D3
D2
D1 D0
DOM
Sample N
FCLKM
FCLKP
T0105-04
Figure 2. Latency
DCLKP
Bit Clock
DCLKM
tsu
th
tsu
Output Data
DOP, DOM
th
Dn+1
Dn
T0106-03
Figure 3. LVDS Timing
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DEVICE PROGRAMMING MODES
ADS644X offers flexibility with several programmable features that are easily configured.
The device can be configured independently using either parallel interface control or serial interface
programming.
In addition, the device supports a third configuration mode, where both the parallel interface and the serial control
registers are used. In this mode, the priority between the parallel and serial interfaces is determined by a priority
table (refer to Table 4). If this additional level of flexibility is not required, the user can select either the serial
interface programming or the parallel interface control.
USING PARALLEL INTERFACE CONTROL ONLY
To control the device using parallel interface, keep RESET tied to high (LVDD). Pins CFG1, CFG2, CFG3,
CFG4, PDN, SEN, SCLK, and SDATA are used to directly control certain functions of the ADC. After power-up,
the device is automatically configured as per the parallel pin voltage settings (refer to Table 5 to Table 8) and no
reset is required. In this mode, SEN, SCLK, and SDATA function as parallel interface control pins.
Frequently used functions are controlled in this mode—output data interface and format, power down modes,
coarse gain and internal/external reference. The parallel pins can be configured using a simple resistor string as
illustrated in Figure 4.
Table 3 has a description of the modes controlled by the parallel pins.
Table 3. Parallel Pin Definition
PIN
SEN
SCLK, SDATA
CONTROL FUNCTIONS
Coarse gain and internal/external reference.
Sync, deskew patterns and global power down.
PDN
Dedicated pin for global power down
CFG1
1-wire/2-wire and DDR/SDR bit clock
CFG2
14x/16x serialization and SDR bit clock capture edge
CFG3
Reserved function. Tie CFG3 to Ground.
CFG4
MSB/LSB first and data format.
USING SERIAL INTERFACE PROGRAMMING ONLY
In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal
registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET
pin or by a high setting on the <RST> bit (in register ). After reset, the RESET pin must be kept low.
The serial interface section describes the register programming and register reset in more detail.
Because the parallel pins (CFG1-4 and PDN) are not used in this mode, they must be tied to ground. The
register override bit <OVRD> - D10 in register 0x0D has to be set high to disable the control of parallel interface
pins in this serial interface control ONLY mode.
USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (CFG1-4 and PDN)
also can be used to configure the device.
The parallel interface control pins CFG1 to CFG4 and PDN are available. After power-up, the device is
automatically configured as per the parallel pin voltage settings (refer to Table 5 through Table 11) and no reset
is required. A simple resistor string can be used as illustrated in Figure 4.
SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC.
The registers must first be reset to their default values either by applying a pulse on RESET pin or by a high
setting on the <RST> bit (in register ). After reset, the RESET pin must be kept low.
The Serial Interface section describes the register programming and register reset in more detail.
Since some functions are controlled using both the parallel pins and serial registers, the priority between the two
is determined by a priority table (refer to Table 4).
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Table 4. Priority Between Parallel Pins and Serial Registers
PIN
FUNCTIONS SUPPORTED
PRIORITY
As described in Table 8
through Table 11
Register bits can control the modes only if the register bit <OVRD> is high. If <OVRD> bit
is low, then the control voltage on these parallel pins determines the function.
PDN
Global power down
Register bit <PDN GLOBAL> controls global power down only if PDN pin is low. If PDN is
high, device is in global power down.
SEN
Serial interface enable
CFG1 to CFG4
Coarse gain is controlled by register bit <COARSE GAIN> only if the <OVRD> bit is high.
Else, device has 0 dB coarse gain.
Internal/external reference setting is determined by register bit <REF>.
SCLK, SDATA
Serial interface clock and
serial interface data pins
Register bits <PATTERNS> control the sync and deskew output patterns.
Power down is determined by bit <PDN GLOBAL>
AVDD
(5/8) AVDD
3R
(5/8) AVDD
GND
2R
AVDD
(3/8) AVDD
(3/8) AVDD
3R
To Parallel Pin
GND
Figure 4. Simple Scheme to Configure Parallel Pins
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DESCRIPTION OF PARALLEL PINS
Table 5. SCLK, SDATA Control Pins
SCLK
SDATA
DESCRIPTION
LOW
LOW
NORMAL conversion.
LOW
HIGH
SYNC – ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the
deserialized data to the frame boundary. See Capture Test Patterns for details.
HIGH
LOW
POWER DOWN – Global power down, all channels of the ADC are powered down, including internal references,
PLL and output buffers.
HIGH
HIGH
DESKEW – ADC outputs deskew pattern on all channels. This pattern can be used by the receiver to ensure
deserializer uses the right clock edge. See Capture Test Patterns for details.
Table 6. SEN Control Pin
SEN
0
DESCRIPTION
External reference and 0 dB coarse gain (full-scale = 2 VPP)
(3/8)LVDD
External reference and 3.5 dB coarse gain (full-scale = 1.34 VPP)
(5/8)LVDD
Internal reference and 3.5 dB coarse gain (full-scale = 1.34 VPP)
LVDD
Internal reference and 0 dB coarse gain (full-scale = 2 VPP)
Independent of the programming mode used, after power-up the parallel pins PDN, CFG1 to CFG4 automatically
configure the device as per the voltage applied (refer to Table 7 to Table 11).
Table 7. PDN Control Pin
PDN
0
AVDD
DESCRIPTION
Normal operation
Power down global
Table 8. CFG1 Control Pin
CFG1
0
DESCRIPTION
DDR Bit clock and 1-wire interface
(3/8)LVDD
Not used
(5/8)LVDD
SDR Bit clock and 2-wire interface
LVDD
DDR Bit clock and 2-wire interface
Table 9. CFG2 Control Pin
CFG2
DESCRIPTION
0
14x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode)
(3/8)LVDD
16x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode)
(5/8)LVDD
16x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode)
LVDD
14x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode)
Table 10. CFG3 Control Pin
CFG3
RESERVED - TIE TO GROUND
Table 11. CFG4 Control Pin
CFG4
0
MSB First and 2s complement
(3/8)LVDD
MSB First and offset binary
(5/8)LVDD
LSB First and offset binary
LVDD
14
DESCRIPTION
LSB First and 2s complement
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SERIAL INTERFACE
The ADC has a serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock),
SDATA (serial interface data) and RESET. Serial shift of bits into the device is enabled when SEN is low. Serial
data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the
register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits,
the excess bits are ignored. Data can be loaded in multiple of 16 bit words within a single active SEN pulse. The
interface can work with SCLK frequency from 20 MHz down to very low speeds (few hertz) and even with non50% duty cycle SCLK.
The first 5 bits of the 16 bit word are the address of the register while the next 11 bits are the register data.
Register Reset
After power-up, the internal registers must be reset to their default values. This can be done in one of two ways:
1. Either by applying a high-going pulse on RESET (of width greater than 10 ns) OR
2. By applying software reset. Using the serial interface, set the <RST> bit in register 0x00 to high – this resets
the registers to their default values and then self-resets the <RST> bit to LOW.
When RESET pin is not used, it must be tied to LOW.
Register Address
SDATA
A4
A3
A2
A1
Register Data
A0
D10
D9
D8
D7
D6
t(SCLK)
D5
D4
D3
D2
D1
D0
t(DH)
t(DSU)
SCLK
t(SLOADH)
t(SLOADS)
SEN
RESET
T0109-03
Figure 5. Serial Interface Timing
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SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25°C, min and max values across the full junction temperature range TJ,MIN = –55°C to TJ,MAX = 125°C,
AVDD = LVDD = 3.3 V, unless otherwise noted.
PARAMETER
MIN
TYP
> DC
MAX
UNIT
20
MHz
fSCLK
SCLK Frequency, fSCLK = 1/tSCLK
tSLOADS
SEN to SCLK Setup time
25
ns
tSLOADH
SCLK to SEN Hold time
25
ns
tDSU
SDATA Setup time
25
ns
tDH
SDATA Hold time
25
ns
100
ns
Time taken for register write to take effect after 16th SCLK falling edge
RESET TIMING
Typical values at 25°C, min and max values across the full junction temperature range TJ,MIN = –55°C to TJ,MAX = 125°C,
AVDD = LVDD = 3.3 V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
5
MAX
UNIT
t1
Power-on delay time
Delay from power-up of AVDD and LVDD to RESET pulse
active
t2
Reset pulse width
Pulse width of active RESET signal
t3
Register write delay time Delay from RESET disable to SEN active
25
ns
tPO
Power-up delay time
6.5
ms
10
Delay from power-up of AVDD and LVDD to output stable
ms
ns
Power Supply
AVDD, LVDD
t1
RESET
t2
t3
SEN
T0108-03
Figure 6. Reset Timing
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SERIAL REGISTER MAP
Table 12. Summary of Functions Supported By Serial Interface
REGISTER
ADDRESS
A4 - A0
REGISTER FUNCTIONS (1)
D10
D9
D8
D7
00
<RST>
S/W RESET
0
0
0
04
0
0
0
0
0
<DF>
DATA
FORMAT 2S
COMP OR
STRAIGHT
BINARY
0
0A
0D
10
11
(1)
(2)
0
D5
<REF>
INTERNAL
OR
EXTERNAL
D4
D3
<PDN CHD>
POWER
DOWN CH D
<PDN CHC>
POWER
DOWN CHC
D2
<PDN CHB>
POWER
DOWN CH B
<CLKIN GAIN>
INPUT CLOCK BUFFER GAIN CONTROL
<PATTERNS>
TEST PATTERNS
0
0
0
D1
D0
<PDN CHA>
POWER
DOWN CH A
<PDN
GLOBAL>
GLOBAL
POWER
DOWN
0
0
0
0
<CUSTOM A>
CUSTOM PATTERN (LOWER 11 BITS)
0B
0C
D6
(2)
<FINE GAIN>
FINE GAIN CONTROL (1 dB to 6 dB)
<OVRD>
OVERRIDE
BIT
0
0
0
0
0
0
0
BYTE-WISE
OR BITWISE
MSB OR
LSB FIRST
<COARSE
GAIN>
COURSE
GAIN
ENABLE
FALLING OR
RISING BIT
CLOCK
CAPTURE
EDGE
0
<TERM CLK>
LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS
WORD-WISE CONTROL
0
0
<LVDS CURR>
LVDS CURRENT SETTINGS
0
0
<CUSTOM B>
CUSTOM PATTERN (UPPER 3 BITS)
14 BIT OR
16 BIT
SERIALIZE
DDR OR
SDR BIT
CLOCK
1-WIRE OR
2-WIRE
INTERFACE
<CURR DOUBLE>
LVDS CURRENT DOUBLE
<TERM DATA>
LVDS INTERNAL TERMINATION - DATA OUTPUTS
The unused bits in each register (shown by blank cells in above table) must be programmed as 0.
Multiple functions in a register can be programmed in a single write operation.
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DESCRIPTION OF SERIAL REGISTERS
Table 13. Serial Register A
REGISTER
ADDRESS
A4 - A0
BITS
D10
<RST>
S/W RESET
00
D9
0
D8
D7
0
0
D6
D5
D4
D3
D2
D1
D0
0
<REF>
INTERNAL
OR
EXTERNAL
<PDN CHD>
POWER
DOWN CH D
<PDN CHC>
POWER
DOWN CHC
<PDN CHB>
POWER
DOWN CH B
<PDN CHA>
POWER
DOWN CH A
<PDN>
GLOBAL
POWER
DOWN
D0 - D4
Power down modes
D0
<PDN GLOBAL>
0
Normal operation
1
Global power down, including all channels ADCs, internal references, internal PLL and output
buffers
D1
<PDN CHA>
0
CH A Powered up
1
CH A ADC Powered down
D2
<PDN CHB>
0
CH B Powered up
1
CH B ADC Powered down
D3
<PDN CHC>
0
CH C Powered up
1
CH C ADC Powered down
D4
<PDN CHD>
0
CH D Powered up
1
CH D ADC Powered down
D5
<REF> Reference
0
Internal reference enabled
1
External reference enabled
D10
<RST>
1
Software reset applied – resets all internal registers and self-clears to 0
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Table 14. Serial Register B
REGISTER
ADDRESS
A4 - A0
04
BITS
D10
0
D9
0
D8
D7
0
D6
D5
D4
D3
D2
<CLKIN GAIN>
INPUT CLOCK BUFFER GAIN CONTROL
0
D6 - D2
<CLKIN GAIN> Input clock buffer gain control
11000
Gain 0, minimum gain
00000
Gain 1, default gain after reset
01100
Gain 2
01010
Gain 3
01001
Gain 4
01000
Gain 5, maximum gain
D1
D0
0
0
Table 15. Serial Register C
REGISTER
ADDRESS
A4 - A0
00
BITS
D10
D9
D8
0
<DF>
DATA
DORMAT 2S
COMP OR
STRAIGHT
BINARY
0
D7
D6
D5
<PATTERNS>
TEST PATTERNS
D4
D3
D2
D1
D0
0
0
0
0
0
D7 - D5
<PATTERNS> Capture test patterns
000
Normal ADC operation
001
Output all zeros
010
Output all ones
011
Output toggle pattern
100
Unused
101
Output custom pattern (contents of CUSTOM pattern registers 0x0B and 0x0C)
110
Output DESKEW pattern (serial stream of 1010..)
111
Output SYNC pattern
D9
<DF> Data format selection
0
2s Complement format
1
Straight binary format
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Table 16. Serial Register D
REGISTER
ADDRESS
A4 - A0
BITS
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D2
D1
D0
<CUSTOM A>
CUSTOM PATTERN (LOWER 11 BITS)
0B
D10 - D0
<CUSTOM A> Lower 11 bits of custom pattern <D10>…<D0>
Table 17. Serial Register E
REGISTER
ADDRESS
A4 - A0
BITS
D10
D9
D8
<FINE GAIN>
FINE GAIN CONTROL (1 dB to 6 dB)
0C
D7
D6
D5
D4
D3
0
0
0
0
0
D4 - D0
<CUSTOM B> Upper 3 bits of custom pattern <D13>…<D11>
D10-D8
<FINE GAIN> Fine gain control
000
0 dB Gain (full-scale range = 2.00 VPP)
001
1 dB Gain (full-scale range = 1.78 VPP)
010
2 dB Gain (full-scale range = 1.59 VPP)
011
3 dB Gain (full-scale range = 1.42 VPP)
100
4 dB Gain (full-scale range = 1.26 VPP)
101
5 dB Gain (full-scale range = 1.12 VPP)
110
6 dB Gain (full-scale range = 1.00 VPP)
<CUSTOM B>
CUSTOM PATTERN (UPPER 3 BITS)
Table 18. Serial Register F
REGISTER
ADDRESS
A4 - A0
0D
BITS
D10
<OVRD>
OVER-RIDE
BITE
D9
D8
0
D7
BYTE-WISE
OR BITWISE
0
D6
MSB OR
LSB FIRST
D5
D4
D3
D2
D1
D0
<COARSE
GAIN>
COURSE
GAIN
ENABLE
FALLING OR
RISING BIT
CLOCK
CAPTURE
EDGE
0
14 BIT OR
16 BIT
SERIALIZE
DDR OR
SDR BIT
CLOCK
1-WIRE OR
2- WIRE
INTERFACE
D0
Interface selection
0
1-Wire interface
1
2-Wire interface
D1
Bit clock selection (only in 2-wire interface)
0
DDR Bit clock
1
SDR Bit clock
D2
Serialization factor selection
0
14X Serialization
1
16X Serialization
D4
Bit clock capture edge (only when SDR bit clock is selected, D1 = 1)
0
Capture data with falling edge of bit clock
1
Capture data with rising edge of bit clock
D5
<COARSE GAIN> Coarse gain control
0
0 dB Coarse gain (full-scale range = 2.0 VPP)
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1
3.5 dB Coarse gain (full-scale range = 1.34 VPP)
D6
MSB or LSB First selection
0
MSB First
1
LSB First
D7
Byte/bit wise outputs (only when 2-wire is selected)
0
Byte wise
1
Bit wise
D10
<OVRD> Over-ride bit. All the functions in register 0x0D also can be controlled using the
parallel control pins. By setting bit <OVRD> = 1, the contents of register 0x0D will over-ride
the settings of the parallel pins.
0
Disable over-ride
1
Enable over-ride
Table 19. Serial Register G
REGISTER
ADDRESS
A4 - A0
10
BITS
D10
D9
D8
D7
D6
D5
<TERM CLK>
LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS
D4
D3
D2
<LVDS CURR>
LVDS CURRENT SETTINGS
D0
<CURR DOUBLE> LVDS current double for data outputs
0
Nominal LVDS current, as set by <D5…D2>
1
Double the nominal value
D1
<CURR DOUBLE> LVDS current double for bit and word clock outputs
0
Nominal LVDS current, as set by <D5…D2>
1
Double the nominal value
D3-D2
<LVDS CURR> LVDS current setting for data outputs
00
3.5 mA
01
4 mA
10
2.5 mA
11
3 mA
D5-D4
<LVDS CURR> LVDS current setting for bit and word clock outputs
00
3.5 mA
01
4 mA
10
2.5 mA
11
3 mA
D10-D6
<TERM CLK> LVDS internal termination for bit and word clock outputs
00000
No internal termination
00001
166 Ω
00010
200 Ω
00100
250 Ω
01000
333 Ω
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D1
D0
<LVDS DOUBLE>
LVDS CURRENT DOUBLE
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500 Ω
10000
Any combination of above bits also can be programmed, resulting in a parallel combination of
the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω
100 Ω
00101
Table 20. Serial Register H
REGISTER
ADDRESS
A4 - A0
11
BITS
D10
D9
WORD-WISE CONTROL
D8
0
D7
0
D6
D5
0
0
D4
D3
D2
D1
D0
<TERM DATA>
LVDS INTERNAL TERMINATION - DATA OUTPUTS
D4-D0
<TERM DATA> LVDS internal termination for data outputs
00000
No internal termination
00001
166 Ω
00010
200 Ω
00100
250 Ω
01000
333 Ω
10000
500 Ω
Any combination of above bits can also be programmed, resulting in a parallel combination
of the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω
00101
100 Ω
D10-D9
Only when 2-wire interface is selected
00
Byte-wise or bit-wise output, 1x frame clock
11
Word-wise output enabled, 0.5x frame clock
01,10
Do not use
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PIN CONFIGURATION (2-WIRE INTERFACE)
LVDD
DC1_P
DC1_M
DC0_P
DC0_M
LGND
FCLKP
FCLKM
DCLKP
DCLKM
LGND
DB1_P
DB1_M
DB0_P
DB0_M
LVDD
ADS644x
RGC PACKAGE
(TOP VIEW)
DA1_P
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
DD0_M
DA1_M
2
47
DD0_P
DA0_P
3
46
DD1_M
DA0_M
4
45
DD1_P
CAP
5
44
SCLK
RESET
6
43
SDATA
LVDD
7
42
SEN
AGND
8
41
PDN
PAD
IND_P
AGND
13
36
AGND
INB_M
14
35
INC_M
INB_P
15
34
INC_P
AGND
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AGND
NC
AVDD
37
AGND
12
CFG1
INA_P
CFG2
IND_M
CFG3
38
AVDD
11
AGND
INA_M
CLKM
AGND
CLKP
39
AGND
10
VCM
AGND
CFG4
AVDD
AVDD
40
AGND
9
AVDD
AVDD
P0056-04
PIN ASSIGNMENTS (2-WIRE INTERFACE)
PINS
NAME
NO.
I/O
NO. OF
PINS
DESCRIPTION
SUPPLY AND GROUND PINS
AVDD
9, 17, 19, 27, 32,
40
6
Analog power supply
AGND
8, 10, 13, 16, 18,
23, 26, 31, 33, 36,
39
11
Analog ground
LVDD
7, 49, 64
3
Digital power supply
LGND
54, 59
2
Digital ground
INPUT PINS
CLKP, CLKM
24, 25
I
2
Differential input clock pair
INA_P, INA_M
12, 11
I
2
Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do not
float.
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PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued)
PINS
NAME
NO.
I/O
NO. OF
PINS
DESCRIPTION
INB_P, INB_M
15, 14
I
2
Differential input signal pair, channel B. If unused, the pins should be tied to VCM. Do not
float.
INC_P, INC_M
34, 35
I
2
Differential input signal pair, channel C If unused, the pins should be tied to VCM. Do not
float.
IND_P, IND_M
37, 38
I
2
Differential input signal pair, channel D. If unused, the pins should be tied to VCM. Do not
float.
1
Connect 2-nF capacitor from pin to ground
CAP
5
SCLK
44
I
1
This pin functions as serial interface clock input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along
with SDATA). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
SDATA
43
I
1
This pin functions as serial interface data input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along
with SCLK). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
SEN
42
I
1
This pin functions as serial interface enable input when RESET is low.
When RESET is high, it controls coarse gain and internal/external reference modes. Refer to
Table 6 for description.
This pin has an internal pull-up resistor.
Serial interface reset input.
RESET
6
I
1
When using the serial interface mode, the user MUST initialize internal registers through
hardware RESET by applying a high-going pulse on this pin or by using software reset
option. Refer to the Serial Interface section. In parallel interface mode, tie RESET
permanently high. (SCLK, SDATA and SEN function as parallel control pins in this mode).
The pin has an internal pull-down resistor to ground.
PDN
41
I
1
Global power down control pin.
CFG1
30
I
1
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock selection.
Refer to Table 8 for description.
Tie to AVDD for 2-wire interface with DDR bit clock.
CFG2
29
I
1
Parallel input pin. It controls 14x or 16x serialization and SDR bit clock capture edge. Refer to
Table 9 for description.
For 14x serialization with DDR bit clock, tie to ground or AVDD.
CFG3
28
I
1
RESERVED pin - Tie to ground.
CFG4
21
I
1
Parallel input pin. It controls data format and MSB or LSB first modes. Refer to Table 11 for
description.
VCM
22
I/O
1
Internal reference mode – common-mode voltage output
External reference mode – reference input. The voltage forced on this pin sets the internal
reference.
DA0_P,DA0_M
3, 4
O
2
Channel A differential LVDS data output pair, wire 0
DA1_P,DA1_M
1, 2
O
2
Channel A differential LVDS data output pair, wire 1
DB0_P,DB0_M
62, 63
O
2
Channel B differential LVDS data output pair, wire 0
DB1_P,DB1_M
60, 61
O
2
Channel B differential LVDS data output pair, wire 1
DC0_P,DC0_M
52, 53
O
2
Channel C differential LVDS data output pair, wire 0
DC1_P,DC1_M
50, 51
O
2
Channel C differential LVDS data output pair, wire 1
DD0_P,DD0_M
47, 48
O
2
Channel D differential LVDS data output pair, wire 0
DD1_P,DD1_M
45, 46
O
2
Channel D differential LVDS data output pair, wire 1
DCLKP,DCLKM
57, 58
O
2
Differential bit clock output pair
FCLKP,FCLKM
55, 56
O
2
Differential frame clock output pair
OUTPUT PINS
NC
20
1
Do Not Connect
PAD
0
1
Connect to ground plane using multiple vias. Refer to Board Design Considerations section.
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PIN CONFIGURATION (1-WIRE INTERFACE)
LVDD
DD_P
DD_M
DC_P
DC_M
LGND
FCLKP
FCLKM
DCLKP
DCLKM
LGND
DB_P
DB_M
DA_P
LVDD
DA_M
ADS644x
RGC PACKAGE
(TOP VIEW)
UNUSED
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
UNUSED
UNUSED
2
47
UNUSED
UNUSED
3
46
UNUSED
UNUSED
4
45
UNUSED
CAP
5
44
SCLK
RESET
6
43
SDATA
LVDD
7
42
SEN
AGND
8
41
PDN
PAD
37
IND_P
AGND
13
36
AGND
INB_M
14
35
INC_M
INB_P
15
34
INC_P
AGND
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AGND
AVDD
AVDD
AVDD
12
AGND
INA_P
CFG1
IND_M
CFG2
38
CFG3
11
AVDD
INA_M
AGND
AGND
CLKM
39
CLKP
10
AGND
AGND
VCM
AVDD
CFG4
40
NC
9
AGND
AVDD
P0056-05
PIN ASSIGNMENTS (1-WIRE INTERFACE)
PINS
NAME
NO.
I/O
NO. OF
PINS
DESCRIPTION
SUPPLY AND GROUND PINS
AVDD
9, 17, 19, 27, 32,
40
6
Analog power supply
AGND
8, 10, 13, 16, 18,
23, 26, 31, 33,
36, 39
11
Analog ground
LVDD
7, 49, 64
3
Digital power supply
LGND
54, 59
2
Digital ground
INPUT PINS
CLKP, CLKM
24, 25
I
2
Differential input clock pair
INA_P, INA_M
12, 11
I
2
Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do not float.
INB_P, INB_M
15, 14
I
2
Differential input signal pair, channel B. If unused, the pins should be tied to VCM. Do not float.
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PIN ASSIGNMENTS (1-WIRE INTERFACE) (continued)
PINS
NAME
NO.
I/O
NO. OF
PINS
DESCRIPTION
INC_P, INC_M
34, 35
I
2
Differential input signal pair, channel C. If unused, the pins should be tied to VCM. Do not float.
IND_P, IND_M
37, 38
I
2
Differential input signal pair, channel D. If unused, the pins should be tied to VCM. Do not float.
1
Connect 2 nF capacitance from pin to ground
CAP
5
SCLK
44
I
1
This pin functions as serial interface clock input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along with
SDATA). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
SDATA
43
I
1
This pin functions as serial interface data input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along with
SCLK). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
SEN
42
I
1
This pin functions as serial interface enable input when RESET is low.
When RESET is high, it controls coarse gain and internal/external reference modes. Refer to
Table 6 for description.
This pin has an internal pull-up resistor.
Serial interface reset input.
When using the serial interface mode, the user MUST initialize internal registers through hardware
RESET by applying a high-going pulse on this pin or by using software reset option. Refer to the
Serial Interface section. In parallel interface mode, tie RESET permanently high. (SCLK, SDATA
and SEN function as parallel control pins in this mode).
RESET
6
I
1
PDN
41
I
1
Global power down control pin.
CFG1
30
I
1
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock selection. Refer
to Table 8 for description.
Tie to ground for 1-wire interface with DDR bit clock.
CFG2
29
I
1
Parallel input pin. It controls 14x or 16x serialization and SDR bit clock capture edge. Refer to
Table 9 for description.
For 14x serialization with DDR bit clock, tie to ground or AVDD.
CFG3
28
I
1
RESERVED pin - Tie to ground.
CFG4
21
I
1
Parallel input pin. It controls data format and MSB or LSB first modes. Refer to Table 11 for
description.
VCM
22
I/O
1
Internal reference mode – common-mode voltage output
External reference mode – reference input. The voltage forced on this pin sets the internal
reference.
DA_P,DA_M
62, 63
O
2
Channel A differential LVDS data output pair
DB_P,DB_M
60, 61
O
2
Channel B differential LVDS data output pair
DC_P,DC_M
52, 53
O
2
Channel C differential LVDS data output pair
DD_P,DD_M
50, 51
O
2
Channel D differential LVDS data output pair
DCLKP,DCLKM
57, 58
O
2
Differential bit clock output pair
FCLKP,FCLKM
55, 56
O
2
Differential frame clock output pair
1–4, 45–48
8
These pins are unused in the 1-wire interface. Do not connect
NC
20
1
Do not connect
PAD
0
1
Connect to ground plane using multiple vias. Refer to Board Design Considerations in the
application section.
The pin has an internal pull-down resistor to ground.
OUTPUT PINS
UNUSED
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SLAS573C – FEBRUARY 2008 – REVISED MAY 2013
TYPICAL CHARACTERISTICS
All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless
otherwise noted)
ADS6445 (Fsrated = 125 MSPS)
FFT for 10 MHz INPUT SIGNAL
FFT for 100 MHz INPUT SIGNAL
0
0
SFDR = 88 dBc
SINAD = 74 dBFS
SNR = 74.3 dBFS
THD = 87.6 dBc
−20
−40
Amplitude − dB
Amplitude − dB
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
50
60
f − Frequency − MHz
0
10
20
40
50
60
G001
G002
Figure 7.
Figure 8.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
SFDR = 77.9 dBc
SINAD = 68 dBFS
SNR = 69.2 dBFS
THD = 75.3 dBc
−20
fIN1 = 185.1 MHz, –7 dBFS
fIN2 = 190.1 MHz, –7 dBFS
2-Tone IMD = –86 dBFS
SFDR = –95 dBFS
−20
−40
Amplitude − dB
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
50
f − Frequency − MHz
60
0
10
20
30
40
50
60
f − Frequency − MHz
G003
Figure 9.
G004
Figure 10.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
75
92
90
74
Gain = 3.5 dB
88
73
86
SNR − dBFS
SFDR − dBc
30
f − Frequency − MHz
0
Amplitude − dB
SFDR = 86 dBc
SINAD = 72.63 dBFS
SNR = 72.76 dBFS
THD = 85 dBc
−20
84
82
80
Gain = 0 dB
72
71
70
Gain = 3.5 dB
69
78
Gain = 0 dB
76
68
74
67
0
50
100
150
200
fIN − Input Frequency − MHz
250
0
50
G005
Figure 11.
100
150
200
250
fIN − Input Frequency − MHz
G006
Figure 12.
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ADS6445 (Fsrated = 125 MSPS) (continued)
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
75
92
Input adjusted to get −1dBFS input
90
4 dB
5 dB
84
3 dB
82
80
2 dB
3 dB
71
70
69
68
2 dB
78
76
0 dB
67
4 dB
66
1 dB
74
5 dB
6 dB
65
50
70
90
20
110 130 150 170 190 210 230
fIN − Input Frequency − MHz
40
60
80
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
G007
Figure 13.
PERFORMANCE vs AVDD
PERFORMANCE vs LVDD
88
77
SFDR
94
76
82
75
80
74
SNR
78
73
76
72
74
71
72
3.0
3.1
3.2
3.3
3.4
AVDD − Supply Voltage − V
74
90
73
86
72
SFDR
82
78
3.0
70
3.6
3.5
75
fIN = 50.1 MHz
AVDD = 3.3 V
SNR
SFDR − dBc
84
SNR − dBFS
SFDR − dBc
98
78
fIN = 50.1 MHz
LVDD = 3.3 V
71
3.1
3.2
PERFORMANCE vs TEMPERATURE
76
75
80
74
SNR
78
73
76
72
SNR − dBFS
SFDR − dBc
SFDR
82
60
110
78
100
77
90
SFDR (dBFS)
76
80
70
75
SNR (dBFS)
74
60
73
50
72
30
−60
80
71
fIN = 20 MHz
−50
−40
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−30
−20
Input Amplitude − dBFS
G011
Figure 17.
28
G010
40
71
T − Temperature − °C
70
3.6
SFDR (dBc)
fIN = 50.1 MHz
40
SFDR − dBc, dBFS
84
20
3.5
PERFORMANCE vs INPUT AMPLITUDE
77
0
3.4
Figure 16.
86
−20
3.3
LVDD − Supply Voltage − V
G009
Figure 15.
74
−40
G008
Figure 14.
SNR − dBFS
30
SNR − dBFS
10
86
1 dB
72
SINAD − dBFS
SFDR − dBc
3.5 dB
73
88
86
0 dB
74
6 dB
−10
70
0
G012
Figure 18.
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ADS6445 (Fsrated = 125 MSPS) (continued)
PERFORMANCE vs CLOCK AMPLITUDE (differential)
86
PERFORMANCE vs CLOCK DUTY CYCLE
90
77
78
fIN = 50.1 MHz
84
76
75
80
74
78
73
SNR
76
72
74
71
SFDR − dBc
82
SNR − dBFS
SFDR − dBc
SFDR
89
77
88
76
87
75
86
SNR − dBFS
SFDR
74
SNR
85
73
fIN = 20.1 MHz
72
0.5
1.0
1.5
2.0
70
3.0
2.5
72
35
40
45
50
60
65
Input Clock Duty Cycle − %
G013
G014
Figure 20.
POWER DISSIPATION vs SAMPLING FREQUENCY
OUTPUT NOISE HISTOGRAM WITH
INPUTS TIED TO COMMON-MODE
2.0
40
1.8
35
RMS (LSB) = 1.064
1.6
30
1.4
1.2
1.0
AVDD
0.8
0.6
25
20
15
10
0.4
LVDD
5
0.2
0
0.0
0
25
50
75
100
fS − Sampling Frequency − MSPS
8187 8188 8189 8190 8191 8192 8193 8194 8195 8196
125
G015
Output Code
Figure 21.
CMRR vs FREQUENCY
78
fIN = 50.1 MHz
External Reference Mode
76
74
SNR
88
72
SNR − dBFS
92
SFDR
86
84
1.30
70
1.35
1.40
1.45
1.50
1.55
1.60
1.65
68
1.70
CMRR − Common-Mode Rejection Ratio − dBc
PERFORMANCE IN EXTERNAL REFERENCE MODE
90
G016
Figure 22.
94
SFDR − dBc
55
Figure 19.
Occurence − %
PD − Power Dissipation − W
Input Clock Amplitude − VPP
84
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
50
100
150
200
250
300
f − Frequency − MHz
VVCM − VCM Voltage − V
G017
Figure 23.
G018
Figure 24.
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ADS6444 (Fsrated = 105 MSPS)
FFT for 10 MHz INPUT SIGNAL
FFT for 70 MHz INPUT SIGNAL
0
SFDR = 91.2 dBc
SINAD = 73.9 dBFS
SNR = 74.1 dBFS
THD = 89.7 dBc
−20
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
50
f − Frequency − MHz
0
10
20
50
G019
G020
Figure 26.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
SFDR = 81 dBc
SINAD = 68.6 dBFS
SNR = 69 dBFS
THD = 79 dBc
fIN1 = 185.1 MHz, –7 dBFS
fIN2 = 190.1 MHz, –7 dBFS
2-Tone IMD = –88 dBFS
SFDR = –89 dBFS
−20
−40
Amplitude − dB
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
f − Frequency − MHz
50
0
10
20
30
40
f − Frequency − MHz
G021
Figure 27.
50
G022
Figure 28.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
92
76
90
75
74
86
SNR − dBFS
88
SFDR − dBc
40
Figure 25.
−20
Gain = 3.5 dB
84
82
73
72
Gain = 0 dB
71
70
Gain = 3.5 dB
69
80
68
Gain = 0 dB
78
67
76
66
0
50
100
150
200
fIN − Input Frequency − MHz
250
0
50
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100
150
fIN − Input Frequency − MHz
G023
Figure 29.
30
30
f − Frequency − MHz
0
Amplitude − dB
SFDR = 81.2 dBc
SINAD = 71.6 dBFS
SNR = 72.6 dBFS
THD = 79.9 dBc
−20
Amplitude − dB
−40
Amplitude − dB
0
200
250
G024
Figure 30.
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ADS6444 (Fsrated = 105 MSPS) (continued)
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
75
92
Input adjusted to get −1dBFS input
90
84
6 dB
80
2 dB
78
69
68
67
66
74
65
30
50
70
90
3 dB
70
76
10
2 dB
71
1 dB
0 dB
1 dB
72
SINAD − dBFS
20
110 130 150 170 190 210 230
fIN − Input Frequency − MHz
4 dB
40
5 dB
60
80
6 dB
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
G025
Figure 31.
PERFORMANCE vs AVDD
88
fIN = 70.1 MHz
LVDD = 3.3 V
77
94
75
fIN = 70.1 MHz
AVDD = 3.3 V
74
75
80
74
78
73
76
SNR − dBFS
SFDR
82
72
SNR
74
SNR
90
86
72
SFDR
82
71
71
72
3.0
3.1
3.2
3.3
3.4
3.5
78
3.0
70
3.6
AVDD − Supply Voltage − V
3.1
3.2
3.3
PERFORMANCE vs TEMPERATURE
79
100
78
86
77
SFDR
76
82
75
80
74
78
73
SFDR − dBc, dBFS
110
88
G028
85
SFDR (dBFS)
80
80
70
75
SNR (dBFS)
70
60
65
50
60
40
72
30
−60
15 30 45 60 75 90 105 120 135
T ± Temperature ± ƒC
90
90
SFDR (dBc)
fIN = 70.1 MHz
76
±60 ±45 ±30 ±15 0
70
3.6
PERFORMANCE vs INPUT AMPLITUDE
80
SNR ± dBFs
SNR
84
3.5
Figure 34.
92
90
3.4
LVDD − Supply Voltage − V
G027
Figure 33.
SFDR ± dBc
73
SNR − dBFS
76
SFDR − dBc
84
SFDR − dBc
PERFORMANCE vs LVDD
98
78
86
G026
Figure 32.
SNR − dBFS
SFDR − dBc
3 dB
82
3.5 dB
73
5 dB
86
0 dB
74
4 dB
88
55
fIN = 20 MHz
−50
−40
−30
−20
−10
50
0
C029
Input Amplitude − dBFS
Figure 35.
G030
Figure 36.
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ADS6444 (Fsrated = 105 MSPS) (continued)
PERFORMANCE vs CLOCK AMPLITUDE (differential)
92
PERFORMANCE vs CLOCK DUTY CYCLE
93
76
fIN = 70.1 MHz
90
76
fIN = 20.1 MHz
75
91
88
75
SFDR
74
84
72
82
71
80
74
SNR
87
70
SFDR
78
1.0
1.5
2.0
85
72
83
68
3.0
2.5
Input Clock Amplitude − VPP
71
35
40
45
50
65
G032
Figure 38.
POWER DISSIPATION vs SAMPLING FREQUENCY
OUTPUT NOISE HISTOGRAM WITH
INPUTS TIED TO COMMON-MODE
40
1.8
35
RMS (LSB) = 1.054
1.6
30
Occurence − %
1.4
1.2
1.0
AVDD
0.8
0.6
25
20
15
10
LVDD
0.4
5
0
0.0
0
20
40
60
80
fS − Sampling Frequency − MSPS
8179 8180 8181 8182 8183 8184 8185 8186 8187 8188
100
G033
Output Code
Figure 39.
CMRR vs FREQUENCY
76
fIN = 70.1 MHz
External Reference Mode
74
SNR
82
72
70
SFDR
81
SNR − dBFS
84
68
1.35
1.40
1.45
1.50
1.55
VVCM − VCM Voltage − V
1.60
1.65
66
1.70
CMRR − Common-Mode Rejection Ratio − dBc
PERFORMANCE IN EXTERNAL REFERENCE MODE
83
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
50
100
150
200
f − Frequency − MHz
G035
Figure 41.
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G034
Figure 40.
85
SFDR − dBc
60
Figure 37.
2.0
80
1.30
55
Input Clock Duty Cycle − %
G031
0.2
32
73
69
76
0.5
PD − Power Dissipation − W
89
SNR − dBFS
73
SFDR − dBc
86
SNR − dBFS
SFDR − dBc
SNR
250
300
G018
Figure 42.
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Contour Plots across Input and Sampling Frequencies
125
120
92
89
80
86
83
fS - Sampling Frequency - MSPS
110
65
86
80
83
89
74
100
77
83
90
86
80
86
83
80
70
68
71
74
86
89
80
60
68
71
77
65
83
50
89
86
30
10
50
74
80
83
150
100
68
71
77
40
200
250
300
65
400
350
450
500
fIN - Input Frequency - MHz
65
75
70
80
85
90
SFDR - dBc
M0049-13
Figure 43. SFDR Contour (no gain)
125
120
85
88
70
76
82
110
fS - Sampling Frequency - MSPS
79
91
91
88
88
100
73
79
85
94
82
90
76
82
88
80
70
91
70
79
85
60
67
73
88
76
50
70
82
40
91
30
10
79
85
50
100
150
200
73
76
250
300
350
400
450
500
fIN - Input Frequency - MHz
65
75
70
80
85
SFDR - dBc
90
M0049-14
Figure 44. SFDR Contour (3.5 dB coarse gain)
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Contour Plots across Input and Sampling Frequencies (continued)
125
120
68
fS - Sampling Frequency - MSPS
73
74
110
64
67
72
70
71
65
66
69
100
90
66
80
70
71
72
73
74
64
65
67
68
69
70
60
66
64
65
50
67
40
30
10
50
69
71 70
72
73
74
150
100
68
66
200
250
64
65
300
63
400
350
62
450
500
fIN - Input Frequency - MHz
60
70
65
75
SNR - dBFS
M0048-13
Figure 45. SNR Contour (no gain)
125
120
72
71
fS - Sampling Frequency - MSPS
110
70
67
68
69
66
65
100
90
67
71
80
68
72
70
70
65
69
64
66
60
50
71
67
72
69
40
30
10
70
50
100
150
66
68
200
250
64
65
64
300
63
62
63
400
350
61
450
500
fIN - Input Frequency - MHz
60
62
64
66
68
70
SNR - dBFS
72
M0048-14
Figure 46. SNR Contour (3.5 dB coarse gain)
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS6445/ADS6444 is a quad channel, 14 bit pipeline ADC based on switched capacitor architecture in
CMOS technology.
The conversion is initiated simultaneously by all the four channels at the rising edge of the external input clock.
After the input signals are captured by the sample and hold circuit of each channel, the samples are sequentially
converted by a series of low resolution stages. The stage outputs are combined in a digital correction logic block
to form the final 14 bit word with a latency of 12 clock cycles. The 14 bit word of each channel is serialized and
output as LVDS levels. In addition to the data streams, a bit clock and frame clock also are output. The frame
clock is aligned with the 14 bit word boundary.
ANALOG INPUT
The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in
Figure 47. This differential topology results in very good AC performance even for high input frequencies. The
INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V, available on VCM pin
13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5 V
and VCM – 0.5 V, resulting in a 2 VPP differential input swing. The maximum swing is determined by the internal
reference voltages REFP (2.0 V nominal) and REFM (1.0 V, nominal). The sampling circuit has a 3 dB bandwidth
that extends up to 500 MHz (see Figure 48, shown by the transfer function from the analog input pins to the
voltage across the sampling capacitors, TF_ADC).
Sampling
Switch
Lpkg
3 nH
25 W
Sampling
Capacitor
RCR Filter
INP
Cbond
2 pF
50 W
Resr
200 W
Lpkg
3 nH
3.2 pF
Cpar2 Ron
1 pF 15 W
Cpar1
0.8 pF
Ron
10 W
50 W
Ron
15 W
25 W
INM
Cpar2
1 pF
Cbond
2 pF
Resr
200 W
Csamp
4.0 pF
Csamp
4.0 pF
Sampling
Capacitor
Sampling
Switch
S0237-01
Figure 47. Input Sampling Circuit
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1
Magnitude − dB
0
−1
−2
−3
−4
−5
−6
0
100
200
300
400
500
600
fIN − Input Frequency − MHz
700
G073
Figure 48. Analog Input Bandwidth (represented by magnitude of TF_ADC, see Figure 50 )
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection.
A 5 Ω resistor in series with each input pin is recommended to damp out ringing caused by the package
parasitics. It is also necessary to present low impedance (< 50 Ω) for the common mode switching currents. For
example, this is achieved by using two resistors from each input terminated to the common mode voltage (VCM).
In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the
desired frequency range and matched impedance to the source. While doing this, the ADC input impedance has
to be taken into account. Figure 49 shows that the impedance (Zin, looking into the ADC input pins) decreases at
high input frequencies. The Smith chart shows that the input impedance is capacitive and can be approximated
by a series R-C up to 500 MHz.
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F1
Freq = 50 MHz
S(1, 1) = 0.967 / –13.241
Impedance = 62.211 – j421.739
1000
F1
Frequency = 50 MHz
Mag(Zin1) = 426.302
900
700
F2
Frequency = 400 MHz
Mag(Zin1) = 65.193
600
F1
500
S(1, 1)
Magnitude of Zin -- W
800
400
F2
300
200
F1
F2
100
0
0
50
100
150
200
250
300
350
400
450
500
fI -- Input Frequency -- MHz
Frequency (100 kHz to 500 MHz)
F2
Freq = 400 MHz
S(1, 1) = 0.273 / –59.329
Impedance = 58.132 – j29.510
M0087-01
Figure 49. ADC Input Impedance, Zin
Using RF-Transformers Based Drive Circuits
Figure 50 shows a configuration using a single 1:1 turns ratio transformer (for example, Coilcraft WBC1-1) that
can be used for low input frequencies up to 100 MHz.
The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated on the
secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by the
sampling circuit from the RF transformer’s leakage inductances. The termination is accomplished by two resistors
connected in series, with the center point connected to the 1.5 V common mode (VCM pin). The value of the
termination resistors (connected to common mode) has to be low (< 100 Ω) to provide a low-impedance path for
the ADC common-mode switching current.
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TF_ADC
0.1 mF
ADS6xxx
5W
INP
0.1 mF
25 W
25 W
INM
5W
1:1
VCM
S0256-01
Figure 50. Single Transformer Drive Circuit
At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results
in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps
minimize this mismatch, and good performance is obtained for high frequency input signals. Figure 51 shows an
example using two transformers (like Coilcraft WBC1-1). An additional termination resistor pair (enclosed within
the shaded box in Figure 51) may be required between the two transformers to improve the balance between the
P and M sides. The center point of this termination must be connected to ground.
ADS6xxx
0.1 µF
5Ω
INP
50 Ω
0.1 µF
50 Ω
50 Ω
50 Ω
INM
1:1
5Ω
1:1
VCM
S0164-04
Figure 51. Two Transformer Drive Circuit
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Using Differential Amplifier Drive Circuits
Figure 52 shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input to
differential output that can be interfaced to the ADC input pins. In addition to the single-ended to differential
conversion, the amplifier also provides gain (10 dB in Figure 52). As shown in the figure, RFIL helps to isolate the
amplifier output from the switching inputs of the ADC. Together with CFIL, it also forms a low-pass filter that
bandlimits the noise (and signal) at the ADC input. As the amplifier outputs are ac-coupled, the common-mode
voltage of the ADC input spins is set using two resistors connected to VCM.
The amplifier outputs also can be dc-coupled. Using the output common-mode control of the THS4509, the ADC
input pins can be biased to 1.5 V. In this case, use +4 V and -1 V supplies for the THS4509 to ensure that it's
output common-mode voltage (1.5 V) is at mid-supply.
RF
+VS
500 W
0.1 mF
RS
0.1 mF 10 mF
RFIL
0.1 mF
5W
INP
RG
0.1 mF
RT
CFIL
200 W
CFIL
200 W
CM THS4509
RG
RFIL
INM
RS || RT
0.1 mF
5W
0.1 mF
500 W
VCM
–VS
ADS6xxx
0.1 mF 10 mF
0.1 mF
RF
S0259-01
Figure 52. Drive Circuit Using THS4509
Refer to the EVM User Guide (SLAU196) for more information.
INPUT COMMON MODE
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1 μF low-inductance capacitor
connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC
sinks a common-mode current in the order of 155 μA at 125 MSPS (per input pin). Equation 1 describes the
dependency of the common-mode current and the sampling frequency.
155 mAxFs
125 MSPS
(1)
This equation helps to design the output capability and impedance of the CM driving circuit accordingly.
REFERENCE
The ADS644X has built-in internal references REFP and REFM, requiring no external components. Design
schemes are used to linearize the converter load seen by the references; this and the on-chip integration of the
requisite reference capacitors eliminates the need for external decoupling. The full-scale input range of the
converter can be controlled in the external reference mode as explained below. The internal or external reference
modes can be selected by programming the register bit <REF> (refer to Table 13).
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INTREF
Internal
Reference
VCM
1 kW
INTREF
4 kW
EXTREF
REFM
REFP
ADS6xxx
S0165-04
Figure 53. Reference Section
Internal Reference
When the device is in internal reference mode, the REFP and REFM voltages are generated internally. Commonmode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog input pins.
External Reference
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the
VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential
input
voltage
corresponding
to
full-scale
is
given
by
Equation
2.
Full−scale differential input pp + (Voltage forced on VCM) 1.33
(2)
In this mode, the range of voltage applied on VCM should be 1.45 V to 1.55 V. The 1.5-V common-mode voltage
to bias the input pins has to be generated externally.
COARSE GAIN AND PROGRAMMABLE FINE GAIN
ADS644X includes gain settings that can be used to get improved SFDR performance (compared to 0 dB gain
mode). The gain settings are 3.5 dB coarse gain and programmable fine gain from 0 dB to 6 dB. For each gain
setting, the analog input full-scale range scales proportionally, as listed in Table 21.
The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR (as
seen in Figure 11 and Figure 12). The fine gain is programmable in 1 dB steps from 0 to 6 dB. With fine gain
also, SFDR improvement is achieved, but at the expense of SNR (there is about 1 dB SNR degradation for every
1 dB of fine gain).
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So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get
best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the
SFDR improvement is significant with marginal degradation in SINAD.
The gains can be programmed using the register bits <COARSE GAIN> (refer to Table 18) and <FINE GAIN>
(refer to Table 17). Note that the default gain after reset is 0 dB.
Table 21. Full-Scale Range Across Gains
GAIN, dB
TYPE
FULL-SCALE, VPP
0
Default (after reset)
2
3.5
Coarse setting (fixed)
1.34
1
1.78
2
1.59
3
1.42
Fine setting (programmable)
4
1.26
5
1.12
6
1.00
CLOCK INPUT
The ADS644X clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
VCM using internal 5 kΩ resistors as shown in Figure 54. This allows using transformer-coupled drive circuits for
sine wave clock or ac-coupling for LVPECL, LVDS clock sources (see Figure 55 and Figure 57).
VCM
VCM
5 kW
5 kW
CLKP
CLKM
ADS6xxx
S0166-04
Figure 54. Internal Clock Buffer
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0.1 mF
CLKP
Differential Sine-Wave
or PECL or LVDS Clock Input
0.1 mF
CLKM
ADS6xxx
S0167-05
Figure 55. Differential Clock Driving Circuit
Figure 56 shows a typical scheme using PECL clock drive from a CDCM7005 clock driver. SNR performance
with this scheme is comparable with that of a low jitter sine wave clock source.
VCC
Reference Clock
REF_IN
VCC
Y0
CLKP
Y0B
CLKM
CDCM7005
VCXO_INP
OUTM
VCXO_INM
CP_OUT
ADS6xxx
VCXO
OUTP
CTRL
S0238-02
Figure 56. PECL Clock Drive Using CDCM7005
Single-ended CMOS clock can be ac coupled to the CLKP input, with CLKM (pin) connected to ground with a
0.1-μF capacitor, as shown in Figure 57.
0.1 mF
CMOS Clock Input
CLKP
0.1 mF
CLKM
ADS6xxx
S0168-07
Figure 57. Single-Ended Clock Driving Circuit
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For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode
noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a non50% duty cycle clock input.
CLOCK BUFFER GAIN
When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is
increased. Hence, it is recommended to use large clock amplitude. As shown by Figure 19, use clock amplitude
greater than 1 VPP to avoid performance degradation.
In addition, the clock buffer has programmable gain to amplify the input clock to support very low clock
amplitude. The gain can be set by programming the register bits <CLKIN GAIN> (refer to Table 14) and
increases monotonically from Gain 0 to Gain 4 settings. Table 22 lists the minimum clock amplitude supported for
each gain setting.
Table 22. Minimum Clock Amplitude across gains
CLOCK BUFFER GAIN
MINIMUM CLOCK AMPLITUDE SUPPORTED
mVPP differential
Gain 0 (minimum gain)
800
Gain 1 (default gain)
400
Gain 2
300
Gain 3
200
Gain 4 (highest gain)
150
POWER DOWN MODES
The ADS644X has three power-down modes – global power down, channel standby and input clock stop.
Global Power Down
This is a global power-down mode in which almost the entire chip is powered down, including the four ADCs,
internal references, PLL and LVDS buffers. As a result, the total power dissipation falls to about 77 mW typical
(with input clock running). This mode can be initiated by setting the register bit <PDN GLOBAL> (refer to
Table 13). The output data and clock buffers are in high-impedance state.
The wake-up time from this mode to data becoming valid in normal mode is 100 μs.
Channel Standby
In this mode, only the ADC of each channel is powered down and this helps to get very fast wake-up times. Each
of the four ADCs can be powered down independently using the register bits <PDN CH> (refer to Table 13). The
output LVDS buffers remain powered up.
The wake-up time from this mode to data becoming valid in normal mode is 200 clock cycles.
Input Clock Stop
The converter enters this mode:
• If the input clock frequency falls below 1 MSPS or
• If the input clock amplitude is less than 400 mVPP, differential with default clock buffer gain setting) at any
sampling frequency.
All ADCs and LVDS buffers are powered down and the power dissipation is about 235 mW. The wake-up time
from this mode to data becoming valid in normal mode is 100 μs.
Table 23. Power-Down Mode Summary
POWER-DOWN MODE
AVDD POWER
(mW)
LVDD POWER
(mW)
WAKE-UP TIME
In power-up
1360
297
–
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Table 23. Power-Down Mode Summary (continued)
POWER-DOWN MODE
Global power down
65
LVDD POWER
(mW)
1115
2 Channels in standby
825
(1)
3 Channels in standby
532
(1)
4 Channels in standby
245
(1)
200
WAKE-UP TIME
100 μs
12
(1)
1 Channel in standby
Input clock stop
(1)
AVDD POWER
(mW)
297
(1)
200 Clocks
297
(1)
200 Clocks
297
(1)
200 Clocks
297
(1)
200 Clocks
35
100 μs
Sampling frequency = 125 MSPS.
POWER SUPPLY SEQUENCING
During power-up, the AVDD and LVDD supplies can come up in any sequence. The two supplies are separated
inside the device. Externally, they can be driven from separate supplies or from a single supply.
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DIGITAL OUTPUT INTERFACE
The ADS644X offers several flexible output options making it easy to interface to an ASIC or an FPGA. Each of
these options can be easily programmed using either parallel pins or the serial interface.
The output interface options are:
• 1-Wire, 1× frame clock, 14× and 16× serialization with DDR bit clock
• 2-Wire, 1× frame clock, 16× serialization, with DDR and SDR bit clock, byte wise/bit wise/word wise
• 2-Wire, 1× frame clock, 14× serialization, with SDR bit clock, byte wise/bit wise/word wise
• 2-Wire, (0.5 x) frame clock, 14× serialization, with DDR bit clock, byte wise/bit wise/word wise
The maximum sampling frequency, bit clock frequency and output data rate will vary depending on the interface
options selected (refer to Table 12).
Table 24. Maximum Recommended Sampling Frequency for Different Output Interface Options
INTERFACE OPTIONS
MAXIMUM
RECOMMENDED
SAMPLING
FREQUENCY,
MSPS
BIT CLOCK
FREQUENCY,
MHZ
FRAME CLOCK
FREQUENCY, MHZ
SERIAL DATA RATE,
Mbps
1-Wire
DDR Bit
clock
14× Serialization
65
455
65
910
16× Serialization
65
520
65
1040
2-Wire
DDR Bit
clock
14× Serialization
125
437.5
62.5
875
16× Serialization
125
500
125
1000
2-Wire
SDR Bit
clock
14× Serialization
65
455
65
910
16× Serialization
65
520
65
1040
Each interface option is described in detail in the following sections.
1-WIRE INTERFACE - 14× AND 16× SERIALIZATION WITH DDR BIT CLOCK
Here the device outputs the data of each ADC serially on a single LVDS pair (1 wire). The data is available at the
rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at the rising edge of every
frame clock, starting with the MSB. Optionally, it can also be programmed to output the LSB first. The data rate is
14 × sample frequency (14× serialization) and 16 × sample frequency (16× serialization).
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Input Clock,
CLKP/M
Freq = Fs
16 Bit Serialization
(1)
12 Bit Serialization
Frame Clock,
FCLKP
Freq = 1 × Fs
Bit Clock – DDR,
DCLKP/M
Freq = 7 × Fs
Output Data
DA, DB, DC, DD
Data Rate = 14 × Fs
D13
(D0)
D12
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D8
(D7)
D7
(D8)
D5
(D8)
D4
(D9)
D3
D2
D1
D0
(D10) (D11) (D12) (D13)
D13
(D0)
D12
(D1)
Bit Clock – DDR,
DCLKP/M
Freq = 8 × Fs
Output Data
DA, DB, DC, DD
Data Rate = 16 × Fs
0
(D0)
0
(D1)
D13
(D2)
D12
(D3)
D11
(D4)
D10
(D5)
D9
(D6)
D6
D5
D4
D3
D2
(D9) (D10) (D11) (D12) (D13)
D1
(0)
Sample N
D0
(0)
0
(D0)
0
(D1)
Sample N + 1
Data Bit in MSB First Mode
D13
(D2)
Data Bit in LSB First Mode
(1)
In 16 Bit serialization, two zero bits are padded to the 14 bit ADC data on the MSB side.
T0225-02
Figure 58. 1-Wire Interface
2-WIRE INTERFACE - 16× SERIALIZATION WITH DDR/SDR BIT CLOCK
The 2-wire interface is recommended for sampling frequencies above 65 MSPS. In 16× serialization, two zero
bits are padded to the 14 bit ADC data on the MSB side and the combined 16 bit data is serialized and output
over two LVDS pairs. The data rate is 8 × Sample frequency since 8 bits are sent on each wire every clock cycle.
The data is available along with DDR bit clock or optionally with SDR bit clock. Each ADC sample is sent over
the 2 wires as byte-wise or bit-wise or word-wise.
Using the 16× serialization makes it possible to upgrade to a 16-bit ADC in the future seamlessly, without
requiring any modification to the receiver capture logic design.
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Input Clock,
CLKP/M
Freq = Fs
Frame Clock,
FCLKP/M
Freq = 1 ´ Fs
Bit Clock – SDR,
DCLKP/M
Freq = 8 ´ Fs
In Byte-Wise Mode
Bit Clock – DDR,
DCLKP/M
Freq = 4 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D7
(D0)
D6
(D1)
D5
(D2)
D4
(D3)
D3
(D4)
D2
(D5)
D1
(D6)
D0
(D7)
D7
(D0)
D6
(D1)
D5
(D2)
D4
(D3)
D3
(D4)
D2
(D5)
D1
(D6)
D0
(D7)
Output Data
DA1, DB1, DC1, DD1
0
(D8)
0
(D9)
D13
D12
D11
D10
D9
(0)
D8
(0)
0
(D8)
0
(D9)
D13
D12
D11
D10
(D10) (D11) (D12) (D13)
(D10) (D11) (D12) (D13)
D9
(0)
D8
(0)
D0
(0)
0
(D0)
D12
(D2)
D10
(D4)
D8
(D6)
D6
(D8)
D2
D0
(D10) (D12)
D1
(0)
0
(D1)
D13
(D3)
D11
(D5)
D9
(D7)
D7
(D9)
(D11) (D13)
D5
D4
D3
In Word-Wise Mode
In Bit-Wise Mode
Data Rate = 8 ´ Fs
Output Data
DA0, DB0, DC0, DD0
0
(D0)
D12
(D2)
D10
(D4)
D8
(D6)
D6
(D8)
(D10) (D12)
Output Data
DA1, DB1, DC1, DD1
0
(D1)
D13
(D3)
D11
(D5)
D9
(D7)
D7
(D9)
(D11) (D13)
Output Data
DA0, DB0, DC0, DD0
0
(D0)
0
(D1)
D13
(D2)
D12
(D3)
D11
(D4)
D10
(D5)
D9
(D6)
D8
(D7)
D7
(D8)
D6
(D9)
(D10) (D11) (D12) (D13)
Output Data
DA1, DB1, DC1, DD1
0
(D0)
0
(D1)
D13
(D2)
D12
(D3)
D11
(D4)
D10
(D5)
D9
(D6)
D8
(D7)
D7
(D8)
D6
(D9)
(D10) (D11) (D12) (D13)
D4
D5
Data Bit in MSB First Mode
D2
D3
D5
D4
D3
D4
D5
D2
D2
D3
(0)
D1
(0)
D1
(0)
D0
(0)
D1
(0)
D0
(0)
White Cells – Sample N
D13
(D3)
Data Bit in LSB First Mode
Grey Cells – Sample N + 1
T0226-02
Figure 59. 2-Wire Interface 16× Serialization
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2-WIRE INTERFACE - 14× SERIALIZATION
The 14 bit ADC data is serialized and output over two LVDS pairs. A frame clock at 1× sample frequency is also
available with an SDR bit clock. With DDR bit clock option, the frame clock frequency is 0.5× sample frequency.
The output data rate will be 7 × sample frequency as 7 data bits are output every clock cycle on each wire. Each
ADC sample is sent over the 2 wires as byte-wise or bit-wise or word-wise.
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Input Clock,
CLK
Freq = Fs
Frame Clock,
FCLK
Freq = 1 ´ Fs
In Byte-Wise Mode
Bit Clock – SDR,
DCLK
Freq = 7 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D6
(D0)
D5
(D1)
D4
(D2)
D3
(D3)
D2
(D4)
D1
(D5)
D0
(D6)
D6
(D0)
D5
(D1)
D4
(D2)
D3
(D3)
D2
(D4)
D1
(D5)
D0
(D6)
D6
(D0)
D5
(D1)
Output Data
DA1, DB1, DC1, DD1
D13
(D7)
D12
(D8)
D11
(D9)
D10
D9
D8
D7
D13
(D7)
D12
(D8)
D11
(D9)
D10
D9
(D10) (D11) (D12) (D13)
(D10) (D11)
D8
(0)
D7
(0)
D13
(D7)
D12
(D8)
D12
(D0)
D10
(D2)
D8
(D4)
D6
(D6)
D4
(D8)
D2
D0
(D10) (D12)
D12
(D0)
D10
(D2)
(D11) (D13)
D13
(D1)
D11
(D3)
D13
(D0)
D12
(D1)
D13
(D0)
D12
(D1)
In Word-Wise Mode
In Bit-Wise Mode
Data Rate = 7 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D12
(D0)
D10
(D2)
D8
(D4)
D6
(D6)
D4
(D8)
(D10) (D12)
Output Data
DA1, DB1, DC1, DD1
D13
(D1)
D11
(D3)
D9
(D5)
D7
(D7)
D5
(D9)
(D11) (D13)
D13
(D1)
D11
(D3)
D9
(D5)
D7
(D7)
D5
(D9)
Output Data
DA0, DB0, DC0, DD0
D13
(D0)
D12
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D5
(D8)
D4
(D9)
D3
D2
(D10) (D11) (D12) (D13)
Output Data
DA1, DB1, DC1, DD1
D13
(D0)
D12
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D5
(D8)
D4
(D9)
(D10) (D11) (D12) (D13)
D2
D3
D0
D1
Data Bit in MSB First Mode
D3
D2
D3
D1
D1
D1
D0
D0
White Cells – Sample N
D6
(D0)
Data Bit in LSB First Mode
Grey Cells – Sample N + 1
T0227-02
Figure 60. 2-Wire Interface 14× Serialization - SDR Bit Clock
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Input Clock,
CLK
Freq = Fs
Frame Clock,
FCLK
Freq = 0.5 ´ Fs
In Byte-Wise Mode
Bit Clock – DDR,
DCLK
Freq = 3.5 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D6
(D0)
D5
(D1)
D4
(D2)
D3
(D3)
D2
(D4)
D1
(D5)
D0
(D6)
D6
(D0)
D5
(D1)
D4
(D2)
D3
(D3)
D2
(D4)
D1
(D5)
D0
(D6)
D6
(D0)
D5
(D1)
Output Data
DA1, DB1, DC1, DD1
D13
(D7)
D12
(D8)
D11
(D9)
D10
D9
D8
(0)
D7
(0)
D13
(D7)
D12
(D8)
D11
(D9)
D10
D9
(D10) (D11)
(D10) (D11)
D8
(0)
D7
(0)
D13
(D7)
D12
(D8)
D2
D0
(0)
D12
(D0)
D10
(D2)
D8
(D4)
D6
(D6)
D4
(D8)
D2
D0
(D10) (D12)
D12
(D0)
D10
(D2)
(D11) (D13)
D13
(D1)
D11
(D3)
0
(D0)
0
(D1)
D13
(D0)
D12
(D1)
In Word-Wise Mode
In Bit-Wise Mode
Data Rate = 7 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D12
(D0)
D10
(D2)
D8
(D4)
D6
(D6)
D4
(D8)
(D10)
Output Data
DA1, DB1, DC1, DD1
D13
(D1)
D11
(D3)
D9
(D5)
D7
(D7)
D5
(D9)
(D11)
D1
(0)
D13
(D1)
D11
(D3)
D9
(D5)
D7
(D7)
D5
(D9)
Output Data
DA0, DB0, DC0, DD0
D13
(D0)
D12
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D5
(D8)
D4
(D9)
D3
D2
(D10) (D11) (D12) (D13)
Output Data
DA1, DB1, DC1, DD1
D13
(D0)
D12
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D5
(D8)
D4
(D9)
(D10) (D11) (D12) (D13)
D3
D3
D2
D3
D1
D1
D1
D0
D0
White Cells – Sample N
Data Bit in MSB First Mode
D6
(D0)
Data Bit in LSB First Mode
Grey Cells – Sample N + 1
T0228-02
Figure 61. 2-Wire interface 14× Serialization - DDR Bit Clock
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OUTPUT BIT ORDER
In the 2-wire interface, three types of bit order are supported - byte-wise, bit-wise and word-wise.
Byte-wise: Each 14 bit sample is split across the 2 wires. Wires DA0, DB0, DC0, and DD0 carry the 7 LSB bits
D6 - D0 and wires DA1, DB1, DC1, and DD1 carry the 7 MSB bits.
Bit-wise: Each 14 bit sample is split across the 2 wires. Wires DA0, DB0, DC0 and DD0 carry the 7 even bits
(D0, D2, D4...) and wires DA1, DB1, DC1 and DD1 carry the 7 odd bits (D1, D3, D5...).
Word-wise: In this case, all 14 bits of a sample are sent over a single wire. Successive samples are sent over
the 2 wires. For example sample N is sent on wires DA0, DB0, DC0 and DD0, while sample N+1 is sent over
wires DA1, DB1, DC1 and DD1. The frame clock frequency is 0.5x sampling frequency, with the rising edge
aligned with the start of each word.
MSB/LSB FIRST
By default after reset, the 14 bit ADC data is output serially with the MSB first (D13, D12, D11,...D1, D0). The
data can be output LSB first also by programming the register bit <MSB_LSB_First>. In the 2-wire mode, the bit
order in each wire is flipped in the LSB first mode.
OUTPUT DATA FORMATS
Two output data formats are supported – 2s complement (default after reset) and offset binary. They can be
selected using the serial interface register bit <DF>. In the event of an input voltage overdrive, the digital outputs
go to the appropriate full-scale level. For a positive overdrive, the output code is 0x3FFF in offset binary output
format, and 0x1FFF in 2s complement output format. For a negative input overdrive, the output code is 0x0000 in
offset binary output format and 0x2000 in 2s complement output format.
LVDS CURRENT CONTROL
The default LVDS buffer current is 3.5 mA. With an external 100 Ω termination resistance, this develops ±350
mV logic levels at the receiver. The LVDS buffer currents also can be programmed to 2.5 mA, 3.0 mA, and 4.5
mA using the register bits <LVDS CURR>. In addition, there exists a current double mode, where the LVDS
nominal current is doubled (register bits <CURR DOUBLE>, refer to Table 19).
LVDS INTERNAL TERMINATION
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. Five termination resistances are available – 166, 200, 250, 333, and 500 Ω
(nominal with ±20% variation). Any combination of these terminations can be programmed; the effective
termination is the parallel combination of the selected resistances. The terminations can be programmed
separately for the clock and data buffers (bits <TERM CLK> and <TERM DATA>, refer to Table 20).
The internal termination helps to absorb any reflections from the receiver end, improving the signal integrity. This
makes it possible to drive up to 10 pF of load capacitance, compared to only 5 pF without the internal
termination. Figure 62 and Figure 63 show the eye diagram with 5 pF and 10 pF load capacitors (connected from
each output pin to ground).
With 100 Ω internal and 100 Ω external termination, the voltage swing at the receiver end will be halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode (bits <CURR DOUBLE>, refer to Table 19).
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C001
Figure 62. LVDS Data Eye Diagram With 5 pF Load Capacitance (No Internal Termination)
C002
Figure 63. LVDS Data Eye Diagram With 10 pF Load Capacitance (100 Ω Internal Termination)
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CAPTURE TEST PATTERNS
ADS644X outputs the bit clock (DCLK), positioned nearly at the center of the data transitions. It is recommended
to route the bit clock, frame clock and output data lines with minimum relative skew on the PCB. This ensures
sufficient setup/hold times for a reliable capture by the receiver.
The DESKEW is a 1010... or 0101... pattern output on the serial data lines that can be used to verify if the
receiver capture clock edge is positioned correctly. This may be useful in case there is some skew between
DCLK and serial data inside the receiver. Once deserialized, it is required to ensure that the parallel data is
aligned to the frame boundary. The SYNC test pattern can be used for this. For example, in the 1-wire interface,
the SYNC pattern is 7 '1's followed by 7 '0's (from MSB to LSB). This information can be used by the receiver
logic to shift the deserialized data until it matches the SYNC pattern.
In addition to DESKEW and SYNC, the ADS644X includes other test patterns to verify correctness of the capture
by the receiver such as all zeros, all ones and toggle. These patterns are output on all four channel data lines
simultaneously. Some patterns like custom and sync are affected by the type of interface selected, serialization
and bit order.
Table 25. Test Patterns
PATTERN
DESCRIPTION
All zeros
Outputs logic low.
All ones
Outputs logic high.
Toggle
Outputs toggle pattern - <D13 – D0> alternates between 10101010101010 and
01010101010101 every clock cycle.
Custom
Outputs a 14 bit custom pattern. The 14 bit custom pattern can be specified into two
serial interface registers. In the 2-wire interface, each code is sent over the 2 wires
depending on the serialization and bit order.
Sync
Deskew
Outputs a sync pattern.
Outputs deskew pattern. Either <D13 – D0> = 10101010101010 or <D11 – D0> =
01010101010101 every clock cycle.
Table 26. SYNC Pattern
INTERFACE
OPTION
1-Wire
2-Wire
SERIALIZATION
SYNC PATTERN ON EACH WIRE
14 X
MSB-11111110000000-LSB
16 X
MSB-111111111000000000-LSB
14 X
MSB-1111000-LSB
16 X
MSB-11110000-LSB
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OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES
Setup, hold, and other timing parameters are specified across sampling frequencies and for each type of output
interface in the following tables.
Table 28 to Table 31: Typical values are at 25°C, min and max values are across the full temperature range TMIN
= –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, CL = 5 pF, IO = 3.5 mA, RL = 100 Ω, no internal termination,
unless otherwise noted.
Timing parameters are ensured by design and characterization and not tested in production.
Ts = 1/ Sampling frequency = 1/Fs
Table 27. Clock Propagation Delay for Different Interface Options
INTERFACE
1-Wire with DDR bit clock
2-Wire with DDR bit clock
SERIALIZATION
CLOCK PROPAGATION DELAY, tpd_clk
14x
tpd_clk = 0.428 x Ts + tdelay
16x
tpd_clk = 0.375 x Ts + tdelay
1
(when tpd_clk < Ts)
0
1
(when tpd_clk ≥ Ts)
tpd_clk = 0.75 x Ts + tdelay
2-Wire with SDR bit clock
(1)
2
(when tpd_clk ≥ Ts)
tpd_clk = 0.428 x Ts + tdelay
16x
(1)
0
tpd_clk = 0.857 x Ts + tdelay
14x
2-Wire with SDR bit clock
2-Wire with DDR bit clock
SERIALIZER LATENCY
clock cycles
0
(when tpd_clk < Ts)
tpd_clk = 0.375 x Ts + tdelay
0
Note that the total latency = ADC latency + internal serializer latency. The ADC latency is 12 clock cycles.
Table 28. Timing for 1-Wire Interface
SERIALIZATION
14×
DATA SETUP TIME, tsu
ns
DATA HOLD TIME, th
ns
SAMPLING
FREQUENCY
MSPS
MIN
TYP
MIN
TYP
65
0.3
0.5
0.4
0.6
40
0.65
0.85
0.7
0.9
20
1.3
1.65
1.6
1.9
10
3.2
3.5
3.2
3.6
65
0.22
0.42
0.35
0.55
MAX
tdelay
ns
MAX
MIN
TYP
MAX
Fs ≥ 40 MSPS
3
4
5
Fs < 40 MSPS
3
4.5
6
Fs ≥ 40 MSPS
3
16×
4
5
Fs < 40 MSPS
3
4.5
6
Table 29. Timing for 2-Wire Interface, DDR Bit Clock
SERIALIZATION
14×
16×
54
DATA SETUP TIME, tsu
ns
DATA HOLD TIME, th
ns
SAMPLING
FREQUENCY
MSPS
MIN
TYP
MIN
TYP
105
0.45
0.65
0.5
0.7
92
0.55
0.75
0.6
0.8
80
0.65
0.85
0.7
0.9
65
0.8
1.1
0.8
1.1
40
1.4
1.7
1.5
1.9
105
0.35
0.55
0.4
0.6
92
0.45
0.65
0.5
0.7
80
0.55
0.75
0.6
0.8
65
0.6
0.9
0.7
1
40
1.1
1.4
1.3
1.7
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MAX
tdelay
ns
MAX
MIN
TYP
MAX
Fs ≥ 45 MSPS
3.4
4.4
5.4
Fs < 45 MSPS
3.7
5.2
6.7
Fs ≥ 45 MSPS
3.4
4.4
5.4
Fs < 45 MSPS
3.7
5.2
6.7
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Table 30. Timing for 2-Wire Interface, SDR Bit Clock
SERIALIZATION
14×
16×
DATA SETUP TIME, tsu
ns
DATA HOLD TIME, th
ns
SAMPLING
FREQUENCY
MSPS
MIN
TYP
MIN
TYP
65
0.8
1
1
1.2
40
1.5
1.7
1.6
1.8
20
3.4
3.6
3.3
3.5
10
6.9
7.2
6.6
6.9
65
0.65
0.85
0.8
1.0
40
1.3
1.5
1.4
1.6
20
2.8
3.0
2.8
3.0
10
6.0
6.3
5.8
6.1
MAX
tdelay
ns
MAX
MIN
TYP
MAX
Fs ≥ 40 MSPS
3.4
4.4
5.4
Fs < 40 MSPS
3.7
5.2
6.7
Fs ≥ 40 MSPS
3.4
4.4
5.4
Fs < 40 MSPS
3.7
5.2
6.7
Table 31. Output Jitter (applies to all interface options)
SAMPLING FREQUENCY
MSPS
BIT CLOCK JITTER, CYCLE-CYCLE
ps, peak-peak
MIN
TYP
≥ 65
MAX
FRAME CLOCK JITTER, CYCLE-CYCLE
ps, peak-peak
MIN
350
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BOARD DESIGN CONSIDERATIONS
Grounding
A single ground plane is sufficient to give optimum performance, provided the analog, digital, and clock sections
of the board are cleanly partitioned. Refer to the EVM User Guide (SLAU196) for board layout schemes.
Supply Decoupling
As the ADS644X already includes internal decoupling, minimal external decoupling can be used without loss in
performance. Note that the decoupling capacitors can help to filter external power supply noise, so the optimum
number of decoupling capacitors would depend on actual application.
It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching
noise from sensitive analog circuitry. In case only a single 3.3 V supply is available, it should be routed first to
AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being
routed to LVDD.
Exposed Thermal Pad
It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal
performance. For detailed information, see application notes QFN Layout Guidelines(SLOA122A) and QFN/SON
PCB Attachment (SLUA271A).
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SLAS573C – FEBRUARY 2008 – REVISED MAY 2013
DEFINITION OF SPECIFICATIONS
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay will be different across channels. The maximum variation is specified as
aperture delay variation (channel-channel).
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate – The maximum sampling rate at which certified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly
1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – The INL is the deviation of the ADC's transfer function from a best fit line
determined by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – The gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The
gain error is given as a percentage of the ideal input full-scale range. The gain error does not include the error
caused by the internal reference deviation from ideal value. This is specified separately as internal reference
error. The maximum variation of the gain error across devices and across channels within a device is specified
separately.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC's actual average
idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation
of the parameter across the TMIN to TMAX range by the difference TMAX–TMIN.
Signal-to-Noise Ratio(SNR) is the ratio of the power of the fundamental (PS) to the noise floor power (PN),
excluding the power at DC and the first nine harmonics.
P
SNR + 10Log10 S
PN
(3)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s fullscale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
PS
SINAD + 10Log10
PN ) PD
(4)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's fullscale range.
Effective Number of Bits (ENOB) – The ENOB is a measure of a converter’s performance as compared to the
theoretical limit based on quantization noise.
ENOB + SINAD * 1.76
6.02
(5)
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the
first nine harmonics (PD).
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: ADS6445-EP ADS6444-EP
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57
ADS6445-EP
ADS6444-EP
SLAS573C – FEBRUARY 2008 – REVISED MAY 2013
THD + 10Log10
www.ti.com
PS
PD
(6)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1
and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given
in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB
to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range.
DC Power Supply Rejection Ratio (DC PSRR) – The DC PSSR is the ratio of the change in offset error to a
change in analog supply voltage. The DC PSRR is typically given in units of mV/V.
AC Power Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the
supply voltage by the ADC. If ΔVsup is the change in supply voltage and ΔVout is the resultant change of the
ADC output code (referred to the input), then
PSRR + 20Log10 DVout , expressed in dBc
DVsup
(7)
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6-dB positive and
negative overload. The deviation of the first few samples after the overload (from their expected values) is noted.
Common Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVcm_in is the change in the common-mode voltage of the input pins and ΔVout
is the resultant change of the ADC output code (referred to the input), then
CMRR + 20Log10 DVout , expressed in dBc
DVcm_in
(8)
Cross-Talk (only for multi-channel ADC)– This is a measure of the internal coupling of a signal from adjacent
channel into the channel of interest. It is specified separately for coupling from the immediate neighboring
channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured
by applying a full-scale signal in the adjacent channel. Cross-talk is the ratio of the power of the coupling signal
(as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel
input. It is typically expressed in dBc.
58
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Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: ADS6445-EP ADS6444-EP
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
ADS6444MRGCTEP
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
6444EP
ADS6445MRGCTEP
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
6445EP
V62/08628-01XE
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
6445EP
V62/08628-02XE
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
6444EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS6444-EP, ADS6445-EP :
• Catalog: ADS6444, ADS6445
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Mar-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS6444MRGCTEP
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS6445MRGCTEP
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Mar-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS6444MRGCTEP
VQFN
RGC
64
250
213.0
191.0
55.0
ADS6445MRGCTEP
VQFN
RGC
64
250
213.0
191.0
55.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGC 64
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
9 x 9, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGC0064A
PLASTIC QUADFLAT PACK- NO LEAD
9.15
8.85
B
A
9.15
8.85
PIN 1 INDEX AREA
(0.1)TYP
DETAIL 'A'
OPTION1
1 MAX
(0.2)TYP
DETAIL 'A'
OPTION2
C
SEATING PLANE
0.05
0.00
EXPOSED
THERMAL PAD
0.08 C
2X
7.5
7.25±0.1
32
17
16
33
SEE DETAIL 'A'
60X
0.5
2X
7.5
SYMM
65
64X0.3
0.18
48
1
PIN1 ID
(OPTIONAL)
64
0.1
0.05
C A B
C
49
SYMM
64X0.5
0.3
4219009/A 10/2018
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGC0064A
PLASTIC QUADFLAT PACK- NO LEAD
2X(8.8)
2X(7.5)
64X(0.6)
(
SEE SOLDER MASK
DETAIL
7.25)
64
49
1
48
64X(0.24)
60X(0.5)
SYMM
65
2X(7.5)
4X
(1.14)
2X
(8.8)
2X
(1.1)
(0.05)
(TYP)
33
16
45X (Ø0.2)
(TYP) VIA
4X
(1.14)
17
SYMM
32
2X
(1.1)
LAND PATTERN EXAMPLE
SCALE: 10X
0.07 MAX
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
METAL UNDER
SOLDER MASK
4219009/A 10/2018
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGC0064A
PLASTIC QUADFLAT PACK- NO LEAD
2X (8.8)
2X(7.5)
36X
(0.94)
SYMM
64x(0.6)
64
49
1
48
65
64X(0.24)
60X(0.5)
2X(0.57)
SYMM
2X(7.5)
2X(8.8)
4X(1.14)
(R0.05)
TYP
33
16
EXPOSED METAL
32
17
2X(0.57)
4X(1.14)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
60% PRINTED COVERAGE BY AREA
SCALE: 12X
4219009/A 10/2018
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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