Texas Instruments | Dual-Channel, 11-Bit, 250-MSPS ADC With DDR LVDS and Parallel CMOS Outputs | Datasheet | Texas Instruments Dual-Channel, 11-Bit, 250-MSPS ADC With DDR LVDS and Parallel CMOS Outputs Datasheet

Texas Instruments Dual-Channel, 11-Bit, 250-MSPS ADC With DDR LVDS and Parallel CMOS Outputs Datasheet
ADS62P19
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SLAS937 – APRIL 2013
Dual-Channel, 11-Bit, 250-MSPS ADC With DDR LVDS and Parallel CMOS Outputs
Check for Samples: ADS62P19
FEATURES
DESCRIPTION
•
•
•
•
The ADS62P19 is part of a family of dual-channel,
11-bit, analog-to-digital converters (ADCs) with
sampling rates up to 250 MSPS. The device
combines high dynamic performance and low power
consumption in a compact QFN-64 package. This
functionality makes the device well-suited for multicarrier, wide-bandwidth communication applications.
1
2
•
•
•
•
•
•
Maximum Sample Rate: 250 MSPS
11-Bit Resolution
Total Power: 1.25 W at 250 MSPS
Output Options:
– DDR LVDS and Parallel CMOS
Programmable Gain:
– Up to 6 dB for SNR and SFDR Trade-Off
DC Offset Correction
Crosstalk: 90 dB
Supports Input Clock Amplitude Down to
400 mVPP, Differential
Internal and External Reference Support
Package: 9-mm × 9-mm QFN-64
The ADS62P19 has gain options that can be used to
improve spurious-free dynamic range (SFDR)
performance at lower full-scale input ranges. The
device includes a dc offset correction loop that can be
used to cancel ADC offset. Both double data rate
(DDR) low-voltage differential signaling (LVDS) and
parallel complementary metal oxide semiconductor
(CMOS) digital output interfaces are available.
Although the device includes internal references, the
traditional reference pins and associated decoupling
capacitors are eliminated. Nevertheless, the device
can also be driven with an external reference. The
device is specified over the industrial temperature
range (–40°C to +85°C).
ADS62Pxx High-Speed Family
RESOLUTION
200 MSPS
210 MSPS
250 MSPS
11-bit
12-bit
ADS62C17
—
ADS62P19
—
ADS62P28
14-bit
ADS62P29
—
ADS62P48
ADS62P49
Table 1. Performance Summary
AT 170-MHz INPUT
SFDR, dBc
SINAD, dBFS
Analog power, W
GAIN (dB)
ADS62P19
ADS62P28
ADS62P29
ADS62P48
ADS62P49
0
75
78
75
78
75
6
82
84
82
84
82
0
65.3
68.7
68.3
70.1
69.8
6
64
65.8
65.8
66.3
66.5
—
1
0.92
1
0.92
1
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
ADS62P19
SLAS937 – APRIL 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE-LEAD
PACKAGE DESIGNATOR
SPECIFIED TEMPERATURE
RANGE
TRANSPORT MEDIA
ADS62P19
QFN-64
RGC
–40°C to +85°C
Tape and Reel
ADS62P28
QFN-64
RGC
–40°C to +85°C
Tape and Reel
ADS62P29
QFN-64
RGC
–40°C to +85°C
Tape and Reel
ADS62P48
QFN-64
RGC
–40°C to +85°C
Tape and Reel
ADS62P49
QFN-64
RGC
–40°C to +85°C
Tape and Reel
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
UNIT
AVDD
–0.3 V to 3.9
V
DRVDD
–0.3 V to 2.2
V
–0.3 to 0.3
V
Voltage between AVDD to DRVDD
AVDD leads DRVDD during power-up and DRVDD
leads AVDD during power-down
–0.3 to 4.2
V
Voltage between DRVDD to AVDD
DRVDD leads AVDD during power-up and AVDD leads
DRVDD during power-down
–2.5 to 1.7
V
Voltage applied to external pin
VCM (in external reference mode)
Voltage applied to analog input pins
INP_A, INM_A, INP_B, INM_B
Voltage applied to input pins
CLKP, CLKM (2), RESET, SCLK, SDATA, SEN, CTRL1,
CTRL2, CTRL3
Supply voltage range
Voltage between AGND and DRGND
Temperature range
–0.3 to 2.0
V
–0.3 to minimum (3.6, AVDD + 0.3)
V
–0.3 to AVDD + 0.3
V
Operating free-air, TA
–40 to +85
°C
Operating junction, TJ
+125
°C
Storage, Tstg
Electrostatic discharge (ESD) rating
(1)
(2)
Human body model (HBM)
–65 to +150
°C
2
kV
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP, CLKM is < |0.3 V|). This
setting prevents the ESD protection diodes at the clock input pins from turning on.
THERMAL INFORMATION
ADS62P19
THERMAL METRIC
(1)
RGC PACKAGE
UNITS
64 PINS
θJA
Junction-to-ambient thermal resistance
23.0
θJCtop
Junction-to-case (top) thermal resistance
10.5
θJB
Junction-to-board thermal resistance
4.2
ψJT
Junction-to-top characterization parameter
0.1
ψJB
Junction-to-board characterization parameter
4.2
θJCbot
Junction-to-case (bottom) thermal resistance
0.57
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
3.15
3.3
3.6
V
DRVDD
Digital supply voltage
1.7
1.8
1.9
V
ANALOG INPUTS
Differential input voltage range
2
Input common-mode voltage
Voltage applied on CM in external reference mode
Maximum analog input
frequency
VPP
1.5 ± 0.1
V
1.5 ± 0.05
V
With 2-Vpp input amplitude (1)
500
MHz
With 1-Vpp input amplitude (1)
800
MHz
CLOCK INPUT
Low-speed mode disabled (default mode after reset)
Input clock sample rate
Low-speed mode enabled
(3)
With multiplexed mode enabled (4)
Sine wave, ac-coupled
Input clock amplitude
differential
(VCLKP – VCLKM) (5) (6)
> 80
250 (2)
MSPS
1
80
MSPS
1
65
MSPS
1.5
VPP
LVPECL, ac-coupled
0.2
1.6
VPP
LVDS, ac-coupled
0.7
VPP
LVCMOS, single-ended, ac-coupled
Input clock duty cycle
3.3
40%
50%
V
60%
DIGITAL OUTPUTS
CLOAD
Maximum external load capacitance from each output pin to DRGND
RLOAD
Differential load resistance between the LVDS output pairs (LVDS mode)
TA
Operating free-air temperature
(1)
(2)
(3)
(4)
(5)
(6)
5
pF
Ω
100
–40
85
°C
See the Theory of Operation section for information.
With LVDS interface only; maximum recommended sample rate with CMOS interface is 210 MSPS.
Use the ENABLE LOW SPEED MODE register bit; refer to the Serial Register Map section for information.
See the Multiplexed Output Mode section for information.
Refer to Figure 25.
Refer to Figure 1 for the definition of clock amplitude.
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ELECTRICAL CHARACTERISTICS: GENERAL
Typical values are at TA = +25°C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input,
and internal reference mode, unless otherwise noted.
Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 3.3 V, and
DRVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
VID
Differential input voltage range
0-dB gain
2
VPP
Differential input resistance
Differential input capacitance
At dc, see Figure 45
>1
MΩ
See Figure 46
3.5
pF
Analog input bandwidth
With 25-Ω source impedance
700
MHz
Analog input common-mode
current
Per channel
3.6
μA/MSPS
VCM
Common-mode output voltage
1.5
V
VCM
Output current capability
±4
mA
DC ACCURACY
EO
Offset error
–20
Temperature coefficient of offset
error
Variation of offset error with
supply
±2
20
mV
0.02
mV/°C
0.5
mV/V
Two sources of gain error: internal
reference inaccuracy and channel
gain error
EGREF
Gain error resulting from internal
reference inaccuracy alone
–1
±0.2
1
% FS
EGCHAN
Gain error of channel alone (1)
–1
±0.2
1
% FS
Temperature coefficient of
EGCHAN
Gain matching
(2)
Δ%/°C
0.002
Difference in gain errors between two
channels within the same device
–2
2
%FS
Difference in gain errors between two
channels across two devices
–4
4
%FS
POWER SUPPLY
IAVDD
Analog supply current
IDRVDD
Output buffer supply current
AVDD
Analog power
DVDD
Digital power
LVDS interface with 100-Ω external
termination
CMOS interface, fIN = 2 MHz, fS = 210 MSPS,
no external load capacitance (3) (4)
LVDS interface
Global power down
(1)
(2)
(3)
(4)
4
305
350
mA
133
175
mA
91
mA
1.01
1.15
0.24
0.315
45
100
W
W
mW
This parameter is specified by design and characterization; not tested in production.
For two channels within the same device, only the channel gain error matters because the reference is common for both channels.
In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the
supply voltage (see Figure 31 and the CMOS Interface Power Dissipation section in the Application Information).
The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the
maximum recommended load capacitance on each digital output line is 10 pF.
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ELECTRICAL CHARACTERISTICS: ADS62P19
Typical values are at TA = +25°C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input,
0-dB gain, and internal reference mode, unless otherwise noted. Minimum and maximum values are across the full
temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 3.3 V, and DRVDD = 1.8 V.
PARAMETER
SNR
Signal to noise ratio, LVDS
TEST CONDITIONS
Signal to noise and distortion ratio,
LVDS
66.4
dBFS
fIN = 100 MHz
66.1
dBFS
65.9
dBFS
64.1
dBFS
fIN = 230 MHz
65.4
dBFS
fIN = 20 MHz
66.5
dBFS
fIN = 60 MHz
66.3
dBFS
fIN = 100 MHz
65.9
dBFS
65.3
dBFS
64
dBFS
fIN = 230 MHz
65.2
dBFS
10.6
LSB
±0.1
LSB
Effective number of bits
fIN = 170 MHz
DNL
Differential nonlinearity
fIN = 170 MHz
INL
Integrated nonlinearity
fIN = 170 MHz
0-dB gain
0-dB gain
Second-order harmonic distortion
Third-order harmonic distortion
Total harmonic distortion
PSRR
Two-tone intermodulation distortion
±2.5
LSB
dBc
fIN = 60 MHz
85
dBc
fIN = 100 MHz
78
dBc
75
dBc
fIN = 230 MHz
77
dBc
fIN = 20 MHz
98
dBc
fIN = 60 MHz
95
dBc
fIN = 100 MHz
88
dBc
88
dBc
fIN = 230 MHz
87
dBc
fIN = 20 MHz
93
dBc
fIN = 60 MHz
90
dBc
fIN = 100 MHz
90
dBc
85
dBc
fIN = 230 MHz
85
dBc
fIN = 20 MHz
89
dBc
fIN = 60 MHz
85
dBc
fIN = 100 MHz
78
dBc
75
dBc
fIN = 230 MHz
77
dBc
fIN = 20 MHz
87
dBc
fIN = 60 MHz
83.5
dBc
fIN = 100 MHz
77.5
dBc
74
dBc
fIN = 170 MHz
IMD
±0.5
89
fIN = 170 MHz
THD
–0.6
fIN = 20 MHz
fIN = 170 MHz
HD3
63.5
6-dB gain
fIN = 170 MHz
HD2
64.5
6-dB gain
fIN = 170 MHz
Spurious-free dynamic range
(excluding HD2, HD3)
UNIT
fIN = 60 MHz
ENOB
SFDR
MAX
dBFS
fIN = 170 MHz
Spurious-free dynamic range
TYP
66.5
fIN = 170 MHz
SINAD
MIN
fIN = 20 MHz
69.5
75
69.5
69.5
68
fIN = 230 MHz
75
dBc
f1 = 46 MHz, f2 = 50 MHz, each tone at –7 dBFS
87
dBFS
dBFS
f1 = 185 MHz, f2 = 190 MHz, each tone at –7 dBFS
85
Crosstalk
Up to 200-MHz crosstalk frequency
90
dB
Input overload recovery
Recovery to within 1% (of final value) for 6-dB overload
with sine-wave input
1
Clock
cycles
AC power-supply rejection ratio
For 100-mVPP signal on AVDD supply
25
dB
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DIGITAL CHARACTERISTICS
The dc specifications refer to the condition where the digital outputs do not switch, but are permanently at a valid logic level
'0' or '1'. AVDD = 3.3 V and DRVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (CTRL1, CTRL2, CTRL3, RESET, SCLK, SDATA, SEN (1))
VIH
High-level input voltage
All digital inputs support 1.8-V and 3.3-V
CMOS logic levels
1.3
V
VIL
Low-level input voltage
All digital inputs support 1.8-V and 3.3-V
CMOS logic levels
IIH
High-level input
current
SDATA, SCLK (2)
VHIGH = 3.3 V
16
μA
SEN (3)
VHIGH = 3.3 V
10
μA
IIL
Low-level input
current
SDATA, SCLK
VLOW = 0 V
0
μA
SEN
VLOW = 0 V
–20
μA
CI
Input capacitance
4
pF
DRVDD
V
0.4
V
DIGITAL OUTPUTS (CMOS INTERFACE: DA[10:0], DB[10:0], CLKOUT, SDOUT)
VOH
High-level output voltage
IOH = 1 mA
VOL
Low-level output voltage
IOL = 1 mA
CO
Output capacitance (internal to device)
DRVDD
– 0.1
0
0.1
2
V
pF
DIGITAL OUTPUTS (LVDS INTERFACE)
VODH
High-level output differential voltage
With external 100-Ω termination
275
350
425
mV
VODL
Low-level output differential voltage
With external 100-Ω termination
–425
–350
–275
mV
VOCM
Output common-mode voltage
1
1.15
1.4
CO
(1)
(2)
(3)
6
Output capacitance
Capacitance inside the device from each
output to ground
2
V
pF
SCLK, SDATA, and SEN function as digital input pins in serial configuration mode.
SDATA, SCLK, RESET, CTRL1, CTRL2, and CTRL3 have an internal 100-kΩ pull-down resistor.
SEN has an internal 100-kΩ pull-up resistor to AVDD. SEN can also be driven by 1.8-V or 3.3-V CMOS buffers because the pull-up
resistor is weak.
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TIMING REQUIREMENTS: LVDS AND CMOS MODES (1)
Typical values are at TA = +25°C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine-wave input clock,
1.5-VPP clock amplitude, CLOAD = 5 pF (2), and RLOAD = 100 Ω (3), unless otherwise noted. Minimum and maximum values are
across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 3.3 V, and DRVDD = 1.7 V to 1.9 V.
PARAMETER
ta
TEST CONDITIONS
Aperture delay
Aperture delay matching
tj
MIN
TYP
MAX
0.7
1.2
1.7
Between two channels within the same device
ns
±50
Aperture jitter
ps
145
Time to valid data after exiting STANDBY mode
Wake-up time
UNIT
Time to valid data after exiting global power-down
fS RMS
1
3
μs
20
50
μs
10
Time to valid data after stopping and restarting the input clock
ADC latency (4)
Clock
cycles
22
Clock
cycles
DDR LVDS MODE (5)
tsu
Data setup time
Data valid (6) to CLKOUTP zero-crossing
0.55
0.9
ns
th
Data hold time
CLKOUTP zero-crossing to data becoming invalid (6)
0.55
0.95
ns
Clock propagation delay
Input clock falling edge crossover to output clock rising edge
crossover
100 MSPS ≤ sampling frequency ≤ 250 MSPS
tS = 1 / sampling frequency
tdelay skew
Difference in tdelay between two devices operating at same
temperature and DRVDD supply voltage
±500
LVDS bit clock duty cycle
Differential clock duty cycle (CLKOUTP – CLKOUTM)
100 MSPS ≤ sampling frequency ≤ 250 MSPS
52%
tRISE,
tFALL
Data rise time,
Data fall time
Rise time measured from –100 mV to +100 mV
Fall time measured from +100 mV to –100 mV
1 MSPS ≤ sampling frequency ≤ 250 MSPS
0.14
ns
tCLKRISE,
tCLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from –100 mV to +10 0mV
Fall time measured from +100 mV to –100 mV
1 MSPS ≤ sampling frequency ≤ 250 MSPS
0.14
ns
tOE
Output buffer enable to
data delay
Time to valid data after output buffer becomes active
100
ns
tPDI
tdelay
(1)
(2)
(3)
(4)
(5)
(6)
tPDI = 0.69 × tS + tdelay
4.2
5.7
7.2
ns
ps
Timing parameters are ensured by design and characterization and are not tested in production.
CLOAD is the effective external single-ended load capacitance between each output pin and ground.
RLOAD is the differential load resistance between the LVDS output pair.
At higher clock frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.
Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and load. Setup and hold time
specifications take into account the effect of jitter on the output data and clock.
Data valid refers to a logic high of +100.0 mV and a logic low of –100.0 mV.
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TIMING REQUIREMENTS: LVDS AND CMOS MODES(1) (continued)
Typical values are at TA = +25°C, AVDD = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine-wave input clock,
1.5-VPP clock amplitude, CLOAD = 5 pF(2), and RLOAD = 100 Ω(3), unless otherwise noted. Minimum and maximum values are
across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 3.3 V, and DRVDD = 1.7 V to 1.9 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PARALLEL CMOS MODE (7) (At fS = 210 MSPS)
tSTART
Input clock to data delay
tDV
Input clock falling edge crossover to start of data valid (8)
2.5
(8)
Data valid time
Time interval of valid data
Clock propagation delay
Input clock falling edge crossover to output clock rising edge
crossover
100 MSPS ≤ sampling frequency ≤ 150 MSPS
tS = 1 / sampling frequency
Output clock duty cycle
Output clock duty cycle , CLKOUT
100 MSPS ≤ sampling frequency ≤ 150 MSPS
tRISE,
tFALL
Data rise time,
Data fall time
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 ≤ sampling frequency ≤ 210 MSPS
1.2
ns
tCLKRISE,
tCLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 ≤ sampling frequency ≤ 150 MSPS
0.8
ns
tOE
Output buffer enable (OE)
to data delay (9)
Time to valid data after output buffer becomes active
100
ns
tPDI
tdelay
(7)
(8)
(9)
1.7
ns
2.7
ns
tPDI = 0.28 × tS + tdelay
5.5
7.0
8.5
ns
43%
For fS > 150 MSPS, TI recommends using an external clock for data capture instead of the device output clock signal (CLKOUT).
Data valid refers to a logic high of 1.26 V and a logic low of 0.54 V.
The output buffer enable is controlled by serial interface register 40h. The output buffer becomes active when serial control data for the
output buffer are latched on the 16th SCLK falling edge when SEN is low.
Table 2. LVDS Timings at Lower Sampling Frequencies
SAMPLING FREQUENCY (MSPS)
SETUP TIME (ns)
MIN
TYP
0.75
185
153
125
1.6
210
< 80
(enable low-speed mode for fS ≤ 80) (1)
HOLD TIME (ns)
MAX
MIN
TYP
1.1
0.75
0.9
1.25
1.15
1.55
2
2
tPDI (ns)
MAX
MIN
TYP
MAX
1.15
7.5
9
10.5
0.85
1.25
7.9
9.4
10.9
1.1
1.5
8.7
10.2
11.7
1.45
1.85
9.7
11.2
12.7
2
1 ≤ fS ≤ 80
(enable low-speed mode for fS ≤ 80) (1)
(1)
12.6
Low-speed mode can only be enabled with the serial interface configuration.
Table 3. CMOS Timings at Lower Sampling Frequencies with Respect to Input Clock
TIMINGS SPECIFIED WITH RESPECT TO INPUT CLOCK
SAMPLING FREQUENCY (MSPS)
tSTART (ns)
MIN
8
TYP
DATA VALID TIME (ns)
MAX
MIN
TYP
210
2.5
1.7
2.7
190
1.9
2
3
170
0.9
2.7
3.7
150
6
3.6
4.6
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Table 4. CMOS Timings at Lower Sampling Frequencies with Respect to CLKOUT
TIMINGS SPECIFIED WITH RESPECT TO CLKOUT
SAMPLING FREQUENCY (MSPS)
SETUP TIME (ns)
HOLD TIME (ns)
MIN
TYP
MIN
TYP
MIN
TYP
MAX
170
2.1
3.7
0.35
1.0
7.1
8.6
10.1
150
2.8
4.4
0.5
1.2
7.4
8.9
10.4
125
3.8
5.4
0.8
1.5
7.7
9.2
10.7
< 80
(enable low-speed mode for fS ≤ 80) (1)
MAX
tPDI (ns)
5
MAX
1.2
1 ≤ fS ≤ 80
(enable low-speed mode for fS ≤ 80) (1)
(1)
9
Low-speed mode can only be enabled with the serial interface configuration.
PARAMETRIC MEASUREMENT INFORMATION
TIMING DIAGRAMS
VCLKP - VCLKM
Vp
0
Vpp
Figure 1. Clock Amplitude Definition Diagram
DAnP/DBnP
Dn_Dn+1_P
Logic 0
VODL = –350 mV
Logic 1
(1)
VODH = 350 mV
(1)
Dn_Dn+1_M
DAnM/DBnM
VOCM
V
GND
GND
T0334-02
(1)
With external 100-Ω termination
Figure 2. LVDS Output Voltage Levels
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PARAMETRIC MEASUREMENT INFORMATION (continued)
N+3
N+2
N+1
Sample
N
N+4
N+24
N+23
N+22
INPUT
SIGNAL
ta
INPUT
CLOCK
CLKM
CLKP
CLKOUTM
CLKOUTP
22 clock cycles *
DDR
LVDS
OUTPUT DATA
DXP, DXM
E
O
E
O
E
O
E
O
E
t PDI
O
E
O
E
O
E
O
E
O
E
O
E – Even bits D0, D2, D4...
N-22
O – Odd bits D1, D3, D5...
N-21
N-20
N-1
N-19
N
N+2
N+1
CLKOUT
t PDI
22 clock cycles *
PARALLEL
CMOS
OUTPUT DATA
D0:D10
N-22
N-21
N-20
N18
N-19
N-1
N
N+1
N+2
Figure 3. Latency Diagram
CLKP
Input
clock
CLKM
t PDI
CLKOUTM
Output
clock
CLKOUTP
t su
Output
data pair
DAnP/M
DBnP/M
th
t su
Dn*
th
Dn+1*
*Dn – Bits D1,D3,D5...
*Dn+1 – Bits D0,D2,D4...
Figure 4. LVDS Interface Timing
10
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PARAMETRIC MEASUREMENT INFORMATION (continued)
Input
Clock
CLKP
CLKM
tPDI
Output
Clock
CLKOUT
th
tsu
Output
Data
Input
Clock
DAn, DBn
Dn
(1)
CLKP
CLKM
tSTART
tDV
Output
Data
DAn, DBn
Dn
(1)
T0107-07
(1)
Dn = bits D0, D1, D2, and so forth of channels A and B.
Figure 5. CMOS Interface Timing
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PARAMETRIC MEASUREMENT INFORMATION (continued)
SERIAL INTERFACE
Table 5. SERIAL INTERFACE TIMING CHARACTERISTICS (1)
PARAMETER
MIN
TYP
UNIT
20
MHz
SCLK frequency (= 1 / tSCLK)
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDS
SDATA setup time
25
ns
tDH
SDATA hold time
25
ns
(1)
> dc
MAX
fSCLK
Typical values are at TA = +25°C, minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX =
+85°C, AVDD = 3.3 V, and DRVDD = 1.8 V, unless otherwise noted.
Serial Register Readout
The device includes an option where the contents of the internal registers can be read back. This functionality
may be useful as a diagnostic check to verify the serial interface communication between the external controller
and the ADC. In order to achieve read back:
• First, set the SERIAL READOUT register bit to '1'. This setting also disables any further writes into the
registers.
• Initiate a serial interface cycle specifying the address of the register (A[7:0]) whose content must be read.
• The device outputs the contents (D[7:0]) of the selected register on the SDOUT pin (pin 64).
• The external controller can latch the contents at the SCLK falling edge.
• To enable register writes, reset the SERIAL READOUT register bit to '0'. SDOUT is a CMOS output pin; the
readout functionality is available whether the ADC output data interface is LVDS or CMOS.
When SERIAL READOUT is disabled, the SDOUT pin is forced low by the device (and is not put in highimpedance). If serial readout is not used, the SDOUT pin must float. Note that contents of register 00h cannot be
read back.
Table 6. Reset Timing (only when the serial interface is used) (1)
PARAMETER
CONDITIONS
t1
Power-on delay
Delay from power-up of AVDD and DRVDD to RESET
pulse active
t2
Reset pulse duration
Pulse duration of active RESET signal
t3
Register write delay
Delay from RESET disable to SEN active
(1)
12
MIN
TYP
MAX
UNIT
1
ms
10
ns
1
100
μs
ns
Typical values are at TA = +25°C, minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX =
+85°C, unless otherwise noted.
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A) Enable serial readout (<SERIAL READOUT> = 1)
Register Data (D7:D0) = 0x01
Register Address (A7:A0) = 0x00
SDATA
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
SDOUT
Pin SDOUT is NOT in high-impedance state; it is forced low by the device (<SERIAL READOUT> = 0)
B) Read contents of register 0x40. This register has been initialized with 0x0C (device is put in global power down mode)
Register Data (D7:D0) = XX (Don't Care)
Register Address (A7:A0) = 0x40
SDATA
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
1
0
0
SCLK
SEN
SDOUT
Pin SDOUT functions as serial readout (<SERIAL READOUT> = 1)
T0386-02
Figure 6. Serial Readout
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Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
T0108-01
NOTE: A high-going pulse on the RESET pin is required in serial interface mode in case of initialization through hardware reset. For parallel
interface operation, RESET must be permanently tied high.
Figure 7. Reset Timing Diagram
14
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PIN CONFIGURATIONS
DB0M
NC
NC
DRGND
D R V DD
C LKO UTP
C LKOU TM
DA 10P
DA 10M
DA8P
DA8 M
DA 6 P
DA 6M
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
DRGND
DB0P
DRVDD
SDOUT
RGC PACKAGE
QFN-64
(Top View)
1
48
DRVDD
DB 2M
2
47
DA4P
DB 2P
3
46
DA4M
PAD (Connected to DRGND)
4
45
DA 2 P
DB4P
5
44
DA 2M
DB 6M
6
43
DA0P
DB 6P
7
42
DA 0 M
DB8M
8
41
NC
DB8P
9
40
NC
DB10M
10
39
DRGND
DB10P
11
38
DRVDD
RESET
12
37
CTRL 3
SCLK
13
36
CTRL 2
SDATA
14
35
CTRL 1
SEN
15
34
AVDD
AVDD
16
29
30
31
32
AGND
28
AGND
27
IN M_ A
26
IN P _ A
NC
25
AGND
AGND
24
AGND
IN M _ B
23
C LKM
22
C LKP
21
AGND
20
VCM
19
IN P _ B
AVDD
18
AGND
AGND
DB4M
Figure 8. LVDS Mode
PIN DESCRIPTIONS (LVDS MODE)
PIN
NO. OF
PINS
I/O
17, 18, 21, 24, 27, 28,
31, 32
8
I
Analog ground
AVDD
16, 33, 34
3
I
Analog power supply
CLKM
26
1
I
Differential clock input
CLKP
25
1
I
Differential clock input
CLKOUTM
56
1
O
Differential output clock, complement
NAME
NO.
AGND
DESCRIPTION
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PIN DESCRIPTIONS (LVDS MODE) (continued)
PIN
16
NAME
NO.
NO. OF
PINS
I/O
CLKOUTP
57
1
O
Differential output clock, true
CTRL1
35
1
I
CTRL2
36
1
I
DESCRIPTION
CTRL3
37
1
I
Digital control input pins.
Together, these pins control various power-down modes.
Each pin has an internal 100-kΩ pull-down resistor.
DA0P, DA0M
Refer to Figure 8
2
O
Differential output data pair, 0 and D0 multiplexed; channel A
DA2P, DA2M
Refer to Figure 8
2
O
Differential output data D1 and D2 multiplexed; channel A
DA4P, DA4M
Refer to Figure 8
2
O
Differential output data D3 and D4 multiplexed; channel A
DA6P, DA6M
Refer to Figure 8
2
O
Differential output data D5 and D6 multiplexed; channel A
DA8P, DA8M
Refer to Figure 8
2
O
Differential output data D7 and D8 multiplexed; channel A
DA10P, DA10M
Refer to Figure 8
2
O
Differential output data D9 and D10 multiplexed; channel A
DB0P, DB0M
Refer to Figure 8
2
O
Differential output data pair, 0 and D0 multiplexed; channel B
DB2P, DB2M
Refer to Figure 8
2
O
Differential output data D1 and D2 multiplexed; channel B
DB4P, DB4M
Refer to Figure 8
2
O
Differential output data D3 and D4 multiplexed; channel B
DB6P, DB6M
Refer to Figure 8
2
O
Differential output data D5 and D6 multiplexed; channel B
DB8P, DB8M
Refer to Figure 8
2
O
Differential output data D7 and D8 multiplexed; channel B
DB10P, DB10M
Refer to Figure 8
2
O
Differential output data D9 and D10 multiplexed; channel B
DRGND
39, 49, 59, PAD
4
I
Output buffer ground
DRVDD
1, 38, 48, 58
4
I
Output buffer supply
INM_A
30
1
I
Differential analog input, channel A
INP_A
29
1
I
Differential analog input, channel A
INM_B
20
1
I
Differential analog input, channel B
INP_B
19
1
I
Differential analog input, channel B
NC
Refer to Figure 8
5
Do not connect
RESET
12
1
I
Serial interface RESET input.
When using the serial interface mode, the internal registers must be
initialized through a hardware RESET by applying a high-going pulse
on this pin or by using a software reset option. Refer to the Serial
Interface section.
In parallel interface mode, the RESET pin must be permanently tied
high. (SCLK and SEN are used as parallel control pins in this mode.)
This pin has an internal 100-kΩ pull-down resistor.
SCLK
13
1
I
This pin functions as serial interface clock input when RESET is low.
SCLK controls the internal or external reference selection when RESET
is tied high. See Table 8 for detailed information.
This pin has an internal 100-kΩ pull-down resistor.
SDATA
14
1
I
Serial interface data input.
SDATA has an internal 100-kΩ pull-down resistor.
This pin has no function in parallel interface mode and can be tied to
ground.
SDOUT
64
1
O
This pin functions as a serial interface register readout when the
SERIAL READOUT bit is enabled.
When SERIAL READOUT is '0', this pin forces a logic low and is not 3stated.
This pin functions as a serial interface enable input when RESET is
low.
SEN controls data format and interface type selection when RESET is
tied high. See Table 9 for detailed information.
This pin has an internal 100-kΩ pull-up resistor to AVDD.
SEN
15
1
I
VCM
23
1
IO
Internal reference mode. Common-mode voltage output.
External reference mode. Reference input; the voltage forced on this
pin sets the internal references.
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DB0
NC
NC
NC
DRGND
DRVDD
CLKOUT
U NUSED
DA10
DA9
DA8
DA7
DA6
DA5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
DRGND
SDOUT
RGC PACKAGE
QFN-64
(Top View)
DRVDD
1
48
DRVDD
DB1
2
47
DA4
DB2
3
46
DA3
DB3
4
45
DA2
DB 4
5
44
DA1
DB 5
6
43
DA0
DB 6
7
42
NC
DB 7
8
41
NC
DB 8
9
40
NC
DB 9
10
39
DRGND
DB10
11
38
DRVDD
RESET
12
37
CTRL 3
SCLK
13
36
CTRL 2
SDATA
14
35
CTRL 1
SEN
15
34
AVDD
AVDD
16
22
23
24
25
26
27
28
29
INM_B
AGND
NC
VCM
AGND
CLKP
CLKM
AGND
AGND
INP_A
30
31
32
AGND
21
AGND
20
INM_A
19
INP_B
AVDD
18
AGND
AGND
PAD (Connected to DRGND)
Figure 9. CMOS Mode
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PIN DESCRIPTIONS (CMOS MODE)
PIN
NO.
NO. OF
PINS
I/O
AVDD
16, 33, 34
3
I
Analog power supply
AGND
17, 18, 21, 24, 27, 28,
31, 32
8
I
Analog ground
CLKM
26
1
I
Differential clock input
CLKP
25
1
I
Differential clock input
CLKOUT
57
1
O
CMOS output clock
CTRL1
35
1
I
CTRL2
36
1
I
CTRL3
37
1
I
Digital control input pins.
Together, these pins control various power-down modes.
Each pin has an internal 100-kΩ pull-down resistor.
DA0 to DA10
Refer to Figure 9
11
O
Channel A ADC output data bits, CMOS levels
DB0 to DB10
Refer to Figure 9
11
O
Channel B ADC output data bits, CMOS levels
DRGND
39, 49, 59, PAD
4
I
Output buffer ground
DRVDD
1, 38, 48, 58
4
I
Output buffer supply
INM_A
30
1
I
Differential analog input, channel A
INP_A
29
1
I
Differential analog input, channel A
INM_B
20
1
I
Differential analog input, channel B
INP_B
19
1
I
Differential analog input, channel B
NC
Refer to Figure 9
7
Do not connect
1
I
Serial interface RESET input.
When using the serial interface mode, the internal registers must be
initialized through a hardware RESET by applying a high-going pulse
on this pin or by using a software reset option. Refer to the Serial
Interface section.
In parallel interface mode, the RESET pin must be permanently tied
high. (SCLK and SEN are used as parallel control pins in this mode.)
This pin has an internal 100-kΩ pull-down resistor.
I
This pin functions as a serial interface clock input when RESET is low.
SCLK controls the internal or external reference selection when RESET
is tied high. See Table 8 for detailed information.
This pin has an internal 100-kΩ pull-down resistor.
I
Serial interface data input.
This pin has an internal 100-kΩ pull-down resistor.
SDATA has no function in parallel interface mode and can be tied to
ground.
O
This pin functions as a serial interface register readout when the
SERIAL READOUT bit is enabled.
When SERIAL READOUT is '0', this pin forces a logic low and is not 3stated.
This pin functions as a serial interface enable input when RESET is
low.
SEN controls data format and interface type selection when RESET is
tied high. See Table 9 for detailed information.
This pin has an internal 100-kΩ pull-up resistor to AVDD.
NAME
RESET
SCLK
SDATA
SDOUT
18
12
13
14
64
1
1
1
SEN
15
1
I
VCM
23
1
IO
DESCRIPTION
Internal reference mode. Common-mode voltage output.
External reference mode. Reference input; the voltage forced on this
pin sets the internal references.
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DRGND
DRVDD
AGND
AVDD
FUNCTIONAL BLOCK DIAGRAM
LVDS Interface
DA0_P,
DA0_M
DA2_P,
DA2_M
INA_P
INA_M
Sample
and
Hold
DA4_P,
DA4_M
Digital
and
DDR
Serializer
11-Bit
ADC
DA6_P,
DA6_M
DA8_P,
DA8_M
DA10_P,
DA10_M
CLKP
Output
Clock
Buffer
CLOCKGEN
CLKM
CLKOUTP,
CLKOUTM
DB0_P,
DB0_M
DB2_P,
DB2_M
INB_P
INB_M
Sample
and
Hold
DB4_P,
DB4_M
Digital
and
DDR
Serializer
11-Bit
ADC
DB6_P,
DB6_M
DB8_P,
DB8_M
DB10_P,
DB10_M
VCM
Control Interface
Reference
SDOUT
CTRL3
CTRL1
CTRL2
SEN
SDATA
SCLK
RESET
Device
Figure 10. Block Diagram
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TYPICAL CHARACTERISTICS
All plots are at TA = +25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, 0-dB
gain, LVDS output interface, and 32K point FFT, unless otherwise noted.
0
0
FIN = 20 MHz
SFDR = 88.2 dBc
SNR = 67 dBFS
SINAD = 66.95 dBFS
THD = 84.98 dBc
−20
−20
−40
Amplitude (dBFS)
Amplitude (dBFS)
−40
−60
−60
−80
−80
−100
−100
−120
FIN = 170 MHz
SFDR = 74.38 dBc
SNR = 66.34 dBFS
SINAD = 65.68 dBFS
THD = 73.18 dBc
20
40
60
80
100
−120
120
Frequency (MHz)
20
60
80
100
120
Frequency (MHz)
G011
Figure 11. FFT FOR 20-MHz INPUT SIGNAL
G012
Figure 12. FFT FOR 170-MHz INPUT SIGNAL
0
0
FIN = 300 MHz
SFDR = 76.86 dBc
SNR = 65.27 dBFS
SINAD = 64.8 dBFS
THD = 73.79 dBc
−20
Each Tone at
−7 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
IMD3 = 86.4 dBFS
−10
−20
−30
−40
Amplitude (dBFS)
−40
Amplitude (dBFS)
40
−60
−80
−50
−60
−70
−80
−90
−100
−100
−110
−120
20
40
60
80
100
Frequency (MHz)
0
15
30
45
60
75
90
105
120
Frequency (MHz)
G013
Figure 13. FFT FOR 300-MHz INPUT SIGNAL
20
−120
120
G014
Figure 14. FFT FOR TWO-TONE INPUT SIGNAL
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TYPICAL CHARACTERISTICS (continued)
All plots are at TA = +25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, 0-dB
gain, LVDS output interface, and 32K point FFT, unless otherwise noted.
0
95
Each Tone at
−36 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
IMD3 = 100 dBFS
−10
−20
−30
90
85
SFDR (dBc)
Amplitude (dBFS)
−40
−50
−60
−70
80
75
−80
70
−90
−100
65
−110
−120
0
15
30
45
60
75
90
105
60
120
Frequency (MHz)
0
50
100
150
200
250
300
350
400
450
500
Input Frequency (MHz)
G015
Figure 15. FFT FOR TWO-TONE INPUT SIGNAL
G016
Figure 16. SFDR vs INPUT FREQUENCY
69
100
68
96
20 MHz
60 MHz
80 MHz
100 MHz
130 MHz
170 MHz
220 MHz
270 MHz
300 MHz
400 MHz
500 MHz
92
67
88
SFDR (dBc)
SNR (dBFS)
66
65
84
80
64
76
63
72
62
61
68
0
50
100
150
200
250
300
350
400
Input Frequency (MHz)
450
500
64
0
2
3
4
5
Digital Gain (dB)
G017
Figure 17. SNR vs INPUT FREQUENCY
1
6
G018
Figure 18. SFDR vs INPUT FREQUENCY ACROSS GAIN
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TYPICAL CHARACTERISTICS (continued)
All plots are at TA = +25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, 0-dB
gain, LVDS output interface, and 32K point FFT, unless otherwise noted.
130
70
69
20 MHz
60 MHz
80 MHz
100 MHz
68
130 MHz
170 MHz
220 MHz
270 MHz
Input Frequency = 60 MHz
300 MHz
400 MHz
500 MHz
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
69.5
120
69
110
68.5
100
SNR (dBFS)
SINAD (dBFS)
66
65
64
63
68
90
67.5
80
67
70
66.5
60
66
50
65.5
40
SFDR (dBc,dBFS)
67
62
61
65
−40
60
0
1
2
3
4
5
−30
6
Digital Gain (dB)
−25
−20
−15
−10
−5
0
30
Amplitude (dBFS)
G020
G019
Figure 19. SINAD vs INPUT FREQUENCY ACROSS GAIN
Figure 20. PERFORMANCE vs INPUT AMPLITUDE
(Single Tone)
88
69.5
Input Frequency = 60 MHz
−35
90
SNR
SFDR
69
87
68.5
86
68
85
67.5
84
67
83
66.5
82
66
81
AVDD = 3.15 V
AVDD = 3.2 V
AVDD = 3.3 V
88
AVDD = 3.4 V
AVDD = 3.5 V
AVDD = 3.6 V
SFDR (dBc)
SFDR (dBc)
SNR (dBFS)
86
84
82
80
78
65.5
1.35
1.4
1.45
1.5
1.55
1.6
1.65
Input Common−Mode Voltage (V)
80
1.7
Input Frequency = 60 MHz
G021
76
−40
−15
10
35
60
Temperature (°C)
Figure 21. PERFORMANCE vs
COMMON-MODE INPUT VOLTAGE
22
85
G022
Figure 22. SFDR vs AVDD SUPPLY VOLTAGE
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TYPICAL CHARACTERISTICS (continued)
All plots are at TA = +25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, 0-dB
gain, LVDS output interface, and 32K point FFT, unless otherwise noted.
Input Frequency = 60 MHz
AVDD = 3.4 V
AVDD = 3.5 V
AVDD = 3.6 V
67
SNR (dBFS)
66.8
66.5
SNR(dBFS)
SFDR(dBc)
68.5
86
68
84
67.5
82
67
80
66.5
78
66
76
65.5
74
SFDR (dBc)
AVDD = 3.15 V
AVDD = 3.2 V
AVDD = 3.3 V
67.2
SNR (dBFS)
88
69
67.5
66.2
66
65.8
65
1.70
Input Frequency = 60 MHz
−15
10
35
60
85
Temperature (°C)
69
86
68
85
67
84
66
83
65
82
64
81
Differential Clock Amplitude (Vpp)
SNR
SFDR
69.5
SNR (dBFS)
87
SFDR (dBc)
SNR (dBFS)
Input Frequency = 20 MHz
70
2.0
95
70
SNR
SFDR
1.5
G024
Figure 24. PERFORMANCE vs DRVDD SUPPLY VOLTAGE
88
Input Frequency = 60 MHz
1.0
72
1.90
1.85
G023
71
0.5
1.80
DRVDD (V)
Figure 23. SNR vs AVDD SUPPLY VOLTAGE
63
1.75
80
69
91
68.5
89
68
87
67.5
85
67
83
66.5
81
66
79
65.5
77
65
30
35
40
45
50
55
60
65
75
Input Clock Duty Cycle (%)
G025
Figure 25. PERFORMANCE vs INPUT CLOCK AMPLITUDE
93
SFDR (dBc)
65.5
−40
G026
Figure 26. PERFORMANCE vs INPUT CLOCK DUTY CYCLE
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TYPICAL CHARACTERISTICS (continued)
All plots are at TA = +25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, 0-dB
gain, LVDS output interface, and 32K point FFT, unless otherwise noted.
88
69.5
Input Frequency = 60 MHz
−76
SNR
SFDR
Signal amplitude on aggressor channel at −0.3 dBFS
69
86
68.5
84
68
82
67.5
80
78
66.5
76
66
74
65.5
1.3
1.35
1.4
1.45
1.5
1.55
1.6
1.65
Crosstalk (dB)
67
−84
SFDR (dBc)
SNR (dBFS)
−80
−88
−92
−96
72
1.7
−100
VCM Voltage (V)
50
G027
100
150
200
250
300
Frequency (MHz)
Figure 27. PERFORMANCE IN EXTERNAL
REFERENCE MODE
G028
Figure 28. CROSSTALK vs FREQUENCY
−30
1.65
−35
1.5
Input Frequency =2.5 MHz
1.35
Power Dissipation (W)
−40
CMRR (dB)
−45
−50
−55
−60
1.2
1.05
0.9
0.75
0.6
−65
−70
0.45
20
70
120
170
220
Frequency (MHz)
270
0.3
25
G029
Figure 29. CMRR vs FREQUENCY
24
LVDS
CMOS
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50
75
100
125
150
175
200
Sampling Speed (MSPS)
225
250
G030
Figure 30. POWER DISSIPATION vs
SAMPLING FREQUENCY
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TYPICAL CHARACTERISTICS (continued)
All plots are at TA = +25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, 0-dB
gain, LVDS output interface, and 32K point FFT, unless otherwise noted.
180
Input Frequency =2.5 MHz
CMOS, No Load
CMOS,15 pF Load
LVDS
DRVDD Current (mA)
150
120
90
60
30
0
25
50
75
100
125
150
175
Sampling Speed (MSPS)
200
225
250
G031
Figure 31. DRVDD CURRENT vs SAMPLING FREQUENCY
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TYPICAL CHARACTERISTICS: Contour
All plots are at TA = +25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, 0-dB
gain, LVDS output interface, and 32K point FFT, unless otherwise noted.
250
76
240
80
76
76
76
fS - Sampling Frequency - MSPS
220
84
200
80
76
76
180
84
72
80
160
76
88
140
80
76
72 76
120
84
100
72
92 88
80
20
76
80
50
76
100
200
150
300
250
400
350
450
500
fIN - Input Frequency - MHz
70
75
85
80
90
95
SFDR - dBc
M0049-17
Figure 32. SFDR CONTOUR
(0-dB Gain, up to 500 MHz)
250
240
85
75
79
82
88
fS - Sampling Frequency - MSPS
220
67
71
63
79
200
85
85
180
82
75
160
79
88
67
71
79
63
140
88
82
120
85
88
82
91
80
20
75
79
88
100
79
79
100
300
200
400
67
71
500
600
700
800
fIN - Input Frequency - MHz
60
65
70
75
80
SFDR - dBc
85
90
M0049-18
Figure 33. SFDR CONTOUR
(6-dB Gain, up to 800 MHz)
26
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TYPICAL CHARACTERISTICS: Contour (continued)
All plots are at TA = +25°C, AVDD = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, internal reference mode, 0-dB
gain, LVDS output interface, and 32K point FFT, unless otherwise noted.
250
240
66
66.5
64.5
65.5
63.5
64
65
63
Sampling Frequency (MSPS)
220
200
180
66
66.5
67
160
65.5
64
64.5
65
63.5
140
120
100
66.5
67
65.5
66
64.5
65
64
63.5
63
80
20
50
100
150
200
250
300
350
400
450
500
Input Frequency (MHz)
61
60
59
62
63
65
64
67
66
SNR (dBFS)
Figure 34. SNR CONTOUR
(0-dB Gain, up to 500 MHz)
250
240
63.4
64.3
62.8
62.2
62.5
220
Sampling Frequency (MSPS)
63.1
64
63.7
64.6
200
180
64.3
64
160
64.9
63.4
63.4
63.1
62.8
64
64.6
140
120
64.6
64.9
100
65.2
64.3
64.3
64
63.7
63.4
62.8
63.1
62.5
80
20
50
100
150
200
250
300
350
400
500
450
Input Frequency (MHz)
60.5
61
61.5
62
62.5
63
63.5
64
64.5
65
SNR (dBFS)
Figure 35. SNR CONTOUR
(6-dB Gain, up to 800 MHz)
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DEVICE CONFIGURATION
The ADS62P19 can be configured independently using either parallel interface control or serial interface
programming.
PARALLEL CONFIGURATION ONLY
To put the device in parallel configuration mode, keep RESET tied high (AVDD or DRVDD).
With RESET high, the SEN, SCLK, CTRL1, CTRL2, and CTRL3 pins can be used to directly control certain
modes of the ADC. The device can be easily configured by connecting the parallel pins to the correct voltage
levels (as described in Table 7 to Table 10). There is no need to apply a reset and the SDATA pin can be
connected to ground.
In this mode, SEN and SCLK function as parallel interface control pins. Frequently-used functions can be
controlled in this mode (such as power-down modes, internal and external reference, selection between LVDS
and CMOS interface, and output data format). Table 7 lists a brief description of the modes controlled by the four
parallel pins.
Table 7. Parallel Pin Definition
PIN
TYPE OF PIN
SCLK
SEN
Analog control pins
(controlled by analog voltage levels, see Figure 36)
CONTROLS MODES
Internal and external reference
LVDS and CMOS interface and output data format
CTRL1
CTRL2
Digital control pins
(controlled by digital logic levels)
Controls power-down modes
CTRL3
Table 8. SCLK Control Pin
VOLTAGE APPLIED ON SCLK
DESCRIPTION
0
+200 mV / 0 mV
Internal reference
(3 / 8) AVDD
±200 mV
External reference
(5 / 8) AVDD
±200mV
External reference
AVDD
0 mV / –200 mV
Internal reference
Table 9. SEN Control Pin
VOLTAGE APPLIED ON SEN
0
+200 mV / 0 mV
Twos complement, DDR LVDS output
(3 / 8) AVDD
±200 mV
Offset binary, DDR LVDS output
(5 / 8) AVDD
±200 mV
Offset binary, parallel CMOS output
AVDD
0 mV / –200 mV
28
DESCRIPTION
Twos compliment, parallel CMOS output
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Table 10. CTRL1, CTRL2, and CTRL3 Pins (1)
CTRL1
CTRL2
CTRL3
Low
Low
Low
Normal operation
Low
Low
High
Not available
Low
High
Low
Not available
Low
High
High
Not available
High
Low
Low
Global power down
High
Low
High
Channel B standby
High
High
Low
Channel A standby
High
High
High
MUX mode of operation, Channel A and B data is multiplexed and output on DA10 to DA0 pins. (2)
(1)
(2)
DESCRIPTION
See the POWER DOWN section in the Application Information.
Low-speed mode must be enabled for the multiplexed output mode (MUX mode). Therefore, MUX mode only functions with the serial
interface configuration and is not supported with the parallel configuration.
SERIAL INTERFACE CONFIGURATION ONLY
To exercise this mode, the serial registers must first be reset to the default values and the RESET pin must be
kept low. SEN, SDATA, and SCLK function as serial interface pins in this mode and can be used to access the
internal registers of the ADC. The registers can be reset either by applying a pulse on the RESET pin or by
setting the RESET bit high. The Serial Interface section describes the register programming and reset in more
detail.
DETAILS OF PARALLEL CONFIGURATION ONLY
The functions controlled by each parallel pin are described in this section. A simple way of configuring the
parallel pins is shown in Figure 36.
AVDD
(5/8) AVDD
3R
(5/8) AVDD
GND
AVDD
2R
(3/8) AVDD
(3/8) AVDD
3R
To Parallel Pin
GND
S0321-01
Figure 36. Simple Scheme to Configure Parallel Pins
USING BOTH SERIAL INTERFACE AND PARALLEL CONTROLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3)
can also be used to configure the device. To allow this flexibility, keep RESET low. The parallel interface control
pins (CTRL1 to CTRL3) are available. After power-up, the device is automatically configured as per the voltage
settings on these pins (see Table 6). SEN, SDATA, and SCLK function as serial interface digital pins and are
used to access the ADC internal registers. The registers must first be reset to the default values either by
applying a pulse on the RESET pin or by setting the RST bit to '1'. After reset, the RESET pin must be kept low.
The Serial Interface section describes register programming and reset in more detail.
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SERIAL INTERFACE
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serially shift bits into the
device is enabled when SEN is low. SDATA serial data are latched at every SCLK falling edge when SEN is
active (low). The serial data are loaded into the register every 16th SCLK falling edge when SEN is low. In case
the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16bit words within a single active SEN pulse.
The first eight bits form the register address and the remaining eight bits are the register data. The interface can
function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50%
SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to the default values. This initialization can be
accomplished in one of two ways:
1. Either through a hardware reset by applying a high-going pulse on the RESET pin (of widths greater than
10 ns), as shown in Figure 37,
or
2. By applying a software reset. Using the serial interface, set the RESET bit (bit D7 in register 00h) high. This
setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this
case, the RESET pin is kept low.
Register Address
SDATA
A7
A6
A5
A4
A3
A2
Register Data
A1
A0
D7
D6
t(SCLK)
D5
D4
D3
D2
D1
D0
t(DH)
t(DSU)
SCLK
t(SLOADH)
t(SLOADS)
SEN
RESET
T0109-01
Figure 37. Serial Interface Timing
30
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SERIAL REGISTER MAP
Table 11. Summary of Functions Supported by Serial Interface (1)
REGISTER
ADDRESS
A[7:0] (Hex)
REGISTER FUNCTIONS
D7
D6
D5
D3
D2
D1
D0
00
RESET
0
0
0
0
0
0
SERIAL
READOUT
20
0
0
0
0
0
ENABLE LOW
SPEED MODE
0
0
3F
0
REF
0
0
0
0
STANDBY
0
40
0
0
0
0
41
LVDS CMOS
0
0
0
44
POWER DOWN MODES
0
0
CLKOUT EDGE CONTROL
0
ENABLE
INDIVIDUAL
CHANNEL
CONTROL
52
0
0
53
0
ENABLE
OFFSET
CORRECTION,
CH A
50
51
0
0
0
0
62
0
0
63
0
0
66
0
ENABLE
OFFSET
CORRECTION,
CH B
68
0
0
0
0
0
0
0
0
0
CUSTOM PATTERN HIGH
0
0
0
GAIN PROGRAMMABILITY, CH A
57
0
DATA FORMAT
CUSTOM PATTERN LOW
55
(1)
D4
0
OFFSET CORRECTION TIME CONSTANT, CH A
FINE GAIN ADJUST, CH A
0
0
0
0
0
0
GAIN PROGRAMMABILITY, CH B
6A
0
75
0
0
76
0
0
TEST PATTERNS, CH A
OFFSET PEDESTAL, CH A
0
0
0
0
0
0
OFFSET CORRECTION TIME CONSTANT, CH B
FINE GAIN ADJUST, CH B
0
0
0
OFFSET PEDESTAL, CH B
TEST PATTERNS, CH B
0
0
0
Multiple functions in a register can be programmed in a single write operation.
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DESCRIPTION OF SERIAL REGISTERS
Table 12. Register 00h
D7
D6
D5
D4
D3
D2
D1
D0
RESET
0
0
0
0
0
0
SERIAL READOUT
Bit D7
RESET: Software reset
1 = Software reset applied; resets all internal registers and self-clears to '0'.
Bits D[6:1]
Always write '0'
Bit D0
SERIAL READOUT
0 = Serial readout disabled. SDOUT is forced low by the device (and not put in high-impedance state).
1 = Serial readout enabled. SDOUT functions as a serial data readout.
Table 13. Register 20h
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
ENABLE LOW-SPEED MODE
0
0
Bits D[7:3]
Always write '0'
Bit D2
ENABLE LOW-SPEED MODE
0 = Low-speed mode disabled; use for sampling frequencies > 80 MSPS
1 = Enable low-speed mode for sampling frequencies ≤ 80 MSPS
Bits D[1:0]
Always write '0'
Table 14. Register 3Fh
D7
0
D6
D5
REF
D4
D3
D2
D1
D0
0
0
0
STANDBY
0
Bit D7
Always write '0'
Bits D[6:5]
REF: Internal or external reference selection
00 = Internal reference enabled
01 = Do not use
10 = Do not use
11 = External reference enabled
Bits D[4:2]
Always write '0'
Bit D1
STANDBY
0 = Normal operation
1 = Both ADC channels are put in standby. Internal references and output buffers are active. This architecture
results in a quick wake-up time from standby.
Bit D0
32
Always write '0'
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Table 15. Register 40h
D7
D6
D5
D4
0
0
0
0
Bits D[3:0]
D3
D2
D1
D0
POWER DOWN MODES
POWER DOWN MODES
0000 = The CTRL1, CTRL2, and CTRL3 pins determine the power-down modes.
1000 = Normal operation
1001 = Output buffer disabled for channel B
1010 = Output buffer disabled for channel A
1011 = Output buffer disabled for channel A and B
1100 = Global power-down
1101 = Channel B standby
1110 = Channel A standby
1111 = Multiplexed mode (MUX), only with CMOS interface.
Channel A and B data are multiplexed and output on the DA10 to DA0 pins. Refer to the Multiplexed Output Mode
section in the Application Information for additional information.
Table 16. Register 41h
D7
D6
D5
D4
D3
D2
D1
D0
LVDS CMOS
0
0
0
0
0
0
0
Bit D7
LVDS CMOS: Output interface
0 = Parallel CMOS interface
1 = DDR LVDS interface
Bits D[6:0]
Always write '0'
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Table 17. Register 44h
D7
D6
D5
D4
D3
D2
CLKOUT EDGE CONTROL
Bits D[7:2]
D1
D0
0
0
CLKOUT EDGE CONTROL: Output clock edge control
These bits control the output clock edge. The output clock rising and falling edge position settings are different for
the LVDS and CMOS interfaces.
LVDS INTERFACE
Bits D[7:5]
CLKOUT POSN: Output clock rising edge position (1)
000 = Default output clock position (refer to the Timing Requirements table)
100 = Default output clock position (refer to the Timing Requirements table)
101 = Falling edge shifted (delayed) by + (4 / 26) × tS (2)
110 = Falling edge shifted (advanced) by – (7 / 26) × tS
111 = Falling edge shifted (advanced) by – (4 / 26) × tS
Bits D[4:2]
CLKOUT POSN: Output clock falling edge position (1)
000 = Default output clock position (refer to the Timing Requirements table)
100 = Default output clock position (refer to the Timing Requirements table)
101 = Rising edge shifted (delayed) by + (4 / 26) × tS
110 = Rising edge shifted (advanced) by – (7 / 26) × tS
111 = Rising edge shifted (advanced) by – (4 / 26) × tS
CMOS INTERFACE
Bits D[7:5]
CLKOUT POSN: Output clock rising edge position (1)
000 = Default output clock position (refer to the Timing Requirements table)
100 = Default output clock position (refer to the Timing Requirements table)
101 = Rising edge shifted (delayed) by + (4 / 26) × tS
110 = Rising edge shifted (advanced) by – (7 / 26) × tS
111 = Rising edge shifted (advanced) by – (4 / 26) × tS
Bits D[4:2]
CLKOUT POSN: Output clock falling edge position (1)
000 = Default output clock position (refer to the Timing Requirements table)
100 = Default output clock position (refer to the Timing Requirements table)
101 = Falling edge shifted (delayed) by + (4 / 26) × tS
110 = Falling edge shifted (advanced) by – (7 / 26) × tS
111 = Falling edge shifted (advanced) by – (4 / 26) × tS
Bits D[1:0]
(1)
(2)
34
Always write '0'. These bit settings are the same for both LVDS and CMOS interfaces.
Keep the same duty cycle, move both edges by the same amount (for instance, write both D[4:2] and D[7:5] to be the same value).
tS = 1 / sampling frequency.
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Data
CLKM
D<7:5> = 000
Default position
of falling edge
D<4:2> = 000
Default position
of rising edge
CLKP
CLKM
D<4:2> = 101
Moves rising edge
by +(4/26)Ts
+(4/26)Ts
D<7:5> = 101
Moves falling edge
by +(4/26)Ts
+(4/26)Ts
CLKP
CLKM
–(7/26)Ts
D<4:2> = 110
Moves rising edge
by –(7/26)Ts
–(7/26)Ts
D<7:5> = 110
Moves falling edge
by –(7/26)Ts
CLKP
CLKM
–(4/26)Ts
D<4:2> = 111
Moves rising edge
by –(4/26)Ts
–(4/26)Ts
D<7:5> = 111
Moves falling edge
by –(4/26)Ts
CLKP
Sampling Time Period Ts
T0490-01
(1) Keep the same duty cycle, move both edges by same amount (for instance, write both D[4:2] and D[7:5] to be the same value).
(2) Refer to the Timing Requirements table for default output clock position.
Figure 38. LVDS Interface Output Clock Edge Movement (Serial Register 0x44)
Data
CLKOUT
D<7:5> = 000
Default position
of rising edge
CLKOUT
D<7:5> = 101
Moves rising edge
by +(4/26)Ts
CLKOUT
CLKOUT
–(7/26)Ts
–(4/26)Ts
D<4:2> = 000
Default position
of falling edge
+(4/26)Ts
D<7:5> = 110
Moves rising edge
by –(7/26)Ts
D<4:2> = 101
Moves falling edge
by +(4/26)Ts
–(7/26)Ts
D<7:5> = 111
Moves rising edge
by –(4/26)Ts
–(4/26)Ts
+(4/26)Ts
D<4:2> = 110
Moves falling edge
by –(7/26)Ts
D<4:2> = 111
Moves falling edge
by –(4/26)Ts
Sampling Time Period Ts
T0491-01
(1) Keep the same duty cycle, move both edges by same amount (for instance, write both D[4:2] and D[7:5] to be the same value).
(2) Refer to the Timing Requirements table for default output clock position.
Figure 39. CMOS Interface Output Clock Edge Movement (Serial Register 44h)
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Table 18. Register 50h
D7
D6
D5
D4
D3
0
ENABLE INDIVIDUAL CHANNEL CONTROL
0
0
0
Bit D7
Always write '0'
Bit D6
ENABLE INDIVIDUAL CHANNEL CONTROL
D2
D1
D0
DATA FORMAT
0
0 = Common control: both channels use common control settings for test patterns, offset correction, fine gain, and
gain correction. These settings can be specified in a single set of registers.
1 = Independent control: both channels can be programmed with independent control settings for test patterns, and
offset correction. Separate registers are available for each channel.
Bits D[2:1]
DATA FORMAT: Twos complement or offset binary
10 = Twos complement
11 = Offset binary
Bit D0
Always write '0'
Table 19. Register 51h
D7
D6
D5
D4
D3
CUSTOM PATTERN LOW
Bits D[7:3]
D2
D1
D0
0
0
0
D1
D0
CUSTOM PATTERN LOW
Five lower custom pattern bits are available at the output instead of ADC data.
Bits D[2:0]
Always write '0'
Table 20. Register 52h
D7
D6
0
0
D5
D4
D3
D2
CUSTOM PATTERN HIGH
Bits D[7:6]
Always write '0'
Bits D[5:0]
CUSTOM PATTERN HIGH
Six upper custom pattern bits are available at the output instead of ADC data.
Use this mode with the TEST PATTERNS register bits (register 62h).
Table 21. Register 53h
D7
D6
D5
D4
D3
D2
D1
D0
0
ENABLE OFFSET CORRECTION, CH A
0
0
0
0
0
0
Bit D7
Always write '0'
Bit D6
ENABLE OFFSET CORRECTION: Common, channel A, offset correction enable
Offset correction enable control for both channels (with common control) or for channel A only (with independent
control).
0 = Offset correction disabled
1 = Offset correction enabled
Bits D[5:0]
36
Always write '0'
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Table 22. Register 55h
D7
D6
D5
D4
D3
GAIN PROGRAMMABILITY, CH A
Bits D[7:4]
D2
D1
D0
OFFSET CORRECTION TIME CONSTANT, CH A
GAIN PROGRAMMABILITY, CH A: Common, channel A
Gain control for both channels (with common control) or for channel A only (with independent control).
0000 = 0-dB gain (default after reset)
0001 = 0.5-dB gain
0010 = 1.0-dB gain
0011 = 1.5-dB gain
0100 = 2.0-dB gain
0101 = 2.5-dB gain
0110 = 3.0-dB gain
0111 = 3.5-dB gain
1000 = 4.0-dB gain
1001 = 4.5-dB gain
1010 = 5.0-dB gain
1011 = 5.5-dB gain
1100 = 6.0-dB gain
Bits D[3:0]
OFFSET CORRECTION TIME CONSTANT, CH A: Common, channel A, offset correction time constant
Correction loop time constant in number of clock cycles.
Applies to both channels (with common control) or for channel A only (with independent control).
0000 = 256 k
0001 = 512 k
0010 = 1 M
0011 = 2 M
0100 = 4 M
0101 = 8 M
0110 = 16 M
0111 = 32 M
1000 = 64 M
1001 = 128 M
1010 = 256 M
1011 = 512 M
Table 23. Register 57h
D7
D6
D5
0
D4
D3
D2
D1
D0
FINE GAIN ADJUST, CH A
Bit D7
Always write '0'
Bits D[6:0]
FINE GAIN ADJUST, CH A: Common, channel A (+0.001 dB to +0.134 dB, in 128 steps)
Using the FINE GAIN ADJUST register bits, the channel gain can be trimmed in fine steps. The trim is only
additive, and has 128 steps and a range of 0.134 dB. The relationship between the FINE GAIN ADJUST bits and
the trimmed channel gain is:
Δ channel gain = 20 × log10[1 + (FINE GAIN ADJUST / 1024)]
Note that the total device gain = ADC gain + Δ channel gain. ADC gain is determined by the GAIN
PROGRAMMABILITY register bits.
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Table 24. Register 62h
D7
D6
D5
D4
D3
0
0
0
0
0
Bits D[2:0]
D2
D1
D0
TEST PATTERNS, CH A
TEST PATTERNS, CH A: Test Patterns to verify data capture
Applies to both channels (with common control) or for channel A only with independent control. Note that in LVDS
mode, the test pattens come out as 12-bit data with the LSB (the dummy bit) coming out at the output clock rising
edge. The analog path, however, gives out only 11-bit data where the dummy bit is always '0'. While capturing, the
dummy bit can always be ignored and the remaining 11 bits should be processed.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern; see Figure 40 and Figure 41 for LVDS and CMOS mode test pattern timing diagrams.
Output data D[10:0] alternates between 01010101010 and 10101010101 every clock cycle.
100 = Outputs digital ramp
Output data increments by one LSB (11-bit) every eighth clock cycle from code 0 to code 2047.
101 = Outputs custom pattern (use registers 51h and 52h for setting the custom pattern); see Figure 43 for an
example of a custom pattern.
110 = Unused
111 = Unused
CLKOUTM
CLKOUTP
1
(D0)
1
0
0
1
1
0
0
(D1)
1
(D2)
1
0
0
1
1
0
DA8, DB8
0
(D7)
1
(D8)
1
0
0
1
1
0
DA10, DB10
0
(D9)
1
(D10)
1
0
0
1
1
0
DA0, DB0
0
DA2, DB2
(1)
•
•
•
•
•
•
Sample N
Sample N+1
Sample N+2
Sample N+3
(1) This bit is the dummy bit.
NOTE: Even bits output at the CLKOUTP rising edge and odd bits output at the CLKOUTP falling edge.
NOTE: Output toggles at half the sampling rate (fS / 2) in this test mode.
Figure 40. Output Toggle Pattern (Serial Register 62h, D[2:0] = 011) in LVDS Mode
38
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CLKOUT
DA0, DB0
1
0
1
0
DA1, DB1
0
1
0
1
DA9, DB9
1
0
1
0
DA10, DB10
0
1
0
1
Sample N
Sample N+1
Sample N+2
Sample N+3
•
•
•
•
•
•
NOTE: Output toggles at half the sampling rate (fS / 2) in this test mode.
Figure 41. Output Toggle Pattern (Serial Register 62h, D[2:0] = 011) in CMOS Mode
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Figure 42. Example: Register 51h = A1h and Register 52h = 2Ah to Toggle Output at fS
CLKOUTM
CLKOUTP
1
(D0)
0
1
0
1
0
1
0
(D1)
1
(D2)
0
1
0
1
0
1
DA8, DB8
0
(D7)
1
(D8)
0
1
0
1
0
1
DA10, DB10
0
(D9)
1
(D10)
0
1
0
1
0
1
DA0, DB0
0
DA2, DB2
(1)
•
•
•
•
•
•
Sample N
Sample N+1
Sample N+2
Sample N+3
(1) This bit is the dummy bit.
NOTE: Even bits output at the CLKOUTP rising edge, and odd bits output at the CLKOUTP falling edge.
NOTE: Output toggles at the sampling rate (fS) in this test mode.
Figure 43. Output Custom Pattern (Serial Register 62h, D[2:0] = 101) in LVDS Mode
Table 25. Register 63h
D7
D6
0
0
D5
D4
D3
OFFSET PEDESTAL, CH A
Bits D[7:6]
Always write '0'
Bits D[5:3]
OFFSET PEDESTAL, CH A: Common, channel A
D2
D1
D0
0
0
0
When the offset correction is enabled, the final converged value (after the offset is corrected) is the ideal ADC midcode value of 1024. A pedestal can be added to the final converged value by programming these bits. Thus, the
final converged value is = ideal mid-code + PEDESTAL.
See the Offset Correction section in the Application Information.
Applies to both channels (with common control) or for channel A only (with independent control).
011 = PEDESTAL is 3 LSB
010 = PEDESTAL is 2 LSB
001 = PEDESTAL is 1 LSB
000 = PEDESTAL is 0 LSB
111 = PEDESTAL is –1 LSB
110 = PEDESTAL is –2 LSB
101 = PEDESTAL is –3 LSB
100 = PEDESTAL is –4 LSB
Bits D[2:0]
40
Always write '0'
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Table 26. Register 66h
D7
D6
D5
D4
D3
D2
D1
D0
0
ENABLE OFFSET CORRECTION, CH B
0
0
0
0
0
0
Bit D7
Always write '0'
Bit D6
ENABLE OFFSET CORRECTION, CH B: Offset correction enable
Offset correction enable control for channel B (only with independent control).
0 = Offset correction disabled
1 = Offset correction enabled
Bits D[5:0]
Always write '0'
Table 27. Register 68h
D7
D6
D5
D4
GAIN PROGRAMMABILITY, CH B
Bits D[7:4]
D3
D2
D1
D0
OFFSET CORRECTION TIME CONSTANT, CH B
GAIN PROGRAMMABILITY, CH B: Gain programmability to 0.5-dB steps
Applies to channel B (only with independent control).
0000 = 0-dB gain (default after reset)
0001 = 0.5-dB gain
0010 = 1.0-dB gain
0011 = 1.5-dB gain
0100 = 2.0-dB gain
0101 = 2.5-dB gain
0110 = 3.0-dB gain
0111 = 3.5-dB gain
1000 = 4.0-dB gain
1001 = 4.5-dB gain
1010 = 5.0-dB gain
1011 = 5.5-dB gain
1100 = 6.0-dB gain
Bits D[3:0]
OFFSET CORRECTION TIME CONSTANT, CH B: Correction loop time constant in number of clock cycles.
Applies to channel B (only with independent control)
0000 = 256 k
0001 = 512 k
0010 = 1 M
0011 = 2 M
0100 = 4 M
0101 = 8 M
0110 = 16 M
0111 = 32 M
1000 = 64 M
1001 = 128 M
1010 = 256 M
1011 = 512 M
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Table 28. Register 6Ah
D7
D6
D5
D4
D3
D2
D1
D0
FINE GAIN ADJUST, CH B
Bits D[7:0]
FINE GAIN ADJUST, CH B: +0.001 dB to +0.134 dB, in 128 steps
Using the FINE GAIN ADJUST register bits, the channel gain can be trimmed in fine steps. The trim is only
additive, and has 128 steps and a range of 0.134 dB. The relationship between the FINE GAIN ADJUST bits and
the trimmed channel gain is:
Δ channel gain = 20 × log10[1 + (FINE GAIN ADJUST / 1024)]
Note that the total device gain = ADC gain + Δ channel gain. The ADC gain is determined by the GAIN
PROGRAMMABILITY register bits.
Table 29. Register 75h
D7
D6
D5
D4
D3
0
0
0
0
0
Bits D[7:3]
Always write '0'
Bits D[2:0]
TEST PATTERNS, CH B: Test patterns to verify data capture
D2
D1
D0
TEST PATTERNS, CH B
Applies to channel B only with independent control. Note that in LVDS mode, the test pattens come out as 12-bit
data with the LSB (the dummy bit) coming out at the output clock rising edge. The analog path, however, gives out
only 11-bit data where the dummy bit is always '0'. While capturing, the dummy bit can always be ignored and the
remaining 11 bits should be processed.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern; see Figure 40 and Figure 41 for LVDS and CMOS modes.
Output data D[10:0] alternates between 01010101010 and 10101010101 every clock cycle.
100 = Outputs digital ramp
Output data increments by one LSB (11-bit) every eighth clock cycle from code 0 to code 2047.
101 = Outputs custom pattern (use registers 51 and 52 for setting the custom pattern); see Figure 43 for an
example of a custom pattern.
110 = Unused
111 = Unused
42
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Table 30. Register 76h
D7
D6
0
0
D5
D4
D3
OFFSET PEDESTAL, CH B
Bits D[7:6]
Always write '0'
Bits D[5:3]
OFFSET PEDESTAL, CH B: Common, channel B
D2
D1
D0
0
0
0
When the offset correction is enabled, the final converged value (after the offset is corrected) is the ideal ADC midcode value of 1024. A pedestal can be added to the final converged value by programming these bits. Thus, the
final converged value is = ideal mid-code + PEDESTAL. See the Offset Correction section in the Application
Information.
Applies to channel B (only with independent control).
011 = PEDESTAL is 3 LSB
010 = PEDESTAL is 2 LSB
001 = PEDESTAL is 1 LSB
000 = PEDESTAL is 0 LSB
111 = PEDESTAL is –1 LSB
110 = PEDESTAL is –2 LSB
101 = PEDESTAL is –3 LSB
100 = PEDESTAL is –4 LSB
Bits D[2:0]
Always write '0'
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS62P19 is a high-performance, low-power, dual-channel, 11-bit analog-to-digital converter (ADC) with
sampling rates up to 250 MSPS. At every input clock falling edge, the analog input signal of each channel is
sampled simultaneously. The sampled signal in each channel is converted by a pipeline of low-resolution stages.
In each stage, the sampled and held signal is converted by a high-speed, low-resolution, flash sub-ADC. The
difference (residue) between the stage input and the quantized equivalent is gained and propagates to the next
stage.
At every clock, each succeeding stage resolves the sampled input with greater accuracy. The digital outputs from
all stages are combined in a digital correction logic block and are processed digitally to create the final code,
after a data latency of 22 clock cycles. The digital output is available as either DDR LVDS or parallel CMOS and
is coded in either straight offset binary or binary twos complement format. The dynamic offset of the first stage
sub-ADC limits the maximum analog input frequency to approximately 500 MHz (with 2-VPP amplitude) and
approximately 800 MHz (with 1-VPP amplitude).
ANALOG INPUT
The analog input consists of a switched-capacitor-based differential sample-and-hold architecture, as shown in
Figure 44. This differential topology results in very good ac performance, even for high input frequencies at high
sampling rates. The INP and INM pins must be externally biased around a common-mode voltage of 1.5 V,
available on the VCM pin. For a full-scale differential input, each input pin (INP, INM) must swing symmetrically
between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The input sampling circuit
has a high 3-dB bandwidth that extends up to 700 MHz (measured from the input pins to the sampled voltage).
Sampling
Switch
Sampling
Capacitor
RCR Filter
Lpkg » 1 nH
10 W
INP
Cbond
» 1 pF
Resr
200 W
Cpar2
0.5 pF
100 W
Ron
15 W
Csamp
2 pF
3 pF
Cpar1
0.25 pF
Ron
10 W
3 pF
100 W
Lpkg » 1 nH
Ron
15 W
10 W
Csamp
2 pF
INM
Cbond
» 1 pF
Sampling
Capacitor
Cpar2
0.5 pF
Resr
200 W
Sampling
Switch
S0322-03
Figure 44. Analog Input Circuit
44
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Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This configuration improves the
common-mode noise immunity and even-order harmonic rejection. A 5-Ω to 15-Ω resistor in series with each
input pin is recommended to damp out ringing caused by package parasitic.
SFDR performance can be limited because of several reasons: the effect of sampling glitches (as described in
this section), nonlinearity of the sampling circuit, and nonlinearity of the quantizer that follows the sampling
circuit. Depending on the input frequency, sample rate, and input amplitude, one of these restrictions plays a
dominant part in limiting performance.
At very high input frequencies (greater than approximately 300 MHz), SFDR is determined largely by the device
sampling circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity usually limits performance.
Glitches are caused by the opening and closing of the sampling switches. The driving circuit should present a
low source impedance to absorb these glitches. Otherwise, these glitches might limit performance, mainly at low
input frequencies (up to approximately 200 MHz). Low impedance (less than 50 Ω) must also be presented for
the common-mode switching currents. This impedance can be achieved by using two resistors from each input
terminated to the common-mode voltage (VCM).
The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the
sampling glitches inside the device itself. The cutoff frequency of the R-C filter involves a trade-off. A lower cutoff
frequency (larger C) absorbs glitches better, but reduces the input bandwidth. On the other hand, with a higher
cutoff frequency (smaller C), bandwidth support is maximized. However, the sampling glitches must be supplied
by the external drive circuit. This configuration has limitations because of the presence of the package bond-wire
inductance.
In the ADS62P19, the R-C component values have been optimized while supporting high input bandwidth (up to
700 MHz). However, in applications with input frequencies up to 200 MHZ to 300 MHz, the filtering of the glitches
can be improved further using an external R-C-R filter (see Figure 47 and Figure 48).
In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency
range and matched impedance to the source. During this process, ADC input impedance must be considered.
Figure 45 and Figure 46 show the impedance (ZIN = RIN || CIN) at the ADC input pins.
100
4.5
4.0
C − Capacitance − pF
R - Resistance - kW
10
1
0.10
3.5
3.0
2.5
2.0
1.5
0.01
0
100 200
300 400
500 600
700 800
900 1000
f - Frequency - MHz
1.0
0
Figure 45. ADC Analog Input Resistance (RIN)
Across Frequency
100 200 300 400 500 600 700 800 900 1000
f − Frequency − MHz
G075
Figure 46. ADC Analog Input Capacitance (CIN)
Across Frequency
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Driving Circuit
Two example driving circuit configurations are shown in Figure 47 and Figure 48, one optimized for low
bandwidth (low input frequencies) and the other one for high bandwidth to support higher input frequencies. In
Figure 47, an external R-C-R filter using 22 pF is used. Together with the series inductor (39 nH), this
combination forms a filter and absorbs the sampling glitches. Because of the large capacitor (22 pF) in the R-C-R
and the 15-Ω resistors in series with each input pin, the drive circuit has low bandwidth and supports low input
frequencies (< 100 MHz).
To support higher input frequencies (up to approximately 300 MHz, as shown in Figure 48), the capacitance used
in the R-C-R is reduced to 3.3 pF and the series inductors are shorted out. Together with the lower series
resistors (5 Ω), this drive circuit provides high bandwidth and supports high input frequencies. Transformers such
as ADT1-1WT or ETC1-1-13 can be used up to 300 MHz.
39 nH
0.1 mF
0.1 mF
15 W
INP
50 W
50 W
25 W
0.1 mF 0.1 mF
0.1 mF
0.1 mF
22 pF
50 W
25 W
50 W
INM
1:1
1:1
15 W
0.1 mF
VCM
39 nH
S0396-01
Figure 47. Drive Circuit With Low Bandwidth (for Low Input Frequencies)
0.1 mF
0.1 mF
5W
INP
50 W
25 W
0.1 mF 0.1 mF
0.1 mF
0.1 mF
3.3 pF
50 W
25 W
INM
1:1
1:1
0.1 mF
5W
VCM
S0397-01
Figure 48. Drive Circuit With High Bandwidth (for High Input Frequencies)
46
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Without the external R-C-R filter, the drive circuit has very high bandwidth and can support very high input
frequencies (> 300 MHz). For example, a transmission line transformer such as ADTL2-18 can be used, as
shown in Figure 49. Note that both drive circuits are terminated by 50 Ω near the ADC side. The termination is
accomplished by a 25-Ω resistor from each input to the 1.5-V common-mode (VCM) from the device. This
configuration allows the analog inputs to be biased around the required common-mode voltage.
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and
good performance is obtained for high-frequency input signals. An additional termination resistor pair may be
required between the two transformers, as described in Figure 47, Figure 48, and Figure 49. The center point of
this termination is connected to ground to improve the balance between the P and M side. The values of the
terminations between the transformers and on the secondary side must be chosen to obtain an effective 50 Ω (in
the case of a 50-Ω source impedance).
0.1mF
INP
0.1mF
25 W
25 W
T1
T2
INM
0.1mF
VCM
Figure 49. Drive Circuit with Very High Bandwidth (> 300 MHz)
These examples show 1:1 transformers used with a 50-Ω source. As explained in the Drive Circuit Requirements
section, this structure helps present a low source impedance to absorb the sampling glitches. With a 1:4
transformer, the source impedance is 200 Ω. The higher impedance can lead to degradation in performance,
compared to the case with 1:1 transformers.
For applications where only a band of frequencies are used, the drive circuit can be tuned to present a low
impedance for the sampling glitches. Figure 50 shows an example with 1:4 transformer, tuned for a band at
approximately 150 MHz.
5W
INP
0.1mF
0.1mF
25 W
100 W
Differential
input signal
72 nH
15 pF
100 W
25 W
INM
1:4
5W
VCM
Figure 50. Drive Circuit with a 1:4 Transformer
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Input Common-Mode
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-μF low-inductance capacitor
connected to ground. The VCM pin is designed to directly drive the ADC inputs. The ADC input stage sinks a
common-mode current in the order of 3.6 μA per MSPS (approximately 900 μA at 250 MSPS).
REFERENCE
The ADS62P19 has built-in internal references (REFP and REFM) that require no external components. Design
schemes are used to linearize the converter load detected by the references; this functionality and the on-chip
integration of the requisite reference capacitors eliminates the need for external decoupling. The full-scale input
range of the converter can be controlled in the external reference mode as explained in Figure 51. The internal or
external reference modes can be selected by programming the REF serial interface register bit.
INTREF
Internal
Reference
VCM
INTREF
EXTREF
REFM
REFP
S0165-09
Figure 51. Reference Section
Internal Reference
When the device is in internal reference mode, the REFP and REFM voltages are generated internally. The
common-mode voltage (1.5 V, nominal) is output on the VCM pin, which can be used to externally bias the
analog input pins.
External Reference
When the device is in external reference mode, the VCM functions as a reference input pin. The voltage forced
on the VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The
differential input voltage corresponding to full-scale is given by the following:
Full-scale differential input peak-to-peak = (voltage forced on VCM) × 1.33
In this mode, the 1.5-V common-mode voltage to bias the input pins must be generated externally.
48
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CLOCK INPUT
The ADS62P19 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
VCM using internal 5-kΩ resistors, as shown in Figure 52. This configuration allows using transformer-coupled
drive circuits for sine-wave clock or ac-coupling for LVPECL and LVDS clock sources (Figure 53, Figure 54, and
Figure 55).
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin 11) connected to ground with
a 0.1-μF capacitor; see Figure 56. For best performance, the clock inputs must be driven differentially, thus
reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock
source with very low jitter. Bandpass filtering of the clock source can help reduce the effect of jitter. There is no
change in performance with a non-50% duty cycle clock input.
Clock Buffer
Lpkg
» 2 nH
20 W
CLKP
Cbond
» 1 pF
Ceq
Resr
» 100 W
Ceq
5 kW
VCM
2 pF
5 kW
Lpkg
» 2 nH
20 W
CLKM
Cbond
» 1 pF
Resr
» 100 W
Ceq » 1 to 3 pF, Equivalent Input Capacitance of Clock Buffer
S0275-04
Figure 52. Internal Clock Buffer
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0.1mF
0.1mF
Zo
CLKP
CLKP
Differential Sine-wave
Clock Input
Typical LVDS
Clock Input
RT
100W
Zo
CLKM
CLKM
0.1mF
0.1mF
RT = termination resistor if necessary
Figure 53. Differential Sine-Wave Clock Driving
Circuit
Zo
Figure 54. Typical LVDS Clock Driving Circuit
0.1mF
0.1mF
CLKP
Typical LVPECL
Clock Input
150W
CLKP
CMOS Clock Input
100W
VCM
Zo
CLKM
CLKM
0.1mF
0.1mF
150W
Figure 55. Typical LVPECL Clock Driving Circuit
Figure 56. Typical LVCMOS Clock Driving Circuit
GAIN PROGRAMMABILITY
The ADS62P19 includes gain settings that can be used to obtain improved SFDR performance (compared to no
gain). Gain is programmable from 0 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input fullscale range scales proportionally, as shown in Table 31. SFDR improvement is achieved at the expense of SNR;
for each 1-dB gain step, SNR degrades by approximately 1 dB. SNR degradation is reduced at high input
frequencies. As a result, gain is very useful at high input frequencies because SFDR improvement is significant
with marginal degradation in SNR. Therefore, gain can be used to trade-off between SFDR and SNR. Note that
the default gain after reset is 0 dB.
Table 31. Full-Scale Range Across Gains
GAIN (dB)
50
DESCRIPTION
FULL-SCALE (VPP)
0
Default after reset
2
1
Fine, programmable
1.78
2
Fine, programmable
1.59
3
Fine, programmable
1.42
4
Fine, programmable
1.26
5
Fine, programmable
1.12
6
Fine, programmable
1.00
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OFFSET CORRECTION
The ADS62P19 has an internal offset correction algorithm that estimates and corrects dc offset up to ±10 mV.
The correction can be enabled with the ENABLE OFFSET CORRECTION serial register bit. When enabled, the
algorithm estimates the channel offset and applies the correction every clock cycle. The correction loop time
constant is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET
CORR TIME CONSTANT register bits, as described in Table 32.
After the offset is estimated, the correction can be frozen by setting ENABLE OFFSET CORRECTION back to
'0'. When frozen, the last estimated value is used for offset correction every clock cycle. The correction does not
affect the phase of the signal. Note that offset correction is disabled by default after reset.
Table 32. Time Constant of Offset Correction Algorithm
(1)
OFFSET CORR TIME CONSTANT
(D[3:0])
TIME CONSTANT
(TCCLK, NUMBER OF CLOCK CYCLES)
TIME CONSTANT
(Seconds, Equal to TCCLK × 1 / fS)
0000
256 k
1 ms
0001
512 k
2 ms
0010
1M
4 ms
0011
2M
8 ms
0100
4M
17 ms
0101
8M
33 ms
0110
16 M
67 ms
0111
32 M
134 ms
1000
64 M
268 ms
1001
128 M
536 ms
1010
256 M
1.1 s
1011
512 M
2.2 s
1100
Reserved
—
1101
Reserved
—
1110
Reserved
—
1111
Reserved
—
(1)
Sampling frequency, fS = 250 MSPS.
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POWER DOWN
The ADS62P19 has two power-down modes: global power down and individual channel standby. These modes
can be set using either the serial register bits or the control pins (CTRL1 to CTRL3). Table 33 describes the
power-down modes.
Table 33. Need Title
CONFIGURE WITH
POWER-DOWN MODES
SERIAL INTERFACE
PARALLEL
CONTROL PINS
Normal operation
POWER DOWN MODES = 0000
Output buffer disabled for channel B
POWER DOWN MODES = 1001
Not Available
—
Output buffer disabled for channel A
POWER DOWN MODES = 1010
Not Available
—
Output buffer disabled for channel A and B
POWER DOWN MODES = 1011
Not Available
Global power-down
POWER DOWN MODES = 1100
High
Channel B standby
POWER DOWN MODES = 1101
Channel A standby
POWER DOWN MODES = 1110
Multiplexed (MUX) mode; output data of channel A
and B are multiplexed and available on the DA[10:0] POWER DOWN MODES = 1111
pins. (1)
(1)
Low
Low
Low
WAKE-UP
TIME
—
—
Low
Low
Slow (30 μs)
High
Low
High
Fast (1 μs)
High
High
Low
Fast (1 μs)
High
High
High
—
Low-speed mode must be enabled for the multiplexed output mode (MUX mode). Therefore, MUX mode only functions with the serial
interface configuration and is not supported with the parallel configuration.
Global Power Down
In this mode, the entire chip (including both ADCs, internal reference, and output buffers) is powered down,
resulting in a reduced total power dissipation of approximately 45 mW. The output buffers are in high-impedance
state. The wake-up time from the global power-down to data becoming valid in normal mode is typically 30 μs.
Channel Standby
In this mode, the ADC for each channel can be powered down. The internal references are active, resulting in a
quick wake-up time of 1 μs. The total power dissipation in standby is approximately 475 mW.
Input Clock Stop
In addition, the converter enters a low-power mode when the input clock frequency falls below 1 MSPS. The
power is approximately 275 mW.
POWER-SUPPLY SEQUENCE
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated in the device. Externally, they can be driven from separate supplies or from a single supply.
DIGITAL OUTPUT INFORMATION
The ADS62P19 provides 11-bit data and an output clock synchronized with the data.
Output Interface
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. These options can
be selected using the LVDS_CMOS serial interface register bit or using the DFS pin in parallel configuration
mode.
52
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DDR LVDS Outputs
In this mode, the data bits and clock are output using low-voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair, as shown in Figure 57.
CLKOUTP
Output Clock
CLKOUTM
DB0_P
DB0_M
Data Bit D0
DB2_P
DB2_M
Data Bits D1, D2
DB4_P
DB4_M
11-Bit ADC Data,
Channel B
Data Bits D3, D4
DB6_P
DB6_M
Data Bits D5, D6
DB8_P
DB8_M
Data Bits D7, D8
DB10_P
DB10_M
Device
Data Bits D9, D10
LVDS Buffers
Figure 57. LVDS Outputs
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Even data bits (D0, D2, D4, and so forth) are output at the CLKOUTP rising edge and the odd data bits (D1, D3,
D5, and so forth) are output at the CLKOUTP falling edge. Both the CLKOUTP rising and falling edges must be
used to capture all the data bits (see Figure 58).
CLKOUTM
CLKOUTP
DA0, DB0
DA2, DB2
DA4, DB4
(1)
D0
0
D0
D1
D2
D1
D2
D3
D4
D3
D4
D5
D6
D5
D6
D7
D8
D7
D8
D9
D10
D9
D10
0
DA6, DB6
DA8, DB8
DA10, DB10
Sample N
SAMPLE N
Sample N+1
SAMPLE N+1
(1) Bit 0 is the dummy bit.
Figure 58. DDR LVDS Interface
54
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LVDS Buffer
The equivalent circuit of each LVDS output buffer is shown in Figure 59. The buffer is designed to present an
output impedance of 100 Ω (ROUT). The differential outputs can be terminated at the receive end by a 100-Ω
termination.
The buffer output impedance behaves like a source-side series termination. By absorbing reflections from the
receiver end, the buffer output impedance helps improve signal integrity. Note that this internal termination
cannot be disabled and its value cannot be changed.
–
Low
+
0.35 V
High
Device
OUTP
+
–
+
–0.35 V
–
High
1.2 V
Low
External
100-W Load
Rout
OUTM
Switch impedance is
nominally 50 W (±10%).
NOTE: When the high switches are closed, OUTP = 1.375 V and OUTM = 1.025 V. When the low switches are closed, OUTP = 1.025 V and
OUTM = 1.375 V. When either high or low switches are closed, ROUT = 100 Ω.
Figure 59. LVDS Buffer Equivalent Circuit
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Parallel CMOS Interface
In CMOS mode, each data bit is output on a separate pin as a CMOS voltage level for every clock cycle, as
shown in Figure 60. This mode is recommended only up to 210 MSPS, beyond which the CMOS data outputs do
not have sufficient time to settle to valid logic levels.
For sampling frequencies up to 150 MSPS, the output clock (CLKOUT) rising edge can be used to latch data in
the receiver. The output data setup and hold times (with respect to CLKOUT) are specified in the Timing
Requirements table up to 150 MSPS.
For sampling frequencies above 150 MSPS, TI recommends using an external clock to capture data. The delay
from the input clock to output data and the data valid times are specified up to 210 MSPS. These timings can be
used to delay the input clock appropriately and use it to capture data. When using the CMOS interface, the load
capacitance detected by the data and clock output pins must be minimized by using short traces on the board.
Pins
DB0
DB1
DB2
DB8
11 bit ADC data
Channel B
DB9
DB10
SDOUT
CLKOUT
DA0
DA1
DA2
DA8
11 bit ADC data
Channel A
DA9
DA10
Figure 60. CMOS Outputs
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CMOS Interface Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. Maximum DRVDD current occurs when each output bit toggles between '0' and '1' every clock cycle.
In actual applications, this condition is unlikely to occur. Actual DRVDD current is determined by the average
number of output bits switching, which is a function of the sampling frequency and the nature of the analog input
signal.
Digital current resulting from CMOS output switching = CL × DRVDD × (N × fAVG),
Where:
CL = load capacitance,
N × fAVG = average number of output bits switching.
Refer to Figure 31 for a plot of the current with various load capacitances across sampling frequencies at 2.5MHz analog input frequency.
Multiplexed Output Mode (Only with CMOS Interface)
In this mode, the digital outputs of both channels are multiplexed and output on a single bus (pins DA[10:0]).
Channel B data bits are output at the CLKOUT rising edge, and channel A data bits are output at the CLKOUT
falling edge. Channel B output data pins (DB[10:0]) are 3-stated; refer to Figure 61 for details. Because the
output data rate on the DA bus is effectively doubled, this mode is recommended only for low sampling
frequencies (less than 65 MSPS).
Low-speed mode must be enabled for the multiplexed output mode (MUX mode). Therefore, MUX mode only
functions with the serial interface configuration and is not supported with the parallel configuration. This mode
can be enabled with the POWER DOWN MODES register bits or the parallel pins (CTRL1 to CTRL3).
CLKOUT
DA0
DB0
DA0
DB0
DA0
DA1
DB1
DA1
DB1
DA1
DA2
DB2
DA2
DB2
DA2
DB10
DA10
DB10
DA10
•
•
•
•
•
•
DA10
Sample N
Sample N+1
(1) Both channel outputs are output on the channel A output data lines.
(2) Channel A outputs are output on the output clock falling edges, whereas channel B outputs are output on the output clock rising edges.
Figure 61. Multiplexed Output Mode Timing
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Output Data Format
Two output data formats are supported: twos complement and offset binary. These modes can be selected using
the DATA FORMAT serial interface register bit or by controlling the DFS pin in parallel configuration mode.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive
overdrive, the output code is 7FFh in offset binary output format, and 3FFh in twos complement output format.
For a negative input overdrive, the output code is 000h in offset binary output format and 400h in twos
complement output format.
BOARD DESIGN CONSIDERATIONS
Grounding: A single ground plane is sufficient to provide good performance, provided the analog, digital, and
clock sections of the board are cleanly partitioned. See the ADS62PXX EVM User's Guide (SLAU237) for details
on layout and grounding.
Supply Decoupling: Because the ADS62P19 already includes internal decoupling, minimal external decoupling
can be used without loss in performance. Note that decoupling capacitors can help filter external power-supply
noise, thus the optimum number of capacitors depends on the actual application. The decoupling capacitors
should be placed very close to the converter supply pins.
Exposed Pad: In addition to providing a path for heat dissipation, the pad is also internally electrically connected
to the digital ground. Therefore, the exposed pad must be soldered to the ground plane for best thermal and
electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and
QFN/SON PCB Attachment (SLUA271).
58
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth: The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low-frequency value.
Aperture Delay: The delay in time between the input sampling clock rising edge and the actual time at which the
sampling occurs. This delay is different across channels. The maximum variation is specified as aperture delay
variation (channel-to-channel).
Aperture Uncertainty (Jitter): The sample-to-sample variation in aperture delay.
Clock Pulse Duration and Duty Cycle: The duty cycle of a clock signal is the ratio of the time the clock signal
remains at a logic high (clock pulse duration) to the period of the clock signal. Duty cycle is typically expressed
as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate: The maximum sampling rate at which certified operation is given. All parametric
testing is performed at this sampling rate, unless otherwise noted.
Minimum Conversion Rate:The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL): An ideal ADC exhibits code transitions at analog input values spaced exactly 1
LSB apart. DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL): INL is the deviation of the ADC transfer function from a best-fit line determined by a
least-squares-curve fit of that transfer function, measured in units of LSBs.
Gain Error: Gain error is the deviation of the ADC actual input full-scale range from its ideal value. Gain error is
given as a percentage of the ideal input full-scale range. Gain error has two components: error resulting from
reference inaccuracy and error resulting from the channel. Both errors are specified independently as EGREF and
EGCHAN, respectively.
To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN.
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5 / 100) × FSideal to (1 + 0.5 / 100) × FSideal.
Offset Error: Offset error is the difference, given in number of LSBs, between the ADC actual average idle
channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.
Temperature Drift: The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. Temperature drift is calculated by dividing the
maximum deviation of the parameter across the TMIN to TMAX range by the difference of TMAX – TMIN.
Signal-to-Noise Ratio (SNR): SNR is the ratio of the power of the fundamental (PS) to the noise floor power
(PN), excluding the power at dc and the first nine harmonics.
SNR = 10Log10
PS
PN
(1)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter fullscale range.
Signal-to-Noise and Distortion (SINAD): SINAD is the ratio of the power of the fundamental (PS) to the power
of all other spectral components, including noise (PN) and distortion (PD), but excluding dc.
SINAD = 10Log10
PS
PN + PD
(2)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter fullscale range.
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Effective Number of Bits (ENOB): ENOB is a measure of the converter performance as compared to the
theoretical limit based on quantization noise.
ENOB =
SINAD - 1.76
6.02
(3)
Total Harmonic Distortion (THD): THD is the ratio of the power of the fundamental (PS) to the power of the first
nine harmonics (PD).
THD = 10Log10
PS
PN
(4)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR): SFDR is the ratio of the power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion (IMD3): IMD3 is the ratio of the power of the fundamental (at frequencies
f1 and f2) to the power of the worst spectral component at either frequency (2f1 – f2) or (2f2 – f1). IMD3 is either
given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or
dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
DC Power-Supply Rejection Ratio (DC PSRR): DC PSSR is the ratio of the change in offset error to a change
in analog supply voltage. DC PSRR is typically given in units of millivolts per volt.
AC Power-Supply Rejection Ratio (AC PSRR): AC PSRR is the measure of rejection of variations in the supply
voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the ADC
output code (referred to the input), then:
DVOUT
PSRR = 20Log 10
(Expressed in dBc)
DVSUP
(5)
Voltage Overload Recovery: The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This overload recovery is tested by separately applying a sine-wave signal with a
6-dB positive and negative overload. The deviation of the first few samples after the overload (from the expected
values) is noted.
Common-Mode Rejection Ratio (CMRR): CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is
the resultant change of the ADC output code (referred to the input), then:
DVOUT
CMRR = 20Log10
(Expressed in dBc)
DVCM
(6)
Crosstalk (only for multichannel ADCs): Crosstalk is a measure of the internal coupling of a signal from an
adjacent channel into the channel of interest. Crosstalk is specified separately for coupling from the immediate
neighboring channel (near-channel) and for coupling from a channel across the package (far-channel). Crosstalk
is usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of
the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the
adjacent channel input. Crosstalk is typically expressed in dBc (dB to carrier).
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PACKAGE OPTION ADDENDUM
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9-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
ADS62P19IRGCR
ACTIVE
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ62P19
ADS62P19IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ62P19
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS62P19IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
ADS62P19IRGCT
VQFN
RGC
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS62P19IRGCR
VQFN
RGC
64
2000
350.0
350.0
43.0
ADS62P19IRGCT
VQFN
RGC
64
250
213.0
191.0
55.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGC 64
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
9 x 9, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
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PACKAGE OUTLINE
RGC0064H
VQFN - 1 mm max height
SCALE 1.500
PLASTIC QUAD FLATPACK - NO LEAD
A
9.15
8.85
B
PIN 1 INDEX AREA
9.15
8.85
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2X 7.5
EXPOSED
THERMAL PAD
SYMM
(0.2) TYP
17
32
16
33
65
SYMM
2X 7.5
7.4 0.1
60X
0.5
1
48
49
64
PIN 1 ID
64X
0.5
0.3
64X
0.30
0.18
0.1
0.05
C A B
4219011/A 05/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGC0064H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 7.4)
SEE SOLDER MASK
DETAIL
SYMM
64X (0.6)
49
64
64X (0.24)
1
48
60X (0.5)
(3.45) TYP
(R0.05) TYP
(1.16) TYP
65
SYMM
(8.8)
( 0.2) TYP
VIA
33
16
32
17
(1.16) TYP
(3.45) TYP
(8.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK DEFINED
SOLDER MASK DETAILS
4219011/A 05/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGC0064H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
64X (0.6)
64X (0.24)
64
49
1
48
60X (0.5)
(R0.05) TYP
(1.16) TYP
65
SYMM
(8.8)
(0.58)
36X ( 0.96)
33
16
17
32
(0.58)
(1.16)
TYP
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
61% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219011/A 05/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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