Texas Instruments | DAC0830/DAC0832 8-Bit uP Compatible, Double-Buffered D to A Converters (Rev. B) | Datasheet | Texas Instruments DAC0830/DAC0832 8-Bit uP Compatible, Double-Buffered D to A Converters (Rev. B) Datasheet

Texas Instruments DAC0830/DAC0832 8-Bit uP Compatible, Double-Buffered D to A Converters (Rev. B) Datasheet
DAC0830, DAC0832
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SNAS534B – MAY 1999 – REVISED MARCH 2013
DAC0830/DAC0832 8-Bit μP Compatible, Double-Buffered D to A Converters
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FEATURES
KEY SPECIFICATIONS
• Double-Buffered, Single-Buffered or FlowThrough Digital Data Inputs
• Easy Interchange and Pin-Compatible with 12bit DAC1230 Series
• Direct Interface to All Popular
Microprocessors
• Linearity Specified with Zero and Full Scale
Adjust Only—NOT BEST STRAIGHT LINE FIT.
• Works with ±10V Reference-Full 4-Quadrant
Multiplication
• Can Be Used in the Voltage Switching Mode
• Logic Inputs Which Meet TTL Voltage Level
Specs (1.4V Logic Threshold)
• Operates “STAND ALONE” (without μP) if
Desired
• Available in 20-Pin SOIC or PLCC Package
•
•
•
1
234
•
•
•
Current Settling Time: 1 μs
Resolution: 8 bits
Linearity: 8, 9, or 10 bits (Ensured Over
Temp.)
Gain Tempco: 0.0002% FS/°C
Low Power Dissipation: 20 mW
Single Power Supply: 5 to 15 VDC
DESCRIPTION
The DAC0830 is an advanced CMOS/Si-Cr 8-bit
multiplying DAC designed to interface directly with the
8080, 8048, 8085, Z80®, and other popular
microprocessors. A deposited silicon-chromium R-2R
resistor ladder network divides the reference current
and provides the circuit with excellent temperature
tracking characteristics (0.05% of Full Scale Range
maximum linearity error over temperature). The circuit
uses CMOS current switches and control logic to
achieve low power consumption and low output
leakage current errors. Special circuitry provides TTL
logic input voltage level compatibility.
Double buffering allows these DACs to output a
voltage corresponding to one digital word while
holding the next digital word. This permits the
simultaneous updating of any number of DACs.
The DAC0830 series are the 8-bit members of a
family of microprocessor-compatible DACs (MICRODAC).
Typical Application
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
BI-FET is a trademark of Texas Instruments.
Z80 is a registered trademark of Zilog Corporation.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Connection Diagrams
(Top Views)
Figure 1. PDIP, CDIP, and SOIC Packages
Figure 2. PLCC Package
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2) (3)
Supply Voltage (VCC)
17 VDC
Voltage at Any Digital Input
VCC to GND
Voltage at VREF Input
Storage Temperature Range
±25V
−65°C to +150°C
Package Dissipation at
TA=25°C (4)
500 mW
DC Voltage Applied to
IOUT1 or IOUT2 (5)
−100 mV to VCC
ESD Susceptability (5) (6)
Lead
Temperature
(Soldering, 10
sec.)
(1)
(2)
(3)
(4)
(5)
(6)
2
800V
PDIP Package (plastic)
260°C
CDIP Package (ceramic)
300°C
SOIC Package
Vapor Phase (60 sec.)
215°C
Infrared (15 sec.)
220°C
All voltages are measured with respect to GND, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its specified operating conditions.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute
Maximum Ratings, whichever is lower. For this device, TJMAX = 125°C (plastic) or 150°C (ceramic), and the typical junction-to-ambient
thermal resistance of the J package when board mounted is 80°C/W. For the NFH package, this number increases to 100°C/W and for
the FN package this number is 120°C/W.
For current switching applications, both IOUT1 and IOUT2 must go to ground or the “Virtual Ground” of an operational amplifier. The
linearity error is degraded by approximately VOS ÷ VREF. For example, if VREF = 10V then a 1 mV offset, VOS, on IOUT1 or IOUT2 will
introduce an additional 0.01% linearity error.
Human body model, 100 pF discharged through a 1.5 kΩ resistor.
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Operating Conditions
TMIN≤TA≤TMAX
Temperature Range
Part numbers with “LCN” suffix
0°C to +70°C
Part numbers with “LCWM” suffix
0°C to +70°C
Part numbers with “LCV” suffix
0°C to +70°C
Part numbers with “LCJ” suffix
−40°C to +85°C
−55°C to +125°C
Part numbers with “LJ” suffix
Voltage at Any Digital Input
VCC to GND
Electrical Characteristics
VREF=10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMIN≤TA≤TMAX. (1) For all other limits
TA=25°C.
Parameter
Conditions
See
Note
VCC = 4.75 VDC
VCC = 15.75 VDC
VCC = 5 VDC ±5%
VCC = 12 VDC ±5%
to 15 VDC ±5%
Limit
Units (2)
Typ (3)
Tested
Limit (4)
Design
Limit (5)
8
8
8
bits
DAC0830LJ & LCJ
0.05
0.05
% FSR
DAC0832LJ & LCJ
0.2
0.2
% FSR
DAC0830LCN, LCWM &
LCV
0.05
0.05
% FSR
DAC0831LCN
0.1
0.1
% FSR
DAC0832LCN, LCWM &
LCV
0.2
0.2
% FSR
DAC0830LJ & LCJ
0.1
0.1
% FSR
DAC0832LJ & LCJ
0.4
0.4
% FSR
DAC0830LCN, LCWM &
LCV
0.1
0.1
% FSR
DAC0831LCN
0.2
0.2
% FSR
DAC0832LCN, LCWM &
LCV
0.4
0.4
% FSR
8
8
bits
CONVERTER CHARACTERISTICS
Resolution
Linearity Error Max
Differential Nonlinearity
Max
Zero and full scale adjusted
−10V≤VREF≤+10V
Zero and full scale adjusted
−10V≤VREF≤+10V
Monotonicity
−10V≤VREF
Gain Error Max
Using Internal Rfb
≤+10V
LJ & LCJ
See (6)
and (2)
See (6)
and (2)
See (6)
LCN, LCWM & LCV
See (7)
±0.2
8
8
bits
±1
±1
% FS
0.0006
%
FS/°C
−10V≤VREF≤+10V
Gain Error Tempco Max
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Using internal Rfb
0.0002
Boldface tested limits apply to the LJ and LCJ suffix parts only.
The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate
dependence on a particular VREF value and to indicate the true performance of the part. The “Linearity Error” specification of the
DAC0830 is “0.05% of FSR (MAX)”. This ensures that after performing a zero and full scale adjustment (see sections Zero Adjustment
and Full-Scale Adjustment), the plot of the 256 analog voltage outputs will each be within 0.05%×VREF of a straight line which passes
through zero and full scale.
Typicals are at 25°C and represent most likely parametric norm.
Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
Ensured, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
For current switching applications, both IOUT1 and IOUT2 must go to ground or the “Virtual Ground” of an operational amplifier. The
linearity error is degraded by approximately VOS ÷ VREF. For example, if VREF = 10V then a 1 mV offset, VOS, on IOUT1 or IOUT2 will
introduce an additional 0.01% linearity error.
Specified at VREF=±10 VDC and VREF=±1 VDC.
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Electrical Characteristics (continued)
VREF=10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMIN≤TA≤TMAX.(1) For all other limits
TA=25°C.
Parameter
Conditions
VCC=14.5V to 15.5V
0.0002
0.0025
11.5V to 12.5V
0.0006
4.5V to 5.5V
0.013
0.015
Max
15
20
20
kΩ
Min
15
10
10
kΩ
All digital inputs latched high
VREF=20 Vp-p, f=100 kHz
All data inputs latched low
Output Leakage
Current Max (8)
All data inputs
IOUT1
IOUT1
IOUT2
LJ & LCJ
%
FSR/V
3
mVp-p
See (8)
100
100
LCN, LCWM & LCV
50
100
All data inputs
LJ & LCJ
100
100
latched high
LCN, LCWM & LCV
50
100
latched low
IOUT2
Design
Limit (5)
Limit
Units (2)
Tested
Limit (4)
Output Feedthrough Error
Output
Capacitance
VCC = 5 VDC ±5%
VCC = 12 VDC ±5%
to 15 VDC ±5%
Typ (3)
Power Supply Rejection
Reference
Input
See
Note
VCC = 4.75 VDC
VCC = 15.75 VDC
All data inputs
45
latched low
All data inputs
130
IOUT2
latched high
30
nA
pF
115
IOUT1
nA
pF
DIGITAL AND DC CHARACTERISTICS
Digital Input
Voltages
Max
Min
Digital Input
Currents
Supply Current
Drain
(8)
4
Max
Logic Low
Logic High
LJ: 4.75V
0.6
LJ: 15.75V
0.8
LCJ:
4.75V
0.7
LCJ:
15.75V
0.8
LCN, LCWM, LCV
0.95
0.8
LJ & LCJ
2.0
2.0
LCN, LCWM, LCV
1.9
2.0
−200
−200
μA
−160
−200
μA
+10
+10
μA
+8
+10
3.5
3.5
1.7
2.0
Digital inputs
<0.8V
LJ & LCJ
Digital
inputs>2.0V
LJ & LCJ
Max
VDC
−50
LCN, LCWM, LCV
0.1
LCN, LCWM, LCV
LJ & LCJ
1.2
LCN, LCWM, LCV
VDC
mA
A 100nA leakage current with Rfb=20k and VREF=10V corresponds to a zero error of (100×10−9×20×103)×100/10 which is 0.02% of FS.
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Electrical Characteristics
VREF=10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMIN≤TA≤TMAX. (1) For all other limits
TA=25°C.
Symbol
Parameter
AC CHARACTERISTICS
See
Note
Conditions
Typ
(2)
Current Setting
Time
VIL=0V, VIH=5V
tW
Write and XFER
VIL=0V, VIH=5V
Data Setup Time
See (
5)
100
See (
Data Hold Time
VIL=0V, VIH=5V
See (
VIL=0V, VIH=5V
See (
VIL=0V, VIH=5V
See
(
See
(
1)
100
Control Setup
Time
1)
1)
110
Min
Control Hold Time
Tested
Limit (3)
VIL=0V, VIH=5V
1)
0
375
320
Design
Limit (4)
Limit
Units
μs
600
900
250
375
320
900
50
30
50
250
0
600
320
0
0
900
ns
900
1100
10
900
600
30
320
Min
(1)
(2)
(3)
(4)
(5)
250
320
Min
tCH
Typ
(2)
VCC=5
VDC±5%
1.0
320
1)
Min
tCS
Design Limit
(4)
VCC=4.75 VDC
1.0
Pulse Width Min
tDH
Tested
Limit (3)
VCC=12 VDC±5%
to 15 VDC ±5%
(5)
ts
tDS
VCC=15.75 VDC
1100
0
0
Boldface tested limits apply to the LJ and LCJ suffix parts only.
Typicals are at 25°C and represent most likely parametric norm.
Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
Ensured, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
The entire write pulse must occur within the valid data interval for the specified tW, tDS, tDH, and tS to apply.
Switching Waveform
Definition of Package Pinouts
Control Signals
(All control signals level actuated)
CS:
Chip Select (active low). The CS in combination with ILE will enable WR1.
ILE:
Input Latch Enable (active high). The ILE in combination with CS enables WR1.
WR1: Write 1. The active low WR1 is used to load the digital input data bits (DI) into the input latch. The data in
the input latch is latched when WR1 is high. To update the input latch–CS and WR1 must be low while ILE
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is high.
WR2: Write 2 (active low). This signal, in combination with XFER, causes the 8-bit data which is available in the
input latch to transfer to the DAC register.
XFER: Transfer control signal (active low). The XFER will enable WR2.
Other Pin Functions
DI0-DI7: Digital Inputs. DI0 is the least significant bit (LSB) and DI7 is the most significant bit (MSB).
IOUT1: DAC Current Output 1. IOUT1 is a maximum for a digital code of all 1's in the DAC register, and is zero for
all 0's in DAC register.
IOUT2: DAC Current Output 2. IOUT2 is a constant minus IOUT1 , or IOUT1 + IOUT2 = constant (I full scale for a fixed
reference voltage).
Rfb:
Feedback Resistor. The feedback resistor is provided on the IC chip for use as the shunt feedback
resistor for the external op amp which is used to provide an output voltage for the DAC. This on-chip
resistor should always be used (not an external resistor) since it matches the resistors which are used in
the on-chip R-2R ladder and tracks these resistors over temperature.
VREF: Reference Voltage Input. This input connects an external precision voltage source to the internal R-2R
ladder. VREF can be selected over the range of +10 to −10V. This is also the analog voltage input for a 4quadrant multiplying DAC application.
VCC: Digital Supply Voltage. This is the power supply pin for the part. VCC can be from +5 to +15VDC.
Operation is optimum for +15VDC
GND: The pin 10 voltage must be at the same ground potential as IOUT1 and IOUT2 for current switching
applications. Any difference of potential (VOS pin 10) will result in a linearity change of :
(1)
For example, if VREF = 10V and pin 10 is 9mV offset from IOUT1 and IOUT2 the linearity change will be 0.03%.
Pin 3 can be offset ±100mV with no linearity change, but the logic input threshold will shift.
Linearity Error
Figure 3. a) End Point Test After
Zero and fs adj.
Figure 4. b) Best Straight Line
Figure 5. c) Shifting fs adj. to
Pass
Best Straight Line Test
Definition of Terms
Resolution: Resolution is directly related to the number of switches or bits within the DAC. For example, the
DAC0830 has 28 or 256 steps and therefore has 8-bit resolution.
Linearity Error: Linearity Error is the maximum deviation from a straight line passing through the endpoints of
the DAC transfer characteristic. It is measured after adjusting for zero and full-scale. Linearity error is a
parameter intrinsic to the device and cannot be externally adjusted.
6
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TI's linearity “end point test” (a) and the “best straight line” test (b,c) used by other suppliers are illustrated above.
The “end point test'' greatly simplifies the adjustment procedure by eliminating the need for multiple iterations of
checking the linearity and then adjusting full scale until the linearity is met. The “end point test'' ensures that
linearity is met after a single full scale adjust. (One adjustment vs. multiple iterations of the adjustment.) The “end
point test'' uses a standard zero and F.S. adjustment procedure and is a much more stringent test for DAC
linearity.
Power Supply Sensitivity: Power supply sensitivity is a measure of the effect of power supply changes on the
DAC full-scale output.
Settling Time: Settling time is the time required from a code transition until the DAC output reaches within
±½LSB of the final output value. Full-scale settling time requires a zero to full-scale or full-scale to zero output
change.
Full Scale Error: Full scale error is a measure of the output error between an ideal DAC and the actual device
output. Ideally, for the DAC0830 series, full scale is VREF −1LSB. For VREF = 10V and unipolar operation, VFULLSCALE = 10,0000V–39mV 9.961V. Full-scale error is adjustable to zero.
Differential Nonlinearity: The difference between any two consecutive codes in the transfer curve from the
theoretical 1 LSB to differential nonlinearity.
Monotonic: If the output of a DAC increases for increasing digital input code, then the DAC is monotonic. An 8bit DAC which is monotonic to 8 bits simply means that increasing digital input codes will produce an increasing
analog output.
Figure 6. DAC0830 Functional Diagram
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Typical Performance Characteristics
8
Digital Input Threshold
vs.
Temperature
Digital Input Threshold
vs.
VCC
Figure 7.
Figure 8.
Gain and Linearity Error Variation
vs.
Temperature
Gain and Linearity Error Variation
vs.
Supply Voltage
Figure 9.
Figure 10.
Write Pulse Width
Data Hold Time
Figure 11.
Figure 12.
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DAC0830 SERIES APPLICATION HINTS
These DAC's are the industry's first microprocessor compatible, double-buffered 8-bit multiplying D to A
converters. Double-buffering allows the utmost application flexibility from a digital control point of view. This 20pin device is also pin for pin compatible (with one exception) with the DAC1230, a 12-bit MICRO-DAC. In the
event that a system's analog output resolution and accuracy must be upgraded, substituting the DAC1230 can
be easily accomplished. By tying address bit A0 to the ILE pin, a two-byte μP write instruction (double precision)
which automatically increments the address for the second byte write (starting with A0=“1”) can be used. This
allows either an 8-bit or the 12-bit part to be used with no hardware or software changes. For the simplest 8-bit
application, this pin should be tied to VCC (also see other uses in Double-Buffered Operation).
Analog signal control versatility is provided by a precision R-2R ladder network which allows full 4-quadrant
multiplication of a wide range bipolar reference voltage by an applied digital word.
DIGITAL CONSIDERATIONS
A most unique characteristic of these DAC's is that the 8-bit digital input byte is double-buffered. This means that
the data must transfer through two independently controlled 8-bit latching registers before being applied to the R2R ladder network to change the analog output. The addition of a second register allows two useful control
features. First, any DAC in a system can simultaneously hold the current DAC data in one register (DAC register)
and the next data word in the second register (input register) to allow fast updating of the DAC output on
demand. Second, and probably more important, double-buffering allows any number of DAC's in a system to be
updated to their new analog output levels simultaneously via a common strobe signal.
The timing requirements and logic level convention of the register control signals have been designed to
minimize or eliminate external interfacing logic when applied to most popular microprocessors and development
systems. It is easy to think of these converters as 8-bit “write-only” memory locations that provide an analog
output quantity. All inputs to these DAC's meet TTL voltage level specs and can also be driven directly with high
voltage CMOS logic in non-microprocessor based systems. To prevent damage to the chip from static discharge,
all unused digital inputs should be tied to VCC or ground. If any of the digital inputs are inadvertantly left floating,
the DAC interprets the pin as a logic “1”.
Double-Buffered Operation
Updating the analog output of these DAC's in a double-buffered manner is basically a two step or double write
operation. In a microprocessor system two unique system addresses must be decoded, one for the input latch
controlled by the CS pin and a second for the DAC latch which is controlled by the XFER line. If more than one
DAC is being driven, Figure 13, the CS line of each DAC would typically be decoded individually, but all of the
converters could share a common XFER address to allow simultaneous updating of any number of DAC's. The
timing for this operation is shown, Figure 14.
It is important to note that the analog outputs that will change after a simultaneous transfer are those from the
DAC's whose input register had been modified prior to the XFER command.
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*TIE TO LOGIC 1 IF NOT NEEDED (SEE Double-Buffered Operation).
Figure 13. Controlling Mutiple DACs
Figure 14.
The ILE pin is an active high chip select which can be decoded from the address bus as a qualifier for the normal
CS signal generated during a write operation. This can be used to provide a higher degree of decoding unique
control signals for a particular DAC, and thereby create a more efficient addressing scheme.
Another useful application of the ILE pin of each DAC in a multiple DAC system is to tie these inputs together
and use this as a control line that can effectively “freeze” the outputs of all the DAC's at their present value.
Pulling this line low latches the input register and prevents new data from being written to the DAC. This can be
particularly useful in multiprocessing systems to allow a processor other than the one controlling the DAC's to
take over control of the data bus and control lines. If this second system were to use the same addresses as
those decoded for DAC control (but for a different purpose) the ILE function would prevent the DAC's from being
erroneously altered.
In a “Stand-Alone” system the control signals are generated by discrete logic. In this case double-buffering can
be controlled by simply taking CS and XFER to a logic “0”, ILE to a logic “1” and pulling WR1 low to load data to
the input latch. Pulling WR2 low will then update the analog output. A logic “1” on either of these lines will prevent
the changing of the analog output.
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ILE=LOGIC “1”; WR2 and XFER GROUNDED
Figure 15.
Single-Buffered Operation
In a microprocessor controlled system where maximum data throughput to the DAC is of primary concern, or
when only one DAC of several needs to be updated at a time, a single-buffered configuration can be used. One
of the two internal registers allows the data to flow through and the other register will serve as the data latch.
Digital signal feedthrough (see Section Digital Signal Feedthrough) is minimized if the input register is used as
the data latch. Timing for this mode is shown in Figure 15.
Single-buffering in a “stand-alone” system is achieved by strobing WR1 low to update the DAC with CS, WR2 and
XFER grounded and ILE tied high.
Flow-Through Operation
Though primarily designed to provide microprocessor interface compatibility, the MICRO-DAC's can easily be
configured to allow the analog output to continuously reflect the state of an applied digital input. This is most
useful in applications where the DAC is used in a continuous feedback control loop and is driven by a binary updown counter, or in function generation circuits where a ROM is continuously providing DAC data.
Simply grounding CS, WR1, WR2, and XFER and tying ILE high allows both internal registers to follow the
applied digital inputs (flow-through) and directly affect the DAC analog output.
Control Signal Timing
When interfacing these MICRO-DAC to any microprocessor, there are two important time relationships that must
be considered to insure proper operation. The first is the minimum WR strobe pulse width which is specified as
900 ns for all valid operating conditions of supply voltage and ambient temperature, but typically a pulse width of
only 180ns is adequate if VCC=15VDC. A second consideration is that the specified minimum data hold time of
50ns should be met or erroneous data can be latched. This hold time is defined as the length of time data must
be held valid on the digital inputs after a qualified (via CS) WR strobe makes a low to high transition to latch the
applied data.
If the controlling device or system does not inherently meet these timing specs the DAC can be treated as a slow
memory or peripheral and utilize a technique to extend the write strobe. A simple extension of the write time, by
adding a wait state, can simultaneously hold the write strobe active and data valid on the bus to satisfy the
minimum WR pulsewidth. If this does not provide a sufficient data hold time at the end of the write cycle, a
negative edge triggered one-shot can be included between the system write strobe and the WR pin of the DAC.
This is illustrated in Figure 16 for an exemplary system which provides a 250ns WR strobe time with a data hold
time of less than 10ns.
The proper data set-up time prior to the latching edge (LO to HI transition) of the WR strobe, is insured if the WR
pulsewidth is within spec and the data is valid on the bus for the duration of the DAC WR strobe.
Digital Signal Feedthrough
When data is latched in the internal registers, but the digital inputs are changing state, a narrow spike of current
may flow out of the current output terminals. This spike is caused by the rapid switching of internal logic gates
that are responding to the input changes.
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There are several recommendations to minimize this effect. When latching data in the DAC, always use the input
register as the latch. Second, reducing the VCC supply for the DAC from +15V to +5V offers a factor of 5
improvement in the magnitude of the feedthrough, but at the expense of internal logic switching speed. Finally,
increasing CC (Figure 19) to a value consistent with the actual circuit bandwidth requirements can provide a
substantial damping effect on any output spikes.
Figure 16. Accommodating a High Speed System
ANALOG CONSIDERATIONS
The fundamental purpose of any D to A converter is to provide an accurate analog output quantity which is
representative of the applied digital word. In the case of the DAC0830, the output, IOUT1, is a current directly
proportional to the product of the applied reference voltage and the digital input word. For application versatility, a
second output, IOUT2, is provided as a current directly proportional to the complement of the digital input.
Basically:
where the digital input is the decimal (base 10) equivalent of the applied 8-bit binary word (0 to 255), VREF is the
voltage at pin 8 and 15 kΩ is the nominal value of the internal resistance, R, of the R-2R ladder network
(discussed in Section The Current Switching R-2R Ladder).
Several factors external to the DAC itself must be considered to maintain analog accuracy and are covered in
subsequent sections.
The Current Switching R-2R Ladder
The analog circuitry, Figure 17, consists of a silicon-chromium (SiCr or Si-chrome) thin film R-2R ladder which is
deposited on the surface oxide of the monolithic chip. As a result, there are no parasitic diode problems with the
ladder (as there may be with diffused resistors) so the reference voltage, VREF, can range −10V to +10V even if
VCC for the device is 5VDC.
The digital input code to the DAC simply controls the position of the SPDT current switches and steers the
available ladder current to either IOUT1 or IOUT2 as determined by the logic input level (“1” or “0”) respectively, as
shown in Figure 17. The MOS switches operate in the current mode with a small voltage drop across them and
can therefore switch currents of either polarity. This is the basis for the 4-quadrant multiplying feature of this
DAC.
12
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Basic Unipolar Output Voltage
To maintain linearity of output current with changes in the applied digital code, it is important that the voltages at
both of the current output pins be as near ground potential (0VDC) as possible. With VREF=+10V every millivolt
appearing at either IOUT1 or IOUT2 will cause a 0.01% linearity error. In most applications this output current is
converted to a voltage by using an op amp as shown in Figure 18.
The inverting input of the op amp is a “virtual ground” created by the feedback from its output through the internal
15 kΩ resistor, Rfb. All of the output current (determined by the digital input and the reference voltage) will flow
through Rfb to the output of the amplifier. Two-quadrant operation can be obtained by reversing the polarity of
VREF thus causing IOUT1 to flow into the DAC and be sourced from the output of the amplifier. The output voltage,
in either case, is always equal to IOUT1×Rfb and is the opposite polarity of the reference voltage.
The reference can be either a stable DC voltage source or an AC signal anywhere in the range from −10V to
+10V. The DAC can be thought of as a digitally controlled attenuator: the output voltage is always less than or
equal to the applied reference voltage. The VREF terminal of the device presents a nominal impedance of 15 kΩ
to ground to external circuitry.
Always use the internal Rfb resistor to create an output voltage since this resistor matches (and tracks with
temperature) the value of the resistors used to generate the output current (IOUT1).
Figure 17.
Figure 18.
Op Amp Considerations
The op amp used in Figure 18 should have offset voltage nulling capability (See Section Zero Adjustment).
The selected op amp should have as low a value of input bias current as possible. The product of the bias
current times the feedback resistance creates an output voltage error which can be significant in low reference
voltage applications. BI-FET™ op amps are highly recommended for use with these DACs because of their very
low input current.
Transient response and settling time of the op amp are important in fast data throughput applications. The largest
stability problem is the feedback pole created by the feedback resistance, Rfb, and the output capacitance of the
DAC. This appears from the op amp output to the (−) input and includes the stray capacitance at this node.
Addition of a lead capacitance, CC in Figure 19, greatly reduces overshoot and ringing at the output for a step
change in DAC output current.
Finally, the output voltage swing of the amplifier must be greater than VREF to allow reaching the full scale output
voltage. Depending on the loading on the output of the amplifier and the available op amp supply voltages (only
±12 volts in many development systems), a reference voltage less than 10 volts may be necessary to obtain the
full analog output voltage range.
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Bipolar Output Voltage with a Fixed Reference
The addition of a second op amp to the previous circuitry can be used to generate a bipolar output voltage from
a fixed reference voltage. This, in effect, gives sign significance to the MSB of the digital input word and allows
two-quadrant multiplication of the reference voltage. The polarity of the reference can also be reversed to realize
full 4-quadrant multiplication: ±VREF×±Digital Code=±VOUT. This circuit is shown in Figure 20.
This configuration features several improvements over existing circuits for bipolar outputs with other multiplying
DACs. Only the offset voltage of amplifier 1 has to be nulled to preserve linearity of the DAC. The offset voltage
error of the second op amp (although a constant output voltage error) has no effect on linearity. It should be
nulled only if absolute output accuracy is required. Finally, the values of the resistors around the second amplifier
do not have to match the internal DAC resistors, they need only to match and temperature track each other. A
thin film 4-resistor network available from Beckman Instruments, Inc. (part no. 694-3-R10K-D) is ideally suited for
this application. These resistors are matched to 0.1% and exhibit only 5 ppm/°C resistance tracking temperature
coefficient. Two of the four available 10 kΩ resistors can be paralleled to form R in Figure 20 and the other two
can be used independently as the resistances labeled 2R.
Zero Adjustment
For accurate conversions, the input offset voltage of the output amplifier must always be nulled. Amplifier offset
errors create an overall degradation of DAC linearity.
The fundamental purpose of zeroing is to make the voltage appearing at the DAC outputs as near 0VDC as
possible. This is accomplished for the typical DAC — op amp connection (Figure 18) by shorting out Rfb, the
amplifier feedback resistor, and adjusting the VOS nulling potentiometer of the op amp until the output reads zero
volts. This is done, of course, with an applied digital code of all zeros if IOUT1 is driving the op amp (all one's for
IOUT2). The short around Rfb is then removed and the converter is zero adjusted.
Figure 19.
ts
OP Amp
CC
(O to Full Scale)
LF356
22 pF
4 μs
LF351
22 pF
5 μs
LF357 (1)
10 pF
2 μs
(1)
2.4 kΩ RESISTOR ADDED FROM−INPUT TO GROUND TO
INSURE STABILITY
*THESE RESISTORS ARE AVAILABLE FROM BECKMAN INSTRUMENTS, INC. AS THEIR PART NO. 694-3-R10KD
Figure 20.
14
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Input Code
MSB
IDEAL VOUT
LSB
11
1
1
1
1
1
1
11
0
0
0
0
0
0
10
0
0
0
0
0
0
01
1
1
1
1
1
1
00
1
1
1
1
1
1
00
0
0
0
0
0
0
+VREF
−VREF
Full-Scale Adjustment
In the case where the matching of Rfb to the R value of the R-2R ladder (typically ±0.2%) is insufficient for fullscale accuracy in a particular application, the VREF voltage can be adjusted or an external resistor and
potentiometer can be added as shown in Figure 21 to provide a full-scale adjustment.
The temperature coefficients of the resistors used for this adjustment are of an important concern. To prevent
degradation of the gain error temperature coefficient by the external resistors, their temperature coefficients
ideally would have to match that of the internal DAC resistors, which is a highly impractical constraint. For the
values shown in Figure 21, if the resistor and the potentiometer each had a temperature coefficient of ±100
ppm/°C maximum, the overall gain error temperature coefficent would be degraded a maximum of 0.0025%/°C
for an adjustment pot setting of less than 3% of Rfb.
Using the DAC0830 in a Voltage Switching Configuration
The R-2R ladder can also be operated as a voltage switching network. In this mode the ladder is used in an
inverted manner from the standard current switching configuration. The reference voltage is connected to one of
the current output terminals (IOUT1 for true binary digital control, IOUT2 is for complementary binary) and the output
voltage is taken from the normal VREF pin. The converter output is now a voltage in the range from 0V to 255/256
VREF as a function of the applied digital code as shown in Figure 22.
Figure 21. Adding Full-Scale Adjustment
Figure 22. Voltage Mode Switching
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This configuration offers several useful application advantages. Since the output is a voltage, an external op amp
is not necessarily required but the output impedance of the DAC is fairly high (equal to the specified reference
input resistance of 10 kΩ to 20 kΩ) so an op amp may be used for buffering purposes. Some of the advantages
of this mode are illustrated in Figure 23, Figure 24, Figure 25, and Figure 26.
There are two important things to keep in mind when using this DAC in the voltage switching mode. The applied
reference voltage must be positive since there are internal parasitic diodes from ground to the IOUT1 and IOUT2
terminals which would turn on if the applied reference went negative. There is also a dependence of conversion
linearity and gain error on the voltage difference between VCC and the voltage applied to the normal current
output terminals. This is a result of the voltage drive requirements of the ladder switches. To ensure that all 8
switches turn on sufficiently (so as not to add significant resistance to any leg of the ladder and thereby introduce
additional linearity and gain errors) it is recommended that the applied reference voltage be kept less than +5VDC
and VCC be at least 9V more positive than VREF. These restrictions ensure less than 0.1% linearity and gain error
change. Figure 27, Figure 28, and Figure 29 characterize the effects of bringing VREF and VCC closer together as
well as typical temperature performance of this voltage switching configuration.
•
Voltage switching mode eliminates output signal inversion and therefore a need for a negative power supply.
•
Zero code output voltage is limited by the low level output saturation voltage of the op amp. The 2 kΩ pull-down
resistor helps to reduce this voltage.
•
VOS of the op amp has no effect on DAC linearity.
Figure 23. Single Supply DAC
Figure 24. Obtaining a Bipolar Output from a Fixed Reference with a Single Op Amp
16
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Figure 25. Bipolar Output with Increased Output Voltage Swing
Figure 26. Single Supply DAC with Level Shift and Span- Adjustable Output
Gain and Linearity Error Variation
vs.
Supply Voltage
Gain and Linearity Error Variation
vs.
Reference Voltage
Note: For these curves, VREF is the voltage applied to pin 11 (IOUT1)
with pin 12 (IOUT2) grounded.
Figure 27.
Figure 28.
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Gain and Linearity Error Variation
vs.
Temperature
Figure 29.
Miscellaneous Application Hints
These converters are CMOS products and reasonable care should be exercised in handling them to prevent
catastrophic failures due to static discharge.
Conversion accuracy is only as good as the applied reference voltage so providing a stable source over time and
temperature changes is an important factor to consider.
A “good” ground is most desirable. A single point ground distribution technique for analog signals and supply
returns keeps other devices in a system from affecting the output of the DACs.
During power-up supply voltage sequencing, the −15V (or −12V) supply of the op amp may appear first. This will
cause the output of the op amp to bias near the negative supply potential. No harm is done to the DAC, however,
as the on-chip 15 kΩ feedback resistor sufficiently limits the current flow from IOUT1 when this lead is internally
clamped to one diode drop below ground.
Careful circuit construction with minimization of lead lengths around the analog circuitry, is a primary concern.
Good high frequency supply decoupling will aid in preventing inadvertant noise from appearing on the analog
output.
Overall noise reduction and reference stability is of particular concern when using the higher accuracy versions,
the DAC0830 and DAC0831, or their advantages are wasted.
GENERAL APPLICATION IDEAS
The connections for the control pins of the digital input registers are purposely omitted. Any of the control formats
discussed in Digital Considerations of the accompanying text will work with any of the circuits shown. The
method used depends on the overall system provisions and requirements.
The digital input code is referred to as D and represents the decimal equivalent value of the 8-bit binary input, for
example:
Binary Input
18
D
Pin 13
Pin 7
Decimal
MSB
LSB
Equivalent
1
1
1
1
1
1
1
1
255
1
0
0
0
0
0
0
0
128
0
0
0
1
0
0
0
0
16
0
0
0
0
0
0
1
0
2
0
0
0
0
0
0
0
0
0
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Applications
Figure 30. DAC Controlled Amplifier (Volume Control)
Figure 31. Capacitance Multiplier
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Figure 32. Variable fO, Variable QO, Constant BW Bandpass Filter
Figure 33. DAC Controlled Function Generator
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Figure 34. Two Terminal Floating 4 to 20 mA Current Loop Controller
•
•
•
•
DAC0830 linearly controls the current flow from the input terminal to the output terminal to be 4 mA (for D=0)
to 19.94 mA (for D=255).
Circuit operates with a terminal voltage differential of 16V to 55V.
P2 adjusts the magnitude of the output current and P1 adjusts the zero to full scale range of output current.
Digital inputs can be supplied from a processor using opto isolators on each input or the DAC latches can
flow-through (connect control lines to pins 3 and 10 of the DAC) and the input data can be set by SPST
toggle switches to ground (pins 3 and 10).
Figure 35. DAC Controlled Exponential Time Response
•
•
•
Output responds exponentially to input changes and automatically stops when VOUT=VIN
Output time constant is directly proportional to the DAC input code and capacitor C
Input voltage must be positive (See Using the DAC0830 in a Voltage Switching Configuration
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REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
•
22
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 21
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PACKAGE OPTION ADDENDUM
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6-Jun-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC0832LCWM/NOPB
LIFEBUY
SOIC
DW
20
36
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
0 to 70
DAC0832
LCWM
DAC0832LCWMX/NOPB
LIFEBUY
SOIC
DW
20
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
0 to 70
DAC0832
LCWM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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6-Jun-2019
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DAC0832LCWMX/NOPB
Package Package Pins
Type Drawing
SOIC
DW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
10.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.3
3.25
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC0832LCWMX/NOPB
SOIC
DW
20
1000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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