Texas Instruments | 8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter w/Inter Sam-and-Hold (Rev. G) | Datasheet | Texas Instruments 8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter w/Inter Sam-and-Hold (Rev. G) Datasheet

Texas Instruments 8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter w/Inter Sam-and-Hold (Rev. G) Datasheet
ADC08L060
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SNAS167G – MAY 2002 – REVISED MARCH 2013
ADC08L060 8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter with Internal
Sample-and-Hold
Check for Samples: ADC08L060
FEATURES
DESCRIPTION
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•
The ADC08L060 is a low-power, 8-bit, monolithic
analog-to-digital converter with an on-chip track-andhold circuit. Optimized for low cost, low power, small
size and ease of use, this product operates at
conversion rates of 10 MSPS to 60 MSPS while
consuming just 0.65 mW per MHz of clock frequency,
or 39 mW at 60 MSPS. Raising the PD pin puts the
ADC08L060 into a Power Down mode where it
consumes about 1 mW.
1
2
Single-ended input
Internal sample-and-hold function
Low voltage (single +3V) operation
Small package
Power-down feature
KEY SPECIFICATIONS
•
•
•
•
•
•
•
•
•
•
Resolution 8 bits
Conversion rate 60 MSPS
DNL ±0.25 LSB (typ)
INL +0.5/−0.2 LSB (typ)
SNR (10.1 MHz) 48 dB (typ)
ENOB (10.1 MHz) 7.6 bits (typ)
THD (10.1 MHz) −57 dB (typ)
Latency 5 Clock Cycles
No missing codes Ensured
Power Consumption
– Operating 0.65 mW/MSPS (typ)
– Power Down Mode 1.0 mW (typ)
The unique architecture achieves 7.6 Effective Bits.
The ADC08L060 is resistant to latch-up and the
outputs are short-circuit proof. The top and bottom of
the ADC08L060s reference ladder are available for
connections, enabling a wide range of input
possibilities. The digital outputs are TTL/CMOS
compatible with a separate output power supply pin
to support interfacing with 1.8V to 3V logic. The
output coding is straight binary and the digital inputs
(CLK and PD) are TTL/CMOS compatible.
The ADC08L060 is offered in a 24-lead plastic
package (TSSOP) and is specified over the industrial
temperature range of −40°C to +85°C.
APPLICATIONS
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•
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Digital Imaging
Set-top boxes
Portable Instrumentation
Communication Systems
X-ray imaging
Viterbi decoders
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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ADC08L060
SNAS167G – MAY 2002 – REVISED MARCH 2013
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Block Diagram
VDR
VA
(pin 18)
VRT
17
COARSE/FINE
COMPARATORS
1
ENCODER
& ERROR
CORRECTION
8
17
8
SWITCHES
V RM
MUX
17
COARSE/FINE
COMPARATORS
256
VRB
ENCODER
& ERROR
CORRECTION
8
OUTPUT
DRIVERS
DATA
OUT
8
CLOCK
GEN
CLK
VIN
VIN GND
AGND
PD
DR GND
(pin 17)
Pin Configuration
2
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Table 1. Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
6
VIN
Analog signal input. Conversion range is VRB to VRT.
3
VRT
Analog Input that is the high (top) side of the reference ladder of the
ADC. Nominal range is 0.5V to VA. Voltage on VRT and VRB inputs
define the VIN conversion range. Bypass well. See Section 2.0 for
more information.
9
VRM
Mid-point of the reference ladder. This pin should be bypassed to a
quiet point in the analog ground plane with a 0.1 µF capacitor.
10
VRB
Analog Input that is the low side (bottom) of the reference ladder of
the ADC. Nominal range is 0.0V to (VRT – 0.5V). Voltage on VRT
and VRB inputs define the VIN conversion range. Bypass well. See
Section 2.0 for more information.
23
PD
24
CLK
VA
Description
Power Down input. When this pin is high, the converter is in the
Power Down mode and the data output pins hold the last
conversion result.
CMOS/TTL compatible digital clock Input. VIN is sampled on the
rising edge of CLK input.
GND
13 thru 16
and
19 thru 22
D0–D7
7
VIN GND
1, 4, 12
VA
Positive analog supply pin. Connect to a quiet voltage source of
+3V. VA should be bypassed with a 0.1 µF ceramic chip capacitor
for each pin, plus one 10 µF capacitor. See Section 3.0 for more
information.
18
VDR
Power supply for the output drivers. If connected to VA, decouple
well from VA.
17
DR GND
2, 5, 8, 11
AGND
Conversion data digital Output pins. D0 is the LSB, D7 is the MSB.
Valid data is output after the rising edge of the CLK input.
Reference ground for the single-ended analog input, VIN.
The ground return for the output driver supply.
The ground return for the analog supply.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
Supply Voltage (VA)
3.8V
Driver Supply Voltage (VDR)
VA +0.3V
−0.3V to VA
Voltage on Any Input or Output Pin
Reference Voltage (VRT, VRB)
VA to AGND
−0.05V to (VA + 0.05V)
CLK, PD Voltage Range
Input Current at Any Pin
Package Input Current
(3)
±25 mA
(3)
±50 mA
Power Dissipation at TA = 25°C
See
(4)
(5)
ESD Susceptibility
Human Body Model
Machine Model
2500V
200V
Soldering Temperature, Infrared,
10 seconds
(5)
235°C
−65°C to +150°C
Storage Temperature
(1)
(2)
(3)
(4)
(5)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such condition.
All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified.
When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DR GND, or greater than VA or VDR), the
current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can
safely exceed the power supplies with an input current of 25 mA to two.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when this device is operated in a severe
fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Obviously, such conditions should always be avoided.
See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability” (SNOA742).
(1) (2)
Operating Ratings
−40°C ≤ TA ≤ +85°C
Operating Temperature Range
Supply Voltage, VA
+2.4V to +3.6V
Driver Supply Voltage, VDR
+2.4V to VA
Output Driver Voltage, VDR
1.8V to VA
Ground Difference |GND − DR GND|
0V to 300 mV
Upper Reference Voltage (VRT)
0.5V to (VA −0.3V)
Lower Reference Voltage (VRB)
0V to (VRT −0.5V)
VIN Voltage Range
(1)
(2)
VRB to VRT
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such condition
All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified.
Package Thermal Resistance
4
Package
θJA
24-Lead TSSOP
92°C/W
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Converter Electrical Characteristics
The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty
cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1) (2) (3)
Symbol
Parameter
Conditions
Typical
Limits
(4)
Units
(Limits)
(4)
DC ACCURACY
INL
Integral Non-Linearity
+0.5
−0.2
+1.9
−1.35
LSB (max)
LSB (min)
DNL
Differential Non-Linearity
±0.25
±0.90
LSB (max)
0
(max)
FSE
Missing Codes
Full Scale Error
3.0
±13
mV (max)
VOFF
Zero Scale Offset Error
19
27
mV (max)
ANALOG INPUT AND REFERENCE CHARACTERISTICS
V (min)
VRT
V (max)
Input Voltage
CIN
VIN Input Capacitance
4
pF
RIN
RIN Input Resistance
>1
MΩ
BW
Full Power Bandwidth
270
MHz
VRT
Top Reference Voltage
1.9
VRB
RREF
(1)
(2)
(3)
(4)
VIN = 0.75V +0.5 Vrms
(CLK LOW)
(CLK HIGH)
Bottom Reference Voltage
VRT - VRB
Iref
1.6
VRB
VIN
0.3
Reference Delta
Reference Ladder Resistance
Reference Ladder Current
3
1.6
VRT to VRB
VRT to VRB
720
2.2
pF
VA
V (max)
0.5
V (min)
VRT − 0.5
V (max)
0
V (min)
2.3
V (max)
1.0
V (min)
590
Ω (min)
1070
Ω (max)
1.5
mA (min)
2.7
mA (max)
The Electrical characteristics tables list ensured specifications under the listed Recommended Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations for room temperature only
and are not ensured.
The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not
damage this device. However, errors in the A/D conversion can occur if the input goes above VDR or below GND by more than 100 mV.
For example, if VA is 2.7VDC the full-scale input voltage must be ≤2.8VDC to ensure accurate conversions.
To ensure accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
Typical figures are at TJ = 25°C, and represent most likely parametric norms at specific conditions at the time of product characterization
and are not ensured. Test limits are specifid to TI's AOQL (Average Outgoing Quality Level).
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Converter Electrical Characteristics (continued)
The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty
cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1)(2) (3)
Symbol
Parameter
Typical
Conditions
(4)
Limits
(4)
Units
(Limits)
CLK, PD DIGITAL INPUT CHARACTERISTICS
VIH
Logical High Input Voltage
VDR = VA = 3.6V
2.0
V (min)
VIL
Logical Low Input Voltage
VDR = VA = 2.7V
0.8
V (max)
IIH
Logical High Input Current
VIH = VDR = VA = 3.6V
10
nA
IIL
Logical Low Input Current
VIL = 0V, VDR = VA = 2.7V
−50
nA
CIN
Logic Input Capacitance
3
pF
DIGITAL OUTPUT CHARACTERISTICS
VOH
High Level Output Voltage
VA = VDR = 2.7V, IOH = −400 µA
2.6
2.4
V (min)
VOL
Low Level Output Voltage
VA = VDR = 2.7V, IOL = 1.0 mA
0.4
0.5
V (max)
fIN = 10.1 MHz, VIN = FS − 0.25 dB
7.6
6.9
Bits (min)
fIN = 29 MHz, VIN = FS − 0.25 dB
7.4
fIN = 10.1 MHz, VIN = FS − 0.25 dB
47.4
43.3
dB (min)
fIN = 29 MHz, VIN = FS − 0.25 dB
46.1
DYNAMIC PERFORMANCE
ENOB
Effective Number of Bits
SINAD
Signal-to-Noise & Distortion
SNR
Signal-to-Noise Ratio
SFDR
Spurious Free Dynamic Range
THD
Total Harmonic Distortion
HD2
2nd Harmonic Distortion
HD3
3rd Harmonic Distortion
IMD
Intermodulation Distortion
fIN = 10.1 MHz, VIN = FS − 0.25 dB
48
Bits
dB
44.5
dB (min)
fIN = 29 MHz, VIN = FS − 0.25 dB
47.2
dB
fIN = 10.1 MHz, VIN = FS − 0.25 dB
59.1
dBc
fIN = 29 MHz, VIN = FS − 0.25 dB
54.5
dBc
fIN = 10.1 MHz, VIN = FS − 0.25 dB
−56.9
dBc
fIN = 29 MHz, VIN = FS − 0.25 dB
−53.3
dBc
fIN = 10.1 MHz, VIN = FS − 0.25 dB
-61.1
dBc
fIN = 29 MHz, VIN = FS − 0.25 dB
−54.9
dBc
fIN = 10.1 MHz, VIN = FS − 0.25 dB
−64.2
dBc
fIN = 29 MHz, VIN = FS − 0.25 dB
−63.1
dBc
f1 = 11 MHz, VIN = FS − 6.25 dB
f2 = 12 MHz, VIN = FS − 6.25 dB
−55
dBc
DC Input
13
fIN = 10 MHz, VIN = FS − 3 dB
14
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
DRID
Output Driver Supply Current
DC Input
fIN = 10 MHz, VIN = FS − 3 dB
0.04
(5)
DC Input
IA + DRID
PC
Total Operating Current
Power Consumption
CLK Low, PD = Hi
0.33
DC Input
39
fIN = 10 MHz, VIN = FS − 3 dB, PD =
Low
53
CLK Low, PD = Hi
Power Supply Rejection Ratio
PSRR2
Power Supply Rejection Ratio
SNR reduction with 200 mV at 1MHz on
supply
(5)
6
13
18.2
PSRR1
mA (max)
0.2
mA (max)
mA
4.2
fIN = 10 MHz, VIN = FS − 3 dB, PD =
Low
FSE change with 2.7V to 3.3V change in
VA
15.9
mA
16.1
mA (max)
mA
mA
48.3
mW (max)
mW
1
mW
−51
dB
45
dB
IDR is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output
pins, the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent), IDR = VDR (CO x fO + C1 x f1
+ … + C71 x f7) where VDR is the output driver power supply voltage, Cn is the total capacitance on any given output pin, and fn is the
average frequency at which that pin is toggling.
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Converter Electrical Characteristics (continued)
The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty
cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1)(2) (3)
Symbol
Parameter
Conditions
Typical
Limits
(4)
Units
(Limits)
60
MHz (min)
(4)
AC ELECTRICAL CHARACTERISTICS
fC1
Maximum Conversion Rate
80
fC2
Minimum Conversion Rate
10
MHz
tCL
Minimum Clock Low Time
0.62
ns (min)
tCH
Minimum Clock High Time
0.62
ns (min)
5
95
%(min)
%(max)
DC
Clock Duty Cycle
tOH
Output Hold Time
tOD
Output Delay
CLK to Data Invalid
CLK to Data Transition
Pipeline Delay (Latency)
tAD
Sampling (Aperture) Delay
tAJ
Aperture Jitter
5.2
7.1
5
CLK Rise to Acquisition of Data
ns
5.0
9.4
ns (min)
ns (max)
Clock Cycles
2.6
ns
2
ps rms
Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after the rise of the clock input for the sampling switch to
open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode tAD after
the clock goes high.
APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input
noise.
CLOCK DUTY CYCLE is the ratio of the time that the clock wave form is at a logic high to the total time of one
clock period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB. Measured at 60 MSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio, or SINAD. ENOB is defined as (SINAD – 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
FULL-SCALE ERROR is a measure of how far the last code transition is from the ideal 1½ LSB below VRT and
is defined as:
Vmax + 1.5 LSB – VRT
(1)
where Vmax is the voltage at which the transition to the maximum (full scale) code occurs.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
zero scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code value.
The end point test method is used. Measured at 60 MSPS with a ramp input.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. it is defined as the ratio of the power in
the second and third order intermodulation products to the power in one of the original frequencies. IMD is
usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is
(VRT − VRB) / 2n
(2)
where “n” is the ADC resolution, which is 8 in the case of the ADC08L060.
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MISSING CODES are those output codes that are skipped and will never appear at the ADC outputs. These
codes cannot be reached with any input value.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.
OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the
output pins.
OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data
is presented to the output driver stage. New data is available at every clock cycle, but the data lags the
conversion by the Pipeline Delay plus the Output Delay.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power
supply voltage. For the ADC08L060, PSRR1 is the ratio of the change in Full-Scale Error that results from a
change in the d.c. power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding
upon the power supply is rejected and is here defined as
(3)
where SNR0 is the SNR measured with no noise or signal on the supply lines and SNR1 is the SNR measured
with a 1 MHz, 200 mVP-P signal riding upon the supply lines.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output
to the rms value of the sum of all other spectral components below one-half the sampling frequency, not
including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of
the input signal at the output to the rms value of all of the other spectral components below half the clock
frequency, including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the
output spectrum that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the output. THD is calculated as
THD = 20 x log
A 2 +... +A 2
f2
f10
A f12
(4)
where Af1 is the RMS power of the fundamental (output) frequency and Af2 through Af10 are the RMS power of
the first 9 harmonic frequencies in the output spectrum.
ZERO SCALE OFFSET ERROR is the error in the input voltage required to cause the first code transition. It is
defined as
VOFF = VZT − VRB
(5)
where VZT is the first code transition input voltage.
2nd HARMONIC DISTORTION (2nd HARM) is the difference, expressed in dB, between the rms power in the
output fundamental frequency and the power in its 2nd harmonic at the output.
3rd HARMONIC DISTORTION (3rd HARM) is the difference, expressed in dB, between the rms power in the
output fundamental frequency and the power in its 3rd harmonic at the output.
8
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Timing Diagram
Figure 1. ADC08L060 Timing Diagram
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Typical Performance Characteristics
VA = VDR = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated
10
INL
INL vs Temperature
Figure 2.
Figure 3.
INL vs Supply Voltage, VA
INL vs Sample Rate
Figure 4.
Figure 5.
INL vs Clock Duty Cycle
DNL
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
VA = VDR = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated
DNL vs Temperature
DNL vs Supply Voltage, VA
Figure 8.
Figure 9.
DNL vs Sample Rate
DNL vs Clock Duty Cycle
Figure 10.
Figure 11.
SNR, SINAD and SFDR vs Temperature
SNR, SINAD and SFDR vs Supply Voltage, VA
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
VA = VDR = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated
12
SNR, SINAD and SFDR vs Sample Rate
SNR, SINAD and SFDR vs Input Frequency
Figure 14.
Figure 15.
SNR, SINAD and SFDR vs Clock Duty Cycle
Distortion vs Temperature
Figure 16.
Figure 17.
Distortion vs Supply Voltage, VA
Distortion vs Sample Rate
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
VA = VDR = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated
Distortion vs Input Frequency
Distortion vs Clock Duty Cycle
Figure 20.
Figure 21.
Power Consumption (Active) vs.
Sample Rate (fIN = d.c.)
Power Consumption (Active) vs.
Sample Rate (fIN = d.c.)
Figure 22.
Figure 23.
Power Consumption (Active) vs.
Sample Rate (fIN = 1 MHz)
Power Consumption (Active) vs.
Sample Rate (fIN = 1 MHz)
Figure 24.
Figure 25.
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Typical Performance Characteristics (continued)
VA = VDR = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated
14
Spectral Response @ fIN = 10 MHz
Spectral Response @ fIN = 29 MHz
Figure 26.
Figure 27.
Spectral Response @ fIN = 75 MHz
Spectral Response @ fIN = 98.9 MHz
Figure 28.
Figure 29.
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FUNCTIONAL DESCRIPTION
The ADC08L060 uses a unique architecture that achieves over 7 effective bits at input frequencies up to and
beyond Nyquist.
The analog input signal that is within the voltage range set by VRT and VRB is digitized to eight bits. Input voltages
below VRB will cause the output word to consist of all zeroes. Input voltages above VRT will cause the output word
to consist of all ones.
Incorporating a switched capacitor bandgap, the ADC08L060 exhibits a power consumption that is proportional to
frequency, limiting power consumption to what is needed at the clock rate that is used. This and its excellent
performance over a wide range of clock frequencies makes it an ideal choice as a single ADC for many 8-bit
needs.
Data is acquired at the rising edge of the clock and the digital equivalent of that data is available at the digital
outputs 5 clock cycles plus tOD later. The ADC08L060 will convert as long as an adequate clock signal is present
at pin 24. The output coding is straight binary.
The device is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the device is in
the power down mode, where the output pins hold the last conversion before the PD pin went high and the
device consumes about 1.4 mW. Holding the clock input low will further reduce the power consumption in the
power down mode to about 1 mW
APPLICATION INFORMATION
REFERENCE INPUTS
The reference inputs VRT and VRB are the top and bottom of the reference ladder, respectively. Input signals
between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should
be within the range specified in the Operating Ratings table. Any device used to drive the reference pins should
be able to source sufficient current into the VRT pin and sink sufficient current from the VRB pin to keep these
voltages stable.
Chok
e
+3V
10 PF
+
0.1 PF
1
6
+3V
7
24.9
1
%
1.5V,
nominal
+
0.1 PF
34.8
1
%
0.1 PF
VIN
0.1 PF
18
R
GND
D7
D6
D5
D4
D3
D2
D1
D0
VR
3
10 PF
VD
VA
VIN
T
+
10 PF
12
4
+
10 PF
9
0.1 PF
13
14
15
16
19
20
21
22
10
VRB
23
PD
2
A.
AGN
D
5 8 11
DR
CLK
GND
17
24
Because of the ladder and external resistor tolerances, the reference voltage of this circuit can vary too much for
some applications.
Figure 30. Simple, Low Component Count Reference Biasing
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The reference bias circuit of Figure 30 is very simple and the performance is adequate for many applications.
However, circuit tolerances will lead to a wide reference voltage range. Better reference stability can be achieved
by driving the reference pins with low impedance sources.
The circuit of Figure 31 will allow a more accurate setting of the reference voltages. The upper amplifier must be
able to source the reference current as determined by the value of the reference resistor and the value of (VRT VRB). The lower amplifier must be able to sink this reference current. Both should be stable with a capacitive
load. The LM8272 was chosen because of its rail-to-rail input and output capability, its high current output and its
ability to drive large capacitance loads. Of course, the divider resistors at the amplifier input could be changed to
suit your reference voltage needs, or the divider can be replaced with potentiometers for precise settings. The
bottom of the ladder (VRB) may simply be returned to ground if the minimum input signal excursion is 0V. Be sure
that the driving source can source sufficient current into the VRT pin and sink enough current from the VRB pin to
keep these pins stable.
VRT should always be more positive than VRB by the minimum VRT - VRB difference in the Electrical
Characteristics table to minimize noise. Furthermore, the difference between VRT and VRB should not exceed the
maximum value specified in the Electrical Characteristics table to avoid signal distortion.
The VRM pin is the center of the reference ladder and should be bypassed to a quiet point in the analog ground
plane with a 0.1 µF capacitor. DO NOT allow this pin to float.
+3V
Choke
10 PF
+
10 PF
0.1 PF
3
8
+
2
1
1
4 12
1/2 LM8272
VIN
-
0.1 PF
18
VA
6
DR VD
7
4
0.1 PF
VIN GND
0.01 PF
3
VRT
1 PF
4.7k
9
1.62k
ADC08L060
0.1 PF
4.7k
10
D7
D6
D5
D4
D3
D2
D1
D0
13
14
15
16
19
20
21
22
VRB
1 PF
0.1 PF
10 PF
+3V
1 PF
604:
LM4040-2.5
+
+
470:
0.01 PF
6
5
+
7
23
PD
AGND
1/2 LM8272
2
5 8 11
DR GND CLK
17
24
309:
A.
Driving the reference to force desired values requires driving with a low impedance source.
Figure 31. Setting of Reference Voltages
THE ANALOG INPUT
The analog input of the ADC08L060 is a switch followed by an integrator. The input capacitance changes with
the clock level, appearing as 3 pF when the clock is low, and 4 pF when the clock is high. The sampling nature
of the analog input causes current spikes that result in voltage spikes at the analog input pin. Any circuit used to
drive the analog input must be able to drive that input and to settle within the clock low time. The LMH6702 has
been found to be a good amplifier to drive the ADC08L060.
Figure 32 shows an example of an input circuit using the LMH6702. Any input amplifier should incorporate some
gain as operational amplifiers exhibit better phase margin and transient response with gains above 2 or 3 than
with unity gain. If an overall gain of less than 3 is required, attenuate the input and operate the amplifier at a
higher gain, as shown in Figure 32.
16
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The RC at the amplifier output filters the clock rate energy that comes out of the analog input due to the input
sampling circuit. The optimum time constant for this circuit depends not only upon the amplifier and ADC, but
also on the circuit layout and board material. A resistor value should be chosen between 10Ω and 47Ω and the
capacitor value chose according to the formula
(6)
This will provide optimum SNR performance. Best THD performance is realized when the capacitor and resistor
values are both zero. To optimize SINAD, reduce the capacitor value until SINAD performance is optimized. That
is, until SNR = −THD. This value will usually be in the range of 20& to 65% of the value calculated with the
above formula. An accurate calculation is not possible because of the board material and layout dependence.
The circuit of Figure 32 has both gain and offset adjustments. If you eliminate these adjustments normal circuit
tolerances may result in signal clipping unless care is exercised in the worst case analysis of component
tolerances and the input signal excursion is appropriately limited to account for the worst case conditions.
Choke
+3V
200
-
10
240
1
47
LMH6702
+
100
47
51 pF
6
7
4 12
VIN
VDR
VIN GND
D7
D6
D5
D4
D3
D2
D1
D0
VRT
3
*
*
2.7k
9 VRM
+3V
1k
1k
Offset Adjust
-3V to -5V
0.1 PF
18
VA
0.1 PF
0.33 PF
13
14
15
16
19
20
21
22
10
VRB
23
17
DR GND
PD
*URXQG FRQQHFWLRQV PDUNHG ZLWK ³*´
should enter the ground plane at a
common point.
A.
10 PF
0.1 PF
12
*
+
10 PF
0.1 PF
Gain
Adjust
Signal
Input
+
+5V
CLK
24
AGND
2
5
7 8 11
The input amplifier should incorporate some gain for best performance (see text).
Figure 32. Input Amplifier
POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A
10 µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 cm) of the A/D power
pins, with a 0.1 µF ceramic chip capacitor placed within one centimeter of the converter's power supply pins.
Leadless chip capacitors are preferred because they have low lead inductance.
While a single voltage source is recommended for the VA and VDR supplies of the ADC08L060, these supply pins
should be well isolated from each other to prevent any digital noise from being coupled into the analog portions
of the ADC. A choke or 27Ω resistor is recommended between these supply lines with adequate bypass
capacitors close to the supply pins.
As is the case with all high speed converters, the ADC08L060 should be assumed to have little power supply
rejection. None of the supplies for the converter should be the supply that is used for other digital circuitry in any
system with a lot of digital power being consumed. The ADC supplies should be the same supply used for other
analog circuitry.
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No pin should ever have a voltage on it that is in excess of the supply voltage or below ground by more than 300
mV, not even on a transient basis. This can be a problem upon application of power and power shut-down. Be
sure that the supplies to circuits driving any of the input pins, analog or digital, do not come up any faster than
does the voltage at the ADC08L060 power pins.
THE DIGITAL INPUT PINS
The ADC08L060 has two digital input pins: The PD pin and the Clock pin.
The PD Pin
The Power Down (PD) pin, when high, puts the ADC08L060 into a low power mode where power consumption is
reduced to 1.4 mW with the clock running, or to about 1 mW with the clock held low. Output data is valid and
accurate about 1 microsecond after the PD pin is brought low.
The digital output pins retain the last conversion output code when either the clock is stopped or the PD pin is
high.
The ADC08L060 Clock
Although the ADC08L060 is tested and its performance is ensured with a 60 MHz clock, it typically will function
well with clock frequencies from 10 MHz to 80 MHz.
Clock Duty Cycle
The low and high times of the clock signal can affect the performance of any A/D Converter. Because achieving
a precise duty cycle is difficult, the ADC08L060 is designed to maintain performance over a range of duty cycles.
While it is specified and performance is ensured with a 50% clock duty cycle and 60 Msps, ADC08L060
performance is typically maintained with clock high and low times of 0.83 ns, corresponding to a clock duty cycle
range of 5% to 95% with a 60 MHz clock. Note that minimum low and high times may not be simultaneously
asserted.
Clock Line Termination
The CLOCK line should be series terminated at the clock source in the characteristic impedance of that line. If
the clock line is longer than
(7)
where tr is the clock rise time and tprop is the propagation rate of the signal along the trace. The CLOCK pin
should be a.c. terminated with a series RC to ground such that the resistor value is equal to the characteristic
impedance of the clock line and the capacitor value is
(8)
where “L” is the line length in inches and ZO is the characteristic impedance of the clock line. Typical tPROP is
about 150 ps/inch on FR-4 board material. For FR-4 board material, the value of C becomes
(9)
This termination should be located as close as possible to, but within one centimeter of, the ADC08L060 clock
pin.
LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A combined
analog and digital ground plane should be used.
Since digital switching transients are composed largely of high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise because of the skin effect. Total surface area is more
important than is total ground plane volume. Capacitive coupling between the typically noisy digital circuitry and
the sensitive analog circuitry can lead to poor performance that may seem impossible to isolate and remedy. The
solution is to keep the analog circuitry well separated from the digital circuitry.
18
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The DR GND connection to the ground plane should not use the same feedthrough used by other ground
connections.
High power digital components should not be located on or near a straight line between the ADC or any linear
component and the power supply area as the resulting common return current path could cause fluctuation in the
analog input “ground” return of the ADC.
Keeping analog and digital return (ground) currents separate from each other will improve system noise
performance. Two methods may be used to do this. Use of traces rather than a solid plane to route power to all
components will accomplish this because return currents follow the path of the outgoing currents. However, the
advantage of the distributed capacitance of a power plane and a ground plane is lost. Analog and digital power
should be routed as far from each other as is practical. The analog power trace should also be routed away from
digital areas of the board.
The use of power and ground planes in adjacent layers will provide distributed capacitance for a low impedance
power distribution system and better system noise performance. The use of separate analog and digital power
planes, both in the same PC board layer, and the use of a single, non-split ground plane will keep analog and
digital currents separated from each other. Of course, locate all analog circuitry and traces over the analog power
plane and the digital circuitry and traces over the digital power plane. To minimize RFI/EMI, give proper attention
to any lines crossing the analog/digital power plane boundary.
Noise performance is also enhanced by driving a single gate with each ADC output pin and locating the gate as
close as possible to the ADC output. Inserting a 47Ω resistor in series with the ADC digital output pins will also
help reduce ADC noise. Be sure to keep the resistors as close to the ADC output pins as possible. Eliminating
ground plane copper beneath the ADC output lines can also help ADC noise performance, but could produce
unacceptable radiation from the board.
Analog and digital circuitry should be kept well away from each other. Especially troublesome is high power
digital components such as processors and large PLDs. Switch mode power supplies, including capacitive DCDC converters, can cause noise problems with high speed ADCs. Keep such components well away from ADCs
and low level analog signal areas. Such components should be located as close to the power supply as possible
and should not be in the path of analog signal or power supply currents.
Digital circuits create substantial supply and ground current transients. The noise thus generated could have
significant impact upon system noise performance. The best logic family to use in systems with A/D converters is
one that employs non-saturating transistor designs, or has low noise characteristics, like the 74LS and the
74AC(T)Q families. The worst noise generators are logic families that draw the largest supply current transients
during clock or signal edges, like the 74HC, 74F and 74AC(T) families.
Since digital switching transients are composed largely of high frequency components, total ground plane copper
weight will have little effect upon logic-generated noise. This is because of the skin effect. Total surface area is
more important than is total ground plane volume.
Clock lines should be isolated from ALL other lines, analog AND digital. Even the generally accepted 90°
crossing should be avoided as even a little coupling can cause problems at high frequencies. Best performance
at high frequencies is obtained with a straight signal path.
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Single
Ground
Plane
ADC Clock
Source
Locate driving amplifier
near ADC input pin
RF
Locate Clock Source
near ADC clock pin
RIN
R
C
LMH6702
ADC
08L060
Locate power supply on
the digital side of the
ADC
Figure 33. Layout Example
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input and ground should be
connected to a very clean point in the ground plane.
Figure 33 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference
components, etc.) should be placed together away from any digital components.
DYNAMIC PERFORMANCE
The ADC08L060 is a.c. tested and its dynamic performance is ensured. To meet the published specifications, the
clock source driving the CLK input should exhibit less than 10 ps (rms) of jitter. For best a.c. performance,
isolating the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock tree. See
Figure 34.
It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other
signals. Other signals can introduce jitter into the clock signal. The clock signal can also introduce noise into the
analog path.
Figure 34. Isolating the ADC Clock from Digital Circuitry
COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should
not go more than 300 mV below the ground pins or 300 mV above the supply pins. Exceeding these limits on
even a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits
(e.g., 74F and 74AC devices) to exhibit undershoot that goes more than a volt below ground. A 51Ω resistor in
series with the offending digital input will usually eliminate the problem.
Care should be taken not to overdrive the inputs of the ADC08L060. Such practice may lead to conversion
inaccuracies and even to device damage.
20
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Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must
charge for each conversion, the more instantaneous digital current is required from VDR and DR GND. These
large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the
digital data outputs (with a 74F541, for example) may be necessary if the data bus capacitance exceeds 5 pF.
Dynamic performance can also be improved by adding 100Ω series resistors at each digital output, reducing the
energy coupled back into the converter input pins.
Using an inadequate amplifier to drive the analog input. As explained in Section 2.0, the capacitance seen at
the input alternates between 3 pF and 4 pF with the clock. This dynamic capacitance is more difficult to drive
than is a fixed capacitance, and should be considered when choosing a driving device.
Driving the VRT pin or the VRB pin with devices that can not source or sink the current required by the
ladder. As mentioned in Section 1.0, care should be taken to see that any driving devices can source sufficient
current into the VRT pin and sink sufficient current from the VRB pin. If these pins are not driven with devices than
can handle the required current, these reference pins will not be stable, resulting in a reduction of dynamic
performance.
Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other
signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive
output noise and a reduction in SNR performance. The use of simple gates with RC timing is generally
inadequate as a clock source.
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REVISION HISTORY
Changes from Revision F (March 2013) to Revision G
•
22
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 21
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADC08L060CIMT/NOPB
ACTIVE
TSSOP
PW
24
61
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
ADC08L060
CIMT
ADC08L060CIMTX/NOPB
ACTIVE
TSSOP
PW
24
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
ADC08L060
CIMT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADC08L060CIMTX/NOPB TSSOP
PW
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADC08L060CIMTX/NOPB
TSSOP
PW
24
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
13
B
0.30
0.19
0.1
C A B
24X
4.5
4.3
NOTE 4
1.2 MAX
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
13
12
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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