Texas Instruments | 12-Bit 4-Channel Serial-Output Sampling Analog-to-Digital Converter.. (Rev. C) | Datasheet | Texas Instruments 12-Bit 4-Channel Serial-Output Sampling Analog-to-Digital Converter.. (Rev. C) Datasheet

Texas Instruments 12-Bit 4-Channel Serial-Output Sampling Analog-to-Digital Converter.. (Rev. C) Datasheet
ADS7841-Q1
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SBAS469C – MARCH 2009 – REVISED OCTOBER 2012
12-BIT 4-CHANNEL SERIAL-OUTPUT SAMPLING ANALOG-TO-DIGITAL CONVERTER
Check for Samples: ADS7841-Q1
FEATURES
1
•
•
•
•
•
•
•
•
•
DBQ PACKAGE
(TOP VIEW)
Qualified for Automotive Applications
Single Supply: 2.7 V To 5 V
Four-Channel Single-Ended Or Two-Channel
Differential Input
Up To 200-kHz Conversion Rate
±2 LSB Max INL and DNL
No Missing Codes
71-dB Typ SINAD
Serial Interface
Alternate Source For MAX1247
VCC
1
16
DCLK
CH0
2
15
CS
CH1
3
14
DIN
CH2
4
13
BUSY
CH3
5
12
DOUT
COM
6
11
MODE
SHDN
7
10
GND
VREF
8
9
VCC
DESCRIPTION
The ADS7841 is a 4-channel 12-bit sampling analog-to-digital converter (ADC) with a synchronous serial
interface. The resolution is programmable to either 8 bits or 12 bits. Typical power dissipation is 2 mW at a 200kHz throughput rate and a 5-V supply. The reference voltage (VREF) can be varied between 100 mV and VCC,
providing a corresponding input voltage range of 0 V to VREF. The device includes a shutdown mode that reduces
power dissipation to under 15 μW. The ADS7841 is specified down to 2.7-V operation.
Low power, high speed, and on-board multiplexer make the ADS7841 ideal for battery-operated systems. The
serial interface also provides low-cost isolation for remote data acquisition. The ADS7841 is available in a SSOP16 package.
SAR
CH2
CS
Comparator
CH0
CH1
DCLK
Four
Channel
Multiplexer
CH3
COM
CDAC
Serial
Interface
and
Control
SHDN
DIN
DOUT
MODE
BUSY
VREF
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2012, Texas Instruments Incorporated
ADS7841-Q1
SBAS469C – MARCH 2009 – REVISED OCTOBER 2012
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
TA
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–40°C to 85°C
ADS7841EIDBQRQ1
S7841E
–40°C to 125°C
ADS7841ESQDBQRQ1
S7841S
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
VCC
1
CH0
2
I
Analog input channel 0
CH1
3
I
Analog input channel 1
CH2
4
I
Analog input channel 2
CH3
5
I
Analog input channel 3
COM
6
I
Ground reference for analog inputs. Sets zero code voltage in single-ended mode. Connect this pin to ground
or ground reference point.
SHDN
7
I
Shutdown. When low, the device enters a very low power shutdown mode.
VREF
8
I
Voltage reference
VCC
9
Power supply
GND
10
Ground
MODE
11
I
Conversion mode. When low, the device always performs a 12-bit conversion. When high, the resolution is
set by the MODE bit in the CONTROL byte.
DOUT
12
O
Serial data output. Data is shifted on the falling edge of DCLK. This output is high-impedance when CS is
high.
BUSY
13
O
Busy output. This output is high-impedance when CS is high.
DIN
14
I
Serial data input. If CS is low, data is latched on rising edge of DCLK.
CS
15
I
Chip select input. Controls conversion timing and enables the serial input/output register.
DCLK
16
I
External clock input. This clock runs the SAR conversion process and synchronizes serial data I/O.
2
Power supply
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
VIN
Input voltage
PD
Power dissipation
TJ
Maximum virtual-junction temperature
TA
Operating free-air temperature range
Tstg
Storage temperature range
(1)
–0.3 V to 6 V
Analog inputs to GND
–0.3 V to (VCC + 0.3 V)
Digital inputs to GND
–0.3 V to 6 V
250 mW
150°C
ADS7841EIDBQRQ1
–40°C to 85°C
ADS7841ESQDBQRQ1
–40°C to 125°C
–65°C to 150°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ELECTROSTATIC DISCHARGE RATINGS
RATING
Human-Body Model (HBM)
ESD
Electrostatic discharge rating
2000 V
Machine Model (MM)
150 V
Charged-Device Model (CDM)
1000 V
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
VREF
Reference voltage, VREF terminal
VCC = 5 V (nom)
VCC = 2.7 V (nom)
Differential, full-scale
VIN
Input voltage, analog inputs
VIH
High-level input voltage, digital inputs
| IIH | ≤ 5 μA
VIL
Low-level input voltage, digital inputs
| IIL | ≤ 5 μA
TA
Operating free-air temperature
MAX
5.25
2.7
3.6
0.1
VCC
0
VREF
–0.2
VCC + 0.2
VCC = 5 V (nom)
–0.2
1.25
VCC = 2.7 V (nom)
–0.2
0.2
3
5.5
0.7 VCC
5.5
VCC = 5 V (nom)
–0.3
0.8
VCC = 2.7 V (nom)
–0.3
0.8
Positive input
Negative input
MIN
4.75
VCC = 5 V (nom)
VCC = 2.7 V (nom)
ADS7841EIDBQRQ1
–40
85
ADS7841ESQDBQRQ1
–40
125
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UNIT
V
V
V
V
V
°C
3
ADS7841-Q1
SBAS469C – MARCH 2009 – REVISED OCTOBER 2012
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ELECTRICAL CHARACTERISTICS
VCC = 5 V, VREF = 5 V, fSAMPLE = 200 kHz, fCLK = 16 × fSAMPLE = 3.2 MHz, over operating temperature –40°C to 125°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Analog Input
CI
Input capacitance
Ileak
Leakage current
25
pF
200
nA
System Performance
Resolution
No missing codes
INL
Integral linearity error
DNL
Differential linearity error
12
ADS7841EIDBQRQ1
12
ADS7841ESQDBQRQ1
11
bits
bits
±2
±0.8
Offset error
Offset error match
0.15
Gain error
Gain error match
0.1
LSB (
1)
LSB
±3
LSB
1
LSB
±4
LSB
1
LSB
Vn
Noise
30
μVrm
PSRR
Power-supply ripple rejection
70
dB
s
Sampling Dynamics
tconv
Conversion time
tacq
Acquisition time
CLK
12 cycle
s
CLK
cycle
s
3
Throughput rate
tsettle
Multiplexer settling time
td
tjitter
200
kHz
500
ns
Aperture delay
30
ns
Aperture jitter
100
ps
Dynamic Characteristics
THD
Total harmonic distortion (2)
VIN = 5 Vp-p at 10 kHz
SINAD
Signal to noise + distortion ratio
VIN = 5 Vp-p at 10 kHz
68
71
dB
Spurious-free dynamic range
VIN = 5 Vp-p at 10 kHz
72
79
dB
Channel-to-channel isolation
VIN = 5 Vp-p at 50 kHz
120
dB
–78
–72
dB
Reference Input
RI
Resistance
DCLK static
5
40
II
Input current
fSAMPLE = 12.5 kHz
GΩ
100
μA
2.5
DCLK static
0.001
3
Digital Input/Output
VOH
High-level output voltage
IOH = –250 μA
VOL
Low-level output voltage
IOL = 250 μA
3.5
V
0.4
V
Power Supply
550
IQ
Quiescent current
fSAMPLE = 12.5 kHz
Power-down mode (3), CS = VCC
(1)
(2)
(3)
4
900
μA
300
3
LSB = least significant bit. With VREF = 5 V, one LSB is 1.22 mV.
First five harmonics of the test frequency
Auto power-down mode (PD1 = PD0 = 0) active or SHDN = GND
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ELECTRICAL CHARACTERISTICS
VCC = 2.7 V, VREF = 2.5 V, fSAMPLE = 125 kHz, fCLK = 16 × fSAMPLE = 2 MHz, over operating temperature –40°C to 85°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Input
CI
Input capacitance
25
pF
Ileak
Leakage current
±1
μA
12
bits
System Performance
Resolution
No missing codes
INL
Integral linearity error
DNL
Differential linearity error
12
bits
±2 LSB (1)
±0.8
Offset error
Offset error match
0.15
Gain error
LSB
±3
LSB
1
LSB
±4
LSB
Gain error match
0.1
Vn
Noise
30
1
μVrms
LSB
PSRR
Power-supply ripple rejection
70
dB
Sampling Dynamics
tconv
Conversion time
tacq
Acquisition time
12
CLK
cycles
3
Throughput rate
tsettle
Multiplexer settling time
td
tjitter
CLK
cycles
125
kHz
500
ns
Aperture delay
30
ns
Aperture jitter
100
ps
Dynamic Characteristics
THD
Total harmonic distortion (2)
VIN = 2.5 Vp-p at 10 kHz
SINAD
Signal to noise + distortion ratio
VIN = 2.5 Vp-p at 10 kHz
68
71
dB
Spurious-free dynamic range
VIN = 2.5 Vp-p at 10 kHz
72
78
dB
Channel-to-channel isolation
VIN = 2.5 Vp-p at 50 kHz
100
dB
–77
–72
dB
Reference Input
RI
Resistance
DCLK static
5
13
II
Input current
fSAMPLE = 12.5 kHz
GΩ
40
μA
2.5
DCLK static
0.001
3
Digital Input/Output
VOH
High-level output voltage
IOH = –250 μA
VOL
Low-level output voltage
IOL = 250 μA
0.8 VCC
V
0.4
V
Power Supply
280
IQ
Quiescent current
fSAMPLE = 12.5 kHz
Power-down mode (3), CS = VCC
(1)
(2)
(3)
650
μA
220
3
LSB = least significant bit. With VREF = 2.5 V, one LSB is 0.61 mV.
First five harmonics of the test frequency
Auto power-down mode (PD1 = PD0 = 0) active or SHDN = GND
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TYPICAL CHARACTERISTICS, VCC = 5 V
VCC = 5 V, TA = 25°C, VREF = 5 V, fSAMPLE = 200 kHz, fCLK = 16 × fSAMPLE = 3.2 MHz (unless otherwise noted)
FREQUENCY SPECTRUM
(4096 Point FFT; f IN = 10.3kHz, –0.2dB)
0
0
–20
–20
–40
–40
Amplitude (dB)
Amplitude (dB)
FREQUENCY SPECTRUM
(4096 Point FFT; f IN = 1,123Hz, –0.2dB)
–60
–80
–60
–80
–100
–100
–120
–120
0
25
50
75
0
100
25
50
Frequency (kHz)
75
100
Frequency (kHz)
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO(NOISE+DISTORTION) vs INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
–85
85
74
SNR
SFDR
SINAD
71
THD
75
–75
70
–70
THD (dB)
–80
80
72
SFDR (dB)
SNR and SINAD (dB)
73
70
69
1
10
1
100
10
Input Frequency (kHz)
Input Frequency (kHz)
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
0.6
12.0
0.4
11.8
Delta from 25°C (dB)
Effective Number of Bits
–65
100
65
68
11.6
11.4
0.2
0.0
–0.2
11.2
–0.4
11.0
–0.6
fIN = 10kHz, –0.2dB
1
10
100
–40
6
–20
0
20
40
60
80
100
Temperature (°C)
Input Frequency (kHz)
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TYPICAL CHARACTERISTICS, VCC = 2.7 V
VCC = 2.7 V, TA = 25°C, VREF = 2.5 V, fSAMPLE = 125 kHz, fCLK = 16 × fSAMPLE = 2 MHz (unless otherwise noted)
FREQUENCY SPECTRUM
(4096 Point FFT; f IN = 10.6kHz, –0.2dB)
0
0
–20
–20
–40
–40
Amplitude (dB)
–60
–80
–100
–60
–80
–100
–120
–120
0
15.6
31.3
46.9
62.5
0
Frequency (kHz)
15.6
31.3
46.9
62.5
Frequency (kHz)
SPURIOUS-FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO(NOISE+DISTORTION) vs INPUT FREQUENCY
–90
78
SNR
85
–85
SFDR
80
70
SFDR (dB)
SNR and SINAD (dB)
74
66
SINAD
62
58
–80
75
–75
70
–70
THD
65
–65
60
–60
55
–55
50
54
1
10
–50
1
100
THD (dB)
Amplitude (dB)
FREQUENCY SPECTRUM
(4096 Point FFT; f IN = 1,129Hz, –0.2dB)
10
100
Input Frequency (kHz)
Input Frequency (kHz)
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
12.0
0.4
11.5
0.2
Delta from 25°C (dB)
Effective Number of Bits
fIN = 10kHz, –0.2dB
11.0
10.5
10.0
0.0
–0.2
–0.4
–0.6
9.5
–0.8
9.0
1
10
100
–40
–20
0
20
40
60
80
100
Temperature (°C)
Input Frequency (kHz)
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TYPICAL CHARACTERISTICS, VCC = 2.7 V (continued)
VCC = 2.7 V, TA = 25°C, VREF = 2.5 V, fSAMPLE = 125 kHz, fCLK = 16 × fSAMPLE = 2 MHz (unless otherwise noted)
SUPPLY CURRENT vs TEMPERATURE
POWER DOWN SUPPLY CURRENT
vs TEMPERATURE
400
140
120
300
Supply Current (nA)
Supply Current (µA)
350
250
200
150
100
80
60
40
100
–40
–20
0
20
40
60
80
20
100
–40
Temperature (°C)
1.00
0.75
0.75
0.50
0.50
DLE (LSB)
ILE (LSB)
INTEGRAL LINEARITY ERROR vs CODE
0.25
0.00
–0.25
–0.50
–0.50
–0.75
–0.75
–1.00
000H
FFFH
60
80
100
800H
FFFH
Output Code
CHANGE IN OFFSET vs TEMPERATURE
CHANGE IN GAIN vs TEMPERATURE
0.15
0.6
0.10
0.4
Delta from 25°C (LSB)
Delta from 25°C (LSB)
40
0.00
Output Code
0.05
0.00
–0.05
0.2
0.0
–0.2
–0.4
–0.10
–0.6
–0.15
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
8
20
0.25
–0.25
800H
0
Temperature (°C)
DIFFERENTIAL LINEARITY ERROR vs CODE
1.00
–1.00
000H
–20
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TYPICAL CHARACTERISTICS, VCC = 2.7 V (continued)
VCC = 2.7 V, TA = 25°C, VREF = 2.5 V, fSAMPLE = 125 kHz, fCLK = 16 × fSAMPLE = 2 MHz (unless otherwise noted)
REFERENCE CURRENT vs TEMPERATURE
18
12
16
Reference Current (µA)
Reference Current (µA)
REFERENCE CURRENT vs SAMPLE RATE
14
10
8
6
4
14
12
10
8
2
0
6
0
25
50
75
100
125
–40
–20
Sample Rate (kHz)
0
20
40
60
80
100
Temperature (°C)
MAXIMUM SAMPLE RATE vs V CC
SUPPLY CURRENT vs V CC
1M
320
fSAMPLE = 12.5kHz
280
Sample Rate (Hz)
Supply Current (µA)
300
VREF = V CC
260
240
220
100k
10k
VREF = V CC
200
1k
180
2
2.5
3
3.5
4
4.5
5
2
2.5
3
3.5
4
4.5
5
VCC (V)
V CC (V)
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APPLICATION INFORMATION
The ADS7841 is a classic successive approximation register (SAR) ADC. The architecture is based on capacitive
redistribution that inherently includes a sample-and-hold function. The converter is fabricated on a 0.6-μs CMOS
process.
The basic operation of the ADS7841 is shown in Figure 1. The device requires an external reference and an
external clock. It operates from a single supply of 2.7 V to 5.25 V. The external reference can be any voltage
between 100 mV and VCC. The value of the reference voltage directly sets the input range of the converter. The
average reference input current depends on the conversion rate of the ADS7841.
2.7 V to 5 V
ADS7841
1µF +
to
10µF
0.1µF
Single-ended
or differential
analog inputs
1
V CC
DCLK 16
2
CH0
CS 15
3
CH1
DIN 14
4
CH2
BUSY 13
5
CH3
DOUT 12
6
COM
MODE 11
7
SHDN
8
VREF
Serial/Conversion Clock
Chip Select
Serial Data In
Serial Data Out
GND 10
VCC
9
0.1µF
Figure 1. Basic Operation of the ADS7841
The analog input to the converter is differential and is provided via a four-channel multiplexer. The input can be
provided in reference to a voltage on the COM pin (which is generally ground) or differentially by using two of the
four input channels (CH0-CH3). The particular configuration is selectable via the digital interface.
Analog Input
Figure 2 shows a block diagram of the input multiplexer on the ADS7841. The differential input of the converter is
derived from one of the four inputs in reference to the COM pin or two of the four inputs. Table 1 and Table 2
show the relationship between the A2, A1, A0, and SGL/DIF control bits and the configuration of the analog
multiplexer. The control bits are provided serially via the DIN pin, see the Digital Interface section of this data
sheet for more details.
A2-A0
(Shown 001B)
CH0
CH1
CH2
+IN
CH3
Converter
–IN
COM
SGL/DIF
(Shown HIGH)
Figure 2. Simplified Diagram of the Analog Input
10
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Table 1. Single-Ended Channel Selection (SGL/DIF high)
A2
A1
A0
CH0
0
0
1
+IN
CH1
1
0
1
0
1
0
1
1
0
A2
A1
A0
CH0
0
0
1
+IN
–IN
1
0
1
–IN
+IN
0
1
1
1
CH2
CH3
COM
–IN
+IN
–IN
+IN
–IN
+IN
–IN
Table 2. Differential Channel Control (SGL/DIF low)
CH1
CH2
CH3
0
+IN
–IN
0
–IN
+IN
COM
When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs (as shown in
Figure 2) is captured on the internal capacitor array. The voltage on the –IN input is limited between –0.2 V and
1.25 V, allowing the input to reject small signals that are common to both the +IN and –IN input. The +IN input
has a range of –0.2 V to VCC + 0.2 V.
The input current on the analog inputs depends on the conversion rate of the device. During the sample period,
the source must charge the internal sampling capacitor (typically 25 pF). After the capacitor has been fully
charged, there is no further input current. The rate of charge transfer from the analog source to the converter is a
function of conversion rate.
Reference Input
The external reference sets the analog input range. The ADS7841 operates with a reference in the range of 100
mV to VCC. Keep in mind that the analog input is the difference between the +IN input and the –IN input, see
Figure 2. For example, in the single-ended mode, a 1.25-V reference, and with the COM pin grounded, the
selected input channel (CH0-CH3) digitizes a signal in the range of 0 V to 1.25 V. If the COM pin is connected to
0.5 V, the input range on the selected channel is 0.5 V to 1.75 V.
There are several critical items concerning the reference input and its wide voltage range. As the reference
voltage is reduced, the analog voltage weight of each digital output code is also reduced. This is often referred to
as the LSB (least significant bit) size and is equal to the reference voltage divided by 4096. Any offset or gain
error inherent in the ADC appears to increase, in terms of LSB size, as the reference voltage is reduced. For
example, if the offset of a given converter is 2 LSBs with a 2.5-V reference, then it is typically 10 LSBs with a
0.5-V reference. In each case, the actual offset of the device is the same, 1.22 mV.
Likewise, the noise or uncertainty of the digitized output increases with lower LSB size. With a reference voltage
of 100 mV, the LSB size is 24 μV. This level is below the internal noise of the device. As a result, the digital
output code is not stable and varies around a mean value by a number of LSBs. The distribution of output codes
is gaussian, and the noise can be reduced by simply averaging consecutive conversion results or applying a
digital filter.
With a lower reference voltage, care should be taken to provide a clean layout including adequate bypassing, a
clean (low-noise, low-ripple) power supply, a low-noise reference, and a low-noise input signal. Because the LSB
size is lower, the converter is also more sensitive to nearby digital signals and electromagnetic interference.
The voltage into the VREF input is not buffered and directly drives the Capacitor Digital-to-Analog Converter
(CDAC) portion of the ADS7841. Typically, the input current is 13 μA with a 2.5-V reference. This value varies by
microamps depending on the result of the conversion. The reference current diminishes directly with both
conversion rate and reference voltage. As the current from the reference is drawn on each bit decision, clocking
the converter more quickly during a given conversion period does not reduce overall current drain from the
reference.
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Digital Interface
Figure 3 shows the typical operation of the ADS7841's digital interface. This diagram assumes that the source of
the digital signals is a microcontroller or digital signal processor with a basic serial interface (note that the digital
inputs are over-voltage tolerant up to 5.5 V, regardless of VCC). Each communication between the processor and
the converter consists of eight clock cycles. One complete conversion can be accomplished with three serial
communications, for a total of 24 clock cycles on the DCLK input.
CS
tACQ
DCLK
1
DIN
8
S
A2
A1
8
1
1
8
A0 MODE SGL/
DIF PD1 PD0
(START)
Idle
Acquire
Conversion
Idle
BUSY
DOUT
11
10
9
8
7
6
5
4
3
2
1
(MSB)
A.
0
Zero Filled...
(LSB)
24 clock cycles per conversion, 8-bit bus interface. No DCLK delay required with dedicated serial port.
Figure 3. Conversion Timing
The first eight clock cycles are used to provide the control byte via the DIN pin. When the converter has enough
information about the following conversion to set the input multiplexer appropriately, it enters the acquisition
(sample) mode. After three more clock cycles, the control byte is complete and the converter enters the
conversion mode. At this point, the input sample-and-hold goes into the hold mode. The next twelve clock cycles
accomplish the actual Analog-to-Digital conversion. A thirteenth clock cycle is needed for the last bit of the
conversion result. Three more clock cycles are needed to complete the last byte (DOUT is low). These are
ignored by the converter.
Control Byte
Also shown in Figure 3 is the placement and order of the control bits within the control byte. Table 3 and Table 4
give detailed information about these bits. The first bit, the 'S' bit, must always be high and indicates the start of
the control byte. The ADS7841 ignores inputs on the DIN pin until the start bit is detected. The next three bits
(A2-A0) select the active input channel or channels of the input multiplexer (see Table 1, Table 2, and Figure 2).
Table 3. Order of Control Bits in Control Byte
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
S
A2
A1
A0
MODE
SGL/DIF
PD1
PD0
Table 4. Descriptions of Control Bits Within Control Byte
BIT
12
NAME
DESCRIPTION
Start bit. Control byte starts with first high bit on DIN. A new control byte can start every 15th clock
cycle in 12-bit conversion mode or every 11th clock cycle in 8-bit conversion mode.
7
S
6-4
A2-A0
Channel select bits. Along with the SGL/DIF bit, these bits control the setting of the multiplexer input,
see Table 1 and Table 2.
3
MODE
12-bit/8-bit conversion select bit. If the MODE pin is high, this bit controls the number of bits for the
next conversion: 12-bits (low) or 8-bits (high). If the MODE pin is low, this bit has no function and the
conversion is always 12 bits.
2
SGL/DIF
Single-ended/differential select bit. Along with bits A2-A0, this bit controls the setting of the multiplexer
input, see Table 1 and Table 2.
1-0
PD1-PD0
Power-down mode select bits. See Table 5 for details.
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The MODE bit and the MODE pin work together to determine the number of bits for a given conversion. If the
MODE pin is low, the converter always performs a 12-bit conversion regardless of the state of the MODE bit. If
the MODE pin is high, then the MODE bit determines the number of bits for each conversion, either 12 bits (low)
or 8 bits (high).
The SGL/DIF bit controls the multiplexer input mode: either single-ended (high) or differential (low). In singleended mode, the selected input channel is referenced to the COM pin. In differential mode, the two selected
inputs provide a differential input. See Table 1, Table 2, and Figure 2 for more information. The last two bits
(PD1-PD0) select the powerdown mode, as shown in Table 5. If both inputs are high, the device is always
powered up. If both inputs are low, the device enters a power-down mode between conversions. When a new
conversion is initiated, the device resumes normal operation instantly—no delay is needed to allow the device to
power up and the very first conversion is valid.
Table 5. Power-Down Selection
PD1
PD0
DESCRIPTION
0
0
Power-down between conversions. When each conversion is finished, the converter enters a low power mode. At
the start of the next conversion, the device instantly powers up to full power. There is no need for additional
delays to assure full operation and the very first conversion is valid.
0
1
Reserved
1
0
Reserved
1
1
No power-down between conversions, device always powered.
16 Clock Cycles Per Conversion
The control bits for conversion n+1 can be overlapped with conversion 'n' to allow for a conversion every 16
clock cycles, as shown in Figure 4. This figure also shows possible serial communication occurring with other
serial peripherals between each byte transfer between the processor and the converter. This is possible provided
that each conversion completes within 1.6ms of starting. Otherwise, the signal that has been captured on the
input sample-and-hold may droop enough to affect the conversion result. In addition, the ADS7841 is fully
powered while other serial communications are taking place.
CS
DCLK
8
1
DIN
1
8
S
1
8
1
S
CONTROL BITS
CONTROL BITS
BUSY
DOUT
A.
11 10 9
8
7
6
5
4
3
2
1
0
11 10 9
16 clock cycles per conversion, 8-bit bus interface. No DCLK delay required with dedicated serial port.
Figure 4. Conversion Timing
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Digital Timing
Figure 5, Table 6, and Table 7 provide detailed timing for the digital interface of the ADS7841.
CS
tCSS
tCL
tCH
tBD
tBD
tCSH
tD0
DCLK
tDH
tDS
DIN
PD0
tBDV
tBTR
BUSY
tDV
tTR
DOUT
11
10
Figure 5. Detailed Timing Diagram
Table 6. Timing Specifications, VCC = 2.7 V to 3.6 V, TA = –40°C to 85°C, CLOAD = 50 pF
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
tACQ
Acquisition time
1500
ns
tDS
DIN valid prior to DCLK rising
100
ns
tDH
DIN hold after DCLK high
10
ns
tDO
DCLK falling to DOUT valid
200
ns
tDV
CS falling to DOUT enabled
200
ns
tTR
CS rising to DOUT disabled
200
ns
tCSS
CS falling to first DCLK rising
tCSH
CS rising to DCLK ignored
100
ns
0
tCH
ns
DCLK high
200
ns
200
tCL
DCLK low
tBD
DCLK falling to BUSY rising
200
ns
ns
tBDV
CS falling to BUSY enabled
200
ns
tBTR
CS rising to BUSY disabled
200
ns
Table 7. Timing Specifications, VCC = 4.75 V to 5.25 V, TA = –40°C to 85°C, CLOAD = 50 pF
SYMBOL
14
DESCRIPTION
MIN
MAX
UNIT
tACQ
Acquisition time
900
ns
tDS
DIN valid prior to DCLK rising
50
ns
10
tDH
DIN hold after DCLK high
tDO
DCLK falling to DOUT valid
100
ns
ns
tDV
CS falling to DOUT enabled
70
ns
70
ns
tTR
CS rising to DOUT disabled
tCSS
CS falling to first DCLK rising
50
ns
tCSH
CS rising to DCLK ignored
0
ns
tCH
DCLK high
150
ns
150
tCL
DCLK low
tBD
DCLK falling to BUSY rising
100
ns
tBDV
CS falling to BUSY enabled
70
ns
tBTR
CS rising to BUSY disabled
70
ns
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15 Clock Cycles Per Conversion
Figure 6 provides the fastest way to clock the ADS7841. This method does not work with the serial interface of
most microcontrollers and digital signal processors as they are generally not capable of providing 15 clock cycles
per serial transfer. However, this method could be used with field programmable gate arrays (FPGAs) or
application specific integrated circuits (ASICs). Note that this effectively increases the maximum conversion rate
of the converter beyond the values given in the specification tables, which assume 16 clock cycles per
conversion.
CS
DCLK
15
1
DIN
S
SGL/
A2 A1 A0 MODE DIF PD1 PD0
1
S
15
SGL/
A2 A1 A0 MODE DIF PD1 PD0
1
S
A2
5
4
A1 A0
BUSY
DOUT
11 10
9
8
7
6
5
4
3
2
1
0
11 10
9
8
7
6
3
2
Figure 6. Maximum Conversion Rate, 15 Clock Cycles Per Conversion
Data Format
The ADS7841 output data is in straight binary format, as shown in Figure 7. This figure shows the ideal output
code for the given input voltage and does not include the effects of offset, gain, or noise.
FS = Full-Scale Voltage = VREF
1LSB = V REF/4096
1LSB
11...111
Output Code
11...110
11...101
00...010
00...001
00...000
FS – 1LSB
0V
Input Voltage (V) (see Note A)
A.
Voltage at converter input, after multiplexer: +IN – (–IN). See Figure 2.
Figure 7. Ideal Input Voltages and Output Codes
8-Bit Conversion
The ADS7841 provides an 8-bit conversion mode that can be used when faster throughput is needed and the
digital result is not as critical. By switching to the 8-bit mode, a conversion is complete four clock cycles earlier.
This could be used in conjunction with serial interfaces that provide a 12-bit transfer or two conversions could be
accomplished with three 8-bit transfers. Not only does this shorten each conversion by four bits (25% faster
throughput), but each conversion can actually occur at a faster clock rate. This is because the internal settling
time of the ADS7841 is not as critical, settling to better than 8 bits is all that is needed. The clock rate can be as
much as 50% faster. The faster clock rate and fewer clock cycles combine to provide a 2x increase in conversion
rate.
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Power Dissipation
There are three power modes for the ADS7841: full power (PD1-PD0 = 11b), auto power-down (PD1-PD0 =
00b), and shutdown (SHDN low). The affects of these modes varies depending on how the ADS7841 is being
operated. For example, at full conversion rate and 16 clocks per conversion, there is very little difference
between full power mode and auto power-down. Likewise, if the device has entered auto power-down, a
shutdown (SHDN low) does not lower power dissipation.
When operating at full-speed and 16-clocks per conversion (see Figure 4), the ADS7841 spends most of its time
acquiring or converting. There is little time for auto power-down, assuming that this mode is active. Thus, the
difference between full power mode and auto power-down is negligible. If the conversion rate is decreased by
simply slowing the frequency of the DCLK input, the two modes remain approximately equal. However, if the
DCLK frequency is kept at the maximum rate during a conversion, but conversion are simply done less often,
then the difference between the two modes is dramatic. Figure 8 shows the difference between reducing the
DCLK frequency ("scaling" DCLK to match the conversion rate) or maintaining DCLK at the highest frequency
and reducing the number of conversion per second. In the later case, the converter spends an increasing
percentage of its time in power-down mode (assuming the auto power-down mode is active).
1000
Supply Current (µA)
fCLK = 16 × f SAMPLE
100
fCLK = 2 MHz
10
TA = 25°C
VCC = 2.7 V
VREF = 2.5 V
PD1 = PD0 = 0
1
1k
10k
100k
1M
fSAMPLE (Hz)
A.
Directly scaling the frequency of DCLK with sample rate or keeping DCLK at the maximum possible frequency
Figure 8. Supply Current vs Sample Rate
If DCLK is active and CS is low while the ADS7841 is in auto power-down mode, the device continues to
dissipate some power in the digital logic. The power can be reduced to a minimum by keeping CS high. The
differences in supply current for these two cases are shown in Figure 9.
14
TA = 25° C
VCC = 2.7 V
VREF = 2.5 V
fCLK = 16 × f SAMPLE
PD1 = PD0 = 0
Supply Current (µA)
12
10
8
6
CS LOW
(GND)
4
2
CS HIGH (+VCC)
0
0.09
0.00
1k
10k
100k
1M
fSAMPLE (Hz)
A.
Varied with state of CS
Figure 9. Supply Current vs Sample Rate
16
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Operating the ADS7841 in auto power-down mode results in the lowest power dissipation, and there is no
conversion time "penalty" on power-up. The very first conversion is valid. SHDN can be used to force an
immediate power-down.
PCB Layout
For optimum performance, care should be taken with the physical layout of the ADS7841 circuitry. This is
particularly true if the reference voltage is low and/or the conversion rate is high.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, during
any single conversion for an n-bit SAR converter, there are n "windows" in which large external transient voltages
can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby
digital logic, and high power devices. The degree of error in the digital output depends on the reference voltage,
layout, and the exact timing of the external event. The error can change if the external event changes in time
with respect to the DCLK input.
With this in mind, power to the ADS7841 should be clean and well bypassed. A 0.1-μF ceramic bypass capacitor
should be placed as close to the device as possible. In addition, a 1-μF to 10-μF capacitor and a 5Ω or 10Ω
series resistor may be used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a 0.1-μF capacitor. Again, a series resistor and large capacitor
can be used to low-pass filter the reference voltage. If the reference voltage originates from an op amp, make
sure that it can drive the bypass capacitor without oscillation (the series resistor can help in this case). The
ADS7841 draws very little current from the reference on average, but it does place larger demands on the
reference circuitry over short periods of time (on each rising edge of DCLK during a conversion).
The ADS7841 architecture offers no inherent rejection of noise or voltage variation in regards to the reference
input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple
from the supply appears directly in the digital results. While high-frequency noise can be filtered out as discussed
in the previous paragraph, voltage variation due to line frequency (50 Hz or 60 Hz) can be difficult to remove.
The GND pin should be connected to a clean ground point. In many cases, this is the "analog" ground. Avoid
connections that are too near the grounding point of a microcontroller or digital signal processor. If needed, run a
ground trace directly from the converter to the power supply entry point. The ideal layout includes an analog
ground plane dedicated to the converter and associated analog circuitry.
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REVISION HISTORY
Changes from Revision B (September, 2011) to Revision C
•
18
Page
Deleted package column from Ordering Information table; changed top-side marking of ADS7841EIDBQRQ1 from
ADS7841E to S7841E and changed top-side marking for ADS7841ESQDBQRQ1 from ADS7841S to S7841S. .............. 2
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
ADS7841EIDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
ADS7841ESQDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
(4)
S7841E
-40 to 125
S7841S
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS7841-Q1 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
• Catalog: ADS7841
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Sep-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS7841EIDBQRQ1
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ADS7841ESQDBQRQ1
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Sep-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS7841EIDBQRQ1
SSOP
DBQ
16
2500
367.0
367.0
35.0
ADS7841ESQDBQRQ1
SSOP
DBQ
16
2500
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBQ0016A
SSOP - 1.75 mm max height
SCALE 2.800
SHRINK SMALL-OUTLINE PACKAGE
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
16
1
14X .0250
[0.635]
2X
.175
[4.45]
.189-.197
[4.81-5.00]
NOTE 3
8
9
B
.150-.157
[3.81-3.98]
NOTE 4
16X .008-.012
[0.21-0.30]
.007 [0.17]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
[0.11-0.25]
0 -8
.016-.035
[0.41-0.88]
(.041 )
[1.04]
DETAIL A
TYPICAL
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
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EXAMPLE BOARD LAYOUT
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SEE
DETAILS
SYMM
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
LAND PATTERN EXAMPLE
SCALE:8X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
.002 MAX
[0.05]
ALL AROUND
METAL
.002 MIN
[0.05]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635]
9
8
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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