Texas Instruments | 8-Bit, 8-Channel Sampling Analog-to-Digital Converter with I²C Interface (Rev. C) | Datasheet | Texas Instruments 8-Bit, 8-Channel Sampling Analog-to-Digital Converter with I²C Interface (Rev. C) Datasheet

Texas Instruments 8-Bit, 8-Channel Sampling Analog-to-Digital Converter with I²C Interface (Rev. C) Datasheet
ADS7830
www.ti.com
SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012
8-Bit, 8-Channel Sampling
ANALOG-TO-DIGITAL CONVERTER
with I2C™ Interface
Check for Samples: ADS7830
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
1
23
•
•
•
70kHz SAMPLING RATE
±0.5LSB INL/DNL
8 BITS NO MISSING CODES
4 DIFFERENTIAL/8 SINGLE-ENDED INPUTS
2.7V TO 5V OPERATION
BUILT-IN 2.5V REFERENCE/BUFFER
SUPPORTS ALL THREE I2C MODES:
Standard, Fast, and High-Speed
LOW POWER:
180μW (Standard Mode)
300μW (Fast Mode)
675μW (High-Speed Mode)
DIRECT PIN COMPATIBLE WITH ADS7828
TSSOP-16 PACKAGE
VOLTAGE-SUPPLY MONITORING
ISOLATED DATA ACQUISITION
TRANSDUCER INTERFACE
BATTERY-OPERATED SYSTEMS
REMOTE DATA ACQUISITION
DESCRIPTION
The ADS7830 is a single-supply, low-power, 8-bit
data acquisition device that features a serial I2C
interface and an 8-channel multiplexer. The Analogto-Digital (A/D) converter features a sample-and-hold
amplifier and internal, asynchronous clock. The
combination of an I2C serial, 2-wire interface and
micropower consumption makes the ADS7830 ideal
for applications requiring the A/D converter to be
close to the input source in remote locations and for
applications requiring isolation. The ADS7830 is
available in a TSSOP-16 package.
CH0
SAR
CH1
CH2
CH3
CH4
8-Channel
MUX
CH5
SDA
CH6
SCL
CH7
CDAC
Serial
Interface
COM
A0
S/H Amp
Comparator
A1
2.5V VREF
REFIN/REFOUT
Buffer
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I C is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
2
2
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2012, Texas Instruments Incorporated
ADS7830
SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
PRODUCT
MAXIMUM
INTEGRAL
LINEARITY ERROR
(LSB)
ADS7830I
±0.5
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
TSSOP-16
PW
–40°C to +125°C
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS7830IPWT
Tape and Reel, 250
ADS7830IPWR
Tape and Reel, 2500
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
–0.3 to +6
V
–0.3 to +VDD + 0.3
V
Operating Temperature Range
–40 to +125
°C
Storage Temperature Range
–65 to +150
°C
+150
°C
+VDD to GND
Digital Input Voltage to GND
Junction Temperature (TJ max)
TSSOP Package
Power Dissipation
(TJ max – TA)/θJA
θJA Thermal Impedance
(1)
240
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
PIN DESCRIPTIONS
PIN CONFIGURATION
PW PACKAGE
TSSOP-16
(Top View)
PIN
NAME
DESCRIPTION
1
CH0
Analog Input Channel 0
2
CH1
Analog Input Channel 1
3
CH2
Analog Input Channel 2
4
CH3
Analog Input Channel 3
CH0
1
16
+VDD
5
CH4
Analog Input Channel 4
CH1
2
15
SDA
6
CH5
Analog Input Channel 5
7
CH6
Analog Input Channel 6
8
CH7
Analog Input Channel 7
9
GND
Analog Ground
CH2
3
14
SCL
CH3
4
13
A1
CH4
5
12
A0
10
REFIN /
REFOUT
CH5
6
11
COM
11
COM
CH6
7
10
REFIN / REFOUT
12
A0
Slave Address Bit 0
GND
13
A1
Slave Address Bit 1
14
SCL
Serial Clock
15
SDA
Serial Data
16
+VDD
CH7
2
°C/W
8
9
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Internal +2.5V Reference, External Reference Input
Common to Analog Input Channel
Power Supply, 3.3V Nominal
Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Links: ADS7830
ADS7830
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SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012
ELECTRICAL CHARACTERISTICS: +2.7V
At TA = –40°C to +125°C, +VDD = +2.7V, VREF = +2.5V, and SCL Clock Frequency = 3.4MHz (High-Speed Mode), unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-Scale Input Scan
Absolute Input Range
Positive Input – Negative Input
0
VREF
V
Positive Input
–0.2
+VDD + 0.2
V
Negative Input
–0.2
+0.2
V
Capacitance
25
pF
Leakage Current
±1
µA
SYSTEM PERFORMANCE
No Missing Codes
8
Bits
±0.1
±0.5
LSB (1)
Differential Linearity Error
±0.1
±0.5
LSB
Offset Error
+0.5
+1
LSB
Offset Error Match
±0.05
±0.25
LSB
Gain Error
±0.1
±0.5
LSB
Gain Error Match
±0.05
±0.25
Integral Linearity Error
LSB
Noise
100
µVRMS
Power-Supply Rejection
72
dB
SAMPLING DYNAMICS
70
kSPS (2)
Fast Mode: SCL = 400kHz
10
kSPS
Standard Mode, SCL = 100kHz
2.5
kSPS
High-Speed Mode: SCL = 3.4MHz
Throughput Frequency
Conversion Time
5
µs
AC ACCURACY
Total Harmonic Distortion
VIN = 2.5VPP at 1kHz
–72
dB (3)
Signal-to-Ratio
VIN = 2.5VPP at 1kHz
50
dB
Signal-to-(Noise+Distortion) Ratio
VIN = 2.5VPP at 1kHz
49
dB
Spurious-Free Dynamic Range
VIN = 2.5VPP at 1kHz
68
dB
90
dB
Isolation Channel-to-Channel
VOLTAGE REFERENCE OUTPUT
Range
Internal Reference Drift
Output Impedance
Quiescent Current
TA = –40°C to +85°C
2.48
2.52
TA = –40°C to +125°C
2.47
2.53
TA = –40°C to +85°C
V
V
15
ppm/°C
ppm/°C
TA = –40°C to +125°C
40
Internal Reference ON
110
Ω
Internal Reference OFF
1
GΩ
Internal Reference ON,
SCL and SDA pulled HIGH
850
µA
VOLTAGE REFERENCE INPUT
Range
0.05
Resistance
Current Drain
(1)
(2)
(3)
High-Speed Mode: SCL= 3.4MHz
VDD
V
1
GΩ
20
µA
LSB means least significant bit. When VREF = 2.5V, 1LSB is 9.8mV.
kSPS means kilo samples-per-second.
THD measured out to the 9th-harmonic.
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ADS7830
SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: +2.7V (continued)
At TA = –40°C to +125°C, +VDD = +2.7V, VREF = +2.5V, and SCL Clock Frequency = 3.4MHz (High-Speed Mode), unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
CMOS
VIH
+VDD × 0.7
+VDD + 0.5
V
VIL
–0.3
+VDD × 0.3
V
0.4
V
10
µA
VOL
Input Leakage
Minimum 3mA Sink Current
IIH
VIH = +VDD + 0.5V
IIL
VIL = –0.3V
–10
Data Format
µA
Straight Binary
ADS7830 HARDWARE ADDRESS (10010 Binary)
Power-Supply Requirements
Power-Supply Voltage, +VDD
Quiescent Current
Power Dissipation
Power-Down Mode
Power-Down Mode with Wrong Address Selected
Full Power-Down
Specified Performance
2.7
High-Speed Mode: SCL = 3.4MHz
225
Fast Mode: SCL = 400kHz
100
Standard Mode, SCL = 100kHz
60
High-Speed Mode: SCL = 3.4MHz
675
3.6
V
320
µA
µA
µA
1000
µW
Fast Mode: SCL = 400kHz
300
µW
Standard Mode, SCL = 100kHz
180
µW
High-Speed Mode: SCL = 3.4MHz
70
µA
µA
Fast Mode: SCL = 400kHz
25
Standard Mode, SCL = 100kHz
6
SCL Pulled HIGH, SDA Pulled HIGH
400
µA
3000
nA
+125
°C
TEMPERATURE RANGE
Specified Performance
4
–40
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Product Folder Links: ADS7830
ADS7830
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SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012
ELECTRICAL CHARACTERISTICS: +5V
At TA = –40°C to +125°C, +VDD = +5.0V, VREF = External +5.0V, and SCL Clock Frequency = 3.4MHz (High-Speed Mode),
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-Scale Input Scan
Absolute Input Range
Positive Input – Negative Input
0
VREF
V
Positive Input
–0.2
+VDD + 0.2
V
Negative Input
–0.2
+0.2
V
Capacitance
25
pF
Leakage Current
±1
µA
SYSTEM PERFORMANCE
No Missing Codes
8
Bits
±0.1
±0.5
LSB (1)
Differential Linearity Error
±0.1
±0.5
LSB
Offset Error
+0.5
+1
LSB
Offset Error Match
±0.05
±0.25
LSB
Gain Error
±0.1
±0.5
LSB
Gain Error Match
±0.05
±0.25
Integral Linearity Error
LSB
Noise
100
µVRMS
Power-Supply Rejection
72
dB
SAMPLING DYNAMICS
70
kSPS (2)
Fast Mode: SCL = 400kHz
10
kSPS
Standard Mode, SCL = 100kHz
2.5
kSPS
High-Speed Mode: SCL = 3.4MHz
Throughput Frequency
Conversion Time
5
µs
AC ACCURACY
Total Harmonic Distortion
VIN = 5VPP at 1kHz
–72
dB (3)
Signal-to-Ratio
VIN = 5VPP at 1kHz
50
dB
Signal-to-(Noise+Distortion) Ratio
VIN = 5VPP at 1kHz
49
dB
Spurious-Free Dynamic Range
VIN = 5VPP at 1kHz
68
dB
90
dB
Isolation Channel-to-Channel
VOLTAGE REFERENCE OUTPUT
Range
Internal Reference Drift
Output Impedance
Quiescent Current
TA = –40°C to +85°C
2.48
2.52
TA = –40°C to +125°C
2.47
2.53
TA = –40°C to +85°C
V
V
15
ppm/°C
ppm/°C
TA = –40°C to +125°C
40
Internal Reference ON
110
Ω
Internal Reference OFF
1
GΩ
Internal Reference ON,
SCL and SDA pulled HIGH
1300
µA
VOLTAGE REFERENCE INPUT
Range
0.05
Resistance
Current Drain
(1)
(2)
(3)
High-Speed Mode: SCL= 3.4MHz
VDD
V
1
GΩ
20
µA
LSB means least significant bit. When VREF = 2.5V, 1LSB is 9.8mV.
kSPS means kilo samples-per-second.
THD measured out to the 9th-harmonic.
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ADS7830
SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012
www.ti.com
ELECTRICAL CHARACTERISTICS: +5V (continued)
At TA = –40°C to +125°C, +VDD = +5.0V, VREF = External +5.0V, and SCL Clock Frequency = 3.4MHz (High-Speed Mode),
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
CMOS
VIH
+VDD × 0.7
+VDD + 0.5
V
VIL
–0.3
+VDD × 0.3
V
0.4
V
10
µA
VOL
Input Leakage
Minimum 3mA Sink Current
IIH
VIH = +VDD + 0.5V
IIL
VIL = –0.3V
–10
Data Format
µA
Straight Binary
ADS7830 HARDWARE ADDRESS (10010 Binary)
Power-Supply Requirements
Power-Supply Voltage, +VDD
Quiescent Current
Power Dissipation
Power-Down Mode
Power-Down Mode with Wrong Address Selected
Full Power-Down
Specified Performance
4.75
5
5.25
V
High-Speed Mode: SCL = 3.4MHz
750
1000
µA
Fast Mode: SCL = 400kHz
300
Standard Mode, SCL = 100kHz
150
High-Speed Mode: SCL = 3.4MHz
3.75
µA
µA
5
mW
Fast Mode: SCL = 400kHz
1.5
mW
Standard Mode, SCL = 100kHz
0.75
mW
High-Speed Mode: SCL = 3.4MHz
400
µA
µA
Fast Mode: SCL = 400kHz
150
Standard Mode, SCL = 100kHz
35
SCL Pulled HIGH, SDA Pulled HIGH
400
µA
3000
nA
+125
°C
TEMPERATURE RANGE
Specified Performance
6
–40
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Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Links: ADS7830
ADS7830
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SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012
TIMING DIAGRAM
SDA
tBUF
tLOW
tF
tR
tSP
tHD; STA
SCL
tHD; STA
tSU; STA
tHD; DAT
STOP
START
tHIGH
tSU; STO
tSU; DAT
REPEATED
START
TIMING CHARACTERISTICS (1)
At TA = –40°C to +125°C and +VDD = +2.7V, unless otherwise noted.
PARAMETER
SCL Clock Frequency
Bus Free Time Between a STOP
and START Condition
Hold Time (Repeated) START
Condition
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Setup Time
(1)
(2)
SYMBOL
fSCL
tBUF
tHD; STA
tLOW
tHIGH
tSU; STA
tSU; DAT
CONDITIONS
MIN
MAX
UNIT
Standard Mode
100
kHz
Fast Mode
400
kHz
High-Speed Mode, CB = 100pF max
3.4
MHz
High-Speed Mode, CB = 400pF max
1.7
MHz
Standard Mode
4.7
µs
Fast Mode
1.3
µs
Standard Mode
4.0
µs
ns
Fast Mode
600
High-Speed Mode
160
ns
Standard Mode
4.7
µs
Fast Mode
1.3
µs
High-Speed Mode, CB = 100pF max (2)
160
ns
High-Speed Mode, CB = 400pF max (2)
320
ns
Standard Mode
4.0
µs
Fast Mode
600
ns
High-Speed Mode, CB = 100pF max (2)
60
ns
High-Speed Mode, CB = 400pF max (2)
120
ns
Standard Mode
4.7
µs
Fast Mode
600
ns
High-Speed Mode
160
ns
Standard Mode
250
ns
Fast Mode
100
ns
High-Speed Mode
10
ns
All values referred to VIHMIN and VILMAX levels.
For bus line loads CB between 100pF and 400pF the timing parameters must be linearly interpolated.
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ADS7830
SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012
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TIMING CHARACTERISTICS(1) (continued)
At TA = –40°C to +125°C and +VDD = +2.7V, unless otherwise noted.
PARAMETER
Data Hold Time
SYMBOL
tHD; DAT
CONDITIONS
MIN
MAX
UNIT
Standard Mode
0
3.45
µs
Fast Mode
0
0.9
µs
High-Speed Mode, CB = 100pF max (3)
0 (4)
70
ns
High-Speed Mode, CB = 400pF max (3)
0 (4)
150
ns
Standard Mode
Rise Time of SCL Signal
tRCL
1000
ns
Fast Mode
20 + 0.1CB
300
ns
High-Speed Mode, CB = 100pF max (3)
10
40
ns
(3)
20
High-Speed Mode, CB = 400pF max
Standard Mode
Rise Time of SCL Signal After a
Repeated START Condition and
After an Acknowledge Bit
tRCL1
Fast Mode
20 + 0.1CB
tFCL
tRDA
Setup Time for STOP Condition
tFDA
tSU; STO
Capacitive Load for SDA and
SCL Line
CB
Pulse Width of Spike Suppressed
tSP
Noise Margin at the HIGH Level
for Each Connected Device
(Including Hysteresis)
VNH
Noise Margin at the LOW Level
for Each Connected Device
(Including Hysteresis)
VNL
(3)
(4)
8
ns
10
80
ns
20
160
ns
300
ns
20 + 0.1CB
300
ns
(3)
10
40
ns
High-Speed Mode, CB = 400pF max (3)
20
80
ns
1000
ns
Fast Mode
High-Speed Mode, CB = 100pF max
Fast Mode
20 + 0.1CB
300
ns
High-Speed Mode, CB = 100pF max (3)
10
80
ns
High-Speed Mode, CB = 400pF max (3)
20
160
ns
Standard Mode
Fall Time of SDA Signal
ns
300
High-Speed Mode, CB = 400pF max (3)
High-Speed Mode, CB = 100pF max
Standard Mode
Rise Time of SDA Signal
ns
(3)
Standard Mode
Fall Time of SCL Signal
80
1000
300
ns
Fast Mode
20 + 0.1CB
300
ns
High-Speed Mode, CB = 100pF max (3)
10
80
ns
High-Speed Mode, CB = 400pF max (3)
20
160
ns
Standard Mode
4.0
µs
Fast Mode
600
ns
High-Speed Mode
160
ns
400
pF
Fast Mode
50
ns
High-Speed Mode
10
ns
Standard Mode
0.2VDD
V
Fast Mode
0.2VDD
V
High-Speed Mode
0.2VDD
V
Standard Mode
0.1VDD
V
Fast Mode
0.1VDD
V
High-Speed Mode
0.1VDD
V
For bus line loads CB between 100pF and 400pF the timing parameters must be linearly interpolated.
A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
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SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012
TYPICAL CHARACTERISTICS
At TA = +25°C, VDD = +2.7V, VREF = External +2.5V, and fSAMPLE = 50kHz, unless otherwise noted.
INTEGRAL LINEARITY ERROR vs CODE
(2.5V Internal Reference)
FFT vs FREQUENCY
0.5
0
0.4
0.3
0.2
ILE (LSB)
Amplitude (dB)
-20
-40
-60
0.1
0
-0.1
-0.2
-0.3
-80
-0.4
-0.5
-100
0
10
20
25
0
64
128
Output Code
192
255
Figure 1.
Figure 2.
DIFFERENTIAL LINEARITY ERROR vs CODE
(2.5V Internal Reference)
INTEGRAL LINEARITY ERROR vs CODE
(2.5V External Reference)
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
ILE (LSB)
ILE (LSB)
Frequency (kHz)
0
-0.1
0
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
-0.5
-0.5
0
64
128
Output Code
192
0
255
64
128
Output Code
Figure 3.
192
255
Figure 4.
DIFFERENTIAL LINEARITY ERROR vs CODE
(2.5V External Reference)
CHANGE IN OFFSET vs TEMPERATURE
0.5
0.10
0.4
Delta from 25°C (LSB)
0.3
ILE (LSB)
0.2
0.1
0
-0.1
-0.2
0.05
0
-0.05
-0.3
-0.4
-0.10
-0.5
0
64
128
Output Code
192
255
-50
-25
0
25
50
75
100
Temperature (°C)
Figure 5.
Figure 6.
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ADS7830
SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VDD = +2.7V, VREF = External +2.5V, and fSAMPLE = 50kHz, unless otherwise noted.
CHANGE IN GAIN vs TEMPERATURE
INTERNAL REFERENCE vs TEMPERATURE
0.10
2.51875
Internal Reference (V)
Delta from 25°C (LSB)
2.51250
0.05
0
-0.05
2.50625
2.50000
2.49375
2.48750
2.48125
-0.10
-50
0
-25
25
50
75
100
-50
0
-25
Temperature (°C)
Figure 7.
400
600
350
Supply Current (mA)
Supply Current (nA)
75
100
SUPPLY CURRENT vs TEMPERATURE
750
450
300
150
300
250
200
150
0
100
-150
-50
-25
0
25
50
75
100
125
-50
0
-25
25
50
75
100
Temperature (°C)
Temperature (°C)
Figure 9.
Figure 10.
SUPPLY CURRENT vs I2C BUS RATE
INTERNAL VREF vs TURN-ON TIME
100
300
250
No Cap
(37ms)
8-Bit Settling
80
Internal VREF (%)
Supply Current (mA)
50
Figure 8.
POWER-DOWN SUPPLY CURRENT
vs TEMPERATURE
200
150
100
1mF Cap
(930ms)
8-Bit Settling
60
40
20
50
0
0
10
100
1k
10k
0
2
200
400
600
800
1000
1200
1400
Turn-On Time (ms)
I C Bus Rate (KHz)
Figure 11.
10
25
Temperature (°C)
Figure 12.
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SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012
THEORY OF OPERATION
REFERENCE
The ADS7830 is a classic Successive Approximation
Register (SAR) A/D converter. The architecture is
based on capacitive redistribution which inherently
includes a sampleand- hold function. The converter is
fabricated on a 0.6µ CMOS process.
The ADS7830 can operate with an internal 2.5V
reference or an external reference. If a +5V supply is
used, an external +5V reference is required in order
to provide full dynamic range for a 0V to +VDD analog
input. This external reference can be as low as
50mV. When using a +2.7V supply, the internal +2.5V
reference will provide full dynamic range for a 0V to
+VDD analog input.
The ADS7830 core is controlled by an internally
generated free-running clock. When the ADS7830 is
not performing conversions or being addressed, it
keeps the A/D converter core powered off, and the
internal clock does not operate.
As the reference voltage is reduced, the analog
voltage weight of each digital output code is reduced.
This is often referred to as the LSB (least significant
bit) size and is equal to the reference voltage divided
by 256. This means that any offset or gain error
inherent in the A/D converter will appear to increase,
in terms of LSB size, as the reference voltage is
reduced.
The simplified diagram of input and output for the
ADS7830 is shown in Figure 13.
ANALOG INPUT
When the converter enters the hold mode, the
voltage on the selected CHx pin is captured on the
internal capacitor array. The input current on the
analog inputs depends on the conversion rate of the
device. During the sample period, the source must
charge the internal sampling capacitor (typically
25pF). After the capacitor has been fully charged,
there is no further input current. The amount of
charge transfer from the analog source to the
converter is a function of conversion rate.
The noise inherent in the converter will also appear to
increase with lower LSB size. With a 2.5V reference,
the internal noise of the converter typically contributes
only 0.02LSB peak-to-peak of potential error to the
output code. When the external reference is 50mV,
the potential error contribution from the internal noise
will be 50 times larger—1LSB. The errors due to the
internal noise are Gaussian in nature and can be
reduced by averaging consecutive conversion results.
+2.7V to +3.6V
5W
+ 1mF to
10mF
0.1mF
REFIN/
REFOUT
SDA
CH1
SCL
CH4
2kW
+ 1mF to
10mF
CH0
CH2 ADS7830
CH3
2kW
VDD
Microcontroller
A0
A1
GND
CH5
CH6
CH7
COM
Figure 13. Simplified I/O of the ADS7830
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ADS7830
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DIGITAL INTERFACE
The ADS7830 supports the I2C serial bus and data
transmission protocol, in all three defined modes:
standard, fast, and high-speed. A device that sends
data onto the bus is defined as a transmitter, and a
device receiving data as a receiver. The device that
controls the message is called a “master.” The
devices that are controlled by the master are “slaves.”
The bus must be controlled by a master device that
generates the serial clock (SCL), controls the bus
access, and generates the START and STOP
conditions. The ADS7830 operates as a slave on the
I2C bus. Connections to the bus are made via the
open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (as
shown in Figure 14):
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as control signals.
Accordingly, the following bus conditions have been
defined:
Bus Not Busy: Both data and clock lines remain
HIGH.
Start Data Transfer: A change in the state of the
data line, from HIGH to LOW, while the clock is
HIGH, defines a START condition.
Stop Data Transfer: A change in the state of the
data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data Valid: The state of the data line represents valid
data, when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock
signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number
of data bytes transferred between START and STOP
conditions is not limited and is determined by the
master device. The information is transferred bytewise and each receiver acknowledges with a ninth-bit.
Within the I2C bus specifications a standard mode
(100kHz clock rate), a fast mode (400kHz clock rate),
and a highspeed mode (3.4MHz clock rate) are
defined. The ADS7830 works in all three modes.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device
must generate an extra clock pulse that is associated
with this acknowledge bit.
12
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that
has been clocked out of the slave. In this case, the
slave must leave the data line HIGH to enable the
master to generate the STOP condition.
Figure 14 details how data transfer is accomplished
on the I2C bus. Depending upon the state of the R/W
bit, two types of data transfer are possible:
1. Data transfer from a master transmitter to a
slave receiver. The first byte transmitted by the
master is the slave address. Next follows a
number of data bytes. The slave returns an
acknowledge bit after the slave address and each
received byte.
2. Data transfer from a slave transmitter to a
master receiver. The first byte, the slave
address, is transmitted by the master. The slave
then returns an acknowledge bit. Next, a number
of data bytes are transmitted by the slave to the
master. The master returns an acknowledge bit
after all received bytes other than the last byte. At
the end of the last received byte, a notacknowledge is returned.
The master device generates all of the serial clock
pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or a
repeated START condition. Since a repeated START
condition is also the beginning of the next serial
transfer, the bus will not be released.
The ADS7830 may operate in the following two
modes:
• Slave Receiver Mode: Serial data and clock are
received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted.
START and STOP conditions are recognized as
the beginning and end of a serial transfer.
Address recognition is performed by hardware
after reception of the slave address and direction
bit.
• Slave Transmitter Mode: The first byte (the slave
address) is received and handled as in the slave
receiver mode. However, in this mode the
direction bit will indicate that the transfer direction
is reversed. Serial data is transmitted on SDA by
the ADS7830 while the serial clock is input on
SCL. START and STOP conditions are
recognized as the beginning and end of a serial
transfer.
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SDA
MSB
Slave Address
R/W
Direction
Bit
Acknowledgement
Signal from
Receiver
Acknowledgement
Signal from
Receiver
1
SCL
2
6
7
8
9
1
2
3-8
8
9
ACK
ACK
START
Condition
STOP Condition
or Repeated
START Condition
Repeated If More Bytes Are Transferred
Figure 14. Basic Operation of the ADS7830
Address Byte
Command Byte
MSB
6
5
4
3
2
1
LSB
MSB
6
5
4
3
2
1
LSB
1
0
0
1
0
A1
A0
R/W
SD
C2
C1
C0
PD1
PD0
X
X
The address byte is the first byte received following
the START condition from the master device. The
first five bits (MSBs) of the slave address are factory
pre-set to 10010. The next two bits of the address
byte are the device select bits, A1 and A0. Input pins
(A1-A0) on the ADS7830 determine these two bits of
the device address for a particular ADS7830. A
maximum of four devices with the same pre-set code
can therefore be connected on the same bus at one
time.
The A1-A0 Address Inputs can be connected to VDD
or digital ground. The device address is set by the
state of these pins upon power-up of the ADS7830.
The last bit of the address byte (R/W) defines the
operation to be performed. When set to a ‘1’ a read
operation is selected; when set to a ‘0’ a write
operation is selected. Following the START condition
the ADS7830 monitors the SDA bus, checking the
device type identifier being transmitted. Upon
receiving the 10010 code, the appropriate device
select bits, and the R/W bit, the slave device outputs
an acknowledge signal on the SDA line.
The ADS7830 operating mode is determined by a
command byte which is illustrated above.
SD: Single-Ended/Differential Inputs
0: Differential Inputs
1: Single-Ended Inputs
C2 - C0: Channel Selections
PD1: Power-Down
0: Power-Down Selection
X: Unused
See Table 1 for a power-down selection summary.
See Table 2 for a channel selection control summary.
Table 1. Power-Down Selection
PD1
PD0
0
0
Power Down Between A/D Converter Conversions
DESCRIPTION
0
1
Internal Reference OFF and A/D Converter ON
1
0
Internal Reference ON and A/D Converter OFF
1
1
Internal Reference ON and A/D Converter ON
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ADS7830
SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012
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Table 2. Channel Selection Control Addressed by Command BYTE
CHANNEL SELECTION CONTROL
SD
C2
C1
C0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
0
0
0
0
+IN
–IN
—
—
—
—
—
—
—
0
0
0
1
—
—
+IN
–IN
—
—
—
—
—
0
0
1
0
—
—
—
—
+IN
–IN
—
—
—
0
0
1
1
—
—
—
—
—
—
+IN
–IN
—
0
1
0
0
–IN
+IN
—
—
—
—
—
—
—
0
1
0
1
—
—
–IN
+IN
—
—
—
—
—
0
1
1
0
—
—
—
—
–IN
+IN
—
—
—
0
1
1
1
—
—
—
—
—
—
–IN
+IN
—
1
0
0
0
+IN
—
—
—
—
—
—
—
–IN
1
0
0
1
—
—
+IN
—
—
—
—
—
–IN
1
0
1
0
—
—
—
—
+IN
—
—
—
–IN
1
0
1
1
—
—
—
—
—
—
+IN
—
–IN
1
1
0
0
—
+IN
—
—
—
—
—
—
–IN
1
1
0
1
—
—
—
+IN
—
—
—
—
–IN
1
1
1
0
—
—
—
—
—
+IN
—
—
–IN
1
1
1
1
—
—
—
—
—
—
—
+IN
–IN
INITIATING CONVERSION
READING DATA
Provided the master has write-addressed it, the
ADS7830 turns on the A/D converter section and
begins conversions when it receives BIT 4 of the
command byte shown in the Command Byte. If the
command byte is correct, the ADS7830 will return an
ACK condition.
Data can be read from the ADS7830 by readaddressing the part (LSB of address byte set to ‘1’)
and receiving the transmitted byte. Converted data
can only be read from the ADS7830 once a
conversion has been initiated as described in the
preceding section.
Each 8-bit data word is returned in one byte, as
shown below, where D7 is the MSB of the data word,
and D0 is the LSB.
DATA
14
MSB
6
5
4
3
2
1
LSB
D7
D6
D5
D4
D3
D2
D1
D0
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READING IN F/S MODE
At the end of reading conversion data the ADS7830
can be issued a repeated START condition by the
master to secure bus operation for subsequent
conversions of the A/D converter. This would be the
most efficient way to perform continuous conversions.
Figure 15 describes the interaction between the
master and the slave ADS7830 in Fast or Standard
(F/S) mode.
ADC Power-Down Mode
S
1
0
0
1
0
A1
A0
W
A
ADC Sampling Mode
SD C2
0
0
1
0
A1
X
A
ADC Power-Down Mode
(depending on power-down selection bits)
ADC Converting Mode
1
C0 PD1 PD0 X
Command Byte
Write-Addressing Byte
Sr
C1
A0
R
A
D7
D6
D5 D4
D3
D2
D1
D0
N
P
See Note (1)
Read-Addressing Byte
From Master to Slave
From Slave to Master
1 x (8 Bits + not-ack)
A = acknowledge (SDA LOW)
N = not acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
Sr = repeated START condition
W = '0' (WRITE)
R = '1' (READ)
(1) To secure bus operation and loop back to the stage of write-addressing for next conversion, use repeated START.
Figure 15. Typical Read Sequence in F/S Mode
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ADS7830
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READING IN HS MODE
See Figure 16 for a typical read sequence for HS
mode. Included in the read sequence is the shift from
F/S to HS modes. It may be desirable to remain in
HS mode after reading a conversion; to do this, issue
a repeated START instead of a STOP at the end of
the read sequence, since a STOP causes the part to
return to F/S mode.
High Speed (HS) mode is fast enough that codes can
be read out one at a time. In HS mode, there is not
enough time for a single conversion to complete
between the reception of a repeated START condition
and the read-addressing byte, so the ADS7830
stretches the clock after the read-addressing byte has
been fully received, holding it LOW until the
conversion is complete.
F/S Mode
S
0
0
0
0
1
X
X
X
N
HS Mode Master Code
HS Mode Enabled
ADC Power-Down Mode
Sr
1
0
0
1
0
A1
A0
W
A
ADC Sampling Mode
SD
C2 C1
Write-Addressing Byte
C0 PD1 PD0 X
X
A
Command Byte
HS Mode Enabled
ADC Converting Mode
Sr
1
0
0
1
0
A1
A0
R
A
SCLH
(2)
is stretched LOW waiting for data conversion
Read-Addressing Byte
HS Mode Enabled
Return to F/S Mode
(1)
ADC Power-Down Mode
(depending on power-down selection bits)
D7
D6
D5
D4
D3
D2
D1
D0
N
P
1 x (8 Bits + not-ack)
A = acknowledge (SDA LOW)
N = not acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
Sr = repeated START condition
From Master to Slave
From Slave to Master
W = '0' (WRITE)
R = '1' (READ)
(1) To remain in HS mode, use repeated START instead of STOP.
(2) SCLH is SCL in HS mode.
Figure 16. Typical Read Sequence in HS Mode
16
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READING WITH REFERENCE ON/OFF
The internal reference defaults to off when the
ADS7830 power is on. To turn the internal reference
on or off, see Table 1. If the reference (internal or
external) is constantly turned on and off, a proper
amount of settling time must be added before a
normal conversion cycle can be started. The exact
amount of settling time needed varies depending on
the configuration.
See Figure 17 for an example of the proper internal
reference turn-on sequence before issuing the typical
read sequences required for the F/S mode when an
internal reference is used.
When using an internal reference, there are three
things that must be done:
1. In order to use the internal reference, the PD1 bit
of Command Byte must always be set to logic ‘1’
for each sample conversion that is issued by the
sequence, as shown in Figure 15.
2. In order to achieve 8-bit accuracy conversion
when using the internal reference, the internal
reference settling time must be considered, as
shown in the Internal VREF vs Turn-On Time
Typical Characteristic plot. If the PD1 bit has
been set to logic ‘0’ while using the ADS7830,
then the settling time must be reconsidered after
PD1 is set to logic ‘1’. In other words, whenever
the internal reference is turned on after it has
been turned off, the settling time must be long
enough to get 8-bit accuracy conversion.
3. When the internal reference is off, it is not turned
on until both the first Command Byte with PD1 =
‘1’ is sent and then a STOP condition or repeated
START condition is issued. (The actual turn-on
time occurs once the STOP or repeated START
condition is issued.) Any Command Byte with
PD1 = ‘1’ issued after the internal reference is
turned on serves only to keep the internal
reference on. Otherwise, the internal reference
would be turned off by any Command Byte with
PD1 = ‘0’.
The example in Figure 17 can be generalized for a
HS mode conversion cycle by simply swapping the
timing of the conversion cycle.
If using an external reference, PD1 must be set to ‘0’,
and the external reference must be settled. The
typical sequence in Figure 15 or Figure 16 can then
be used.
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ADS7830
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Internal Reference
Turn-On
Settling Time
Internal Reference Turn-On Sequence
S
1
0
0
1
0
A1
A0
W
A
X
X
Write-Addressing Byte
X
X
1
X
X
X
A
P
Command Byte
Typical Read
Settled Internal Reference
(1)
ADC Power-Down Mode
S
1
0
0
1
0
A1
Wait until the required
settling time is reached
A0
W
A
ADC Sampling Mode
SD C2
Write-Addressing Byte
C1
C0
1
PD0
X
X
Sequence
in F/S Mode
A
Command Byte
Settled Internal Reference
ADC Power-Down Mode
(depending on power-down selection bits)
ADC Converting Mode
Sr
1
0
0
1
0
A1
A0
R
A
D7
D6
D5
D4
D3
D2 D1
D0
N
P
See Note (2)
Read-Addressing Byte
From Master to Slave
From Slave to Master
1 x (8 Bits + not-ack)
A = acknowledge (SDA LOW)
N = not acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
Sr = repeated START condition
W = '0' (WRITE)
R = '1' (READ)
(1) Typical read sequences can be reused after the internal reference is settled.
(2) To secure bus operation and loop back to the stage of write-addressing for next conversion, use repeated START.
Figure 17. Internal Reference Turn-On Sequence and Typical Read Sequence (F/S mode shown)
LAYOUT
For optimum performance, care should be taken with
the physical layout of the ADS7830 circuitry. The
basic SAR architecture is sensitive to glitches or
sudden changes on the power supply, reference,
ground connections, and digital inputs that occur just
prior to latching the output of the analog comparator.
Therefore, during any single conversion for an “n-bit”
SAR converter, there are n “windows” in which large
external transient voltages can easily affect the
conversion result. Such glitches might originate from
switching power supplies, nearby digital logic, and
high-power devices.
With this in mind, power to the ADS7830 should be
clean and well-bypassed. A 0.1μF ceramic bypass
capacitor should be placed as close to the device as
possible. A 1μF to 10μF capacitor may also be
needed if the impedance of the connection between
+VDD and the power supply is high.
18
The ADS7830 architecture offers no inherent
rejection of noise or voltage variation in regards to
using an external reference input. This is of particular
concern when the reference input is tied to the power
supply. Any noise and ripple from the supply will
appear directly in the digital results. While highfrequency noise can be filtered out, voltage variation
due to line frequency (50Hz or 60Hz) can be difficult
to remove.
The GND pin should be connected to a clean ground
point. In many cases, this will be the “analog” ground.
Avoid connections that are too near the grounding
point of a microcontroller or digital signal processor.
The ideal layout will include an analog ground plane
dedicated to the converter and associated analog
circuitry.
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SBAS302C – DECEMBER 2003 – REVISED OCTOBER 2012
REVISION HISTORY
Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2008) to Revision C
Page
•
Extended specified temperature range from –40°C to +85°C to –40°C to +125°C throughout document .......................... 1
•
Changed operating temperature range maxmimum value in Absolute Maximum Ratings table ......................................... 2
•
Changed Voltage Reference Output, Range and Internal Reference Drift parameters in 2.7V Electrical
Characteristics table ............................................................................................................................................................. 3
•
Changed Voltage Reference Output, Range and Internal Reference Drift parameters in 5V Electrical Characteristics
table ...................................................................................................................................................................................... 5
Changes from Revision A (March 2005) to Revision B
•
Page
Changed Low Power sub-bullets in Features section to show correct values; High Speed and Fast modes were
reversed (typo). ..................................................................................................................................................................... 1
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
ADS7830IPWR
ACTIVE
TSSOP
PW
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ADS
7830I
ADS7830IPWRG4
ACTIVE
TSSOP
PW
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ADS
7830I
ADS7830IPWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ADS
7830I
ADS7830IPWTG4
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ADS
7830I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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25-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Oct-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS7830IPWR
TSSOP
PW
16
2500
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
ADS7830IPWT
TSSOP
PW
16
250
180.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Oct-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS7830IPWR
TSSOP
PW
16
2500
367.0
367.0
35.0
ADS7830IPWT
TSSOP
PW
16
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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