Texas Instruments | 24-Bit Analog-to-Digital Converter. | Datasheet | Texas Instruments 24-Bit Analog-to-Digital Converter. Datasheet

Texas Instruments 24-Bit Analog-to-Digital Converter. Datasheet
ADS1243-HT
SBAS525 – DECEMBER 2011
www.ti.com
24-BIT ANALOG-TO-DIGITAL CONVERTER
Check for Samples: ADS1243-HT
FEATURES
1
•
•
2
•
•
•
•
•
•
•
•
•
•
•
24-Bits No Missing Codes
Simultaneous 50-Hz and 60-Hz Rejection
(–90 dB Minimum)
0.0025% INL
PGA Gains From 1 to 128
Single-Cycle Settling
Programmable Data Output Rates
External Differential Reference of 0.1 V to 5 V
On-Chip Calibration
SPI™ Compatible
2.7 V to 5.25 V Supply Range
600-µW Power Consumption
Up to Eight Input Channels
Up to Eight Data I/O
SUPPORTS EXTREME TEMPERATURE
APPLICATIONS
•
•
•
•
•
•
•
•
APPLICATIONS
•
•
•
•
•
•
Down-Hole Drilling
High Temperature Environments
Vibration/Modal Analysis
Multi-Channel Data Acquisition
Acoustics/Dynamic Strain Gauges
Pressure Sensors
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Extreme (–55°C/210°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Texas Instruments’ high temperature products
utilize highly optimized silicon (die) solutions
with design and process enhancements to
maximize performance over extended
temperatures. All devices are characterized
and qualified for 1000 hours of continuous
operating life at maximum rated temperatures.
VREF+
VDD
VREF–
XIN
XOUT
VDD
Clock Generator
2µA
Offset
DAC
AIN0/D0
A = 1:128
AIN1/D1
IN+
AIN2/D2
AIN3/D3
AIN4/D4
MUX
IN–
BUF
+
2nd-Order
Modulator
PGA
Digital
Filter
Controller
Registers
AIN5/D5
AIN6/D6
AIN7/D7
Serial Interface
2µA
GND
CS
GND
(1)
SCLK
DIN
DOUT
PDWN
DRDY
Custom temperature ranges available
DESCRIPTION
The ADS1243 is a precision, wide dynamic range, delta-sigma, analog-to-digital (A/D) converter with 24-bit
resolution operating from 2.7-V to 5.25-V supplies. This delta-sigma, A/D converter provides up to 24 bits of no
missing code performance and effective resolution of 21 bits.
The input channels are multiplexed. Internal buffering can be selected to provide a very high input impedance for
direct connection to transducers or low-level voltage signals. Burnout current sources are provided that allow for
the detection of an open or shorted sensor. An 8-bit digital-to-analog converter (DAC) provides an offset
correction with a range of 50% of the FSR (Full-Scale Range).
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
ADS1243-HT
SBAS525 – DECEMBER 2011
www.ti.com
The Programmable Gain Amplifier (PGA) provides selectable gains of 1 to 128 with an effective resolution of 19
bits at a gain of 128. The A/D conversion is accomplished with a second-order delta-sigma modulator and
programmable FIR filter that provides a simultaneous 50-Hz and 60-Hz notch. The reference input is differential
and can be used for ratiometric conversion.
The serial interface is SPI compatible. Up to eight bits of data I/O are also provided that can be used for input or
output. The ADS1243 is designed for high-resolution measurement applications in smart transmitters, industrial
process control, weight scales, chromatography and portable instrumentation.
ORDERING INFORMATION (1)
TA
PACKAGE
ORDERABLE PART NUMBER
TOP-SIDE MARKING
JD
ADS1243SJD
ADS1243SJD
KGD
ADS1243SKGD1
NA
–55°C to 210°C
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
VDD to GND
–0.3 to 6
V
Input Current
100, Momentary
mA
Input Current
10, Continuous
mA
GND – 0.5 to VDD + 0.5
V
Digital Input Voltage to GND
–0.3V to VDD + 0.3
V
Digital Output Voltage to GND
–0.3V to VDD + 0.3
V
215
°C
Operating Temperature Range
–55 to 210
°C
Storage Temperature Range
–65 to 100
°C
AIN
Maximum Junction Temperature
(1)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
θJC
MIN
Junction-to-case thermal resistance
TYP
HKJ package
MAX
UNIT
8.1
°C/W
DIGITAL CHARACTERISTICS
VDD 2.7 V to 5.25 V
PARAMETER
TEST CONDITIONS
TA = –55°C to 125°C
MIN
TYP
TA = 210°C
MAX
MIN
TYP
MAX
UNIT
Digital Input/Output
Logic Family
CMOS
VIH
Logic Level
Input Leakage
VIL
(1)
(1)
2
0.8 ● VDD
VDD
0.8 ● VDD
VDD
V
GND
0.2 ● VDD
GND
0.2 ● VDD
V
VOH
IOH = 1 mA
VDD – 0.4
VOL
IOL = 1 mA
GND
IIH
VI = VDD
IIL
VI = 0
Master Clock Rate:
fOSC
CMOS
VDD – 0.4
GND + 0.4
GND
10
–10
1
V
GND + 0.4
V
10
µA
–10
5
1
µA
5
MHz
VIL for XIN is GND to GND + 0.05 V.
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DIGITAL CHARACTERISTICS (continued)
VDD 2.7 V to 5.25 V
PARAMETER
TA = –55°C to 125°C
TEST CONDITIONS
Master Clock Period:
tOSC
MIN
1/fOSC
TYP
200
TA = 210°C
MAX
MIN
1000
200
TYP
UNIT
MAX
1000
ns
ELECTRICAL CHARACTERISTICS: VDD = 5 V
All specifications VDD = 5 V, fMOD = 19.2 kHz, PGA = 1, Buffer ON, fDATA = 15 Hz,
VREF ≡ (REF IN+) – (REF IN–) = 2.5 V, unless otherwise specified.
PARAMETER
TA = –55°C to 125°C
TEST CONDITIONS
MIN
TA = 210°C
TYP
MAX
MIN
TYP
UNIT
MAX
ANALOG INPUT (AIN0 – AIN7)
Analog Input Range
Full-Scale Input Range
Buffer OFF
GND – 0.1
VDD + 0.1
GND – 0.1
VDD + 0.1
V
Buffer ON
GND + 0.05
VDD – 1.5
GND + 0.05
VDD – 1.5
V
±VREF/PGA
±VREF/PGA
V
±VREF/
(2 ● PGA)
±VREF/
(2 ● PGA)
V
(In+) – (In–),
See Block Diagram,
RANGE = 0
RANGE = 1
Differential Input Impedance
Bandwidth
Buffer OFF
Buffer ON
5/PGA
12/PGA
MΩ
5
8
GΩ
fDATA = 3.75 Hz
–3 dB
1.65
Hz
fDATA = 7.50 Hz
–3 dB
3.44
Hz
fDATA = 15 Hz
–3 dB
14.6
Hz
Programmable Gain
Amplifier
User-Selectable Gain Ranges
1
Input Capacitance
Input Leakage Current
Modulator OFF, T = 25°C
Burnout Current Sources
128
1
128
9
25
pF
5
6
pA
µA
2
OFFSET DAC
RANGE = 0
±VREF /
(2 ● PGA)
±VREF /
(2 ● PGA)
V
RANGE = 1
±VREF /
(4 ● PGA)
±VREF /
(4 ● PGA)
V
Offset DAC Range
Offset DAC Monotonicity
8
Offset DAC Gain Error
Offset DAC Gain Error Drift
8
Bits
±10
±15
%
1
2.2
ppm/°C
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Nonlinearity
End Point Fit
24
24
Bits
±0.0015
±0.0018
% of FS
Offset Error (1)
7.5
15
ppm of
FS
Offset Drift (1)
0.02
0.04
ppm of
FS/°C
Gain Error (1)
0.005
0.100
%
0.5
1.118
ppm°°C
Gain Error Drift (1)
at DC
Common-Mode Rejection
Normal-Mode Rejection
94
dB
130
100
dB
fCM = 50 Hz, fDATA = 15 Hz
120
100
dB
fSIG = 50 Hz, fDATA = 15 Hz
100
95
dB
fSIG = 60 Hz, fDATA = 15 Hz
100
95
dB
Output Noise
(1)
100
fCM = 60 Hz, fDATA = 15 Hz
See Typical Characteristics
Calibration can minimize these errors.
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ELECTRICAL CHARACTERISTICS: VDD = 5 V (continued)
All specifications VDD = 5 V, fMOD = 19.2 kHz, PGA = 1, Buffer ON, fDATA = 15 Hz,
VREF ≡ (REF IN+) – (REF IN–) = 2.5 V, unless otherwise specified.
PARAMETER
Power-Supply Rejection
TA = –55°C to 125°C
TEST CONDITIONS
MIN
TYP
80
95
at DC,
dB = –20 log(ΔVOUT /VDD) (2)
TA = 210°C
MAX
MIN
TYP
79
95
MAX
UNIT
dB
VOLTAGE REFERENCE INPUT
Reference Input Range
REF IN+, REF IN–
VREF
VREF ≡ (REF IN+) – (REF IN–),
RANGE = 0
0
0.1
RANGE = 1
0.1
2.5
VDD
0
2.6
0.1
VDD
0.1
2.5
VDD
V
2.6
V
VDD
V
Common-Mode Rejection
at DC
120
98
dB
Common-Mode Rejection
fVREFCM = 60 Hz, fDATA = 15 Hz
120
95
dB
Bias Current (3)
VREF = 2.5 V
1.3
10
µA
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
Current
VDD
5.25
V
PGA = 1, Buffer OFF
4.75
240
375
250
480
µA
PGA = 128, Buffer OFF
450
800
630
940
µA
PGA = 1, Buffer ON
290
425
350
585
µA
PGA = 128, Buffer ON
960
1400
1200
2050
µA
(2)
(3)
4.75
60
80
µA
Read Data Continuous Mode
230
350
µA
PDWN
0.5
10
PGA = 1, Buffer OFF
1.2
SLEEP Mode
Power Dissipation
5.25
1.9
1.3
nA
2.52
mW
ΔVOUT is a change in digital result.
12-pF switched capacitor at fSAMP clock frequency.
ELECTRICAL CHARACTERISTICS: VDD = 3 V
All specifications VDD = 3 V, fMOD = 19.2 kHz, PGA = 1, Buffer ON, fDATA = 15 Hz,
VREF ≡ (REF IN+) – (REF IN–) = 1.25 V, unless otherwise specified.
PARAMETER
TA = –55°C to 125°C
TEST CONDITIONS
MIN
TYP
TA = 210°C
TYP
MAX
UNIT
MAX
MIN
GND – 0.1
VDD + 0.1
GND – 0.1
VDD + 0.1
V
GND +
0.05
VDD – 1.5
GND + 0.05
VDD – 1.5
V
±VREF/
PGA
±VREF/
PGA
V
±VREF/
(2 • PGA)
±VREF/
(2 • PGA)
V
ANALOG INPUT (AIN0 – AIN7)
Buffer OFF
Analog Input Range
Full-Scale Input Voltage
Range
Input Impedance
Bandwidth
Buffer ON
(In+) – (In–), See Block
Diagram, RANGE = 0
RANGE = 1
Buffer OFF
Buffer ON
5/PGA
10/PGA
MΩ
5
8
GΩ
fDATA = 3.75 Hz
–3 dB
1.65
Hz
fDATA = 7.50 Hz
–3 dB
3.44
Hz
fDATA = 15 Hz
–3 dB
14.6
Hz
Programmable Gain
Amplifier
User-Selectable Gain Ranges
Input Capacitance
Input Leakage Current
Modulator OFF, T = 25°C
Burnout Current Sources
1
128
1
128
9
25
pF
5
6
pA
µA
2
OFFSET DAC
RANGE = 0
±VREF/
(2 ● PGA)
±VREF/
(2 ● PGA)
V
RANGE = 1
±VREF/
(4 ● PGA)
±VREF/
(4 ● PGA)
V
Offset DAC Range
4
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ELECTRICAL CHARACTERISTICS: VDD = 3 V (continued)
All specifications VDD = 3 V, fMOD = 19.2 kHz, PGA = 1, Buffer ON, fDATA = 15 Hz,
VREF ≡ (REF IN+) – (REF IN–) = 1.25 V, unless otherwise specified.
PARAMETER
TA = –55°C to 125°C
TEST CONDITIONS
MIN
Offset DAC Monotonicity
TA = 210°C
TYP
MAX
8
Offset DAC Gain Error
Offset DAC Gain Error Drift
MIN
TYP
UNIT
MAX
8
Bits
±10
±12
1
2
%
ppm/°C
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Nonlinearity
End Point Fit
24
24
Bits
±0.0015
±0.0025
% of FS
75
40
ppm of
FS
Offset Drift (1)
0.02
0.20
ppm of
FS/°C
Gain Error (1)
0.005
0.1
0.5
1.118
Offset Error (1)
Gain Error Drift (1)
at DC
Common-Mode Rejection
Normal-Mode Rejection
100
87
dB
fCM = 60 Hz, fDATA = 15 Hz
130
98
dB
fCM = 50 Hz, fDATA = 15 Hz
120
95
dB
fSIG = 50 Hz, fDATA = 15 Hz
100
90
dB
100
90
dB
90
dB
fSIG = 60 Hz, fDATA = 15 Hz
Output Noise
Power-Supply Rejection
%
ppm/°C
See Typical Characteristics
at DC,
dB = –20 log(ΔVOUT /VDD) (2)
80
95
75
VOLTAGE REFERENCE INPUT
Reference Input Range
REF IN+, REF IN–
VREF
VREF ≡ (REF IN+) –
(REF IN–), RANGE = 0
0
0.1
RANGE = 1
0.1
1.25
VDD
0
1.30
0.1
VDD
0.1
1.25
VDD
V
1.30
V
2.6
V
Common-Mode Rejection
at DC
120
95
dB
Common-Mode Rejection
fVREFCM = 60 Hz,
fDATA = 15 Hz
120
93
dB
VREF = 1.25 V
1.3
8
µA
Bias Current
(3)
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
Current
VDD
3.3
V
PGA = 1, Buffer OFF
2.7
190
375
200
480
µA
PGA = 128, Buffer OFF
460
700
600
940
µA
PGA = 1, Buffer ON
240
375
350
585
µA
PGA = 128, Buffer ON
870
1325
1200
1800
(1)
(2)
(3)
2.7
µA
75
110
µA
Read Data Continuous Mode
113
250
µA
PDWN = 0
0.5
7.5
PGA = 1, Buffer OFF
0.6
SLEEP Mode
Power Dissipation
3.3
1.2
0.66
nA
1.58
mW
Calibration can minimize these errors.
ΔVOUT is a change in digital result.
12-pF switched capacitor at fSAMP clock frequency.
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10,000,000
Estimated Life (Hours)
1,000,000
100,000
10,000
1000
80
100
120
140
160
180
200
220
Continuous TJ (°C)
(1)
See data sheet for absolute maximum and minimum recommended operating conditions.
(2)
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3)
The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the
dominant failure mechanism affecting device wearout for the specific device process and design characteristics.
Figure 1. ADS1243-HT Operating Life Derating Chart
6
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PIN CONFIGURATION
CDIP PACKAGE
(TOP VIEW)
VDD
1
20 DRDY
XIN
2
19 SCLK
XOUT
3
18 DOUT
PDWN
4
17 DIN
VREF+
5
16 CS
VREF–
6
15 GND
AIN0/D0
7
14 AIN3/D3
AIN1/D1
8
13 AIN2/D2
AIN4/D4
9
12 AIN7/D7
AIN5/D5 10
11 AIN6/D6
PIN ASSIGNMENTS
PIN #
NAME
1
VDD
Power Supply
DESCRIPTION
2
XIN
Clock Input
3
XOUT
4
PDWN
Clock Output, used with crystal or ceramic resonator.
Active LOW. Power Down. The power down function shuts down the analog and digital circuits.
5
VREF+
Positive Differential Reference Input
6
VREF–
Negative Differential Reference Input
7
AIN0/D0
Analog Input 0/Data I/O 0
8
AIN1/D1
Analog Input 1/Data I/O 1
9
AIN4/D4
Analog Input 4/Data I/O 4
10
AIN5/D5
Analog Input 5/Data I/O 5
11
AIN6/D6
Analog Input 6/Data I/O 6
12
AIN7/D7
Analog Input 7/Data I/O 7
13
AIN2/D2
Analog Input 2/Data I/O 2
14
AIN3/D3
Analog Input 3/Data I/O 3
15
GND
Ground
16
CS
Active LOW, Chip Select
17
DIN
Serial Data Input, Schmitt Trigger
18
DOUT
Serial Data Output
19
SCLK
Serial Clock, Schmitt Trigger
20
DRDY
Active LOW, Data Ready
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BARE DIE INFORMATION
DIE THICKNESS
BACKSIDE FINISH
BACKSIDE
POTENTIAL
BOND PAD
METALLIZATION COMPOSITION
15 mils
Silicon with backgrind
GND
AlCu
Table 1. Bond Pad Coordinates in Microns (1)
(1)
8
DISCRIPTION
PAD NUMBER
X MIN
Y MIN
X MAX
Y MAX
VDD
1
1268.55
2471.55
1478.15
2572.55
Connect to substrate
2
1030.45
2471.55
1132.45
2572.55
Connect to substrate
3
692.45
2471.55
902.05
2572.55
XIN
4
450.05
2471.55
552.05
2572.55
XOUT
5
6.45
2016.65
107.45
2118.65
NC
6
6.45
1721.75
107.45
1823.75
NC
7
6.45
1468.60
107.45
1570.60
PDWN
8
6.45
1224.80
107.45
1326.80
NC
9
6.45
929.95
107.45
1031.95
VREF+
10
6.45
655.20
107.45
757.20
VREF-
11
6.45
373.25
107.45
475.25
AIN0/D0
12
361.15
3.55
462.15
105.55
AIN1/D1
13
636.45
3.55
737.45
105.55
AIN4/D4
14
911.70
3.55
1012.70
105.55
AIN5/D5
15
1186.85
3.55
1287.85
105.55
AIN6/D6
16
1466.25
3.55
1567.25
105.55
AIN7/D7
17
1742.50
3.55
1843.50
105.55
AIN2/D2
18
2017.60
3.55
2118.60
105.55
AIN3/D3
19
2292.75
3.55
2393.75
105.55
NC
20
2608.70
310.50
2709.70
412.50
GND
21
2608.75
553.25
2709.75
762.85
GND
22
2608.70
832.20
2709.70
934.20
NC
23
2608.75
1001.60
2709.75
1211.20
NC
24
2608.70
1335.65
2709.70
1437.65
CS
25
2608.70
1571.45
2709.70
1673.45
DIN
26
2608.70
1797.90
2709.70
1899.90
DOUT
27
2608.70
2076.55
2709.70
2178.55
SCLK
28
2234.80
2471.55
2336.80
2572.55
DRDY
29
1931.10
2471.55
2033.10
2572.55
NC
30
1637.90
2471.55
1739.90
2572.55
For signal descriptions see the Pin Assignments table.
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2713.55 µm
XIN
NC
VDD
NC
DRDY
SCLK
DOUT
PAD #1
XOUT
Connect to Connect to
Substrate Substrate
DIN
NC
PDWN
NC
50 µm
2578.90 µm
CS
NC
NC
GND
VREF+
GND
VREF-
NC
AIN0/D0 AIN1/D1 AIN4/D4 AIN5/D5 AIN6/D6 AIN7/D7 AIN2/D2 AIN3/D3
0
0 EDGE OF
SCRIBE
50 µm
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TIMING DIAGRAMS
CS
t3
t1
t2
t10
SCLK
t4
DIN
MSB
t2
t6
t5
t11
LSB
t7
(Command or Command and Data)
DOUT
t8
t9
MSB(1)
LSB(1)
NOTE: (1) Bit order = 0.
SCLK Reset Waveform
Resets On
Falling Edge
t13
t13
300 • tOSC < t12 < 500 • tOSC
t13 : > 5 • tOSC
550 • tOSC < t14 < 750 • tOSC
SCLK
t12
t14
t15
1050 • tOSC < t15 < 1250 • tOSC
t16
tDATA
DRDY
PDWN
t17
t18
SCLK
t19
10
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TIMING REQUIREMENTS
PARAMETER
TEST CONDITIONS
MIN
MAX
tOSC
Periods
4
t1
SCLK Period
3
t2
SCLK Pulse Width, HIGH and LOW
t3
CS low to first SCLK Edge; Setup Time (1)
t4
t5
t6
Delay between last SCLK edge for DIN and first SCLK
edge for DOUT: RDATA, RDATAC, RREG, WREG
ns
0
ns
DIN Valid to SCLK Edge; Setup Time
50
ns
Valid DIN to SCLK Edge; Hold Time
50
ns
50
tOSC
Periods
SCLK Edge to Valid New DOUT
t8 (2)
SCLK Edge to DOUT, Hold Time
0
Last SCLK Edge to DOUT Tri-State
NOTE: DOUT goes tri-state immediately when CS goes
HIGH.
6
t10
t11
50
ns
ns
10
tOSC
Periods
Read from the device
0
tOSC
Periods
Write to the device
8
tOSC
Periods
RREG, WREG, DSYNC,
SLEEP, RDATA,
RDATAC, STOPC
4
tOSC
Periods
SELFGCAL,
Final SCLK edge of one command until first edge SCLK SELFOCAL, SYSOCAL,
SYSGCAL
of next command:
2
DRDY
Periods
4
DRDY
Periods
16
tOSC
Periods
4
tOSC
Periods
CS LOW time after final SCLK edge.
SELFCAL
RESET (also SCLK
Reset)
(1)
(2)
DRDY
Periods
200
t7 (2)
t9
UNIT
t16
Pulse Width
t17
Allowed analog input change for next valid conversion.
t18
DOR update, DOR data not valid.
t19
First SCLK after DRDY goes LOW:
5000
tOSC
Periods
4
tOSC
Periods
RDATAC Mode
10
tOSC
Periods
Any other mode
0
tOSC
Periods
CS may be tied LOW.
Load = 20 pF|| 10 kΩ to GND.
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TYPICAL CHARACTERISTICS
All specifications VDD = 5 V, fOSC = 2.4576 MHz, PGA = 1, fDATA = 15 Hz, and VREF ≡ (REF IN+) – (REF IN–) = 2.5 V,
unless otherwise specified.
EFFECTIVE NUMBER OF BITS
vs
PGA SETTING
21.5
EFFECTIVE NUMBER OF BITS
vs
PGA SETTING
22
DR = 10
21.0
21
DR = 10
DR = 01
20
20.0
ENOB (rms)
ENOB (rms)
20.5
19.5
19.0
DR = 00
18.5
19
DR = 01
18
DR = 00
17
18.0
Buffer ON
Buffer OFF
16
17.5
15
17.0
1
2
4
8
16
32
64
1
128
2
EFFECTIVE NUMBER OF BITS
vs
PGA SETTING
19.0
Noise (rms, ppm of FS)
ENOB (rms)
64
128
1.8
DR = 10
19.5
DR = 01
18.5
18.0
DR = 00
17.5
Buffer OFF, V REF = 1.25V
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–2.5
16.0
1
2
4
8
16
32
64
128
–1.5
–0.5
0.5
1.5
2.5
VIN (V)
PGA Setting
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
140
140
120
120
100
100
PSRR (dB)
CMRR (dB)
32
2.0
20.0
80
60
80
60
40
40
20
20
Buffer ON
Buffer ON
0
0
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
Frequency of Power Supply (Hz)
Frequency of Power Supply (Hz)
12
16
NOISE
vs
INPUT SIGNAL
20.5
16.5
8
PGA Setting
PGA Setting
17.0
4
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TYPICAL CHARACTERISTICS (continued)
All specifications VDD = 5 V, fOSC = 2.4576 MHz, PGA = 1, fDATA = 15 Hz, and VREF ≡ (REF IN+) – (REF IN–) = 2.5 V,
unless otherwise specified.
OFFSET
vs
TEMPERATURE
(Cal AT 25°C)
GAIN
vs
TEMPERATURE
(Cal AT 25°C)
50
1.020
PGA16
PGA1
1.016
1.012
Gain (Normalized)
Offset (ppm of FS)
0
–50
–100
PGA64
–150
PGA128
1.008
1.004
1.000
0.996
0.992
0.988
–200
0.984
0.980
–250
–55 –35 –15 5
–55 –35 –15 5
25 45 65 85 105 125 145 165 185 205
INTEGRAL NONLINEARITY
vs
INPUT SIGNAL
CURRENT
vs
TEMPERATURE
325
10
8
–40°C
300
6
4
+85°C
Current (µA)
INL (ppm of FS)
25 45 65 85 105 125 145 165 185 205
Temperature (°C)
Temperature (°C)
2
0
–2
–4
275
250
225
+25°C
–6
200
–8
–10
–2.5 –2.0 –1.5 –1.0 – 0.5
0
0.5
1.0
1.5
2.0
175
2.5
–55 –35 –15 5
VIN (V)
Temperature (°C)
CURRENT
vs
VOLTAGE
SUPPLY CURRENT
vs
SUPPLY
350
300
Normal
4.91MHz
Current ( µA)
250
Normal
2.45MHz
250
IDIGITAL ( µA)
300
200
150
SLEEP
2.45MHz
SLEEP
4.91MHz
100
200
SLEEP
4.91MHz
Normal
2.45MHz
Normal
4.91MHz
150
100
50
Power Down
50
0
–50
25 45 65 85 105 125 145 165 185 205
SLEEP
2.45MHz
Power Down
0
3.0
3. 25
3.5
3.75
4.0
4.2 5
4.5
4.75
5.0
3.0
VDD (V)
3.5
4.0
4 .5
5.0
VDD (V)
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TYPICAL CHARACTERISTICS (continued)
All specifications VDD = 5 V, fOSC = 2.4576 MHz, PGA = 1, fDATA = 15 Hz, and VREF ≡ (REF IN+) – (REF IN–) = 2.5 V,
unless otherwise specified.
OFFSET DAC OFFSET
vs
TEMPERATURE
(Cal AT 25°C)
NOISE HISTOGRAM
3500
150
Offset (ppm of FSR)
3000
Number of Occurrences
200
10k Readings
VIN = 0V
2500
2000
1500
1000
100
50
0
–50
–100
–150
500
–200
–250
0
–3.5 –3.0 –2.5 –2.0 –1.5 –1 –0.5 0
–55 –35 –15 5
0.5 1.0 1.5 2.0 2.5 3.0 3.5
25 45 65 85 105 125 145 165 185 205
Temperature (°C)
ppm of FS
OFFSET DAC GAIN
vs
TEMPEARTURE
(Cal AT 25°C)
OFFSET DAC NOISE
vs
SETTING
1.0005
0.8
1.0004
0.7
Noise (rms, ppm of FS)
Gain (Normalized)
1.0003
1.0002
1.0001
1.0000
0.9999
0.9998
0.9997
0.6
0.5
0.4
0.3
0.2
0.1
0.9996
0.9995
–55 –35 –15 5
25 45 65 85 105 125 145 165 185 205
0
–128
–96
Temperature (°C)
14
–64
–32
0
32
64
96
128
Offset DAC Setting
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OVERVIEW
INPUT MULTIPLEXER
The input multiplexer provides for any combination of differential inputs to be selected on any of the input
channels, as shown in Figure 2. For example, if AIN0 is selected as the positive differential input channel, any
other channel can be selected as the negative terminal for the differential input channel. With this method, it is
possible to have up to seven single-ended input channels or four independent differential input channels for the
ADS1243.
The ADS1243 features a single-cycle settling digital filter that provides valid data on the first conversion after a
new channel selection. In order to minimize the settling error, synchronize MUX changes to the conversion
beginning, which is indicated by the falling edge of DRDY. In other words, issuing a MUX change through the
WREG command immediately after DRDY goes LOW minimizes the settling error. Increasing the time between
the conversion beginning (DRDY goes LOW) and the MUX change command (tDELAY) results in a settling error in
the conversion data, as shown in Figure 3.
AIN0/D0
AIN1/D1
VDD
Burnout Current Source
AIN2/D2
AIN3/D3
Input
Buffer
AIN4/D4
AIN5/D5
Burnout Current Source
AIN6/D6
GND
AIN7/D7
Figure 2. Input Multiplexer Configuration
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New Conversion Begins,
Previous Conversion Data
Complete Previous Conversion
New Conversion Complete
DRDY
tDELAY
SCLK
MSB
DIN
LSB
SETTLING ERROR vs DELAY TIME
fCLK = 2.4576MHz
10
1
Settling Error (%)
0.1
0.01
0.001
0.0001
0.00001
0.000001
0
2
4
6
8
10
Delay Time, tDELAY (ms)
12
14
16
Figure 3. Input Multiplexer Configuration
BURNOUT CURRENT SOURCES
The Burnout Current Sources can be used to detect sensor short-circuit or open-circuit conditions. Setting the
Burnout Current Sources (BOCS) bit in the SETUP register activates two 2µA current sources called burnout
current sources. One of the current sources is connected to the converter’s negative input and the other is
connected to the converter’s positive input.
Figure 4 shows the situation for an open-circuit sensor. This is a potential failure mode for many kinds of
remotely connected sensors. The current source on the positive input acts as a pull-up, causing the positive input
to go to the positive analog supply, and the current source on the negative input acts as a pull-down, causing the
negative input to go to ground. The ADS1243 therefore outputs full-scale (7FFFFF Hex).
Figure 5 shows a short-circuited sensor. Since the inputs are shorted and at the same potential, the ADS1243
signal outputs are approximately zero. (Note that the code for shorted inputs is not exactly zero due to internal
series resistance, low-level noise and other error sources.)
VDD
2mA
VDD
ADC
OPEN CIRCUIT
CODE = 0x7FFFFFH
0V
2mA
Figure 4. Burnout Detection While Sensor is Open-Circuited.
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VDD
2mA
VDD/2
SHORT
CIRCUIT
ADC
CODE ≅0
VDD/2
2mA
Figure 5. Burnout Detection While Sensor is Short-Circuited.
INPUT BUFFER
The input impedance of ADS1243 without the buffer enabled is approximately 5MΩ/PGA. For systems requiring
very high input impedance, the ADS1243 provides a chopper-stabilized differential FET-input voltage buffer.
When activated, the buffer raises the ADS1243 input impedance to approximately 5 GΩ.
The buffer’s input range is approximately 50mV to VDD – 1.5 V. The buffer’s linearity will degrade beyond this
range. Differential signals should be adjusted so that both signals are within the buffer’s input range.
The buffer can be enabled using the BUFEN pin or the BUFEN bit in the ACR register. The buffer is on when the
BUFEN pin is high and the BUFEN bit is set to one. If the BUFEN pin is low, the buffer is disabled. If the BUFEN
bit is set to zero, the buffer is also disabled.
The buffer draws additional current when activated. The current required by the buffer depends on the PGA
setting. When the PGA is set to 1, the buffer uses approximately 50 µA; when the PGA is set to 128, the buffer
uses approximately 500µA.
PGA
The Programmable Gain Amplifier (PGA) can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can
improve the effective resolution of the A/D converter. For instance, with a PGA of 1 on a 5-V full-scale signal, the
A/D converter can resolve down to 1 µV. With a PGA of 128 and a full-scale signal of 39 mV, the A/D converter
can resolve down to 75 nV. VDD current increases with PGA settings higher than 4.
OFFSET DAC
The input to the PGA can be shifted by half the full-scale input range of the PGA using the Offset DAC (ODAC)
register. The ODAC register is an 8-bit value; the MSB is the sign and the seven LSBs provide the magnitude of
the offset. Using the offset DAC does not reduce the performance of the A/D converter. For more details on the
ODAC in the ADS1243, please refer to TI application report SBAA077 (available through the TI website).
MODULATOR
The modulator is a single-loop second-order system. The modulator runs at a clock speed (fMOD) that is derived
from the external clock (fOSC). The frequency division is determined by the SPEED bit in the SETUP register, as
shown in Table 2.
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Table 2. Output Configuration
fOSC
2.4576 MHz
4.9152 MHz
DR BITS
SPEED
BIT
fMOD
0
19,200 Hz
15 Hz
1
9,600 Hz
7.5 Hz
0
38,400 Hz
30 Hz
1
19,200 Hz
15 Hz
10
1st NOTCH
FREQUENCY
7.5 Hz
3.75 Hz
50/60 Hz
3.75 Hz
1.875 Hz
25/30 Hz
15 Hz
7.5 Hz
100/120 Hz
7.5 Hz
3.75 Hz
50/60 Hz
00
01
CALIBRATION
The offset and gain errors can be minimized with calibration. The ADS1243 supports both self and system
calibration.
Self-calibration of the ADS1243 corrects internal offset and gain errors and is handled by three commands:
SELFCAL, SELFGAL, and SELFOCAL. The SELFCAL command performs both an offset and gain calibration.
SELFGCAL performs a gain calibration and SELFOCAL performs an offset calibration, each of which takes two
tDATA periods to complete. During self-calibration, the ADC inputs are disconnected internally from the input pins.
The PGA must be set to 1 prior to issuing a SELFCAL or SELFGCAL command. Any PGA is allowed when
issuing a SELFOCAL command. For example, if using PGA = 64, first set PGA = 1 and issue SELFGCAL.
Afterwards, set PGA = 64 and issue SELFOCAL. For operation with a reference voltage greater than (VDD – 1.5)
volts, the buffer must also be turned off during gain self-calibration to avoid exceeding the buffer input range.
System calibration corrects both internal and external offset and gain errors. While performing system calibration,
the appropriate signal must be applied to the inputs. The system offset calibration command (SYSOCAL)
requires a zero input differential signal (see Table 5). It then computes the offset that nullifies the offset in the
system. The system gain calibration command (SYSGCAL) requires a positive full-scale input signal. It then
computes a value to nullify the gain error in the system. Each of these calibrations takes two tDATA periods to
complete. System gain calibration is recommended for the best gain calibration at higher PGAs.
Calibration should be performed after power on, a change in temperature, or a change of the PGA. The RANGE
bit (ACR bit 2) must be zero during calibration.
Calibration removes the effects of the ODAC; therefore, disable the ODAC during calibration, and enable again
after calibration is complete.
At the completion of calibration, the DRDY signal goes low, indicating the calibration is finished. The first data
after calibration should be discarded since it may be corrupt from calibration data remaining in the filter. The
second data is always valid.
EXTERNAL VOLTAGE REFERENCE
The ADS1243 requires an external voltage reference. The selection for the voltage reference value is made
through the ACR register.
The external voltage reference is differential and is represented by the voltage difference between the pins:
+VREF and –VREF. The absolute voltage on either pin, +VREF or –VREF, can range from GND to VDD. However, the
following limitations apply:
• For VDD = 5 V and RANGE = 0 in the ACR, the differential VREF must not exceed 2.5 V.
• For VDD = 5 V and RANGE = 1 in the ACR, the differential VREF must not exceed 5 V.
• For VDD = 3 V and RANGE = 0 in the ACR, the differential VREF must not exceed 1.25 V.
• For VDD = 3 V and RANGE = 1 in the ACR, the differential VREF must not exceed 2.5 V.
CLOCK GENERATOR
The clock source for ADS1243 can be provided from a crystal, oscillator, or external clock. When the clock
source is a crystal, external capacitors must be provided to ensure start-up and stable clock frequency. This is
shown in both Figure 6 and Table 3. XOUT is only for use with external crystals and it should not be used as a
clock driver for external circuitry.
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C1
XIN
Crystal
C2
XOUT
Figure 6. Crystal Connection.
Table 3. Recommended Crystals
CLOCK
SOURCE
FREQUENCY
C1
C2
PART
NUMBER
Crystal
2.4576
0-20 pF
0-20 pF
ECS, ECSD 2.45 – 32
Crystal
4.9152
0-20 pF
0-20 pF
ECS, ECSL 4.91
Crystal
4.9152
0-20 pF
0-20 pF
ECS, ECSD 4.91
Crystal
4.9152
0-20 pF
0-20 pF
CTS, MP 042 4M9182
DIGITAL FILTER
The ADS1243 has a 1279 tap linear phase Finite Impulse Response (FIR) digital filter that a user can configure
for various output data rates. When a 2.4576-MHz crystal is used, the device can be programmed for an output
data rate of 15 Hz, 7.5 Hz, or 3.75 Hz. Under these conditions, the digital filter rejects both 50Hz and 60Hz
interference. Figure 7 shows the digital filter frequency response for data output rates of 15 Hz, 7.5 Hz, and 3.75
Hz.
If a different data output rate is desired, a different crystal frequency can be used. However, the rejection
frequencies shift accordingly. For example, a 3.6864-MHz master clock with the default register condition has:
(3.6864 MHz/2.4576 MHz) ● 15 Hz = 22.5 Hz data output rate
and the first and second notch is:
1.5 ● (50 Hz and 60 Hz) = 75 Hz and 90 Hz
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FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN fDATA = 15Hz
ADS1243
FILTER RESPONSE WHEN f DATA = 15Hz
0
–40
–20
–50
–40
–60
Magnitude (dB)
Gain (dB)
–60
–80
–100
–120
–140
–90
–100
–110
–130
–180
–140
0
20
40
60
80
100
120 140
160 180
200
Frequency (Hz)
55
Frequency (Hz)
ADS1243
FILTER RESPONSE WHEN f DATA = 7.5Hz
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN fDATA = 7.5Hz
45
0
–40
–20
–50
–40
–60
Magnitude (dB)
–60
Gain (dB)
–80
–120
–160
–80
–100
–120
50
60
65
–70
–80
–90
–100
–110
–140
–120
–160
–130
–180
–140
0
20
40
60
80
100
120 140
160 180
45
200
50
55
60
Frequency (Hz)
Frequency (Hz)
ADS1243
FILTER RESPONSE WHEN f DATA = 3.75Hz
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN fDATA = 3.75Hz
0
–40
–20
–50
–40
–60
–60
–70
Magnitude (dB)
Gain (dB)
–70
–80
–100
–120
–140
65
–80
–90
–100
–110
–120
–160
–130
–180
–140
0
20
40
60
80
100
120 140
160 180
45
200
50
55
Frequency (Hz)
60
65
Frequency (Hz)
fOSC = 2.4576MHz, SPEED = 0 or fOSC = 4.9152MHz, SPEED = 1
DATA
OUTPUT RATE
–3dB
BANDWIDTH
15Hz
14.6Hz
7.5Hz
3.75Hz
ATTENUATION
f
fIN = 60 ± 0.3Hz
fIN = 50 ± 1Hz
fIN = 60 ± 1Hz
–80.8dB
–87.3dB
–68.5dB
–76.1dB
3.44Hz
–85.9dB
–87.4dB
–71.5dB
–76.2dB
1.65Hz
–93.8dB
–88.6dB
–86.8dB
–77.3dB
IN
= 50 ± 0.3Hz
Figure 7. Filter Frequency Responses
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DATA I/O INTERFACE
The ADS1243 has eight pins that serve a dual purpose as both analog inputs and data I/O. These pins are
configured through the IOCON, DIR, and DIO registers and can be individually configured as either analog inputs
or data I/O. See Figure 8 for the equivalent schematic of an Analog/Data I/O pin.
The IOCON register defines the pin as either an analog input or data I/O. The power-up state is an analog input.
If the pin is configured as an analog input in the IOCON register, the DIR and DIO registers have no effect on the
state of the pin.
If the pin is configured as data I/O in the IOCON register, then DIR and DIO are used to control the state of the
pin. The DIR register controls the direction of the data pin, either as an input or output. If the pin is configured as
an input in the DIR register, then the corresponding DIO register bit reflects the state of the pin. Make sure the
pin is driven to a logic one or zero when configured as an input to prevent excess current dissipation. If the pin is
configured as an output in the DIR register, then the corresponding DIO register bit value determines the state of
the output pin (0 = GND, 1 = VDD).
It is still possible to perform A/D conversions on a pin configured as data I/O. This may be useful as a test mode,
where the data I/O pin is driven and an A/D conversion is done on the pin.
IOCON
DIR
DIO WRITE
AINx/Dx
To Analog Mux
DIO READ
Figure 8. Analog/Data Interface Pin
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) allows a controller to communicate synchronously with the ADS1243. The
ADS1243 operates in slave-only mode. The serial interface is a standard four-wire SPI (CS, SCLK, DIN and
DOUT) interface.
Chip Select (CS)
The chip select (CS) input must be externally asserted before communicating with the ADS1243. CS must stay
LOW for the duration of the communication. Whenever CS goes HIGH, the serial interface is reset. CS may be
hard-wired LOW.
Serial Clock (SCLK)
The serial clock (SCLK) features a Schmitt-triggered input and is used to clock DIN and DOUT data. Make sure to
have a clean SCLK to prevent accidental double-shifting of the data. If SCLK is not toggled within three DRDY
pulses, the serial interface resets on the next SCLK pulse and starts a new communication cycle. A special
pattern on SCLK resets the entire chip; see the RESET section for additional information.
Data Input (DIN) and Data Output (DOUT)
The data input (DIN) and data output (DOUT) receive and send data from the ADS1243. DOUT is high impedance
when not in use to allow DIN and DOUT to be connected together and driven by a bidirectional bus. Note: the
Read Data Continuous Mode (RDATAC) command should not be issued when DIN and DOUT are connected.
While in RDATAC mode, DIN looks for the STOPC or RESET command. If either of these 8-bit bytes appear on
DOUT (which is connected to DIN), the RDATAC mode ends.
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DATA READY (DRDY) PIN
The DRDY line is used as a status signal to indicate when data is ready to be read from the internal data
register. DRDY goes LOW when a new data word is available in the DOR register. It is reset HIGH when a read
operation from the data register is complete. It also goes HIGH prior to the updating of the output register to
indicate when not to read from the device to ensure that a data read is not attempted while the register is being
updated.
The status of DRDY can also be obtained by interrogating bit 7 of the ACR register (address 2H). The serial
interface can operate in 3-wire mode by tying the CS input LOW. In this case, the SCLK, DIN, and DOUT lines are
used to communicate with the ADS1243. This scheme is suitable for interfacing to microcontrollers. If CS is
required as a decoding signal, it can be generated from a port bit of the microcontroller.
DSYNC OPERATION
Synchronization can be achieved through the DSYNC command. When the DSYNC command is sent, the digital
filter is reset on the edge of the last SCLK of the DSYNC command. The modulator is held in RESET until the
next edge of SCLK is detected. Synchronization occurs on the next rising edge of the system clock after the first
SCLK following the DSYNC command.
POWER-UP—SUPPLY VOLTAGE RAMP RATE
The power-on reset circuitry was designed to accommodate digital supply ramp rates as slow as 1 V/10 ms. To
ensure proper operation, the power supply should ramp monotonically.
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ADS1243 REGISTERS
The operation of the device is set up through individual registers. Collectively, the registers contain all the
information needed to configure the part, such as data format, multiplexer settings, calibration settings, data rate,
etc. The 16 registers are shown in Table 4.
Table 4. Registers
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00H
SETUP
ID
ID
ID
ID
BOCS
PGA2
PGA1
PGA0
01H
MUX
PSEL3
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL1
NSEL0
02H
ACR
DRDY
U/B
SPEED
BUFEN
BIT ORDER
RANGE
DR1
DR0
03H
ODAC
SIGN
OSET6
OSET5
OSET4
OSET3
OSET2
OSET1
OSET0
04H
DIO
DIO_7
DIO_6
DIO_5
DIO_4
DIO_3
DIO_2
DIO_1
DIO_0
05H
DIR
DIR_7
DIR_6
DIR_5
DIR_4
DIR_3
DIR_2
DIR_1
DIR_0
06H
IOCON
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
07H
OCR0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
08H
OCR1
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR09
OCR08
09H
OCR2
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
0AH
FSR0
FSR07
FSR06
FSR05
FSR04
FSR03
FSR02
FSR01
FSR00
FSR08
0BH
FSR1
FSR15
FSR14
FSR13
FSR12
FSR11
FSR10
FSR09
0CH
FSR2
FSR23
FSR22
FSR21
FSR20
FSR19
FSR18
FSR17
FSR16
0DH
DOR2
DOR23
DOR22
DOR21
DOR20
DOR19
DOR18
DOR17
DOR16
0EH
DOR1
DOR15
DOR14
DOR13
DOR12
DOR11
DOR10
DOR09
DOR08
0FH
DOR0
DOR07
DOR16
FSR21
DOR04
DOR03
DOR02
DOR01
DOR00
DETAILED REGISTER DEFINITIONS
Setup
(Address 00H) Setup Register
Reset Value = iiii0000
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ID
ID
ID
ID
BOCS
PGA2
PGA1
PGA0
bit 7–4
Factory Programmed Bits
bit 3
BOCS: Burnout Current Source
0 = Disabled (default)
1 = Enabled
bit 2–0
PGA2: PGA1: PGA0: Programmable Gain Amplifier
Gain Selection
000 = 1 (default)
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 128
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MUX
(Address 01H) Multiplexer Control Register
Reset Value = 01H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSEL3
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL1
NSEL0
bit 7–4
PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel
Select
0000 = AIN0 (default)
0001 = AIN1
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1111 = Reserved
NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel
Select
0000 = AIN0
0001 = AIN1 (default)
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1111 = Reserved
bit 3–0
ACR
(Address 02H) Analog Control Register
Reset Value = X0H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DRDY
U/B
SPEED
BUFEN
BIT ORDER
RANGE
DR1
DR0
bit 7
DRDY: Data Ready (Read Only)
This bit duplicates the state of the DRDY pin.
bit 6
U/B: Data Format
0 = Bipolar (default)
1 = Unipolar
U/B
0
1
24
ANALOG INPUT
DIGITAL OUTPUT (Hex)
+FSR
0x7FFFFF
Zero
0x000000
–FSR
0x800000
+FSR
0xFFFFFF
Zero
0x000000
–FSR
0x000000
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bit 5
SPEED: Modulator Clock Speed
0 = fMOD = fOSC/128 (default)
1 = fMOD = fOSC/256
bit 4
BUFEN: Buffer Enable
0 = Buffer Disabled (default)
1 = Buffer Enabled
bit 3
BIT ORDER: Data Output Bit Order
0 = Most Significant Bit Transmitted First (default)
1 = Least Significant Bit Transmitted First
Data is always shifted in or out MSB first.
bit 2
RANGE: Range Select
0 = Full-Scale Input Range equal to ±VREF (default).
1 = Full-Scale Input Range equal to ±1/2 VREF
NOTE: This allows reference voltages as high as
VDD, but even with a 5V reference voltage the
calibration must be performed with this bit set to 0.
bit 1–0
DR1: DR0: Data Rate
(fOSC = 2.4576MHz, SPEED = 0)
00 = 15 Hz (default)
01 = 7.5 Hz
10 = 3.75 Hz
11 = Reserved
ODAC
(Address 03) Offset DAC
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SIGN
OSET6
OSET5
OSET4
OSET3
OSET2
OSET1
OSET0
bit 7
Sign
0 = Positive
1 = Negative
Offset =
æ OSET [6:0]ö
VREF
· ç
÷ RANGE = 0
2 · PGA
127
è
ø
Offset =
æ OSET[ 6:0]ö
VREF
· ç
÷ RANGE = 1
4 · PGA
127
è
ø
NOTE: The offset DAC must be enabled after calibration or the calibration nullifies the effects.
DIO
(Address 04H) Data I/O
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIO 7
DIO 6
DIO 5
DIO 4
DIO 3
DIO 2
DIO 1
DIO 0
If the IOCON register is configured for data, a value written to this register appears on the data I/O pins if the pin is configured
as an output in the DIR register. Reading this register returns the value of the data I/O pins.
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DIR
(Address 05H) Direction Control for Data I/O
Reset Value = FFH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
Each bit controls whether the corresponding data I/O pin is an output (= 0) or input (= 1). The default power-up state is as
inputs.
IOCON
(Address 06H) I/O Configuration Register
Reset Value = 00H
bit 7
IO7
bit 7-0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IO6
IO5
IO4
IO3
IO2
IO1
IO0
IO7: IO0: Data I/O Configuration
0 = Analog (default)
1 = Data
Configuring the pin as a data I/O pin allows it to be controlled through the DIO and DIR registers.
ORC0
(Address 07H) Offset Calibration Coefficient
(Least Significant Byte)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
OCR1
(Address 08H) Offset Calibration Coefficient
(Middle Byte)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR09
OCR08
OCR2
(Address 09H) Offset Calibration Coefficient
(Most Significant Byte)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
FSR0
(Address 0AH) Full-Scale Register
(Least Significant Byte)
Reset Value = 59H
26
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR07
FSR06
FSR05
FSR04
FSR03
FSR02
FSR01
FSR00
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FSR1
(Address 0BH) Full-Scale Register
(Middle Byte)
Reset Value = 55H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR15
FSR14
FSR13
FSR12
FSR11
FSR10
FSR09
FSR08
FSR2
(Address 0CH) Full-Scale Register
(Most Significant Byte)
Reset Value = 55H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR23
FSR22
FSR21
FSR20
FSR19
FSR18
FSR17
FSR16
DOR2
(Address 0DH) Data Output Register
(Most Significant Byte) (Read Only)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DOR23
DOR22
DOR21
DOR20
DOR19
DOR18
DOR17
DOR16
DOR1
(Address 0EH) Data Output Register
(Middle Byte) (Read Only)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DOR15
DOR14
DOR13
DOR12
DOR11
DOR10
DOR09
DOR08
DOR0
(Address 0FH) Data Output Register
(Least Significant Byte) (Read Only)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DOR07
DOR06
DOR05
DOR04
DOR03
DOR02
DOR01
DOR00
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ADS1243 CONTROL COMMAND DEFINITIONS
The commands listed in Table IV control the operations of ADS1243. Some of the commands are stand-alone
commands (for example, RESET) while others require additional bytes (for example, WREG requires the count
and data bytes).
Operands:
• n = count (0 to 127)
• r = register (0 to 15)
• x = don’t care
Table 5. Command Summary
COMMANDS
DESCRIPTION
OP CODE
2nd COMMAND BYTE
Read Data
0000 0001 (01H)
—
Read Data Continuously
0000 0011 (03H)
—
Stop Read Data Continuously
0000 1111 (0FH)
—
Read from REG “rrrr”
0001 r r r r (1xH)
xxxx_nnnn (# of regs-1)
Write to REG “rrrr”
0101 r r r r (5xH)
xxxx_nnnn (# of regs-1)
Offset and Gain Self Cal
1111 0000 (F0H)
—
Self Offset Cal
1111 0001 (F1H)
—
Self Gain Cal
1111 0010 (F2H)
—
Sys Offset Cal
1111 0011 (F3H)
—
Sys GainCal
1111 0100 (F4H)
—
Wakup from SLEEP Mode
1111 1011 (FBH)
—
Sync DRDY
1111 1100 (FCH)
—
Put in SLEEP Mode
1111 1101 (FDH)
—
Reset to Power-Up Values
1111 1110 (FEH)
—
RDATA RDATAC
STOPC RREG
WREG SELFCAL
SELFOCAL
SELFGCAL
SYSOCAL
SYSGCAL
WAKEUP
DSYNC SLEEP
RESET
NOTE: The received data format is always MSB first; the data out format is set by the BIT ORDER bit in the ACR register.
RDATA–Read Data
Description:
Read the most recent conversion result from the Data Output Register (DOR). This is a
24-bit value.
Operands:
None
Bytes:
1
Encoding:
0000 0001
Data Transfer
Sequence:
DIN
0000 0001
• • •(1)
DOUT
(1)
xxxx xxxx
xxxx xxxx
xxxx xxxx
MSB
Mid-Byte
LSB
For wait time, refer to timing specification.
RDATAC–Read Data Continuous
Description:
Read Data Continuous mode enables the continuous output of new data on each DRDY. This
command eliminates the need to send the Read Data Command on each DRDY. This mode
may be terminated by either the STOPC command or the RESET command. Wait at least 10
fOSC after DRDY falls before reading.
Operands:
None
Bytes:
1
28
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Encoding:
0000 0011
Data Transfer
Sequence:
Command terminated when “uuuu uuuu” equals STOPC or RESET.
DRDY
• • •(1)
0000 0011
DIN
uuuu uuuu
uuuu uuuu
MSB
Mid-Byte
Mid-Byte
LSB
uuuu uuuu
•••
DOUT
DRDY
LSB
•••
MSB
DOUT
(1)
For wait time, refer to timing specification.
STOPC–Stop Continuous
Description:
Ends the continuous data output mode. Issue after DRDY goes LOW.
Operands:
None
Bytes:
1
Encoding:
0000 1111
Data Transfer
Sequence:
DRDY
DIN
xxx
0000 1111
RREG–Read from Registers
Description:
Output the data from up to 16 registers starting with the register address specified as part of
the instruction. The number of registers read will be one plus the second byte count. If the
count exceeds the remaining registers, the addresses wrap back to the beginning.
Operands:
r, n
Bytes:
2
Encoding:
0001 rrrr xxxx nnnn
Data Transfer
Sequence:
Read Two Registers Starting from Register 01H (MUX)
DIN
0001 0001
0000 0001
DOUT
• • •(1)
xxxx xxxx
xxxx xxxx
MUX
ACR
(1)
For wait time, refer to timing specification.
WREG–Write to Registers
Description:
Write to the registers starting with the register address specified as part of the instruction. The
number of registers that will be written is one plus the value of the second byte.
Operands:
r, n
Bytes:
2
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Encoding:
0101 rrrr xxxx nnnn
Data Transfer
Sequence:
Write Two Registers Starting from 04H (DIO)
0101 0100
DIN
xxxx 0001
Data for DIO
Data for DIR
SELFCAL–Offset and Gain Self Calibration
Description:
Starts the process of self calibration. The Offset Calibration Register (OCR) and the Full-Scale
Register (FSR) are updated with new values after this operation.
Operands:
None
Bytes:
1
Encoding:
1111 0000
Data Transfer
Sequence:
DIN
1111 0000
SELFOCAL–Offset Self Calibration
Description:
Starts the process of self-calibration for offset. The Offset Calibration Register (OCR) is
updated after this operation.
Operands:
None
Bytes:
1
Encoding:
1111 0001
Data Transfer
Sequence:
DIN
1111 0001
SELFGCAL–Gain Self Calibration
Description:
Starts the process of self-calibration for gain. The Full-Scale Register (FSR) is updated with
new values after this operation.
Operands:
None
Bytes:
1
Encoding:
1111 0010
Data Transfer
Sequence:
DIN
1111 0010
SYSOCAL–System Offset Calibration
Description:
Initiates a system offset calibration. The input should be set to 0V, and the ADS1243
computes the OCR value that compensates for offset errors. The Offset Calibration Register
(OCR) is updated after this operation. The user must apply a zero input signal to the
appropriate analog inputs. The OCR register is automatically updated afterwards.
Operands:
None
Bytes:
1
Encoding:
1111 0011
Data Transfer
Sequence:
DIN
30
1111 0011
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SYSGCAL–System Gain Calibration
Description:
Starts the system gain calibration process. For a system gain calibration, the input should be
set to the reference voltage and the ADS1243 computes the FSR value that will compensate
for gain errors. The FSR is updated after this operation. To initiate a system gain calibration,
the user must apply a full-scale input signal to the appropriate analog inputs. FCR register is
updated automatically.
Operands:
None
Bytes:
1
Encoding:
1111 0100
Data Transfer
Sequence:
DIN
1111 0100
WAKEUP
Description:
Wakes the ADS1243 from SLEEP mode.
Operands:
None
Bytes:
1
Encoding:
1111 1011
Data Transfer
Sequence:
DIN
1111 1011
DSYNC–Sync DRDY
Description:
Synchronizes the ADS1243 to an external event.
Operands:
None
Bytes:
1
Encoding:
1111 1100
Data Transfer
Sequence:
DIN
1111 1100
SLEEP–Sleep Mode
Description:
Puts the ADS1243 into a low power sleep mode. To exit sleep mode, issue the WAKEUP
command.
Operands:
None
Bytes:
1
Encoding:
1111 1101
Data Transfer
Sequence:
DIN
1111 1101
RESET–Reset to Default Values
Description:
Restore the registers to their power-up values. This command stops the Read Continuous
mode.
Operands:
None
Bytes:
1
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Encoding:
1111 1110
Data Transfer
Sequence:
DIN
32
1111 1110
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APPLICATION INFORMATION
GENERAL-PURPOSE WEIGHT SCALE
Figure 9 shows a typical schematic of a general-purpose weight scale application using the ADS1243. In this
example, the internal PGA is set to either 64 or 128 (depending on the maximum output voltage of the load cell)
so that the load cell output can be directly applied to the differential inputs of ADS1243.
2.7V ~ 5.25V
EMI Filter
VREF+
VDD
VDD
EMI Filter
AIN0
DRDY
Load Cell
SCLK
DOUT
DOUT
SPI
MSP430x4xx
or other
Microprocessor
CS
EMI Filter
AIN1
XIN
MCLK
XOUT
VREF–
GND
GND
EMI Filter
Figure 9. Schematic of a General-Purpose Weight Scale.
HIGH PRECISION WEIGHT SCALE
Figure 10 shows the typical schematic of a high-precision weight scale application using the ADS1243. The
front-end differential amplifier helps maximize the dynamic range.
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2.7V ~ 5.25V
2.7V ~ 5.25V
EMI Filter
VREF+
VDD
VDD
EMI Filter
RI
OPA2335
AIN0
Load Cell
RF
DRDY
SCLK
DOUT
CI
RG
ADS1243
RF
DIN
SPI
MSP430x4xx
or other
Microprocessor
CS
RI
EMI Filter
OPA2335
AIN1
XIN
MCLK
XOUT
VREF–
GND
GND
EMI Filter
G = 1 + 2 • RF/RG
Figure 10. Block Diagram for a High-Precision Weight Scale.
34
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DEFINITION OF TERMS
An attempt has been made to be consistent with the terminology used in this data sheet. In that regard, the
definition of each term is given as follows:
Analog Input Voltage – the voltage at any one analog input relative to GND.
Analog Input Differential Voltage –given by the following equation: (IN+) – (IN–). Thus, a positive digital output
is produced whenever the analog input differential voltage is positive, while a negative digital output is produced
whenever the differential is negative.
For example, when the converter is configured with a 2.5-V reference and placed in a gain setting of 1, the
positive full-scale output is produced when the analog input differential is 2.5 V. The negative full-scale output is
produced when the differential is –2.5 V. In each case, the actual input voltages must remain within the GND to
VDD range.
Conversion Cycle –the term conversion cycle usually refers to a discrete A/D conversion operation, such as that
performed by a successive approximation converter. As used here, a conversion cycle refers to the tDATA time
period.
Data Rate – The rate at which conversions are completed. See definition for fDATA.
f DATA =
f OSC
128 · 2SPEED · 1280 · 2DR
SPEED = 0,1
DR = 0, 1, 2
fOSC –the frequency of the crystal oscillator or CMOS compatible input signal at the XIN input of the ADS1243.
fMOD – the frequency or speed at which the modulator of the ADS1243 is running. This depends on the SPEED
bit as given by the following equation:
mfactor
f MOD =
SPEED = 0
SPEED = 1
128
256
f osc
f osc
=
mfactor 128 · 2SPEED
PGA SETTING
SAMPLING FREQUENCY
1, 2, 4, 8
f SAMP =
f OSC
mfactor
16
f SAMP =
f OSC · 2
mfactor
32
f SAMP =
f OSC · 4
mfactor
64, 128
f SAMP =
f OSC · 8
mfactor
fSAMP – the frequency, or switching speed, of the input sampling capacitor. The value is given by one of the
following equations:
fDATA – the frequency of the digital output data produced by the ADS1243, fDATA is also referred to as the Data
Rate.
Full-Scale Range (FSR) – as with most A/D converters, the full-scale range of the ADS1243 is defined as the
input, that produces the positive full-scale digital output minus the input, that produces the negative full-scale
digital output.
For example, when the converter is configured with a 2.5-V reference and is placed in a gain setting of 2, the
full-scale range is: [1.25 V (positive full-scale) minus –1.25 V (negative full-scale)] = 2.5 V.
Least Significant Bit (LSB) Weight – this is the theoretical amount of voltage that the differential voltage at the
analog input has to change in order to observe a change in the output data of one least significant bit. It is
computed as follows:
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LSBWeight =
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Full-ScaleRange
2N - 1
where N is the number of bits in the digital output.
tDATA – the inverse of fDATA, or the period between each data output.
Table 6. Full-Scale Range versus PGA Setting
5V SUPPLY ANALOG INPUT (1)
GAIN SETTING
FULL-SCALE
RANGE
DIFFERENTIAL
INPUT
VOLTAGES (2)
1
2
4
8
16
32
64
128
5V
2.5 V
1.25 V
0.625 V
312.5 mV
156.25 mV
78.125 mV
39.0625 mV
±2.5 V
±1.25 V
±0.625 V
±312.5 mV
±156.25 mV
±78.125 mV
±39.0625 mV
±19.531 mV
(1)
(2)
36
PGA OFFSET
RANGE
±1.25 V
±0.625 V
±312.5 mV
±156.25 mV
±78.125 mV
±39.0625 mV
±19.531 mV
±9.766 mV
GENERAL EQUATIONS
FULL-SCALE
RANGE
DIFFERENTIAL
INPUT
VOLTAGES (2)
PGA SHIFT
RANGE
RANGE = 0
V REF
PGA
± V REF
2 · PGA
± V REF
4 · PGA
RANGE = 1
With a 2.5-V reference.
Refer to electrical specification for analog input voltage range.
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PACKAGE OPTION ADDENDUM
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24-Jan-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS1243SJD
ACTIVE
CDIP SB
JD
20
1
TBD
AU
N / A for Pkg Type
-55 to 210
ADS1243SKGD1
ACTIVE
XCEPT
KGD
0
121
Green (RoHS
& no Sb/Br)
Call TI
N / A for Pkg Type
-55 to 210
ADS1243SJD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2019
OTHER QUALIFIED VERSIONS OF ADS1243-HT :
• Catalog: ADS1243
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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Copyright © 2019, Texas Instruments Incorporated
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