Texas Instruments | Low-Power, High-Speed Buffer for CCD Sensor (Rev. A) | Datasheet | Texas Instruments Low-Power, High-Speed Buffer for CCD Sensor (Rev. A) Datasheet

Texas Instruments Low-Power, High-Speed Buffer for CCD Sensor (Rev. A) Datasheet
VSP1000
SBES023A – SEPTEMBER 2011 – REVISED OCTOBER 2011
www.ti.com
Low-Power, High-Speed Buffer
for CCD Sensor
Check for Samples: VSP1000
FEATURES
DESCRIPTION
•
The VSP1000 is a high-speed, low-noise, low-power,
fast-settling, unity-gain buffer. It is specially designed
for use between charge-coupled device (CCD)
sensors and analog front-ends (AFEs). The device
has an adjustable active load current that can load
the CCD sensor output appropriately. The VSP1000
also features an adjustable output drive strength that
can be set in accordance with the bandwidth
requirements. At a 2-mA drive current, the device
provides a bandwidth of 210 MHz, which allows for
very low power operation with good performance. An
ultra-small package of 1 mm × 1 mm and 0.35-mm
height helps in saving printed circuit board (PCB)
space and achieving a very low profile.
1
2
•
•
•
•
•
High Speed:
– 210 MHz, 3-dB Bandwidth
Fast Settling Time
Adjustable Active Load Current
Adjustable Drive Strength
Low Power: 20 mW
Ultra-Small Package:
– 1-mm × 1-mm Ultra-Thin 0.35-mm QFN
The VSP1000 is ideal for driving Texas Instruments
AFEs for CCD sensors and, in general, any
analog-to-digital converter (ADC) inputs. The
adjustable load current allows for easy interfacing
with a variety of CCD sensors from various
manufacturers.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
VSP1000
SBES023A – SEPTEMBER 2011 – REVISED OCTOBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
VSP1000
QFN-6
DSF
0°C to +85°C
VSP1000DSF
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
VSP1000DSFT
Tape and Reel, 250
VSP1000DSFR
Tape and Reel, 5000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over free-air temperature range, unless otherwise noted.
Supply voltage
VCC
VSP1000
UNIT
20.0
V
–0.3 to VCC + 0.3
V
±10
mA
Ambient temperature under bias
–25 to +85
°C
Storage temperature
–55 to +125
°C
Junction temperature
+150
°C
Package temperature (IR reflow, peak)
+250
°C
Input voltage
Input current
(1)
2
Any pin except supplies
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): VSP1000
VSP1000
SBES023A – SEPTEMBER 2011 – REVISED OCTOBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
All specifications at TA = +25°C, VCC = 13 V, RIDRV = 90 kΩ, and CLOAD = 22 pF, unless otherwise noted.
VSP1000
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
10
13
16
UNIT
POWER SUPPLY
VCC
Supply voltage
ICC
Supply current
V
2
mA
0.999
ns
5
ns
ns
DYNAMIC PERFORMANCE
Gain
1-MHz, 200-mVPP input
Rise time
VIN = 7.5 V to 8.5 V
Fall time
VIN = 8.5 V to 7.5 V
6
I/O delay time
VIN = 7.5 V to 8.5 V
1.28
ns
–3-dB bandwidth
100-mVPP input
210
MHz
VIN
Input voltage range
VCC = 13 V
TA
Operating free-air temperature
1.5
10.5
V
0
+85
°C
THERMAL INFORMATION
VSP1000
THERMAL METRIC
(1)
DSF
UNITS
6 PINS
θJA
Junction-to-ambient thermal resistance
333.2
θJCtop
Junction-to-case (top) thermal resistance
56.9
θJB
Junction-to-board thermal resistance
239
ψJT
Junction-to-top characterization parameter
13.9
ψJB
Junction-to-board characterization parameter
236
θJCbot
Junction-to-case (bottom) thermal resistance
202
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): VSP1000
3
VSP1000
SBES023A – SEPTEMBER 2011 – REVISED OCTOBER 2011
www.ti.com
PIN CONFIGURATION
DSF PACKAGE
1-mm × 1-mm × 0.35-mm QFN-6
(TOP VIEW)
IN
1
6
ISF
GND
2
5
VCC
OUT
3
4
IDRV
PIN ASSIGNMENTS
PIN NAME
PIN NUMBER
TYPE
IN
1
Analog input
VEE
2
Ground
DESCRIPTION
Input terminal; connect this pin to the sensor output
Negative supply terminal; must be connected to ground
OUT
3
Analog output
IDRV
4
Analog input
VCC
5
Power
ISF
6
Analog input
Output terminal; connect this pin to the AFE input
Drive current adjustment; refer to the application diagram for further details
Positive supply terminal; must be decoupled to the VEE terminal with a 0.1-µF
capacitor
Sink current adjustment; refer to the application diagram for further details
FUNCTIONAL BLOCK DIAGRAM
IN
1
IIN
ICC
GND
6
ISF
5
VCC
4
IDRV
IISF
2
IIDRV
OUT
3
Figure 1. Block Diagram
4
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): VSP1000
VSP1000
SBES023A – SEPTEMBER 2011 – REVISED OCTOBER 2011
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VCC = 13 V, RIDRV = 90 kΩ, RISF = 300 kΩ, and CLOAD = 22 pF, unless otherwise noted.
BANDWIDTH vs IDRV
INPUT MARGIN FROM VCC vs IDRV
300
4
Input Margin From VCC (V)
Bandwidth (MHz)
250
200
150
100
50
0
60
80
100
IDRV (µA)
120
3
2
1
0
140
50
100
150
IDRV (µA)
G001
Figure 2.
100
4
75
50
25
100
150
200
250
300
G006
INPUT LOAD CURRENT vs RISF
5
Input Load Current (mA)
IDRV Current (µA)
IDRV vs RIDRV
50
250
Figure 3.
125
0
200
350
400
450
IDRV Resistance (kΩ)
3
2
1
0
100 150 200 250 300 350 400 450 500 550 600 650
500
RISF (kΩ)
G002
Figure 4.
G004
Figure 5.
IDRV vs TEMPERATURE
INPUT LOAD CURRENT vs TEMPERATURE
80
3
Input Load Current (mA)
2.8
IDRV (µA)
75
70
65
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
60
−5
10
25
40
55
Temperature (°C)
70
85
1
0
G003
Figure 6.
12.5
25
37.5
50
Temperature (°C)
62.5
75
85
G005
Figure 7.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): VSP1000
5
VSP1000
SBES023A – SEPTEMBER 2011 – REVISED OCTOBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VCC = 13 V, RIDRV = 90 kΩ, RISF = 300 kΩ, and CLOAD = 22 pF, unless otherwise noted.
ICC vs TEMPERATURE
3
ICC (mA)
2.5
2
1.5
1
0
12.5
25
37.5
50
Temperature (°C)
62.5
75
85
G007
Figure 8.
OVERVIEW
TYPICAL APPLICATION CIRCUIT
Figure 9 shows a typical application circuit for the VSP1000.
VCC
0.1 mF
C4
RISF
6
ISF
5
4
VCC
IDRV
RIDRV
Device
IN
1
GND
OUT
2
3
To AFE
From CCD
Figure 9. Typical Application Circuit
6
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): VSP1000
VSP1000
SBES023A – SEPTEMBER 2011 – REVISED OCTOBER 2011
www.ti.com
DESIGN EQUATIONS
The CCD outputs must be loaded with current for proper operation. The VSP1000 provides the ability to draw
adjustable current through the IN pin. The value of the input load current can be set by choosing an appropriate
value of RISF connected to the ISF pin, as per Equation 1.
(VCC ´ 100 kW)
(RISF + 100 kW)
IIN =
- 1.2
1 kW
(1)
The bandwidth of the VSP1000 can be adjusted using the IDRV pin. The resistor connected at IDRV determines
the drive strength of the output buffer as well as the total quiescent current of the VSP1000. Equation 2 and
Equation 3 describe the relationship between RIDRV and the drive strength. CIDRV is used to increase the
power-supply rejection ratio of the device. A value of 0.1 µF for CIDRV is recommended.
(VCC - 5)
IDRV =
(RIDRV + 10 kW)
(2)
ICC = 26 ´ IDRV
(3)
EXAMPLE CONFIGURATIONS
Table 1 details several example configurations for the VSP1000. All examples are with VCC = 13 V.
Table 1. Example Configurations
CONFIGURATION
ICC (mA)
RISF (kΩ)
RIDRV (kΩ)
Bandwidth = 170 MHz , IIN = 2 mA
1.5
300
133
Bandwidth = 170 MHz , IIN = 4 mA
1.5
150
133
Bandwidth = 210 MHz , IIN = 2 mA
2
300
91
Bandwidth = 210 MHz , IIN = 4 mA
2
150
91
Bandwidth = 260 MHz , IIN = 2 mA
3
300
62
Bandwidth = 260 MHz , IIN = 4 mA
3
150
62
LAYOUT GUIDELINES
The decoupling capacitors CIDRV, RIDRV, and RISF should be placed as close as possible to the VSP1000.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): VSP1000
7
VSP1000
SBES023A – SEPTEMBER 2011 – REVISED OCTOBER 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2011) to Revision A
Page
•
Updated Figure 4 .................................................................................................................................................................. 5
•
Updated Figure 5 .................................................................................................................................................................. 5
8
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): VSP1000
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
VSP1000DSFR
ACTIVE
SON
DSF
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
0 to 85
VK
VSP1000DSFT
ACTIVE
SON
DSF
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
0 to 85
VK
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
VSP1000DSFR
SON
DSF
6
5000
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
VSP1000DSFT
SON
DSF
6
250
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Apr-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
VSP1000DSFR
SON
DSF
6
5000
184.0
184.0
19.0
VSP1000DSFT
SON
DSF
6
250
184.0
184.0
19.0
Pack Materials-Page 2
PACKAGE OUTLINE
DSF0006A
X2SON - 0.4 mm max height
SCALE 10.000
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.05
0.95
0.4 MAX
C
SEATING PLANE
0.05 C
(0.11) TYP
SYMM
0.05
0.00
3
4
SYMM
2X
0.7
4X
0.35
6
1
6X
(0.1)
PIN 1 ID
6X
0.45
0.35
0.22
0.12
0.07
0.05
C B A
C
4220597/A 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.
www.ti.com
EXAMPLE BOARD LAYOUT
DSF0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6X (0.17)
6
SYMM
4X (0.35)
4
3
SYMM
(0.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220597/A 06/2017
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DSF0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6
6X (0.17)
SYMM
4X (0.35)
4
3
SYMM
(0.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
4220597/A 06/2017
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising