Texas Instruments | THS1007: 10-Bit, 4 Analog Input, 6-MSPS, Simultaneous Sampling A/D Converte (Rev. B) | Datasheet | Texas Instruments THS1007: 10-Bit, 4 Analog Input, 6-MSPS, Simultaneous Sampling A/D Converte (Rev. B) Datasheet

Texas Instruments THS1007: 10-Bit, 4 Analog Input, 6-MSPS, Simultaneous Sampling A/D Converte (Rev. B) Datasheet
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
10-BIT, 4 ANALOG INPUT, 6-MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
FEATURES
D Simultaneous Sampling of 4 Single-Ended
D
D
D
D
D
D
D
D
D
D
D
Signals or 2 Differential Signals or
Combination of Both
Signal-to-Noise and Distortion Ratio: 59 dB
at fI = 2 MHz
Differential Nonlinearity Error: ±1 LSB
Integral Nonlinearity Error: ±1 LSB
Auto-Scan Mode for 2, 3, or 4 Inputs
3-V or 5-V Digital Interface Compatible
Low Power: 216 mW Max at 5 V
Power Down: 1 mW Max
5-V Analog Single Supply Operation
Internal Voltage References . . . 50 PPM/°C
and ±5% Accuracy
Glueless DSP Interface
Parallel μC/DSP Interface
APPLICATIONS
D Radar Applications
D Communications
D Control Applications
D High-Speed DSP Front-End
D Automotive Applications
DESCRIPTION
The THS1007 is a CMOS, low-power, 10-bit, 6 MSPS
analog-to-digital converter (ADC). The speed, resolution,
bandwidth, and single-supply operation are suited for
applications in radar, imaging, high-speed acquisition, and
communications. A multistage pipelined architecture with
output error correction logic provides for no missing codes
over the full operating temperature range. Internal control
registers are used to program the ADC into the desired
mode. The THS1007 consists of four analog inputs, which
are sampled simultaneously. These inputs can be selected
individually and configured to single-ended or differential
inputs. Internal reference voltages for the ADC (1.5 V and
3.5 V) are provided. An external reference can also be
chosen to suit the dc accuracy and temperature drift
requirements of the application.
The THS1007C is characterized for operation from 0°C to
70°C, and the THS1007I is characterized for operation
from −40°C to 85°C.
DA (TSSOP) PACKAGE
(TOP VIEW)
D0
D1
D2
D3
D4
D5
BVDD
BGND
D6
D7
D8
D9
RA0
RA1
CONV_CLK
SYNC
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
AINP
AINM
BINP
BINM
REFIN
REFOUT
REFP
REFM
AGND
AVDD
CS0
CS1
WR (R/W)
RD
DVDD
DGND
ORDERING INFORMATION
PACKAGED DEVICE
TA
TSSOP
(DA)
0°C to 70°C
THS1007CDA
−40°C to 85°C
THS1007IDA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright © 2002, Texas Instruments Incorporated
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNITS
Supply voltage range
DGND to DVDD
−0.3 V to 6.5 V
BGND to BVDD
−0.3 V to 6.5 V
AGND to AVDD
−0.3 V to 6.5 V
Analog input voltage range
AGND −0.3 V to AVDD + 1.5 V
Reference input voltage
−0.3 V + AGND to AVDD + 0.3 V
Digital input voltage range
−0.3 V to BVDD/DVDD + 0.3 V
Operating virtual junction temperature range, TJ
Operating free-air
free air temperature range
range, TA
−40°C to 150°C
THS1007C
0°C to 70°C
THS1007I
−40°C to 85°C
Storage temperature range, Tstg
−65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
260°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
POWER SUPPLY
Supply
pp y voltage
g
MIN
NOM
MAX
AVDD
4.75
5
5.25
DVDD
4.75
5
5.25
BVDD
3
ANALOG AND REFERENCE INPUTS
MIN
Analog input voltage in single-ended configuration
NOM
1
External reference voltage,VREFP (optional)
External reference voltage, VREFM (optional)
1.4
Input voltage difference, REFP − REFM
DIGITAL INPUTS
High level input voltage,
High-level
voltage VIH
Low level input voltage,
Low-level
voltage VIL
MIN
BVDD = 3.3 V
BVDD = 5.25 V
V
5.25
MAX
VREFM
Common-mode input voltage VCM in differential configuration
UNIT
UNIT
VREFP
V
2.5
4
V
3.5
AVDD−1.2
V
1.5
V
2
V
NOM
MAX
UNIT
2
V
2.6
V
BVDD = 3.3 V
0.6
BVDD = 5.25 V
0.6
V
Input CONV_CLK frequency
DVDD = 4.75 V to 5.25 V
0.1
CONV_CLK pulse duration, clock high, tw(CONV_CLKH)
DVDD = 4.75 V to 5.25 V
80
83
5000
ns
CONV_CLK pulse duration, clock low, tw(CONV_CLKL)
DVDD = 4.75 V to 5.25 V
80
83
5000
ns
Operating free-air
free air temperature,
temperature TA
2
THS1007CDA
THS1007IDA
6
V
0
70
−40
85
MHz
°C
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, AVDD = DVDD = 5 V, BVDD = 3.3 V, VREF = internal (unless otherwise noted)
DIGITAL SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital inputs
IIH
High-level input current
DVDD = digital inputs
−50
50
μA
IIL
Low-level input current
Digital input = 0 V
−50
50
μA
Ci
Input capacitance
5
pF
Digital outputs
VOH
High-level output voltage
IOH = −50 μA,
BVDD = 3.3 V, 5 V
VOL
Low-level output voltage
IOL = 50 μA,
BVDD = 3.3 V, 5 V
IOZ
High-impedance-state output current
CS1 = DGND,
CS0 = DVDD
CO
Output capacitance
CL
Load capacitance at databus D0 − D9
BVDD−0.5
V
−10
0.4
V
10
μA
5
pF
30
pF
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, AVDD = DVDD = 5 V, BVDD = 3.3 V, fs = 6 MSPS, VREF = internal (unless otherwise noted)
DC SPECIFICATIONS
PARAMETER
TEST CONDITIONS
Resolution
MIN
TYP
MAX
10
UNIT
Bits
Accuracy
Integral nonlinearity, INL
±1
LSB
Differential nonlinearity, DNL
±1
LSB
Offset error
After calibration in single-ended mode
Offset error
After calibration in differential mode
Gain error
LSB
±5
−10
10
LSB
−10
10
LSB
Analog input
Input capacitance
Input leakage current
15
VAIN = VREFM to VREFP
pF
±10
μA
V
Internal voltage reference
Accuracy, VREFP
3.3
3.5
3.7
Accuracy, VREFM
1.4
1.5
1.6
Temperature coefficient
50
Reference noise
100
Accuracy, REFOUT
2.475
V
PPM/°
C
μV
2.5
2.525
V
Power supply
IDDA
Analog supply current
AVDD = DVDD = 5 V, BVDD =3.3 V
36
40
mA
IDDD
Digital supply current
AVDD = DVDD = 5 V, BVDD = 3.3 V
0.5
3
mA
IDDB
Buffer supply current
AVDD = DVDD = 5 V, BVDD = 3.3 V
1.5
4
mA
Power dissipation
AVDD = DVDD = 5 V, BVDD = 3.3 V
186
216
mW
Power dissipation in power down with conversion
clock inactive
AVDD = DVDD = 5 V, BVDD = 3.3 V
0.25
mW
3
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, VREF = internal, fs = 6 MSPS, fI = 2 MHz at −1 dBFS (unless otherwise noted)
AC SPECIFICATIONS, AVDD = DVDD = 5 V, BVDD = 3.3 V, CL < 30 pF
PARAMETER
SINAD
SNR
THD
ENOB
(SNR)
SFDR
Signal to noise ratio + distortion
Signal-to-noise
Signal to noise ratio
Signal-to-noise
Total harmonic distortion
MIN
TYP
Differential mode
TEST CONDITIONS
56
59
dB
Single-ended mode
55
58
dB
Differential mode
59
61
dB
Single-ended mode
58
60
−64
−61
Single-ended mode
−63
−60
Single-ended mode
Spurious free dynamic range
UNIT
dB
Differential mode
Differential mode
Effective number of bits
MAX
dB
dB
9
9.5
Bits
8.85
9.35
Bits
Differential mode
61
65
dB
Single-ended mode
60
64
dB
Analog Input
Full-power bandwidth with a source impedance of 150 Ω in
differential configuration.
Full scale sinewave, −3 dB
96
MHz
Full-power bandwidth with a source impedance of 150 Ω in
single-ended configuration.
Full scale sinewave, −3 dB
54
MHz
Small-signal bandwidth with a source impedance of 150 Ω in
differential configuration.
100 mVpp sinewave, −3 dB
96
MHz
Small-signal bandwidth with a source impedance of 150 Ω in
single-ended configuration.
100 mVpp sinewave, −3 dB
54
MHz
TIMING REQUIREMENTS
AVDD = DVDD = 5 V, BVDD = 3.3 V, VREF = internal, CL < 30 pF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CONV
CLK
tpipe
Latency
tsu(CONV_CLKL-READL)
Setup time, CONV_CLK low before CS valid
10
tsu(READH-CONV_CLKL)
Setup time, CS invalid to CONV_CLK low
20
td(CONV_CLKL-SYNCL)
Delay time, CONV_CLK low to SYNC low
10
ns
td(CONV_CLKL-SYNCH)
Delay time, CONV_CLK low to SYNC high
10
ns
4
5
ns
ns
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AINP
32
I
Analog input, single-ended or positive input of differential channel A
AINM
31
I
Analog input, single-ended or negative input of differential channel A
BINP
30
I
Analog input, single-ended or positive input of differential channel B
BINM
29
I
Analog input, single-ended or negative input of differential channel B
AVDD
23
I
Analog supply voltage
AGND
24
I
Analog ground
BVDD
7
I
Digital supply voltage for buffer
BGND
8
I
Digital ground for buffer
CONV_CLK
15
I
Digital input. This input is the conversion clock input.
CS0
22
I
Chip select input (active low)
CS1
21
I
Chip select input (active high)
SYNC
16
O
Synchronization output. This signal indicates in a multichannel operation that data of channel A is brought to
the digital output and can therefore be used for synchronization.
DGND
17
I
Digital ground. Ground reference for digital circuitry.
DVDD
18
I
Digital supply voltage
1−6,
9−12
I/O/Z
RA0
13
I
Digital input. RA0 is used as an address line for the control register. This is required for writing to the control
register 0 and control register 1. See Table 7.
RA1
14
I
Digital input. RA1 is used as an address line for the control register. This is required for writing to control
register 0 and control register 1. See Table 7.
REFIN
28
I
Common-mode reference input for the analog input channels. It is recommended that this pin be connected to
the reference output REFOUT.
REFP
26
I
Reference input, requires a bypass capacitor of 10 μF to AGND in order to bypass the internal reference
voltage. An external reference voltage at this input can be applied. This option can be programmed through
control register 0. See Table 8.
REFM
25
I
Reference input, requires a bypass capacitor of 10 μF to AGND in order to bypass the internal reference
voltage. An external reference voltage at this input can be applied. This option can be programmed through
control register 0. See Table 8.
REFOUT
27
O
Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 μA. The reference output
requires a capacitor of 10 μF to AGND for filtering and stability.
RD(1)
19
I
The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input,
active low as a data read select from the processor. See timing section.
WR (R/W)(1)
20
I
This input is programmable. It functions as a read-write input R/W and can also be configured as a write-only
input WR, which is active low and used as data write select from the processor. In this case, the RD input is
used as a read input from the processor. See timing section.
D0 – D9
(1)
Digital input, output; D0 = LSB
The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.
5
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
2.5 V
3.5 V
REFP
1.225 V
REF
1.5 V
REFOUT
REFM
REFIN
AINP
VREFM
S/H
VREFP
AINM
S/H
BINP
S/H
BINM
S/H
CONV_CLK
CS0
CS1
RD
WR (R/W)
Logic
and
Control
Single
Ended
and/or
Differential
MUX
+
−
BVDD
10 Bit
Pipeline
ADC
10
Buffers
Control
Register
BGND
SYNC
AGND
6
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
RA0
RA1
DGND
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
SIGNAL-TO-NOISE AND DISTORTION
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
80
SINAD − Signal-to-Noise and Distortion − dB
THD − Total Harmonic Distortion − dB
90
80
70
60
50
40
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −0.5 dB FS
30
20
0
1
2
3
4
5
6
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −0.5 dB FS
70
60
50
40
30
20
7
0
1
fs − Sampling Frequency − MHz
2
Figure 1
5
6
7
SIGNAL-TO-NOISE
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
90
80
80
70
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −0.5 dB FS
SNR − Signal-to-Noise − dB
SFDR − Spurious Free Dynamic Range − dB
4
Figure 2
SPURIOUS FREE DYNAMIC RANGE
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
70
60
50
40
60
50
40
30
30
20
3
fs − Sampling Frequency − MHz
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −0.5 dB FS
0
1
2
3
4
5
fs − Sampling Frequency − MHz
Figure 3
6
20
7
0
1
2
3
4
5
6
7
fs − Sampling Frequency − MHz
Figure 4
7
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
SIGNAL-TO-NOISE AND DISTORTION
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
80
SINAD − Signal-to-Noise and Distortion − dB
THD − Total Harmonic Distortion − dB
90
80
70
60
50
40
30
20
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −0.5 dB FS
0
1
2
3
4
5
6
70
60
50
40
30
20
7
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −0.5 dB FS
0
1
fs − Sampling Frequency − MHz
2
Figure 5
6
7
80
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −0.5 dB FS
90
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −0.5 dB FS
70
SNR − Signal-to-Noise − dB
SFDR − Spurious Free Dynamic Range − dB
5
SIGNAL-TO-NOISE
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
100
80
70
60
60
50
40
30
50
20
0
1
2
3
4
5
fs − Sampling Frequency − MHz
Figure 7
8
4
Figure 6
SPURIOUS FREE DYNAMIC RANGE
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
40
3
fs − Sampling Frequency − MHz
6
7
0
1
2
3
4
5
fs − Sampling Frequency − MHz
Figure 8
6
7
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY (SINGLE-ENDED)
80
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = −1 dB FS
80
SINAD − Signal-to-Noise and Distortion − dB
THD − Total Harmonic Distortion − dB
90
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY (SINGLE-ENDED)
70
60
50
40
30
20
0
1
2
3
4
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = −1 dB FS
70
60
50
40
30
20
fi − Input Frequency − MHz
0
1
SIGNAL-TO-NOISE
vs
INPUT FREQUENCY (SINGLE-ENDED)
80
90
75
80
70
SNR − Signal-to-Noise − dB
SFDR − Spurious Free Dynamic Range − dB
4
Figure 10
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY (SINGLE-ENDED)
60
3
fi − Input Frequency − MHz
Figure 9
70
2
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = −1 dB FS
50
40
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = −1 dB FS
65
60
55
50
45
40
35
30
30
25
20
0.0
0.5
1.0
1.5
2.0
2.5
fi − Input Frequency − MHz
Figure 11
3.0
3.5
20
0.0
0.5
1.0
1.5
2.0
2.5
fi − Input Frequency − MHz
3.0
3.5
Figure 12
9
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY (DIFFERENTIAL)
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY (DIFFERENTIAL)
80
80
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = −0.5 dB FS
SINAD − Signal-to-Noise and Distortion − dB
THD − Total Harmonic Distortion − dB
90
70
60
50
40
30
20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
70
60
50
40
30
20
0.0
3.5
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = −0.5 dB FS
0.5
fi − Input Frequency − MHz
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY (DIFFERENTIAL)
2.5
3.0
3.5
80
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = −0.5 dB FS
80
70
SNR − Signal-to-Noise − dB
SFDR − Spurious Free Dynamic Range − dB
2.0
SIGNAL-TO-NOISE
vs
INPUT FREQUENCY (DIFFERENTIAL)
90
70
60
50
40
30
0.5
1.0
1.5
2.0
2.5
Figure 15
3.0
60
50
40
30
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = −0.5 dB FS
fi − Input Frequency − MHz
10
1.5
Figure 14
Figure 13
20
0.0
1.0
fi − Input Frequency − MHz
3.5
20
0.0
0.5
1.0
1.5
2.0
2.5
fi − Input Frequency − MHz
Figure 16
3.0
3.5
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
EFFECTIVE NUMBER OF BITS
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
12
AVDD = 5 V, DVDD = BVDD = 3 V,
fin = 500 kHz, AIN = −0.5 dB FS
ENOB − Effective Number of Bits − Bits
ENOB − Effective Number of Bits − Bits
12
11
10
9
8
7
6
0
1
2
3
4
5
6
AVDD = 5 V, DVDD = BVDD = 3 V,
fin = 500 kHz, AIN = −0.5 dB FS
11
10
9
8
7
6
7
0
1
2
fs − Sampling Frequency − MHz
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY (SINGLE-ENDED)
ENOB − Effective Number of Bits − Bits
ENOB − Effective Number of Bits − Bits
6
7
12
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = −1 dB FS
10
9
8
7
0.0
5
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY (DIFFERENTIAL)
12
6
4
Figure 18
Figure 17
11
3
fs − Sampling Frequency − MHz
0.5
1.0
1.5
2.0
2.5
fi − Input Frequency − MHz
Figure 19
3.0
3.5
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = −0.5 dB FS
11
10
9
8
7
6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
fi − Input Frequency − MHz
Figure 20
11
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
vs
TEMPERATURE
INTEGRAL NONLINEARITY
vs
TEMPERATURE
0.70
0.66
0.64
0.68
DNL − Differential Nonlinearity − LSB
INL − Integral Nonlinearity − LSB
0.68
0.70
AVDD = 5 V,
BVDD = DVDD = 3.3 V,
Differential Mode,
Internal Reference,
Internal Oscillator
0.62
0.60
0.58
0.56
0.54
0.52
0.50
−40
−15
10
35
60
85
0.66
0.64
0.62
0.60
0.58
0.56
0.54
AVDD = 5 V,
BVDD = DVDD = 3.3 V,
Differential Mode,
Internal Reference,
Internal Oscillator
0.52
0.50
−40
−15
TA − Temperature − °C
Figure 21
Figure 22
GAIN
vs
INPUT FREQUENCY (SINGLE-ENDED)
5
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = −0.5 dB FS
0
G − Gain − dB
−5
−10
−15
−20
−25
−30
0
10 20 30 40 50 60 70 80 90 100 110 120
fi − Input Frequency − MHz
Figure 23
12
10
35
TA − Temperature − °C
60
85
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS
FAST FOURIER TRANSFORM (4096 POINTS)
(SINGLE-ENDED)
vs
FREQUENCY
0
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = −0.5 dB FS, fin = 1 MHz
Magnitude − dB
−20
−40
−60
−80
−100
−120
−140
0.0
0.5
1.0
1.5
2.0
2.5
3.0
f − Frequency − MHz
Figure 24
FAST FOURIER TRANSFORM (4096 POINTS)
(DIFFERENTIAL)
vs
FREQUENCY
0
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MSPS, AIN = −0.5 dB FS, fin = 1 MHz
Magnitude − dB
−20
−40
−60
−80
−100
−120
−140
0.0
0.5
1.0
1.5
2.0
2.5
3.0
f − Frequency − MHz
Figure 25
13
THS1007
www.ti.com
SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS
DNL − Differential Nonlinearity − LSB
DIFFERENTIAL NONLINEARITY
vs
ADC CODE
1.0
0.8
AVDD = 5 V,
DVDD = BVDD = 3 V,
fs = 8 MSPS
0.6
0.4
0.2
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0
256
512
768
1024
ADC Code
Figure 26
INL − Integral Nonlinearity − LSB
INTEGRAL NONLINEARITY
vs
ADC CODE
1.0
0.8
0.6
AVDD = 5 V,
DVDD = BVDD = 3 V,
fs = 8 MSPS
0.4
0.2
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0
256
512
ADC Code
Figure 27
14
768
1024
THS1007
www.ti.com
SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
DETAILED DESCRIPTION
Reference Voltage
The THS1007 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V
and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP
and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish
the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.
Analog Inputs
The THS1007 consists of 4 analog inputs, which are sampled simultaneously. These inputs can be selected
individually and configured as single-ended or differential inputs. The desired analog input channel can be
programmed.
Converter
The THS1007 uses a 10-bit pipelined multistaged architecture, which achieves a high sample rate with low
power consumption. The THS1007 distributes the conversion over several smaller ADC sub-blocks, refining
the conversion with progressively higher accuracy as the device passes the results from stage to stage. This
distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC.
A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input
sample while the second through the eighth stages operate on the seven preceding samples.
Conversion Clock
An external clock signal with a duty cycle of 50% has to be applied to the clock input (CONV_CLK). A new
conversion is started with every falling edge of the applied clock signal. The conversion values are available
at the output with a latency of 5 clock cycles.
SYNC
In multichannel mode, the first SYNC signal is delayed by [7+ (# Channels Sampled)] cycles of the CONV_CLK
after a SYNC reset. This is due to the latency of the pipeline architecture of the THS1007.
Sampling Rate
The maximum possible conversion rate per channel is dependent on the selected analog input channels.
Table 1 shows the maximum conversion rate for different combinations.
Table 1. Maximum Conversion Rate in Continuous Conversion Mode
NUMBER OF
CHANNELS
MAXIMUM CONVERSION
RATE PER CHANNEL
1 single-ended channel
1
6 MSPS
2 single-ended channels
2
3 MSPS
3 single-ended channels
3
2 MSPS
4 single-ended channels
4
1.5 MSPS
1 differential channel
1
6 MSPS
2 differential channels
2
3 MSPS
1 single-ended and 1 differential channel
2
3 MSPS
2 single-ended and 1 differential channels
3
2 MSPS
CHANNEL CONFIGURATION
The maximum conversion rate per channel, fc, is given by:
fc + 6 MSPS
# channels
15
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
Conversion
During conversion, the ADC operates with a free running external clock applied to the input CONV_CLK. With
every falling edge of the CONV_CLK signal a new converted value is available to the data bus with the
corresponding read signal. The THS1007 allows up to four analog inputs to be selected. The inputs can be
configured as two differential channels, four single-ended channels or a combination of differential and
signle-ended.
To provide the system with channel information, the THS1007 utilizes an active low SYNC signal. When
operated in a multichannel configuration, the SYNC signal is active low when data from channel 1 is available
to the databus. When operated in signle-channel mode (single-ended or differential operation) the SYNC signal
is disabled.
Figure 28 shows the timing of the conversion, when one analog input channel is selected. The maximum
throughput rate is 6 MSPS in this mode. The signal SYNC is disabled for the selection of one analog input since
this information is not necessary. There is a certain timing relationship required for the read signal with respect
to the conversion clock. This can be seen in Figure 28 and the timing specifications. A more detailed description
of the timing is given in the timing section and signal description of the THS1007.
Sample N
Channel 1
Sample N+1
Channel 1
Sample N+2
Channel 1
Sample N+3
Channel 1
Sample N+4
Channel 1
Sample N+5
Channel 1
Sample N+6
Channel 1
AIN
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
CONV_CLK
tc
tsu(READH-CONV_CLKL)
tsu(CONV_CLKL-READL)
READ†
Data N−4
Channel 1
†READ
Data N−3
Channel 1
Data N−2
Channel 1
Data N−1
Channel 1
Data N
Channel 1
Data N+1
Channel 1
Data N+2
Channel 1
is the logical combination from CS0, CS1 and RD
Figure 28. Conversion Timing in 1-Channel Operation
Figure 29 shows the conversion timing when two analog input channels are selected. The maximum throughput
rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted
data is available to the data bus. The SYNC pulse is active low when the data of channel one is available to
the databus. The data of channel one is followed by the data of channel two before the SYNC signal is active
low again.
16
THS1007
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Sample N+1
Channel 1, 2
Sample N
Channel 1, 2
AIN
Sample N+3
Channel 1, 2
Sample N+2
Channel 1, 2
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
CONV_CLK
tc
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
READ†
td(CONV_CLKL-SYNCL)
td(CONV_CLKL-SYNCH)
SYNC
Data N−2
Channel 1
†READ
Data N−2
Channel 2
Data N−1
Channel 1
Data N−1
Channel 2
Data N
Channel 1
Data N
Channel 2
Data N+1
Channel 1
is the logical combination from CS0, CS1 and RD
Figure 29. Conversion Timing in 2-Channel Operation
Figure 30 shows the conversion timing when three analog input channels are selected. The maximum
throughput rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which
order the converted data is available to the data bus. The SYNC signal is active low when the data of channel
one is available to the data bus. The data of channel one is followed by the data of channel two and channel
three before channel one is again available and the SYNC signal is active low.
Sample N
Channel 1, 2, 3
Sample N+1
Channel 1, 2, 3
Sample N+2
Channel 1, 2, 3
AIN
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
CONV_CLK
tc
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
READ†
td(CONV_CLKL-SYNCH)
td(CONV_CLKL-SYNCL)
SYNC
Data N−2
Channel 3
†READ
Data N−1
Channel 1
Data N−1
Channel 2
Data N−1
Channel 3
Data N
Channel 1
Data N
Channel 2
Data N
Channel 3
is the logical combination from CS0, CS1 and RD
Figure 30. Conversion Timing in 3-Channel Operation
17
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
Figure 31 shows the conversion timing when four analog input channels are selected. The maximum throughput
rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows in which order the
converted data is available to the databus. The SYNC signal is active low when the data of channel one is
available to the data bus. The data of channel one is followed by the data of channel two, the data of channel
three and the data of channel four before channel one is again available to the databus and SYNC is active low.
Sample N
Channel 1, 2, 3, 4
Sample N+1
Channel 1, 2, 3, 4
AIN
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
CONV_CLK
tc
tsu(READH-CONV_CLKL)
tsu(CONV_CLKL-READL)
READ†
tsu(CONV_CLKL-SYNCH)
tsu(CONV_CLKL-SYNCL)
SYNC
Data N−1
Channel 1
†READ
Data N−1
Channel 2
Data N−1
Channel 3
Data N−1
Channel 4
Data N
Channel 1
Data N
Channel 2
is the logical combination from CS0, CS1 and RD
Figure 31. Timing of Continuous Conversion Mode (4-channel operation)
18
Data N
Channel 3
THS1007
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DIGITAL OUTPUT DATA FORMAT
The digital output data format of the THS1007 can either be in binary format or in twos complement format. The
following tables list the digital outputs for the analog input voltages.
Table 2. Binary Output Format for Single-Ended Configuration
SINGLE-ENDED, BINARY OUTPUT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
AIN = VREFP
3FFh
AIN = (VREFP + VREFM)/2
200h
AIN = VREFM
000h
Table 3. Two’s Complement Output Format for Single-Ended Configuration
SINGLE-ENDED, TWOS COMPLEMENT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
AIN = VREFP
1FFh
AIN = (VREFP + VREFM)/2
000h
AIN = VREFM
200h
Table 4. Binary Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
Vin = AINP − AINM
VREF = VREFP − VREFM
Vin = VREF
3FFh
Vin = 0
200h
Vin = −VREF
000h
Table 5. Two’s Complement Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
Vin = AINP − AINM
VREF = VREFP − VREFM
Vin = VREF
1FFh
Vin = 0
000h
Vin = −VREF
200h
19
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
ADC CONTROL REGISTER
The THS1007 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the
desired mode. The bit definitions of both control registers are shown in 6.
Table 6. Bit Definitions of Control Register CR0 and CR1
REG
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CR0
TEST1
TEST0
SCAN
DIFF1
DIFF0
CHSEL1
CHSEL0
PD
RES
VREF
CR1
RESERVED
OFFSET
BIN/2’s
R/W
RES
RES
RES
RES
SRST
RESET
Writing to Control Register 0 and Control Register 1
The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control
register and writing the register value to the ADC. The addressing is performed with the upper bits RA0 and
RA1. During this write process, the data bits D0 to D9 contain the desired control register value. Table 7 shows
the addressing of each control register.
Table 7. Control Register Addressing
20
D0 – D9
RA0
RA1
Addressed Control Register
Desired register value
0
0
Control register 0
Desired register value
1
0
Control register 1
Desired register value
0
1
Reserved for future
Desired register value
1
1
Reserved for future
THS1007
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INITIALIZATION OF THE THS1007
The initialization of the THS1007 should be done according to the configuration flow shown in Figure 32.
Start
Use Default
Values?
No
Yes
Write 0x401 to
THS1007
(Set Reset Bit in CR1)
Write 0x401 to
THS1007
(Set Reset Bit in CR1)
Clear RESET By
Writing 0x400 to
CR1
Clear RESET By
Writing 0x400 to
CR1
Write the User
Configuration to
CR0
Write the User
Configuration to
CR1 ( Must Exclude
RESET)
Continue
Figure 32. THS1007 Configuration Flow
21
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
ADC CONTROL REGISTERS
Control Register 0, Write Only (see Table 7)
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
TEST1
TEST0
SCAN
DIFF1
DIFF0
CHSEL1
CHSEL0
PD
RES
VREF
Table 8. Control Register 0 Bit Functions
BITS
RESET
VALUE
NAME
0
0
VREF
Vref select:
Bit 0 = 0 → The internal reference is selected
Bit 0 = 1 → The external reference voltage is used for the ADC
1
0
RES
RESERVED
2
0
PD
3, 4
0,0
CHSEL0,
CHSEL1
5,6
1,0
DIFF0, DIFF1
7
0
SCAN
Autoscan enable
Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 9.
8,9
0,0
TEST0,
TEST1
Test input enable
Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This
feedback allows the check of all hardware connections and the ADC operation.
FUNCTION
Power down.
Bit 2 = 0 → The ADC is active
Bit 2 = 1 → Power down
The reading and writing to and from the digital outputs is possible during power down.
Channel select
Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 9.
Number of differential channels
Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 9.
Refer to Table 10 for selection of the three different test voltages.
22
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
ANALOG INPUT CHANNEL SELECTION
The analog input channels of the THS1007 can be selected via bits 3 to 7 of control register 0. One single
channel (single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the
selection between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more
than one input channel is selected. Table 10 shows the possible selections.
Table 9. Analog Input Channel Configurations
BIT 7
SCAN
BIT 6
DIFF1
BIT 5
DIFF0
BIT 4
CHSEL1
BIT 3
CHSEL0
0
0
0
0
0
Analog input AINP (single ended)
0
0
0
0
1
Analog input AINM (single ended)
0
0
0
1
0
Analog input BINP (single ended)
0
0
0
1
1
Analog input BINM (single ended)
0
0
1
0
0
Differential channel (AINP−AINM)
0
0
1
0
1
Differential channel (BINP−BINM)
1
0
0
0
1
Autoscan two single ended channels: AINP, AINM, AINP, …
1
0
0
1
0
Autoscan three single ended channels: AINP, AINM, BINP, AINP, …
1
0
0
1
1
Autoscan four single ended channels: AINP, AINM, BINP, BINM, AINP, …
1
0
1
0
1
Autoscan one differential channel and one single ended channel AINP,
(BINP−BINM), AINP, (BINP−BINM), …
1
0
1
1
0
Autoscan one differential channel and two single ended channel AINP,
AINM, (BINP−BINM), AINP, …
1
1
0
0
1
Autoscan two differential channels (AINP−AINM), (BINP−BINM),
(AINP−AINM), …
0
0
1
1
0
Reserved
0
0
1
1
1
Reserved
1
0
0
0
0
Reserved
1
0
1
0
0
Reserved
1
0
1
1
1
Reserved
1
1
0
0
0
Reserved
1
1
0
1
0
Reserved
1
1
0
1
1
Reserved
1
1
1
0
0
Reserved
1
1
1
0
1
Reserved
1
1
1
1
0
Reserved
1
1
1
1
1
Reserved
DESCRIPTION OF THE SELECTED INPUTS
23
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
Test Mode
The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown
in Table 10.
Table 10. Test Mode
BIT 9
TEST1
BIT 8
TEST0
OUTPUT RESULT
0
0
Normal mode
0
1
VREFP
1
0
((VREFM)+(VREFP))/2
1
1
VREFM
Three different options can be selected. This feature allows support testing of hardware connections between
the ADC and the processor.
Control Register 1, Write Only (see Table 7)
BIT 11
BIT10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
1
RESERVED
OFFSET
BIN/2s
R/W
RES
RES
RES
RES
SRST
RESET
Table 11. Control Register 1 Bit Functions
BITS
RESET
VALUE
NAME
0
0
RESET
FUNCTION
Reset
Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values.
To bring the device out of RESET, a 0 has to be written into this bit.
1
0
SRST
Writing a 1 into this bit resets the sync generator. When running in multichannel mode, this must be set during the
configuration cycle.
2, 3
0,0
RES
Reserved
4
1
RES
Reserved
5
1
RES
Reserved
6
0
R/W
R/W, RD/WR selection
Bit 6 of control register 1 controls the function of the inputs RD and WR. When bit 6 in control register 1 is set to
1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write with
R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input WR
becomes a write input.
7
0
BIN/2s
Complement select
If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of
control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 2 through Table 5.
8
0
OFFSET
Offset cancellation mode
Bit 8 = 0 → normal conversion mode
Bit 8 = 1 → offset calibration mode
If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conversion. The conversion result is stored in an offset register and subtracted from all conversions in order to
reduce the offset error.
9
24
0
RESERVED
Always write 0.
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
TIMING AND SIGNAL DESCRIPTION OF THE THS1007
The reading from the THS1007 and writing to the THS1007 is performed by using the chip select inputs (CS0,
CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input
(R/W). This is desired in cases where the connected processor consists of a combined read/write output signal
(R/W). The two chip select inputs can be used to interface easily to a processor.
Reading from the THS1007 takes place by an internal RDint signal, which is generated from the logical
combination of the external signals CS0, CS1 and RD (see Figure 33). This signal is then used to strobe the
words and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid makes
RDint active while the write input (WR) is inactive. The first of those external signals switching to its inactive state
deactivates RDint again.
Writing to the THS1007 takes place by an internal WRint signal, which is generated from the logical combination
of the external signals CS0, CS1 and WR. This signal strobes the control words into the control registers 0 and
1. The last external signal (either CS0, CS1 or WR) to become valid switches WRint active while the read input
(RD) is inactive. The first of those external signals going to its inactive state deactivates WRint again.
CS0
RD
CS1
RD
WR
WR
Control/Data
Registers
Data Bits
Figure 33. Logical Combination of CS0, CS1, RD, and WR
25
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
Read Timing (using R/W, CS0-controlled)
Figure 34 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The reading of the data
should be done with a certain timing relative to the conversion clock CONV_CLK, as illustrated in Figure 34.
t su(CS0H−CONV_CLKL)
t su(CONV_CLKL−CS0L)
CONV_CLK
10%
10%
tw(CS)
CS0
10%
90%
10%
CS1
ÓÓÓÓ
ÓÓÓÓ
R/W
th(R/W)
tsu(R/W)
90%
ÔÔÔÔ
ÔÔÔÔ
90%
RD
t
t
a
h
90%
90%
D(O−11)
Figure 34. Read Timing Diagram Using R/W (CS0-controlled)
Read Timing Parameter (CS0-controlled) †
PARAMETER
MIN
TYP
MAX
UNIT
tsu(CONV_CLKL−CSOL)
Setup time, CONV_CLK low before CS valid
10
ns
tsu(CSOH−CONV_CLKL)
Setup time, CS invalid to CONV_CLK low
20
ns
tsu(R/W)
Setup time, R/W high to last CS valid
0
ns
ta
Access time, last CS valid to data valid
0
10
ns
th
Hold time, first CS invalid to data invalid
0
5
ns
th(R/W)
Hold time, first external CS invalid to R/W change
tw(CS)
Pulse duration, CS active
26
5
ns
10
ns
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
Write Timing (using R/W, CS0-controlled)
Figure 35 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The write into the THS1007
can be performed irrespective of the conversion clock signal CONV_CLK.
tw(CS)
CS0
90%
10%
10%
tsu(R/W)
th(R/W)
CS1
R/W
ÔÔÔ
ÔÔÔ
10%
ÓÓÓ
ÓÓÓ
10%
RD
tsu
th
90%
90%
D(0−11)
Figure 35. Write Timing Diagram Using R/W (CS0-controlled)
Read Timing Parameter (CS0-controlled) †
PARAMETER
MIN
TYP
MAX
UNIT
tsu(R/W)
Setup time, R/W stable to last CS valid
0
ns
tsu
Setup time, data valid to first CS invalid
5
ns
th
Hold time, first CS invalid to data invalid
2
ns
th(R/W)
Hold time, first CS invalid to R/W change
5
ns
tw(CS)
Pulse duration, CS active
10
ns
27
THS1007
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SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
ANALOG INPUT CONFIGURATION AND REFERENCE VOLTAGE
The THS1007 features four analog input channels. These can be configured for either single-ended or
differential operation. Figure 36 shows a simplified model, where a single-ended configuration for channel AINP
is selected. The reference voltages for the ADC itself are VREFP and VREFM (either internal or external reference
voltage). The analog input voltage range is between VREFM to VREFP. This means that VREFM defines the
minimum voltage, and VREFP defines the maximum voltage, which can be applied to the ADC. The internal
reference source provides the voltage VREFM of 1.5 V and the voltage VREFP of 3.5 V (see also section
reference voltage). The resulting analog input voltage swing of 2 V can be expressed by:
V
REFM
v AINP v V
(1)
REFP
VREFP
10-Bit
ADC
AINP
VREFM
Figure 36. Single-Ended Input Stage
A differential operation is desired in many applications due to a better signal-to-noise ration. Figure 37 shows
a simplified model for the analog inputs AINM and AINP, which are configured for differential operation. The
differential operation mode provides in terms of performance benefits over the single-ended mode and is
therefore recommended for best performance. The THS1007 offers 2 differential analog inputs and in the
single-ended mode4 analog inputs. If the analog input architecture is different, common-mode voltages can be
rejected. Additional details for both modes are given below.
AINP
VREFP
+
Σ
VADC
10-Bit
ADC
−
AINM
VREFM
Figure 37. Differential Input Stage
In comparison to the single-ended configuration it can be seen that the voltage VADC, which is applied at the
input of the ADC, is the difference between the input AINP and AINM. The voltage VADC can be calculated as
follows:
V
ADC
+ ABS(AINP–AINM)
(2)
An advantage to single-ended operation is that the common-mode voltage
V
CM
+ AINM ) AINP
2
(3)
can be rejected in the differential configuration, if the following condition for the analog input voltages is true:
AGND v AINM, AINP v AV
1VvV
CM
DD
v4V
(4)
(5)
SINGLE-ENDED MODE OF OPERATION
The THS1007 can be configured for single-ended operation using dc or ac coupling. In either case, the input
of the THS1007 must be driven from an operational amplifier that does not degrade the ADC performance.
Because the THS1007 operates from a 5-V single supply, it is necessary to level-shift ground-based bipolar
signals to comply with its input requirements. This can be achieved with dc and ac-coupling.
28
THS1007
www.ti.com
SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
DC COUPLING
An operational amplifier can be configured to shift the signal level according to the analog input voltage range
of the THS1007. The analog input voltage range of the THS1007 goes from 1.5 V to 3.5 V. An operational
amplifier can be used as shown in Figure 38.
Figure 38 shows an example with the analog input signal in the range between −1 V up to 1 V. This signal is
shifted by an operational amplifier to the analog input range of the THS1007 (1.5 V to 3.5 V). The operational
amplifier is configured as an inverting amplifier with a gain of −1. The required dc voltage of 1.25 V at the
noninverting input is derived from the 2.5-V output reference REFOUT of the THS1007 by using a resistor
divider. Therefore, the operational amplifier output voltage is centered at 2.5 V. The 10 μF tantalum capacitor
is required for bypassing REFOUT. REFIN of the THS1007 must be connected directly to REFOUT in
single-ended mode. The use of ratio matched, thin-film resistor networks minimizes gain and offset errors.
R1
1V
0V
−1 V
R1
1.25 V
3.5 V
2.5 V
1.5 V
5V
_
THS1007
RS
AINP
+
C
REFIN
REFOUT
R2
+
10 μF
R2
Figure 38. Level-Shift for DC-Coupled Input
DIFFERENTIAL MODE OF OPERATION
For the differential mode of operation, a conversion from single-ended to differential is required. A conversion
to differential signals can be achieved by using an RF-transformer, which provides a center tap. Best
performance is achieved in differential mode.
Mini Circuits
T4−1
49.9 Ω
THS1007
R
200 Ω
AINP
C
R
AINM
C
10 μF
+
REFOUT
Figure 39. Transformer Coupled Input
29
THS1007
www.ti.com
SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code transitions.
Signal-to-noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N+
(SINAD * 1.76)
6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, the effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input
signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
30
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THS1007CDA
ACTIVE
TSSOP
DA
32
46
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
THS1007
THS1007IDA
ACTIVE
TSSOP
DA
32
46
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
THS1007I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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