Texas Instruments | 4MSPS, 24-Bit Analog-to-Digital Converter (Rev. D) | Datasheet | Texas Instruments 4MSPS, 24-Bit Analog-to-Digital Converter (Rev. D) Datasheet

Texas Instruments 4MSPS, 24-Bit Analog-to-Digital Converter (Rev. D) Datasheet
ADS1675
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SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010
4MSPS, 24-Bit Analog-to-Digital Converter
Check for Samples: ADS1675
FEATURES
DESCRIPTION
•
The ADS1675 is a high-speed, high-precision
analog-to-digital converter (ADC). Using an advanced
delta-sigma (ΔΣ) architecture, it operates at speeds
up to 4MSPS with outstanding ac performance and
dc accuracy.
1
2
•
•
•
•
•
•
•
AC Performance:
103dB of Dynamic Range at 4MSPS
111dB of Dynamic Range at 125kSPS
–107dB THD
DC Accuracy:
3ppm INL
4mV/°C Offset Drift
4ppm/°C Gain Drift
Programmable Digital Filter with
User-Selectable Path:
– Low-Latency: Completely settles in 2.65ms
– Wide-Bandwidth: 1.7MHz BW with flat
passband
Flexible Read-Only Serial Interface:
– Standard CMOS
– Serialized LVDS
Easy Conversion Control with START Pin
Out-of-Range Detection
Supply: Analog +5V, Digital +3V
Power: 575mW
APPLICATIONS
•
•
•
•
Automated Test Equipment
Medical Imaging
Scientific Instrumentation
Test and Measurement
VREFP VREFN CLK AVDD
PLL
DVDD
3x
Dual Filter
Path
AINP
DS
Modulator
AINN
CMOS and
LVDS
Compatible
Serial
Interface
Low-Latency
Filter
Wide-Bandwidth
Filter
Control
Data Ready
Data Output
AGND
The device offers two speed modes with distinct
interface, resolution, and feature set. In the
high-speed mode the device can be set to operate at
either 4MSPS or 2MSPS. In the low-speed mode, it
can be set to operate at either 1MSPS, 500KSPS,
250KSPS or 125KSPS.
The ADS1675 is controlled through I/O pins—there
are no registers to program. A dedicated START pin
allows for direct control of conversions: toggle the
START pin to begin a conversion, and then retrieve
the output data. The flexible serial interface supports
data readback with either standard CMOS and LVDS
logic levels, allowing the ADS1675 to directly connect
to a wide range of microcontrollers, digital signal
processors (DSPs), or field-programmable grid arrays
(FPGAs).
Serial Shift Clock
Chip Select
Interface Configuration
Master Clock
Filter Path
Data Rate
Start Conversion
Power Down
Out-of-Range
ADS1675
The ADS1675 ADC is comprised of a low-drift
modulator with out-of-range detection and a dual-path
programmable digital filter. The dual filter path allows
the user to select between two post-processing filters:
Low-Latency or Wide-Bandwidth. The Low-Latency
filter settles quickly (as fast as 2.65ms) for
applications with large instantaneous changes, such
as a multiplexer. The Wide-Bandwidth path provides
an
optimized
frequency
response
for
ac
measurements with a passband ripple of less than
±0.00002dB, stop band attenuation of 86dB, and a
bandwidth of 1.7MHz.
The ADS1675 operates from an analog supply of 5V
and digital supply of 3V, and dissipates 575mW of
power. When not in use, the PDWN pin can be used
to power down all device circuitry. The device is fully
specified over the industrial temperature range and is
offered in a TQFP-64 package.
DGND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2010, Texas Instruments Incorporated
ADS1675
SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or visit the device product folder at ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
ADS1675
UNIT
AVDD to AGND
PARAMETER
–0.3 to +5.5
V
DVDD to DGND
–0.3 to +3.6
V
AGND to DGND
–0.3 to +0.3
V
100
mA
Input current
Momentary
10
mA
Analog I/O to AGND
Continuous
–0.3 to AVDD +0.3
V
Digital I/O to DGND
–0.3 to DVDD +0.3
V
Maximum junction temperature
+150
°C
Operating temperature range
–40 to +85
°C
Storage temperature range
–60 to +150
°C
(1)
2
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
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SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010
ELECTRICAL CHARACTERISTICS
All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5kΩ,
unless otherwise noted.
ADS1675
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Full-scale input voltage
Common-mode input voltage
VIN = (AINP – AINN)
±VREF
V
VCM = (AINP + AINN)/2
2.5
V
See Table 1
kSPS
AC PERFORMANCE
Data rate (fDATA)
Dynamic range
Signal-to-noise ratio (SNR)
Total harmonic distortion (THD)
Spurious-free dynamic range (SFDR)
Inputs shorted together, Low-Latency path,
fDATA = 4MSPS
100
103
Inputs shorted together, Low-Latency path,
fDATA =2MSPS
100.5
103.5
Inputs shorted together, Low-Latency path,
fDATA = 125kSPS
108
111
fIN = 10kHz, –0.5dBFS,
Wide-Bandwidth path, fDATA = 4MSPS
92
fIN = 10kHz, –0.5dBFS,
Wide-Bandwidth path, fDATA = 2MSPS
97
fIN = 1kHz, –0.5dBFS,
Wide-Bandwidth path, fDATA = 125kSPS
107
fIN = 10kHz, –0.5dBFS,
Wide-Bandwidth path, fDATA = 4MSPS
–103
fIN = 10kHz, –0.5dBFS,
Wide-Bandwidth path, fDATA = 2MSPS
–103
fIN = 1kHz, –0.5dBFS,
Wide-Bandwidth path, fDATA = 125kSPS
–107
fIN = 1kHz, –0.5dBFS, Wide-Bandwidth path,
fDATA = 4MSPS, signal harmonics excluded
120
fIN = 10kHz, –0.5dBFS, Wide-Bandwidth path,
fDATA = 4MSPS, signal harmonics excluded
120
dB
dB
dB
dB
DC PRECISION
Resolution
Low-speed mode (DRATE = 000 to 011)
24
High-speed mode (DRATE = 100, 101)
23
Bits
Bits
Low-speed mode (DRATE = 000 to 011)
24
(monotonic)
Bits
High-speed mode (DRATE = 100, 101)
23
(monotonic)
Bits
Differential nonlinearity
Integral nonlinearity
Offset error
3
TA = +25°C
–5
4
TA = +25°C
mV
mV/°C
1
Gain error drift
4
Noise
Common-mode rejection
ppm of FSR
5
Offset error drift
Gain error
15
%
ppm/°C
See Noise Performance table (Table 1)
At dc
71
dB
DIGITAL FILTER CHARACTERISTICS (WIDE-BANDWIDTH PATH)
Passband
0
Passband ripple
Passband transition
Stop band
–0.1dB attenuation
0.432fDATA
–3dB attenuation
0.488fDATA
0.576fDATA
0.424fDATA
Hz
±0.00002dB
dB
Hz
Hz
fCLK – 0.576fDATA
Hz
Stop band attenuation
86
dB
Group delay
28
tDRDY
Settling time
See the Wide-Bandwidth Filter section
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ADS1675
SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010
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ELECTRICAL CHARACTERISTICS (continued)
All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5kΩ,
unless otherwise noted.
ADS1675
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL FILTER CHARACTERISTICS (LOW-LATENCY PATH)
Bandwidth
–3dB attenuation
See the Low-Latency Filter section
Settling time
Complete settling
See Table 5
VOLTAGE REFERENCE INPUTS
Reference input voltage (VREF)
VREF = (VREFP – VREFN)
VREFP
2.75
3.0
3.5
V
2.75
3.0
3.5
V
VREFN
Short to AGND
V
CLOCK (CLK)
VIH
0.7AVDD
AVDD
V
VIL
AGND
0.3AVDD
V
V
DIGITAL INPUTS
VIH
0.7DVDD
DVDD
VIL
DGND
0.3DVDD
V
±10
mA
Input leakage
DGND < VIN < DVDD
CMOS OUTPUTS
VOH
IOH = –2mA
VOL
IOL = 2mA
0.8DVDD
V
0.2DVDD
V
LVDS OUTPUTS
|VOD(SS)|
Steady-state differential output voltage magnitude
340
mV
Δ|VOD(SS)|
Change in steady-state differential output voltage
magnitude between logic states
±50
mV
VOC(SS)
Δ|VOC(SS)|
Steady-state common-mode voltage output
1.2
V
Change in steady-state common-mode output
voltage between logic states
±50
mV
Peak-to-peak change in
common-mode output voltage
50
VOY or VOZ = 0V
3
mA
VOD = 0V
3
mA
VO = 0V or +DVDD
±5
VOC(pp)
Short-circuit output current (IOS)
High-impedance output current (IOZ)
Load
150
mV
mA
5
pF
V
POWER-SUPPLY REQUIREMENTS
AVDD
4.75
5.0
5.25
DVDD
2.85
3.0
3.15
V
70
74
mA
CMOS outputs, DVDD = 3V, DRATE = 011
53
59
mA
LVDS outputs, DVDD = 3V, DRATE = 101
70
74
mA
CMOS outputs, DRATE = 011,
AVDD = 5V, DVDD = 3V
510
545
mW
LVDS outputs, DRATE = 101,
AVDD = 5V, DVDD = 3V
575
600
mW
Power-down
5
AVDD current
DVDD current
Power dissipation
4
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mW
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SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010
DEVICE INFORMATION
53
52
DVDD
54
DGND
55
DGND
56
DVDD
57
AGND
58
AVDD
59
AGND
60
CLK
61
AVDD
CAP1
62
AGND
VREFN
63
CAP2
64
VREFN
VREFP
VREFP
TQFP PACKAGE
TQFP-64
(TOP VIEW)
51
50
49
AVDD
1
48 DVDD
AGND
2
47 DGND
AGND
3
46 DRDY
AINN
4
45 DRDY
AINP
5
44 DOUT
AGND
6
43 DOUT
AVDD
7
42 SCLK
RBIAS
8
41 SCLK
ADS1675
9
40 OTRA
AGND 10
39 OTRD
AGND
AVDD
11
38 CS
AVDD 12
37 START
22
23
24
25
26
27
28
29
30
31
32
DVDD
PDWN
SCLK _SEL
LVDS
DGND
LL_CONFIG
21
DGND
20
DGND
19
DVDD
18
RSV2
17
RSV1
33 FPATH
DVDD
34 DRATE[2]
DGND 16
DGND
35 DRATE[1]
DGND 15
DGND
DGND 14
DGND
36 DRATE[0]
DGND
VCM 13
TERMINAL FUNCTIONS
PIN
NAME
NO.
FUNCTION
AVDD
1, 7, 11, 12, 53,
58
Analog
Analog supply
AGND
2, 3, 6, 9, 10,
54, 56, 57
Analog
Analog ground
AINN
4
Analog input
Negative analog input
AINP
5
Analog input
Positive analog input
RBIAS
8
Analog
Analog bias setting resistor
VCM
DESCRIPTION
13
Analog
Terminal for external bypass capacitor connection to internal common-mode voltage
DGND
14-20, 25, 26,
31, 47, 50, 51
Digital
Digital ground
RSV2
21
Reserved
Short pin to digital ground
RSV1
22
Reserved
Short pin to digital supply
DVDD
23, 24, 27, 48,
49, 52
Digital
PDWN
28
Digital input
Power-down control, active low
SCLK_SEL
29
Digital input
Shift-clock source select. (1)
If SCLK_SEL = '0', then SCLK is internally generated.
If SCLK_SEL = '1', then SCLK must be externally generated.
LVDS
30
Digital input
Serial interface select. (1)
If LVDS = '0', then interface is LVDS-compatible.
If LVDS = '1', then interface is CMOS-compatible.
(1)
Digital supply
Option not available in high-speed mode.
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ADS1675
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TERMINAL FUNCTIONS (continued)
PIN
NAME
NO.
FUNCTION
LL_CONFIG
32
Digital input
Configure Low-Latency digital filter. (1)
If LL_CONFIG = '0', then single-cycle settling is selected.
If LL_CONFIG = '1', then fast-response is selected.
FPATH
33
Digital input
Digital filter path selection.
If FPATH = '0', then path is Wide-Bandwidth.
If FPATH = '1', then path is Low-Latency.
34-36
Digital input
Data rate selection
START
37
Digital input
Start convert, reset, and synchronization control input
CS
38
Digital input
Chip select; active low
OTRD
39
Digital output
OTRA
40
Digital input
SCLK
41
Digital output
SCLK
42
Digital input/output
DOUT
43
Digital output
Negative LVDS serial data output
DOUT
44
Digital output
Positive LVDS serial data output
DRDY
45
Digital output
Negative data ready output
DRDY
46
Digital output
Positive data ready output
CLK
55
Digital input
CAP1
59
Analog
Terminal for 1mF external bypass capacitor
60, 61
Analog
Negative reference voltage. Short to analog ground
62
Analog
Terminal for 1mF external bypass capacitor
63, 64
Analog
Positive reference voltage
DRATE[2:0]
VREFN
CAP2
VREFP
6
DESCRIPTION
Digital filter out-of-range indicator
Analog input out-of-range indicator
Negative shift clock output.
If SCLK_SEL = '0', then SCLK is the complementary shift clock output.
If SCLK_SEL = '1', then SCLK always output is 3-state.
Positive shift clock output.
If SCLK_SEL = '0', then SCLK is an output.
If SCLK_SEL = '1', then SCLK is an input.
Master clock input
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SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010
TIMING CHARACTERISTICS
tLSCLKDC
tLSCLK
SCLK
tLDRPW
DRDY
tLSCLKDR
tLDOPD
DOUT
MSB
LSB
MSB
(1) High-speed LVDS valid only for DRATE = 100 and DRATE = 101.
(2) Timing shown is the single-end version of the LVDS signal pairs.
Figure 1. High-Speed LVDS Data Retrieval Timing
TIMING REQUIREMENTS: High-Speed LVDS
At TA = –40°C to +85°C, and DVDD = 2.85V to 3.15V.
SYMBOL
DESCRIPTION
MIN
tLDRPW
DRDY pulse width
tLSCLKDR
SCLK to DRDY delay
tLDOPD
Valid data delay time from serial shift clock
tLSCLK
Period of LVDS serial shift clock (SCLK)
tLSCLKDC
Shift clock duty cycle
tCLK
CLK period (1/fCLK)
tLCLKSCLK
Delay from rising edge of CLK to rising edge of SCLK
tLPLLSTL
PLL settling time
tSTCLK
Setup time, rising edge of START to falling edge of CLK
tSETTLE
Digital filter settling time
TYP
MAX
UNIT
4
tLSCLKs
2
3
ns
1.5
2.5
2
0.33
47
ns
tCLKs
53
%
31.25
ns
13
–3
20
ns
80
ms
3
ns
See Table 5 and Table 6
tCLK
CLK
tLPLLSTL
tSTCLK
tLCLKSCLK
tLSCLK
SCLK
tSETTLE
START
tSETTLE
tLSCLKDR
DRDY
Figure 2. PLL Timing
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tCLK
tDC
CLK
tLCLKDR
tLDRPW
DRDY
CS
tLSCLK
tDRSCLK
tSPWH
SCLKinternal
tLDOPD
DOUT
MSB
LSB
Figure 3. Low-Speed Mode Data Retrieval Timing with Internal SCLK (SCLK_SEL = 0)
TIMING REQUIREMENTS: Internal SCLK
At TA = –40°C to +85°C, and DVDD = 2.85V to 3.15V.
SYMBOL
DESCRIPTION
MIN
tDC
CLK duty cycle
tSPWH
SCLK pulse width high
tCLK
CLK period (1/fCLK)
31.25
tCLKDR
CLK to DRDY delay
23
tLDRPW
DRDY pulse width
tDRSCLK
Internal SCLK Rising to DRDY active edge
tLSCLK
Internally-generated SCLK rising edge to DRDY rising edge
tLDOPD
Rising edge of SCLK to new valid data output (propagation delay)
8
47
TYP
MAX
50
53
15.6
ns
1
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%
ns
30
2.2
ns
tCLK
4.4
1
1.9
UNIT
ns
tCLK
2.8
ns
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SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010
tCLK
CLK
tCLKDR
tLSCLKDR
DRDY
tLDRPW
CS
(1)
tCSSC
tSPW
tSPW
SCLKEXTERNAL
tLSCLK
tLDOPD
DOUT
Hi-Z
tCSRDO
MSB
LSB
tCSFDO
(3)
CS may be tied low.
Figure 4. Low-Speed Mode Data Retrieval Timing with External SCLK (SCLK_SEL = 1)
TIMING REQUIREMENTS: External SCLK
At TA = –40°C to +85°C, and DVDD = 2.85V to 3.15V.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
tCLK
CLK period (1/fCLK)
31.25
ns
tCLKDR
CLK to DRDY delay
23
tLDRPW
DRDY pulse width
tCSSC
CS active low to first Shift Clock (setup time)
5
ns
tLSCLK
SCLK period (1/fSCLK)
25
ns
tSPW
SCLK high or low pulse width
12
tLDOPD
Rising edge of SCLK to new valid data output (propagation delay)
tLSCLKDR
Setup time of DRDY rising after SCLK falling edge
tCSRDO
CS rising edge to DOUT 3-state
29
1
ns
tCLK
ns
10.5
15
3
ns
tCLK
8
ns
tSTART_CLKR
CLK
tSETTLE
tCLKDR
START
tSTART
DRDY
Figure 5. START Timing
TIMING REQUIREMENTS: START
At TA = –40°C to +85°C, and DVDD = 2.85V to 3.15V.
SYMBOL
DESCRIPTION
tSTART_CLKR
Setup time, rising edge of START to rising edge of CLK
tSTART
Start pulse width
MIN
TYP
MAX
tCLK
2
tCLK
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UNIT
0.5
9
ADS1675
SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010
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TYPICAL CHARACTERISTICS
All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless
otherwise noted.
SPECTRAL RESPONSE
(DRATE = 000, WB Filter)
0
0
fIN = 1kHz, -0.5dBFS
THD = -106.8dBc
65,536 Points
-20
fIN = 1kHz, -6dBFS
THD = -106.7dBc
65,536 Points
-20
-40
Amplitude (dBFS)
Amplitude (dBFS)
SPECTRAL RESPONSE
(DRATE = 000, WB Filter)
-60
-80
-100
-40
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
10
20
30
40
50
60
0
10
20
Frequency (kHz)
Figure 7.
SPECTRAL RESPONSE
(DRATE = 100, WB Filter)
SPECTRAL RESPONSE
(DRATE = 100, WB Filter)
60
-40
-60
-80
-100
fIN = 10kHz, -6dBFS
THD = -109dBc
65,536 Points
-20
Amplitude (dBFS)
Amplitude (dBFS)
50
0
fIN = 10kHz, -0.5dBFS
THD = -103dBc
65,536 Points
-20
-40
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
100 200 300 400 500 600 700 800 900 1000
0
20
40
60
Frequency (kHz)
80
100 120 140 160 180
200
Frequency (kHz)
Figure 8.
Figure 9.
SPECTRAL RESPONSE
(DRATE = 101, WB Filter)
SPECTRAL RESPONSE
(DRATE = 101, WB Filter, Detailed View)
0
0
fIN = 10kHz, -0.5dBFS
THD = -102.7dBc
65,536 Points
-20
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
-140
-140
-160
fIN = 10kHz, -0.5dBFS
THD = -102.7dBc
65,536 Points
-20
Amplitude (dBFS)
Amplitude (dBFS)
40
Figure 6.
0
-160
0
200 400 600 800 1000 1200 1400 1600 1800 2000
0
Frequency (kHz)
20
40
60
80
100 120 140 160 180
200
Frequency (kHz)
Figure 10.
10
30
Frequency (kHz)
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless
otherwise noted.
SPECTRAL RESPONSE
(DRATE = 101, WB Filter, Detailed View)
SPECTRAL RESPONSE
(DRATE = 101, WB Filter, Detailed View)
0
0
fIN = 10kHz, -6dBFS
THD = -109dBc
65,536 Points
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
20
40
60
80
100 120 140 160 180
200
0
40
60
80
100 120 140 160 180
Frequency (kHz)
Figure 12.
Figure 13.
SPECTRAL RESPONSE
(DRATE = 101, LL Filter)
SPECTRAL RESPONSE
(DRATE = 101, LL Filter, Detailed View)
0
200
0
fIN = 10kHz, -0.5dBFS
THD = -102.7dBc
65,536 Points
fIN = 10kHz, -0.5dBFS
THD = -102.7dBc
65,536 Points
-20
-40
Amplitude (dBFS)
-40
-60
-80
-100
-120
-140
-60
-80
-100
-120
-140
-160
-160
-180
-180
-200
-200
0
200 400 600 800 1000 1200 1400 1600 1800 2000
0
Frequency (kHz)
20
40
60
80
100 120 140 160 180
200
Frequency (kHz)
Figure 14.
Figure 15.
SPECTRAL RESPONSE
(DRATE = 101, LL Filter, Detailed View)
SPECTRAL RESPONSE
(DRATE = 101, WB Filter)
0
0
fIN = 10kHz, -5.9dBFS
THD = -107.8dBc
65,536 Points
-20
-60
-80
-100
-120
-140
fIN = 100kHz, -0.5dBFS
THD = -102.4dBc
65,536 Points
-20
Amplitude (dBFS)
-40
Amplitude (dBFS)
20
Frequency (kHz)
-20
Amplitude (dBFS)
fIN = 10kHz, -60dBFS
THD = -62.7dBc
65,536 Points
-20
Amplitude (dBFS)
Amplitude (dBFS)
-20
-40
-60
-80
-100
-120
-160
-140
-180
-160
-200
0
20
40
60
80
100 120 140 160 180
200
0
200k 400k 600k 800k 1M 1.2M 1.4M 1.6M 1.8M
Frequency (kHz)
Frequency (Hz)
Figure 16.
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless
otherwise noted.
SPECTRAL RESPONSE
(DRATE = 101, WB Filter)
SPECTRAL RESPONSE
(DRATE = 101, WB Filter)
0
0
fIN = 100kHz, -6dBFS
THD = -103.2dBc
65,536 Points
-40
-60
-80
-100
-40
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
0
200k 400k 600k 800k 1M 1.2M 1.4M 1.6M 1.8M
2M
0
200k 400k 600k 800k 1M 1.2M 1.4M 1.6M 1.8M
Frequency (Hz)
Frequency (Hz)
Figure 18.
Figure 19.
SPECTRAL RESPONSE
(DRATE = 101, WB Filter)
SIGNAL-TO-NOISE RATIO
vs INPUT SIGNAL AMPLITUDE
100
fIN = 1600kHz, -6dBFS
THD = -125dBc
65,536 Points
-20
fIN = 10kHz
80
-40
-60
-80
-100
70
60
fDATA = 2MSPS, WB
50
fDATA = 4MSPS, WB
40
-120
30
-140
20
-160
10
0
200k 400k 600k 800k 1M 1.2M 1.4M 1.6M 1.8M
2M
-80
120
-60
-50
-40
-30
-20
-10
Figure 20.
Figure 21.
|TOTAL HARMONIC DISTORTION|
vs INPUT SIGNAL AMPLITUDE
SIGNAL-TO-NOISE RATIO
vs INPUT COMMON-MODE VOLTAGE
95
fIN = 10kHz
fIN = 10kHz
fDATA = 4MSPS
WB Filter
94
110
93
100
90
fDATA = 2MSPS, WB
80
70
0
AIN = -0.5dBFS
92
SNR (dBc)
|THD| (dBc)
-70
Input Signal Amplitude (dBFS)
Frequency (Hz)
fDATA = 4MSPS, WB
91
90
89
88
60
87
50
AIN = -6dBFS
86
40
85
-80
-70
-60
-50
-40
-30
-20
-10
0
1.5
Input Signal Amplitude (dBFS)
2.0
2.5
3.0
3.5
Input Common-Mode Voltage (V)
Figure 22.
12
2M
90
SNR (dBc)
Amplitude (dBFS)
fIN = 1600kHz, -0.5dBFS
THD = -122.9dBc
65,536 Points
-20
Amplitude (dBFS)
Amplitude (dBFS)
-20
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless
otherwise noted.
|TOTAL HARMONIC DISTORTION|
vs INPUT COMMON-MODE VOLTAGE
115
SIGNAL-TO-NOISE RATIO vs RBIAS
93.0
fIN = 10kHz
fDATA = 4MSPS
WB Filter
110
92.5
fCLK = 8MHz
92.0
SNR (dBc)
|THD| (dBc)
91.5
AIN = -6dBFS
105
91.0
fCLK = 16MHz
90.5
90.0
89.5
100
fCLK = 32MHz
89.0
AIN = -0.5dBFS
fIN = 10kHz
AIN = -0.5dBFS
88.5
95
88.0
1.5
2.0
2.5
3.0
3.5
0
10
20
Input Common-Mode Voltage (V)
Figure 24.
40
50
60
Figure 25.
|TOTAL HARMONIC DISTORTION| vs RBIAS
114
POWER vs RBIAS
1100
fIN = 10kHz
AIN = -0.5dBFS
112
fIN = 10kHz
AIN = -0.5dBFS
1000
900
110
800
Power (mW)
108
|THD| (dBc)
30
RBIAS (kW)
fCLK = 8MHz
106
104
102
fCLK = 16MHz
700
600
500
100
400
98
300
96
fCLK = 32MHz
fCLK = 16MHz
200
fCLK = 32MHz
94
fCLK = 8MHz
100
0
10
20
30
40
50
60
0
10
20
RBIAS (kW)
30
40
50
60
RBIAS (kW)
Figure 26.
Figure 27.
SIGNAL-TO-NOISE RATIO AND
|TOTAL HARMONIC DISTORTION|
vs TEMPERATURE
DYNAMIC RANGE vs OVERSAMPLING RATIO
112
105
110
Dynamic Range (dBFS)
SNR, |THD| (dBc)
|THD|
100
fIN = 10kHz
AIN = -0.5dBFS
fDATA = 4MSPS
WB Filter
95
SNR
108
LL Filter
106
WB Filter
104
Input Shorted
fCLK = 32MHz
125kSPS: DRATE = 000
250kSPS: DRATE = 001
500kSPS: DRATE = 010
1MSPS: DRATE = 011
2MSPS: DRATE = 100
4MSPS: DRATE = 101
102
100
98
96
94
92
90
-40
-15
10
35
60
85
8 16
32
64
128
256
Oversampling Ratio
Temperature (°C)
Figure 28.
Figure 29.
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TYPICAL CHARACTERISTICS (continued)
All specifications are at TA = –40°C to +85°C, AVDD = 5V, DVDD = 3V, fCLK = 32MHz, VREF = +3V, and RBIAS = 7.5kΩ, unless
otherwise noted.
CURRENT vs OVERSAMPLING RATIO
Current (mA)
90
Input Shorted
fCLK = 32MHz
LVDS Interface
POWER vs OVERSAMPLING RATIO
590
125kSPS: DRATE = 000
250kSPS: DRATE = 001
500kSPS: DRATE = 010
1MSPS: DRATE = 011
2MSPS: DRATE = 100
4MSPS: DRATE = 101
80
IAVDD, WB/LL Filter
Input Shorted
fCLK = 32MHz
LVDS Interface
580
570
70
60
550
540
530
LL Filter
520
IDVDD, LL Filter
50
510
WB Filter
500
IDVDD, WB Filter
40
490
8 16
32
128
64
256
8 16
32
400
Figure 30.
Figure 31.
NOISE HISTOGRAM
(DRATE = 101, WB Filter)
NOISE HISTOGRAM
(DRATE = 000, WB Filter)
1600
Input Shorted
s = 60LSB
65,536 Points
Wide Bandwidth
fDATA = 4MSPS
Input Shorted
s = 17LSB
65,536 Points
Wide Bandwidth
fDATA = 125kSPS
1400
300
200
100
0
-400
256
Oversampling Ratio
Number of Occurences
Number of Occurrences
500
128
64
Oversampling Ratio
600
125kSPS: DRATE = 000
250kSPS: DRATE = 001
500kSPS: DRATE = 010
1MSPS: DRATE = 011
2MSPS: DRATE = 100
4MSPS: DRATE = 101
560
Power (mW)
100
1200
1000
800
600
400
200
0
-300
-200
-100
0
100
200
300
400
-80
-60
-40
-20
0
20
40
60
80
24-Bit Output Code (LSB)
23-Bit Output Code (LSB)
Figure 32.
Figure 33.
INTEGRAL NONLINEARITY
vs ANALOG INPUT VOLTAGE
3
+25°C
+85°C
-40°C
2
INL (ppm)
1
0
-1
fCLK = 32MHz
fDATA = 125kSPS
Wide Bandwidth
-2
-3
-3
-2
-1
0
1
2
3
Analog Input Voltage (V)
Figure 34.
14
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OVERVIEW
The ADS1675 is a 24-bit, delta-sigma (ΔΣ)
analog-to-digital converter (ADC). It provides
high-resolution measurements of both ac and dc
signals and features an advanced, multi-stage analog
modulator with a programmable and flexible digital
decimation filter.
A dedicated START pin allows precise conversion
control; toggle the pin to begin the conversion
process. The ADS1675 is configured by setting the
appropriate I/O pins—there are no registers to
program. Data are retrieved over a serial interface
that can support either CMOS or LVDS voltage
levels. In addition, the standard CMOS serial
interface can be internally or externally clocked. This
flexibility allows direct connection to a wide range of
digital hosts including DSPs, FPGAs, and
microcontrollers. All data rates are available only
using the LVDS mode interface.
A detection circuit monitors the conversions to
indicate when the inputs are out-of-range for an
extended duration. A power-down pin (PDWN) shuts
off all circuitry when the ADS1675 is not in use.
DVDD
The device offers two speed modes with distinct
interfaces, resolution, and feature set. The
high-speed mode is enabled by setting DRATE[2:0] to
either 100 or 101. The rest of the DRATE
configurations enable the low-speed mode.
AVDD
CLK
VREFN
VREFP
CAP2
CAP1
RBIAS
Figure 35 shows a block diagram of the ADS1675.
The modulator measures the differential input signal
VIN = (AINP – AINN) against the differential reference
VREF = (VREFP – VREFN). The digital filter receives
the modulator signal and processes it through the
user-selected path. The Low-Latency path settles
quickly, and is ideal when using a multiplexer or when
measuring large transients. The Wide-Bandwidth path
provides outstanding frequency response with very
low passband ripple, a steep transition band, and
large stop band attenuation. This path is well-suited
for
applications
that
require
high-resolution
measurements of high-frequency ac signal content.
PLL
VCM
Biasing
3x
AINN
S
VIN
PDWN
START
S
Dual Filter
Path
VREF
AINP
ADS1675
Low-Latency Filter
DS
Modulator
Wide-Bandwidth Filter
CLK
CMOS- and
LVDSCompatible
Serial
Interface
and
Control
DRDY, DRDY
DOUT, DOUT
SCLK, SCLK
CS
LVDS
SCLK_SEL
DRATE[2:0]
FPATH
LL_CONFIG
OTRD
DGND
AGND
OTRA
Figure 35. Block Diagram
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NOISE PERFORMANCE
The ADS1675 offers outstanding noise performance
that can be optimized by adjusting the data rate. As
the averaging is increased (thus reducing the data
rate), the noise drops correspondingly. Table 1 shows
the noise as a function of data rate for both the
Low-Latency and the Wide-Bandwidth filter paths
under the conditions shown.
Table 1 lists some of the more common methods of
specifying noise. The dynamic range is the ratio of
the root-mean-square (RMS) value of a full-scale sine
wave to the RMS noise with the inputs shorted
together. This value is expressed in decibels relative
to full-scale (dBFS). The input-referred noise is the
RMS value of the noise with the inputs shorted,
referred to the input of the ADS1675. The effective
number of bits (ENOB) is calculated from a dc
perspective using the formula in Equation 1, where
full-scale range equals 2VREF.
ln
Full-scale range
RMS noise
Noise-free bits specifies noise, again from a dc
perspective using Equation 1, with peak-to-peak
noise substituted for RMS noise.
ANALOG INPUTS (AINP, AINN)
The ADS1675 measures the differential signal,
VIN = (AINP – AINN), against the differential
reference, VREF = (VREFP – VREFN). The most
positive measurable differential input is VREF, which
produces the most positive digital output code of
7FFFFFh. Likewise, the most negative measurable
differential input is –VREF, which produces the most
negative digital output code of 800000h.
Analog inputs must be driven with a differential signal
to achieve optimum performance. The recommended
common-mode voltage is 2.5V. The ADS1675
samples the analog inputs at very high speeds. It is
critical that a suitable driver be used. See the
Application Information section for recommended
circuit designs.
ENOB =
ln(2)
(1)
Table 1. Noise Performance (1)
FILTER PATH
Low-Latency
(Fast Response
Mode
configuration)
DATA RATE[2:0]
DATA RATE
(kSPS)
DYNAMIC
RANGE (dB)
INPUTREFERRED
NOISE (mVRMS)
ENOB
NOISE-FREE
BITS
000
125
111
6.30
19.86
17.14
001
250
109
7.47
19.61
16.89
010
500
107
9.51
19.27
16.54
011
1000
105
11.72
18.97
16.24
100
2000
104
13.72
18.74
16.02
101
4000
103
14.23
18.69
15.96
000
125
111
6.17
19.89
17.17
001
250
109
7.44
19.62
16.90
010
500
107
9.66
19.25
16.52
011
1000
104
12.99
18.82
16.09
100
2000
101
18.64
18.30
15.57
101
4000
94
44.02
17.06
14.33
Low-speed
modes
High-speed
modes
Low-speed
modes
Wide-Bandwidth
High-speed
modes
(1)
16
VREF = 3V, fCLK = 32MHz.
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VOLTAGE REFERENCE INPUTS
(VREFN, VREFP)
CONVERSION START
The voltage reference for the ADS1675 is the
differential voltage between VREFP and VREFN:
VREF = (VREFP – VREFN)
(2)
A high-quality reference voltage with the appropriate
drive strength is essential for achieving the best
performance from the ADS1675. Noise and drift on
the reference degrade overall system performance.
See the Application Information section for reference
circuit examples.
It is recommended that a minimum 10mF and 0.1mF
ceramic bypass capacitors be used directly across
the reference inputs, VREFP and VREFN. These
capacitors should be placed as close as possible to
the device under test for optimal performance.
COMMON-MODE VOLTAGE (VCM)
The START pin provides an easy and precise
conversion control. To perform a single conversion,
pulse the START pin as shown in Figure 36. The
START signal is latched internally on the rising edge
of CLK. Multiple conversions are performed by
continuing to hold START high after the first
conversion completes; see the digital filter
descriptions for more details on multiple conversions,
because the timing depends on the filter path
selected.
A conversion can be interrupted by issuing another
START pulse before the ongoing conversion
completes. When an interruption occurs, the data for
the ongoing conversion are flushed and a new
conversion begins. DRDY indicates that data are
ready for retrieval after the filter has settled, as shown
in Figure 37.
The VCM pin outputs a voltage of AVDD/2. This pin
must be bypassed with a 1µF capacitor placed close
to the package pin. The VCM pin connects an
external capacitor to compensate the internal
amplifier; it is not intended to drive an external load.
tSTART_CLKR
CLK
(1)
tSETTLE
tSETTLE
(1)
START
tSTART
DRDY
Figure 36. START Pin Used for Single Conversions
Ongoing conversion flushed;
new conversion started
tSTART_CLKR
CLK
(1)
tSETTLE
START
tSTART
DRDY
(1) See the Low-Latency Filter and Wide-Bandwidth Filter sections for specific values of settling time tSETTLE.
Figure 37. Example of Restarting a Conversion with START
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DIGITAL FILTER
LOW-LATENCY DIGITAL FILTER
In ΔΣ ADCs, the digital filter has a critical influence
on device performance. The digital filter sets the
frequency response, data rate, bandwidth, and
settling time. Choosing to optimize some of these
features in a filter means that compromises must be
made with other specifications. These tradeoffs
determine the applications for which the device is
best suited.
The Low-Latency (LL) filter provides a fast settling
response targeted for applications that need
high-precision measurements with minimal latency. A
good example of this type of application is a
multiplexer that measures multiple inputs. The faster
the ADC settles, the faster the measurement can
complete and the multiplexer can advance to the next
input.
The ADS1675 offers two digital filters on-chip, and
allows the user to direct the output data from the
modulator to either the Wide-Bandwidth or
Low-Latency filter. These filters allow the user to use
one converter design to address multiple applications.
The Low-Latency path filter has minimal latency or
settling time. This reduction is achieved by reducing
the bandwidth of the filter. This path is ideal for
measurements with large, quick changes on the
inputs (for example, when using a multiplexer). The
Low-Latency characteristic allows the user to cycle
through the multiplexer at high speeds.
The ADS1675 LL filter supports two configurations to
help optimize performance for these types of
applications.
The other path provides a filter with excellent
frequency response characteristics. The passband
ripple is extremely small, the transition band is very
steep, and there is large stop band attenuation.
These characteristics are needed for high-resolution
measurements of ac signals. The tradeoff here is that
settling time increases; for signal processing,
however, this increase is not generally a critical
concern.
The FPATH digital input pin sets the filter path
selection, as shown in Table 2. Note that the START
pin must be strobed after a change to the filter path
selection or data rate. If a conversion is in process
during a filter path or data rate change, the output
data are not valid and should be discarded.
Table 2. ADS1675 Filter Path Selection
The LL_CONFIG input pin selects the configuration,
as shown in Table 3. Be sure to strobe the START
pin after changing the configuration. If a conversion is
in process during a configuration change, the output
data for that conversion are not valid and should be
discarded.
Table 3. Low-Latency Pin Configurations
LL_CONFIG PIN
LOW-LATENCY
CONFIGURATION
0
Single-cycle settling
1
Fast response
The first configuration is single-cycle settling. As the
name implies, this configuration allows for the filter to
completely settle in one conversion cycle; there is no
need to discard data. Each data output is comprised
of information taken during only the previous
conversion. The DRATE[2:0] digital input pins select
the data rate for the Single-Cycle Settling
configuration, as shown in Table 4. Note that the
START pin must be strobed after a change to the
data rate. If a conversion is in process during a data
rate change, the output data for that conversion are
not valid and should be discarded.
blank
FPATH PIN
SELECTED FILTER PATH
1
Low-Latency path
0
Wide-Bandwidth path
blank
Table 4. Low-Latency Data Rates with Single-Cycle Settling Configuration
DRATE[2:0]
(1)
18
DATA RATE (kSPS)
SETTLING TIME, tSETTLE-LL
–3dB BANDWIDTH (kHz) (1)
000
57.80
17.375ms
556tCLK
54
001
107.53
9.375ms
300tCLK
109
010
188.68
5.375ms
172tCLK
208
011
277.78
3.625ms
116tCLK
344
The input signal aliases when its frequency exceeds fDATA/2, in accordance with the Nyquist theorem.
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The second configuration is fast response. The
DRATE[2:0] digital input pins select the data rate for
the Fast Response Configuration, as shown in
Table 5. When selected, this configuration provides a
higher output data rate. The faster output data rate
allows for more averaging by a post-processor within
a given time interval to reduce noise. It also provides
a faster indication of changes on the inputs when
monitoring quickly-changing signals (for example, in a
control loop application).
Table 5. Low-Latency Data Rates with
Fast-Response Configuration
DRATE
[2:0]
DATA
RATE
(kSPS)
000
125
17.375ms
556tCLK
54
001
250
9.375ms
300tCLK
109
010
500
5.375ms
172tCLK
208
011
1000
3.625ms
116tCLK
344
100
2000
2.76ms
265tLSCLK
350
101
4000
2.385ms
229tLSCLK
355
SETTLING TIME,
tSETTLE-LL
–3dB
BANDWIDTH
(kHz)
1. The input signal aliases when its frequency
exceeds fDATA/2, in accordance with the Nyquist
theorem.
2. For high-speed mode, the first data are unsettled.
Settling Time
The settling time in absolute time (ms) is the same for
both configurations of the Low-Latency filter, as
shown in Table 4 and Table 5. The difference
between the configurations is seen with the timing of
the conversions after the filter has settled from a
pulse on the START pin.
Figure 38 illustrates the response of both
configurations on approximately the same time scale
in order to highlight the differences. With the
single-cycle settling configuration, each conversion
fully settles; in other words, the conversion period
tDRDY-SCS = tSETTLE-LL. The benefit of this configuration
is its simplicity—the ADS1675 functions similar to a
successive-approximation register (SAR) converter
and there is no need to consider discarding
partially-settled data because each conversion is fully
settled.
With the fast response configuration, the data rate for
conversions after initial settling is faster; that is, the
conversion time is less than the settling:
tDRDY-FR < tSETTLE-LL. One benefit of this configuration
is a faster response to changes on the inputs,
because data are supplied at a faster rate. Another
advantage is better support for post-processing. For
example, if multiple readings are averaged to reduce
noise, the higher data rate of the fast response
configuration allows this averaging to happen in less
time than it requires with the single-cycle settling
filter. A third benefit is the ability to measure higher
input frequencies without aliasing as a result of the
higher data rate.
tSTART_CLKR
CLK
tSETTLE-LL
tCLKDR
START
tDRDY-SCS =
tCLKDR + 1tCLK + tSETTLE-LL
DRDYSCS
DRDYFR
tDRDY-FR
NOTE: DRDYSCS is the DRDY output with the Low-Latency single-cycle settling configuration. DRDYFR is the DRDY output with the
Low-Latency fast-response settling configuration.
Figure 38. Low-Latency Single-Cycle Settling and Fast-Response Configuration Conversion Timing
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It is important to note, however, that the absolute
settling time of the Low-Latency path does not
change when using the fast response configuration.
Changes on the input signal during conversions after
the initial settling require multiple cycles to fully settle.
To help illustrate this requirement, consider a change
on the inputs as shown in Figure 42, where START is
assumed to have been taken high before the input
voltage was changed.
0
DRATE = ‘000’
-10
Magnitude (dB)
-20
-30
DRATE = ‘011’
-40
-50
DRATE = ‘101’
-60
The readings after a step change in the input is
settled as shown in Figure 39 for all different data
rates.
DRATE = ‘100’
-70
-80
0
1.4
DRATE = 000,
001, 010
1.2
DRATE = 011
0.2
0.3 0.4 0.5 0.6 0.7 0.8
Normalized Frequency (fIN/fDATA)
0.9
1.0
DRATE = 100
Figure 40. Frequency Response of Low-Latency
Filter in Fast-Response Configuration
1.0
Settling (%)
0.1
0.8
DRATE = 101
0
0.6
-20
Magnitude (dB)
0.4
0.2
0
0
2
4
6
8
10
12
Conversions (1/fDRDY-FR)
-40
-60
-80
-100
Figure 39. Step Response for Low-Latency Filter
with Fast-Response Configuration
-120
-140
0
Frequency Response
0.5
1.0
1.5
2.0
2.5
3.0
Normalized Frequency (fIN/fCLK)
Figure 40 shows the frequency response for the
Low-Latency filter path normalized to the output data
rate, fDATA. The overall frequency response repeats at
the modulator sampling rate, which is the same as
the input clock frequency. Figure 41 shows the
response with the fastest data rate selected (4 MSPS
when fCLK = 32MHz).
Figure 41. Extended Frequency Response of
Low-Latency Path
Change on
Analog Inputs
VIN
Fully-Settled Data Available
(1)
for DRATE = 000 , 001, 010
Data 0
Data 1
Data 2
Data 3
Data 4
DRDYLL-FR
NOTE: START pin held high previous to change on analog inputs.
(1) Refer to Figure 39 for other modes.
Figure 42. Settling Example with the Low-Latency Filter in Fast-Response Configuration
20
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Phase Response
20
0
-20
Magnitude (dB)
The Low-Latency filter uses a multiple-stage,
linear-phase digital filter. Linear phase filters exhibit
constant delay time versus input frequency (also
know as constant group delay). This feature of linear
phase filters means that the time delay from any
instant of the input signal to the corresponding same
instant of the output data is constant and independent
of the input signal frequency. This behavior results in
essentially zero phase error when measuring
multi-tone signals.
-40
-60
-80
-100
-120
-140
WIDE-BANDWIDTH FILTER
0
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.40
0.45
Figure 43. Frequency Response of
Wide-Bandwidth Filter
blank
0.000010
0.000005
0
Magnitude (dB)
While using the Wide-Bandwidth filter path, the
LL_CONFIG pin must be set to logic high. Setting
LL_CONFIG low forces the ADS1675 to switch to a
low-latency filter path, overriding the FPATH pin.
0.2
Normalized Frequency (fIN/fDATA)
The Wide-Bandwidth (WB) filter is well-suited for
measuring high-frequency ac signals. This digital filter
offers excellent passband and stop band
characteristics.
The DRATE[2:0] digital input pins select from the four
data rates available with the WB filter, as shown in
Table 6. Note that the START pin must be strobed
after a change to the data rate. If a conversion is in
process during a data rate change, the output data
for that conversion are not valid and should be
discarded.
0.1
-0.000005
-0.000010
-0.000015
-0.000020
-0.000025
-0.000030
-0.000035
Table 6. Wide-Bandwidth Data Rates
-0.000040
0
000
125
439.44ms
14062tCLK
59.375
001
250
219.81ms
7074tCLK
118.75
010
500
110.00ms
3520tCLK
237.5
011
1000
55.04ms
1763tCLK
475
100
2000
27.52ms
2642tLSCLK
950
101
4000
13.79ms
1324tLSCLK
1900
SETTLING TIME,
tSETTLE-LL
0.05 0.10
–3dB
BANDWIDTH
(kHz)
1. The input signal aliases when its frequency
exceeds fDATA/2, in accordance with the Nyquist
theorem.
Frequency Response
Figure 43 shows the frequency response for the
Wide-Bandwidth filter path normalized to the output
data rate, fDATA. Figure 44 shows the passband ripple,
and the transition from passband to stop band is
illustrated in Figure 45. These three plots are valid for
all of the data rates available on the ADS1675.
Simply substitute the selected data rate to express
the x-axis in absolute frequency.
0.15
0.20
0.25
0.30
0.35
Normalized Frequency (fIN/fDATA)
Figure 44. Passband Response for
Wide-Bandwidth Filter
2
0
Magnitude (dB)
DRATE
[2:0]
DATA
RATE
(kSPS)
-2
-4
-6
-8
-10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Normalized Frequency (fIN/fDATA)
Figure 45. Transition Band Response for
Wide-Bandwidth Filter
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Settling Time
The overall frequency response repeats at the
modulator sampling rate, which is the same as the
input clock frequency. Figure 46 shows the response
with the fastest data rate selected (4 MSPS when fCLK
= 32MHz).
The Wide-Bandwidth filter fully settles before
indicating data are ready for retrieval after the START
pin is taken high, as shown in Figure 48. For this
filter, the settling time is larger than the conversion
time: tSETTLE-WB > tDRDY-WB. Instantaneous steps on
the input require multiple conversions to settle if
START is not pulsed. Figure 47 shows the settling
response with the x-axis normalized to conversions or
data-ready cycles. The output is fully settled after 55
data-ready cycles.
20
0
Magnitude (dB)
-20
-40
-60
120
-80
100
-100
80
Settling (%)
-120
-140
0
0.5
1.0
1.5
2.5
2.0
3.0
Normalized Frequency (fIN/fCLK)
60
Fully Settled at
55 Conversions
40
20
Figure 46. Extended Frequency Response of
Wide-Bandwidth Path
0
-20
0
Phase Response
10
20
30
40
50
60
Conversions (1/fDRDY-WB)
The Wide-Bandwidth filter uses a multiple-stage,
linear-phase digital filter. Linear phase filters exhibit
constant delay time versus input frequency (also
know as constant group delay). This feature means
that the time delay from any instant of the input signal
to the corresponding same instant of the output data
is constant and independent of the input signal
frequency. This behavior results in essentially zero
phase error when measuring multi-tone signals.
Figure 47. Step Response for
Wide-Bandwidth Filter
tSTART_CLKR
CLK
tSETTLE
START
tDRDY
(1)
tDRDY
tDRDY
tDRDY
DRDY
(1) tDRDY = 1/fDATA. See Table 6 for the relationship between tSETTLE and tDRDY when using the Wide-Bandwidth filter.
Figure 48. START Pin Used for Multiple Conversions with Wide-Bandwidth Filter Path
22
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OTRA, OTRD FUNCTIONS
The ADS1675 provides two out-of-range pins (OTRD,
OTRA) that can be used in feedback loops to set the
dynamic range of the input signal.
The OTRA signal is triggered when the analog input
to the modulator exceeds the positive or the negative
full-scale range, as shown in Figure 49. This signal is
triggered synchronous to CLK and returns low when
the input becomes within range. The falling edge of
OTRA is synchronized with the falling edge of DRDY.
OTRA can be used in feedback loops to correct input
over range conditions quicker instead of waiting for
the digital filter to settle.
The OTRD function is triggered when the output code
of the digital filter exceeds the positive or negative
full-scale range. OTRD goes high on the rising edge
of DRDY. When the digital output code returns within
the full-scale range, OTRD returns low on the next
rising edge of DRDY. OTRD can also be used when
small out-of-range input glitches must be ignored.
OTRA can be used in feedback loops to correct input
over-range conditions quickly.
SERIAL INTERFACE
The ADS1675 offers a flexible and easy-to-use,
read-only serial interface designed to connect to a
wide range of digital processors, including DSPs,
microcontrollers, and FPGAs. In the low-speed
modes (DRATE = 000 to 011) the ADS1675 serial
interface can be configured to support either standard
CMOS voltage swings or low-voltage differential
swings (LVDS). In addition, when using standard
CMOS voltage swings, SCLK can be internally or
externally generated.
The high-speed modes (DRATE = 100, 101) are
supported in high-speed LVDS interface mode only.
The state of the LVDS pin and the SCLK_SEL are
ignored. In these two modes, an on-chip PLL is used
to multiply the input clock (CLK) by three, to be used
for the serial interface. This high-speed clock enables
all 23-bit output data to be shifted out at the high data
rate. The DRDY pulse in this case is three serial
clocks wide. The on-chip PLL can lock to input clocks
ranging from 8MHz to 32MHz. To conserve power,
the PLL is enabled only in the high-speed modes.
After power up as well as after the CLK signal is
issued, if the CLK frequency is changed, and when
switching from low-speed mode to high-speed mode,
the PLL needs at least tLPLLSTL to lock on and
generate a proper LVDS serial shift clock. Switching
among the high-speed modes does not require the
user to wait for the PLL to lock. While the PLL is
locking on, DOUT and SCLK are held low. After the
PLL has locked on, the SCLK pin outputs a
continuous clock that is three times the frequency of
CLK. The device gives out a DRDY pulse (regardless
of the status of the START signal) to indicate that the
lock is complete. Disregard the data associated with
this DRDY pulse. After this DRDY pulse, it is
recommended that the user toggle the start signal
before starting to capture data.
The ADS1675 is entirely controlled by pins; there are
no registers to program. Connect the I/O pins to the
appropriate level to set the desired function.
Whenever changing the digital I/O pins that control
the ADS1675, be sure to issue a START pulse
immediately after the change in order to latch the new
values.
3V
AIN
CLK
SCLK
(High-Speed Mode)
DRDY
OTRA
(Low-Speed Mode)
OTRA
(High-Speed Mode)
Figure 49. OTRA Signal Trigger
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USING LVDS OUTPUT SWINGS
When the LVDS pin is set to '0', the ADS1675
outputs are LVDS TIA/EIA-644A compliant. The data
out, shift clock, and data ready signals are output on
the differential pairs of pins DOUT/DOUT,
SCLK/SCLK, and DRDY/DRDY, respectively. The
voltage on the outputs is centered on 1.2V and
swings approximately 350mV differentially. For more
information on the LVDS interface, refer to the
document Low-Voltage Differential Signaling (LVDS)
Design Notes (literature number SLLA014) available
for download at www.ti.com.
When using LVDS, SCLK must be internally
generated. The states of SCLK_SEL pin is ignored.
Do not leave these pins floating; they must be tied
high or low.
USING CMOS OUTPUT SWINGS
When the LVDS pin is set to '1', the ADS1675
outputs are CMOS-compliant and swing from rail to
rail. The data out and data ready signals are output
on the differential pairs of pins DOUT/DOUT and
DRDY/DRDY, respectively. Note that these are the
same pins used to output LVDS signals when the
LVDS pin is set to '0'. DOUT and DRDY are
complementary outputs provided for convenience.
When not in use, these pins should be left floating.
See the Serial Shift Clock section for a description of
the SCLK and SCLK pins.
DATA OUTPUT (DOUT, DOUT)
Data are output serially from the ADS1675, MSB first,
on the DOUT and DOUT pins. When LVDS signal
swings are used, these two pins act as a differential
pair to produce the LVDS-compatible differential
output signal. When CMOS signal swings are used,
the DOUT pin is the complement of DOUT. If DOUT
is not used, it should be left floating.
SERIAL SHIFT CLOCK (SCLK, SCLK,
SCLK_SEL)
The serial shift clock SCLK is used to shift out the
conversion data, MSB first, onto the Data Output
pins. Either an internally- or externally-generated shift
clock can be selected using the SCLK_SEL pin. If
SCLK_SEL is set to '0', a free-running shift clock is
generated internally from the master clock and
outputs on the SCLK and SCLK pins. The LVDS pin
determines if the output voltages are CMOS or LVDS.
If SCLK_SEL is set to '1' and LVDS is set to '1', the
SCLK pin is configured as an input to accept an
externally-generated shift clock. In this case, the
SCLK pin enters a high-impedance state. When
SCLK_SEL is set to '0', the SCLK and SCLK pins are
configured as outputs, and the shift clock is
generated internally using the master clock input
(CLK).
When LVDS signal swings are used, the shift clock is
automatically generated internally regardless of the
state of SCLK_SEL. In this case, SCLK_SEL cannot
be left floating; it must be tied high or low.
Table 7 summarizes the supported serial clock
configurations for the ADS1675.
Table 7. Supported Serial Clock Configurations
DIGITAL OUTPUTS
SHIFT CLOCK (SCLK)
LVDS
Internal
CMOS
Internal (SCLK_SEL = '0')
External (SCLK_SEL = '1')
CHIP SELECT (CS)
DATA READY (DRDY, DRDY)
Data ready for retrieval are indicated on the DRDY
and DRDY pins. When LVDS signal swings are used,
these two pins act as a differential pair to produce the
LVDS-compatible differential output signal. When
CMOS signal swings are used, the DRDY pin is the
complement of DRDY. If one of the data ready pins is
not used when CMOS swings are selected, it should
be left floating.
24
The DRDY pulse is the primary indicator from the
ADS1675 that data are available for retrieval. Table 5
and Table 6 only give approximate values for settling
time after a START signal. The rising edge of DRDY
should be used as an indicator to start the data
capture with the serial shift clock.
The chip select input (CS) allows multiple devices to
share a serial bus. When CS is inactive (high), the
serial interface is reset and the data output pins
DOUT and DOUT enter a high-impedance state.
SCLK is internally generated; the SCLK and SCLK
output pins also enter a high-impedance state when
CS is inactive. The DRDY and DRDY outputs are
always active, regardless of the state of the CS
output. CS may be permanently tied low when the
outputs do not share a bus.
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DATA FORMAT
In the low-speed modes, the ADS1675 outputs 24
bits of data in twos complement format. A positive
full-scale input produces an output code of 7FFFFFh,
and the negative full-scale input produces an output
code of 800000h. The output clips at these codes for
signals that exceed full-scale. Table 8 summarizes
the ideal output codes for different input signals.
When the input is positive out-of-range, exceeding
the positive full-scale value of VREF, the output clips to
all 7FFFFFh. Likewise, when the input is negative
out-of-range by going below the negative full-scale
value of –VREF, the output clips to 800000h.
Table 8. Ideal Output Code vs Input Signal
INPUT SIGNAL
VIN = (AINP – AINN)
IDEAL OUTPUT CODE
≥ VREF
7FFFFFh
+VREF
2
23
000001h
-1
0
000000h
-VREF
2
23
FFFFFFh
-1
23
< -VREF
( 2 2 - 1)
23
8000000h
1. Excludes effects of noise, INL, offset and gain
errors.
Measuring high-frequency, large amplitude signals
requires tight control of clock jitter. The uncertainty
during sampling of the input from clock jitter limits the
maximum achievable SNR. This effect becomes more
pronounced with higher frequency and larger
magnitude inputs. Fortunately, the ADS1675
oversampling topology reduces clock jitter sensitivity
over that of Nyquist rate converters, such as pipeline
and SAR converters, by at least a factor of √8.
SYNCHRONIZING MULTIPLE ADS1675s
The START pin should be applied at power-up and
resets the ADS1675 filters. START begins the
conversion process, and the START pin enables
simultaneous sampling with multiple ADS1675s in
multichannel systems. All devices to be synchronized
must use a common CLK input.
It is recommended that the START pin be aligned to
the falling edge of CLK to ensure proper
synchronization because the START signal is
internally latched by the ADS1675 on the rising edge
of CLK.
With the CLK inputs running, pulse START on the
falling edge of CLK, as shown in Figure 50.
Afterwards, the converters operate synchronously
with the DRDY outputs updating simultaneously. After
synchronization, DRDY is held high until the digital
filter has fully settled.
ADS16751
In the high-speed modes, the ADS1675 has 23 bits of
resolution. The 24th bit in these modes is held low.
START
CLK
START1
DRDY
DRDY1
CLK
CLOCK INPUT (CLK)
ADS16752
The ADS1675 requires an external clock signal to be
applied to the CLK input pin. The sampling of the
modulator is controlled by this clock signal. As with
any high-speed data converter, a high-quality clock is
essential for optimum performance. Crystal clock
oscillators are the recommended CLK source; other
sources, such as frequency synthesizers, are usually
inadequate. Make sure to avoid excess ringing on the
CLK input; keep the trace as short as possible.
START2
DRDY
DRDY2
CLK
CLK
tSETTLE
START
For best performance, the CLK duty cycle should be
very close to 50%. The rise and fall times of the clock
should be less than 1ns and clock amplitude should
be equal to AVDD.
DRDY1
DRDY2
Figure 50. Synchronizing Multiple Converters
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ANALOG POWER DISSIPATION
An external resistor connected between the RBIAS
pin and the analog ground sets the analog current
level, as shown in Figure 51. The current is inversely
proportional to the resistor value. Figure 24 to
Figure 26 (in the Typical Characteristics) show power
and typical performance at values of RBIAS for
different CLK frequencies. Notice that the analog
current can be reduced when using a slower
frequency CLK input because the modulator has
more time to settle. Avoid adding any capacitance in
parallel to RBIAS, because this additional capacitance
interferes with the internal circuitry used to set the
biasing.
ADS1675
RBIAS
RBIAS
AGND
Figure 51. External Resistor Used to Set Analog
Power Dissipation (Depends on fCLK)
POWER DOWN (PDWN)
When not in use, the ADS1675 can be powered down
by taking the PDWN pin low. All circuitry shuts down,
26
including the voltage reference. To minimize the
digital current during power down, stop the clock
signal supplied to the CLK input. Make sure to allow
time for the reference to start up after exiting
power-down mode.
After the reference has stabilized, allow for the
modulator and digital filter to settle before retrieving
data.
POWER SUPPLIES
Two supplies are used on the ADS1675: analog
(AVDD) and digital (DVDD). Each supply must be
suitably bypassed to achieve the best performance. It
is recommended that a 1mF and 0.1mF ceramic
capacitor be placed as close to each supply pin as
possible. AVDD must be very clean and stable in
order to achieve optimum performance from the
device.
Connect each supply-pin bypass capacitor to the
associated ground. Each main supply bus should also
be bypassed with a bank of capacitors from 47mF to
0.1mF. Figure 52 illustrates the recommended method
for ADS1675 power-supply decoupling.
Power-supply pins 53 and 54 are used to drive the
internal clock supply circuits and, as such, are very
noisy. It is highly recommended that the traces from
these pins not be shared or run close to any of the
adjacent AVDD or AGND pins of the ADS1675.
These pins should be well-decoupled, using a 0.1mF
ceramic capacitor close to the pins, and immediately
terminated into power and ground planes.
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+5V
+3V
0.1mF
0.1mF
57
58
10mF
0.1mF
56
54
AVDD AGND AGND
53
52
51
50
49
AGND AVDD DVDD DGND DGND DVDD
1 AVDD
DVDD 48
2 AGND
DGND 47
0.1mF
10mF
3 AGND
+5V
0.1mF
10mF
6 AGND
ADS1675
7 AVDD
9 AGND
10 AGND
11 AVDD
12 AVDD
DGND DGND DGND DGND DVDD DVDD DGND DGND DVDD DGND
17
18
19
20
23
24
25
26
27
31
0.1mF
10mF
Figure 52. Power-Supply Decoupling
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APPLICATION INFORMATION
To obtain the specified performance from the
ADS1675, the following layout and component
guidelines should be considered.
1. Power Supplies: The device requires two power
supplies for operation: DVDD and AVDD. A very
clean and stable AVDD supply is needed to
achieve optimal performance from the device. For
both supplies, use a 10mF tantalum capacitor,
bypassed with a 0.1mF ceramic capacitor, placed
close to the device pins. Alternatively, a single
10mF ceramic capacitor can be used. The
supplies should be relatively free of noise and
should not be shared with devices that produce
voltage spikes (such as relays, LED display
drivers, etc.). If a switching power-supply source
is used, the voltage ripple should be low (less
than 2mV). The power supplies may be
sequenced in any order.
2. Ground Plane: A single ground plane connecting
both AGND and DGND pins can be used. If
separate digital and analog grounds are used,
connect the grounds together at the converter.
3. Digital Inputs: Source terminate the digital inputs
to the device with 50Ω series resistors. The
resistors should be placed close to the driving
end of the digital source (oscillator, logic gates,
DSP, etc.). These resistors help reduce ringing
on the digital lines, which may lead to degraded
ADC performance.
4. Analog/Digital Circuits: Place analog circuitry
(input buffer, reference) and associated tracks
together, keeping them away from digital circuitry
(DSP, microcontroller, logic). Avoid crossing
digital tracks across analog tracks to reduce
noise coupling and crosstalk.
5. Reference Inputs: The ADS1675 reference input
has 400Ω across VREFP and VREFN. The
driving amplifier must source current for this static
current, as well as dynamic switching current as a
result of the 32MHz clock. The reference driving
amplifier should be ready to source at least
10.5mA.
28
6. Analog Inputs: The analog input pins must be
driven differentially to achieve specified
performance. A true differential driver or
transformer (ac applications) can be used for this
purpose. Route the analog inputs tracks (AINP,
AINN) as a pair from the buffer to the converter
using short, direct tracks and away from digital
tracks. A 750pF capacitor should be used directly
across the analog input pins, AINP and AINN. A
low-k dielectric (such as COG or film type) should
be used to maintain low THD. Capacitors from
each analog input to ground should be used.
They should be no larger than 1/10 the size of
the difference capacitor (typically 100pF) to
preserve the ac common-mode performance.
7. Component Placement: Place the power supply,
analog input, and reference input bypass
capacitors as close as possible to the device
pins. This placement is particularly important for
the
small-value
ceramic
capacitors.
Surface-mount components are recommended to
avoid the higher inductance of leaded
components.
Figure 53 through Figure 55 illustrate the basic
connections and interfaces that can be used with the
ADS1675.
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1kW
10nF
+5V
0.1mF
10W
OPA211
100W
1kW
100mF
10mF
0.1mF
1mF
63
62
OUT
VIN
+5V
TRIM
REF5030
0.1mF
64
3V
22mF
1mF
61
60
59
VREFP VREFP CAP2 VREFN VREFN CAP1
10W
4 AINN
VINN
Differential
Inputs
10W
VINP
100pF
750pF
5 AINP
100pF
ADS1675
8 RBIAS
7.5kW
13 VCM
1 mF
Figure 53. Basic Analog Signal Connection
CF
100pF
RF
249W
+9V
RG
249W
CM
2.5V
VIN+
CM
2.5V
VIN-
+
-
VINN
+
VINP
THS4503
RG
249W
CM
2.5V
-4V
RF
249W
CF
100pF
Figure 54. Basic Differential Input Signal Interface
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CF
100pF
Signal Source
RG
243W
RS
50W
RT
59W
VIN
CM
2.5V
CM
2.5V
RS
50W
CM
2.5V
RG
243W
RF
249W
+9V
+
-
RT
59W
CM
2.5V
-
VINN
+
VINP
THS4503
CM
-4V 2.5V
RF
249W
CF
100pF
Figure 55. Basic Single-Ended Input Signal Interface
30
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ form page numbers in the current version.
Changes from Revision C (September 2009) to Revision D
Page
•
Changed 115dB to 86dB in second paragraph of Description section ................................................................................. 1
•
Changed AC Performance, Total harmonic distortion (fDATA = 4MSPS) typical specifiaction in Electrical
Characteristics table ............................................................................................................................................................. 3
•
Changed Digital Filter Characteristics (Wide-Bandwidth Path), Stop band attentuation typical specification in
Electrical Characteristics table .............................................................................................................................................. 3
•
Added footnote 2 to Figure 1 ................................................................................................................................................ 7
•
Updated Figure 3 .................................................................................................................................................................. 8
•
Changed description of tDRSCLK parameter in internal SCLK timing requirements table ....................................................... 8
•
Changed description of tLSCLK parameter in internal SCLK timing requirements table ......................................................... 8
•
Deleted footnote 1 from Figure 5 .......................................................................................................................................... 9
•
Changed the description of the Common-Mode Voltage section ....................................................................................... 17
•
Added description of 24th bit to Data Format section ........................................................................................................ 25
•
Changed description of the Reference Inputs guidline in Application Information section ................................................. 28
Changes from Revision June 2009 (B) to Revision C
Page
•
Changed [1:0] to [2:0] in DRATE column of Table 6 .......................................................................................................... 21
•
Changed REF5030 connections in Figure 53 ..................................................................................................................... 29
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Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1675
31
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
ADS1675IPAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-40 to 85
ADS1675I
ADS1675IPAGR
ACTIVE
TQFP
PAG
64
1500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-40 to 85
ADS1675I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADS1675IPAGR
Package Package Pins
Type Drawing
TQFP
PAG
64
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1500
330.0
24.4
Pack Materials-Page 1
13.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.0
1.5
16.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS1675IPAGR
TQFP
PAG
64
1500
350.0
350.0
43.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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