Texas Instruments | 11 Bit 105 MSPS ADC (Rev. A) | Datasheet | Texas Instruments 11 Bit 105 MSPS ADC (Rev. A) Datasheet

Texas Instruments 11 Bit 105 MSPS ADC (Rev. A) Datasheet
ADS5411
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SLAS487A − SEPTEMBER 2005 − REVISED JANUANRY 2010
11 Bit, 105 MSPS
Analog-to-Digital Converter
D 52 Pin HTQFP Package With Exposed
FEATURES
D 11 Bit Resolution
D 105 MSPS Maximum Sample Rate
D SNR = 66.4 dBc at 105 MSPS and 50 MHz IF
D SFDR = 90 dBc at 105 MSPS and 50 MHz IF
D SNR = 65.7 dBc at 105 MSPS and 170 MHz IF
D SFDR = 81 dBc at 105 MSPS and 170 MHz IF
D 2.2 Vpp Differential Input Range
D 5 V Supply Operation
D 3.3 V CMOS Compatible Outputs
D 1.9 W Total Power Dissipation
D 2s Complement Output Format
D On-Chip Input Analog Buffer, Track and Hold,
Heatsink
D Industrial Temperature Range = −405C to 855C
D Pin Compatible With ADS5423, ADS5424, and
AD6645
APPLICATIONS
D Single and Multichannel Digital Receivers
D Base Station Infrastructure
D Instrumentation
D Video and Imaging
RELATED DEVICES
D Clocking: CDC7005
D Amplifiers: OPA695, THS4509
and Reference Circuit
DESCRIPTION
The ADS5411 is an 11 bit, 105 MSPS analog-to-digital converter (ADC) that operates from a 5 V supply, while providing
3.3 V CMOS compatible digital outputs. The ADS5411 input buffer isolates the internal switching of the on-chip Track and
Hold (T&H) from disturbing the signal source. An internal reference generator is also provided to further simplify the system
design. The ADS5411 has outstanding low noise and linearity, over input frequency. With only a 2.2 VPP input range,
simplifies the design of multicarrier applications, where the carriers are selected on the digital domain.
The ADS5411 is available in a 52 pin HTQFP with heatsink package. The ADS5411 is built on state of the art Texas
Instruments complementary bipolar process (BiCom3) and is specified over full industrial temperature range (−40°C to
85°C).
FUNCTIONAL BLOCK DIAGRAM
AVDD
AIN
AIN
TH1
A1
+
TH2
Σ
A2
+
TH3
ADC1
DAC1
A3
ADC3
−
−
VREF
Σ
DRVDD
ADC2
DAC2
Reference
5
5
6
C1
C2
CLK+
CLK−
Digital Error Correction
Timing
DMID OVR
DRY
D[10:0]
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPad is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
Copyright  2005, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
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ADS5411
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SLAS487A − SEPTEMBER 2005 − REVISED JANUANRY 2010
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
NOTE:
For the most current package and ordering
information, see the Package Option Addendum at
the end of this document, or see the TI Web site at
www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
ADS5411
Supply voltage
AVDD to GND
6
DRVDD to GND
5
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because small parametric changes could cause
the device not to meet its published specifications.
UNIT
V
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
4.75
5
5.25
V
3
3.3
3.6
V
Analog input to GND
−0.3 to
AVDD + 0.3
V
Clock input to GND
−0.3 to
AVDD + 0.3
V
±2.5
V
−0.3 to
DRVDD + 0.3
V
Differential input range
2.2
VPP
−40 to 85
°C
2.4
V
150
°C
Input common-mode voltage,
VCM
−65 to 150
°C
10
pF
CLK to CLK
Digital data output to GND
Operating temperature range
Maximum junction temperature
Storage temperature range
(1)
Analog supply voltage, AVDD
2
Output driver supply voltage,
DRVDD
Analog Input
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
THERMAL CHARACTERISTICS(1)
(1)
Supplies
PARAMETER
TEST
CONDITIONS
TYP
UNIT
θJA
Soldered slug, no
airflow
22.5
°C/W
θJA
Soldered slug,
200-LPFM airflow
15.8
°C/W
θJA
Unsoldered slug,
no airflow
33.3
°C/W
θJA
Unsoldered slug,
200-LPFM airflow
25.9
°C/W
θJC
Bottom of
package
(heatslug)
2
°C/W
Using 25 thermal vias (5 x 5 array). See the Application Section.
Digital Output
Maximum output load
Clock Input
ADCLK input sample rate (sine
wave) 1/tC
30
Clock amplitude, sine wave,
differential
1
Clock duty cycle
40%
Open free-air temperature range
−40
105
MSPS
3
5
VPP
50%
60%
85
°C
ADS5411
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SLAS487A − SEPTEMBER 2005 − REVISED JANUANRY 2010
ELECTRICAL CHARACTERISTICS
Over full temperature range (TMIN = −40°C to TMAX = 85°C), sampling rate = 105 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V,
−1 dBFS differential input, and 3 VPP differential sinusoidal clock, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
UNIT
11
Bits
2.2
VPP
1
kΩ
Analog Inputs
Differential input range
Differential input resistance
See Figure 2
Differential input capacitance
See Figure 2
Analog input bandwidth
1.5
pF
570
MHz
2.4
V
Internal Reference Voltages
Reference voltage, VREF
Dynamic Accuracy
No missing codes
Tested
Differential linearity error, DNL
fIN = 10 MHz
−0.5
±0.25
0.5
LSB
Integral linearity error, INL
fIN = 10 MHz
−0.5
±0.2
0.5
LSB
−5
0
5
Offset error
Offset temperature coefficient
1.7
Gain error
−5
0.9
mV
ppm/°C
5
%FS
PSRR
1
mV/V
Gain temperature coefficient
77
ppm/°C
Power Supply
Analog supply current, IAVDD
VIN = full scale, fIN = 70 MHz
355
410
mA
Output buffer supply current, IDRVDD
VIN = full scale, fIN = 70 MHz
35
47
mA
Power dissipation
Total power with 10-pF load on each digital output
to ground, fIN = 70 MHz
1.9
2.2
W
20
100
ms
Power-up time
Dynamic AC Characteristics
fIN = 10 MHz
fIN = 30 MHz
66.5
65.3
fIN = 50 MHz
Signal-to-noise ratio, SNR
fIN = 70 MHz
66.4
65.3
66.3
fIN = 100 MHz
65.9
fIN = 170 MHz
65.7
fIN = 230 MHz
65.4
fIN = 10 MHz
fIN = 30 MHz
Spurious-free dynamic range, SFDR
66.5
dBc
91
85
91
fIN = 50 MHz
90
fIN = 70 MHz
90
fIN = 100 MHz
89
fIN = 170 MHz
81
fIN = 230 MHz
71
dBc
3
ADS5411
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SLAS487A − SEPTEMBER 2005 − REVISED JANUANRY 2010
ELECTRICAL CHARACTERISTICS
Over full temperature range (TMIN = −40°C to TMAX = 85°C), sampling rate = 105 MSPS, 50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V,
−1 dBFS differential input, and 3 VPP differential sinusoidal clock, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
fIN = 10 MHz
65
fIN = 50 MHz
Second harmonic, HD2
Third harmonic, HD3
Worst-harmonic / spur (other than HD2 and
HD3)
RMS idle channel noise
MAX
UNIT
66.5
fIN = 30 MHz
Signal-to-noise + distortion, SINAD
TYP
66.5
66.3
fIN = 70 MHz
65
66
fIN = 100 MHz
65.9
fIN = 170 MHz
65.4
fIN = 230 MHz
63.6
fIN = 10 MHz
100
fIN = 30 MHz
100
fIN = 50 MHz
98
fIN = 70 MHz
96
fIN = 100 MHz
91
fIN = 170 MHz
87
fIN = 230 MHz
87
fIN = 10 MHz
91
fIN = 30 MHz
91
fIN = 50 MHz
90
fIN = 70 MHz
90
fIN = 100 MHz
89
fIN = 170 MHz
81
fIN = 230 MHz
71
fIN = 10 MHz
94
fIN = 30 MHz
95
fIN = 50 MHz
95
fIN = 70 MHz
90
fIN = 100 MHz
89
fIN = 170 MHz
88
fIN = 230 MHz
88
Input pins tied together
0.3
dBc
dBc
dBc
dBc
LSB
DIGITAL CHARACTERISTICS
Over full temperature range (TMIN = −40°C to TMAX = 85°C), AVDD = 5 V, DRVDD = 3.3 V, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.1
0.6
V
Digital Outputs
Low-level output voltage
CLOAD = 10 pF(1)
High-level output voltage
CLOAD = 10 pF(1)
Output capacitance
DMID
(1)
4
Equivalent capacitance to ground of (load + parasitics of transmission lines).
2.6
3.2
V
3
pF
DRVDD/2
V
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TIMING CHARACTERISTICS(3)
Over full temperature range, AVDD = 5 V, DRVDD = 3.3 V, sampling rate = 105 MSPS
DESCRIPTION
PARAMETER
MIN
TYP
MAX
UNIT
Aperture Time
tA
Aperture delay
500
tJ
Clock slope independent aperture uncertainty (jitter)
150
ps
fs
kJ
Clock slope dependent jitter factor
50
µV
Clock Input
tCLK
Clock period
9.5
ns
tCLKH(1)
Clock pulse width high
4.75
ns
tCLKL(1)
Clock pulse width low
4.75
ns
Clock to DataReady (DRY)
tDR
Clock rising 50% to DRY falling 50%
2.8
3.9
4.7
tDR +
tCLKH
tC_DR
Clock rising 50% to DRY rising 50%
tC_DR_50%
Clock rising 50% to DRY rising 50% with 50% duty cycle clock
7.6
8.7
ns
ns
9.5
ns
Clock to DATA, OVR(4)
tr
Data VOL to data VOH (rise time)
2
tf
Data VOH to data VOL (fall time)
2
ns
L
Latency
3
Cycles
tsu(C)
Valid DATA(2) to clock 50% with 50% duty cycle clock (setup time)
1.8
3.4
ns
2.6
3.6
ns
tH(C)
Clock 50% to invalid
DATA(2)
(hold time)
ns
DataReady (DRY) to DATA, OVR(4)
tsu(DR)_50%
Valid DATA(2) to DRY 50% with 50% duty cycle clock (setup time)
1.6
2.6
ns
th(DR)_50%
DRY 50% to invalid DATA(2) with 50% duty cycle clock (hold time)
3.9
4.4
ns
(1)
See Figure 1 for more information.
(2) See V
OH and VOL levels.
(3) All values obtained from design and characterization.
(4) Data is updated with clock rising edge or DRY falling edge.
tA
N+3
N
AIN
N+1
N+2
tCLKH
tCLK
CLK, CLK
N+1
N
N+4
tCLKL
N+2
N+3
tC_DR
D[13:0], OVR
DRY
N−3
tr
N−2
tf
tsu(C)
N−1
tsu(DR)
N+4
th(C)
N
th(DR)
tDR
Figure 1. Timing Diagram
5
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PIN CONFIGURATION
DRY
D10 (MSB)
D9
D8
D7
D6
D5
D4
D3
DRVDD
GND
D2
D1
PJY PACKAGE
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
DRVDD
GND
VREF
GND
CLK
CLK
GND
AVDD
AVDD
GND
AIN
AIN
GND
1
39
2
3
38
37
4
36
5
6
35
34
7
33
GND
8
9
32
31
10
30
11
12
29
28
13
27
D0(LSB)
DNC
DNC
DNC
DMID
GND
DRVDD
OVR
DNC
AVDD
GND
AVDD
GND
AVDD
GND
AVDD
GND
AVDD
GND
C1
GND
AVDD
GND
C2
GND
AVDD
14 15 16 17 18 19 20 21 22 23 24 25 26
PIN ASSIGNMENTS
TERMINAL
NAME
NO.
DRVDD
1, 33, 43
DESCRIPTION
3.3 V power supply, digital output stage only
GND
2, 4, 7, 10, 13, 15,
17, 19, 21, 23, 25,
27, 29, 34, 42
Ground
VREF
3
2.4 V reference. Bypass to ground with a 0.1-µF microwave chip capacitor.
CLK
5
Clock input. Conversion initiated on rising edge.
CLK
6
Complement of CLK, differential input
AVDD
8, 9, 14, 16, 18,
22, 26, 28, 30
5 V analog power supply
AIN
11
Analog input
AIN
12
Complement of AIN, differential analog input
C1
20
Internal voltage reference. Bypass to ground with a 0.1-µF chip capacitor.
C2
24
Internal voltage reference. Bypass to ground with a 0.1-µF chip capacitor.
DNC
31, 36, 37, 38
OVR
32
Overrange bit. A logic level high indicates the analog input exceeds full scale.
DMID
35
Output data voltage midpoint. Approximately equal to (DRVDD)/2
39
Digital output bit (least significant bit); two’s complement
D0 (LSB)
D1, D2, D3−D9
40, 41, 44−50
Do not connect
Digital output bits in two’s complement
D10 (MSB)
51
Digital output bit (most significant bit); two’s complement
DRY
52
Data ready output
6
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the low
frequency value.
Aperture Delay
The delay in time between the rising edge of the input
sampling clock and the actual time at which the
sampling occurs.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse
width) to the period of the clock signal. Duty cycle is
typically expressed as a percentage. A perfect
differential sine wave clock results in a 50% duty cycle.
Maximum Conversion Rate
The maximum sampling rate at which certified
operation is given. All parametric testing is performed
at this sampling rate unless otherwise noted.
Minimum Conversion Rate
The minimum sampling rate at which the ADC
functions.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input
values spaced exactly 1 LSB apart. The DNL is the
deviation of any single step from this ideal value,
measured in units of LSB.
Integral Nonlinearity (INL)
The INL is the deviation of the ADC’s transfer function
from a best fit line determined by a least squares curve
fit of that transfer function, measured in units of LSB.
Gain Error
The gain error is the deviation of the ADC’s actual input
full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
Temperature Drift
The temperature drift coefficient (with respect to gain
error and offset error) specifies the change per degree
Celsius of the parameter from TMIN or TMAX. It is
computed as the maximum variation of that parameter
over the whole temperature range divided by TMAX −
TMIN.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at dc
and the first five harmonics.
SNR + 10Log 10
PS
PN
SNR is either given in units of dBc (dB to carrier) when
the absolute power of the fundamental is used as the
reference or dBFS (dB to full scale) when the power of
the fundamental is extrapolated to the converter’s
full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS)
to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding
dc.
SINAD + 10Log 10
PS
PN ) PD
SINAD is either given in units of dBc (dB to carrier) when
the absolute power of the fundamental is used as the
reference or dBFS (dB to full scale) when the power of
the fundamental is extrapolated to the converter’s
full-scale range.
Total Harmonic Distortion (THD)
THD is the ratio of the fundamental power (PS) to the
power of the first five harmonics (PD).
THD + 10Log 10
PS
PD
THD is typically given in units of dBc (dB to carrier).
Offset Error
The offset error is the difference, given in number of
LSBs, between the ADC’s actual value average idle
channel output code and the ideal average idle channel
output code. This quantity is often mapped into mV.
Power Up Time
The difference in time from the point where the supplies
are stable at ±5% of the final value, to the time the ac
test is past.
PSRR
The maximum change in offset voltage divided by the
total change in supply voltage, in units of mV/V.
7
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Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the highest
other spectral component (either spur or harmonic). SFDR
is typically given in units of dBc (dB to carrier).
8
Two-Tone Intermodulation Distortion
IMD3 is the ratio of the power of the fundamental (at
frequencies f1, f2) to the power of the worst spectral
component at either frequency 2f1 − f2 or 2f2 − f1). IMD3 is
either given in units of dBc (dB to carrier) when the
absolute power of the fundamental is used as the
reference or dBFS (dB to full scale) when it is referred to
the full-scale range.
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EQUIVALENT CIRCUITS
AVDD
AIN
BUF
T/H
AVDD
500 Ω
BUF
1.2 kΩ
500 Ω
AIN
VREF
−
Bandgap
AVDD
25 Ω
+
VREF
BUF
1.2 kΩ
T/H
Figure 5. Reference
Figure 2. Analog Input
DRVDD
AVDD
−
DAC
Bandgap
+
IOUTP
IOUTM
C1, C2
Figure 3. Digital Output
Figure 6. Decoupling Pin
AVDD
DRVDD
10 kΩ
CLK
1 kΩ
Clock Buffer
DMID
Bandgap
AVDD
1 kΩ
10 kΩ
CLK
Figure 4. Clock Input
Figure 7. DMID Generation
9
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TYPICAL CHARACTERISTICS
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate
= 105 MSPS, 3 VPP sinusoidal clock, 50% duty cycle, 8k FFT points, unless otherwise noted
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
1
0
fS = 105 MSPS
fIN = 30 MHz
SNR = 66.5 dBc
SINAD = 66.5 dBc
SFDR = 92 dBc
THD = 89 dBc
−40
fS = 105 MSPS
fIN = 70 MHz
SNR = 66.2 dBc
SINAD = 66.1 dBc
SFDR = 91 dBc
THD = 88 dBc
−20
Amplitude − dBFS
Amplitude − dBFS
−20
1
0
−60
−80
3
X
4
−40
−60
−80
3
25
6
6
52
−100
−120
−120
0
10
20
30
40
0
50
10
20
Figure 9.
SPECTRAL PERFORMANCE
AC PERFORMANCE
vs
INPUT AMPLITUDE
1
−40
SFDR (dBFS)
80
AC Performance − dB
−20
−60
2
−80
3
X
6
4
60
SNR (dBFS)
40
SFDR (dBc)
20
SNR (dBc)
5
0
−120
10
50
100
fS = 92.16 MSPS
fIN = 170 MHz
SNR = 65.5 dBc
SINAD = 65.3 dBc
SFDR = 80 dBc
THD = 78 dBc
0
40
Figure 8.
0
−100
30
f − Frequency − MHz
f − Frequency − MHz
Amplitude − dBFS
X
4
−100
20
30
−20
−70
40
f − Frequency − MHz
fS = 105 MSPS
fIN = 170 MHz
−60
−50
−40
−30
−20
−10
0
AIN − Input Amplitude − dB
Figure 10.
Figure 11.
TOTAL POWER
vs
SAMPLING FREQUENCY
INPUT BANDWIDTH
1.90
2
1.89
Amplitude − dBFS
PT − Total Power − W
0
1.88
1.87
1.86
1.85
1.84
−2
−4
−6
1.83
−8
1.82
−10
1.81
0
20
40
60
80
100
fS − Sampling Frequency − MSPS
Figure 12.
10
120
140
1
10
100
fIN − Input Frequency − MHz
Figure 13.
1k
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TYPICAL CHARACTERISTICS
SPURIOUS-FREE DYNAMIC RANGE
vs
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
89
66.00
0°C
40°C
88
fS = 105 MSPS
fIN = 170 MHz
87
86
85
100°C
84
85°C
83
−20°C
82
81
80
−40°C
79
2.6
2.8
3.0
3.2
SIGNAL-TO-NOISE RATIO
vs
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
SNR − Signal-to-Noise Ratio − dBc
SFDR − Spurious-Free Dynamic Range − dBc
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate
= 105 MSPS, 3 VPP sinusoidal clock, 50% duty cycle, 8k FFT points, unless otherwise noted
3.4
3.6
65.95
−40°C
65.90
65.85
65.80
65.75
65.70
65.65
65.60
65.55
65.50
2.6
3.8
2.8
3.0
3.2
3.4
3.6
3.8
DRVDD − Supply Voltage − V
Figure 14.
Figure 15.
SPURIOUS-FREE DYNAMIC RANGE
vs
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
SIGNAL-TO-NOISE RATIO
vs
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
89
66.0
fS = 105 MSPS
fIN = 170 MHz
0°C
88
85°C
SNR − Signal-to-Noise Ratio − dBc
SFDR − Spurious-Free Dynamic Range − dBc
40°C
85°C
100°C
DRVDD − Supply Voltage − V
87
86
85
100°C
84
40°C
83
82
−20°C
81
4.6
4.7
4.8
4.9
5.0
−40°C
5.1
5.2
5.3
65.9
65.8
65.7
65.6
100°C
85°C
0°C
65.5
65.4
4.6
5.4
fS = 105 MSPS
fIN = 170 MHz
−40°C
40°C
4.8
AVDD − Supply Voltage − V
5.0
5.2
5.4
AVDD − Supply Voltage − V
Figure 16.
Figure 17.
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
0.3
INL − Integral Nonlinearity − LSB
0.2
DNL − Differential Nonlinearity − LSB
fS = 105 MSPS
fIN = 170 MHz
0°C
0.1
0.0
−0.1
−0.2
0.2
0.1
0.0
−0.1
−0.2
−0.3
0
500
1000
Code
Figure 18.
1500
2000
0
500
1000
1500
2000
Code
Figure 19.
11
ADS5411
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SLAS487A − SEPTEMBER 2005 − REVISED JANUANRY 2010
TYPICAL CHARACTERISTICS
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3 V, differential input amplitude = −1 dBFS, sampling rate
= 105 MSPS, 3 VPP sinusoidal clock, 50% duty cycle, 8k FFT points, unless otherwise noted
130
120
65
66
fS − Sampling Frequency − MHz
110
65
66
100
90
80
65
70
64
60
66
50
65
63
64
40
63
66
30
65
20
65
64
63
63
62
10
0
25
75
50
61
100
56
63
64
60
125
59
62
62
61
150
175
59
225
200
fIN − Input Frequency − MHz
60
62
58
60
58
275
64
275
300
66
SNR − dBc
Figure 20.
130
83
120
92
110
fS − Sampling Frequency − MHz
74
86
89
89
100
71
89
86
83
80
68
65
77
89
89
90
92
92
89
86 89
92
74
92
80
89
70
60
89
71
83
65
86
92
62
77
95
50
68
80
89
40
92
30
74
95
80
20
95
86
89
95
83
71
68
65
62
59
77
10
0
25
75
50
100
125
150
175
225
200
275
275
fIN − Input Frequency − MHz
50
55
60
65
70
75
SFDR − dBc
Figure 21.
12
80
85
90
95
300
ADS5411
www.ti.com
SLAS487A − SEPTEMBER 2005 − REVISED JANUANRY 2010
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5411 is a 11 bit, 105 MSPS, monolithic pipeline
analog to digital converter. Its bipolar analog core
operates from a 5 V supply, while the output uses 3.3 V
supply for compatibility with the CMOS family. The
conversion process is initiated by the rising edge of the
external input clock. At that instant, the differential input
signal is captured by the input track and hold (T&H) and
the input sample is sequentially converted by a series
of small resolution stages, with the outputs combined in
a digital correction logic block. Both the rising and the
falling clock edges are used to propagate the sample
through the pipeline every half clock cycle. This process
results in a data latency of three clock cycles, after
which the output data is available as a 11 bit parallel
word, coded in binary two’s complement format.
INPUT CONFIGURATION
The analog input for the ADS5411 (see Figure 2)
consists of an analog differential buffer followed by a
bipolar track-and-hold. The analog buffer isolates the
source driving the input of the ADC from any internal
switching. The input common mode is set internally
through a 500 Ω resistor connected from 2.4 V to each
of the inputs. This results in a differential input
impedance of 1 kΩ.
of 2.2 VPP. The maximum swing is determined by the
internal reference voltage generator eliminating any
external circuitry for this purpose.
The ADS5411 obtains optimum performance when the
analog inputs are driven differentially. The circuit in
Figure 22 shows one possible configuration using an
RF transformer with termination either on the primary or
on the secondary of the transformer. If voltage gain is
required a step up transformer can be used. For higher
gains that would require impractical higher turn ratios on
the transformer, a single-ended amplifier driving the
transformer can be used (see Figure 23). Another
circuit optimized for performance would be the one on
Figure 24, using the THS4304 or the OPA695. Texas
Instruments has shown excellent performance on this
configuration up to 10 dB gain with the THS4304 and at
14 dB gain with the OPA695. For the best performance,
they need to be configured differentially after the
transformer (as shown) or in inverting mode for the
OPA695 (see SBAA113); otherwise, HD2 from the op
amps limits the useful frequency.
R0
50W
VIN
AIN
1:1
R
50W
AC Signal
Source
For a full-scale differential input, each of the differential
lines of the input signal (pins 11 and 12) swings
symmetrically between 2.4 +0.55 V and 2.4 –0.55 V.
This means that each input is driven with a signal of up
to 2.4 ±0.55 V, so that each input has a maximum signal
swing of 1.1 VPP for a total differential input signal swing
5V
Z0
50W
ADS5411
AIN
ADT1−1WT
Figure 22. Converting a Single-Ended Input to a
Differential Signal Using RF Transformers
−5 V
RS
100 Ω
+
OPA695
−
0.1 µF
1000 µF
RIN
1:1
RT
100 Ω
RIN
AIN
CIN
ADS5411
AIN
R1
400 Ω
R2
57.5 Ω
AV = 8V/V
(18 dB)
Figure 23. Using the OPA695 With the ADS5411
13
ADS5411
www.ti.com
SLAS487A − SEPTEMBER 2005 − REVISED JANUANRY 2010
APPLICATION INFORMATION
RG
RF
CM
5V
−
THS4304
+
1:1
VIN
49.9 Ω
CM
From
50 Ω
Source
5V
AIN
ADS5411
VREF
AIN
+
THS4304
−
RG
CM
RF
CM
Figure 24. Using the THS4304 With the ADS5411
Besides these, Texas Instruments offers a wide
selection of single-ended operational amplifiers
(including the THS3201, THS3202, and OPA847) that
can be selected depending on the application. An RF
gain block amplifier, such as Texas Instrument’s
THS9001, can also be used with an RF transformer for
high input frequency applications. For applications
requiring dc-coupling with the signal source, instead of
using a topology with three single ended amplifiers, a
differential input/differential output amplifier like the
THS4509 (see Figure 25) can be used, which
minimizes board space and reduce number of
components.
14
On this configuration, the THS4509 amplifier circuit
provides 10 dB of gain, converts the single-ended input
to differential, and sets the proper input common-mode
voltage to the ADS5411.
The 225 Ω resistors and 2.7 pF capacitor between the
THS4509 outputs and ADS5411 inputs (along with the
input capacitance of the ADC) limit the bandwidth of the
signal to about 100 MHz (−3 dB).
For this test, an Agilent signal generator is used for the
signal source. The generator is an ac-coupled 50 Ω
source. A band-pass filter is inserted in series with the
input to reduce harmonics and noise from the signal
source.
ADS5411
www.ti.com
SLAS487A − SEPTEMBER 2005 − REVISED JANUANRY 2010
APPLICATION INFORMATION
Input termination is accomplished via the 69.8 Ω
resistor and 0.22 µF capacitor to ground in conjunction
with the input impedance of the amplifier circuit. A
0.22 µF capacitor and 49.9 Ω resistor is inserted to
ground across the 69.8 Ω resistor and 0.22 µF capacitor
on the alternate input to balance the circuit.
Square Wave or
Sine Wave
From VIN
50 Ω
Source
100 Ω
69.8 Ω
348 Ω
+5V
225 Ω
0.22 µF
100 Ω
49.9 Ω
0.22 µF
69.8 Ω
THS 4509
2.7 pF
225 Ω
CM
14-Bit
105 MSPS
AIN
ADS5411
AIN VREF
CLK
0.01 µF
Figure 26. Single-Ended Clock
CLOCK INPUTS
The ADS5411 clock input can be driven with either a
differential clock signal or a single-ended clock input,
with little or no difference in performance between both
configurations. In low input frequency applications,
where jitter may not be a big concern, the use of
single-ended clock (see Figure 26) could save some
cost and board space without any trade-off in
performance. When driven on this configuration, it is
best to connect CLKM (pin 6) to ground with a 0.01 µF
capacitor, while CLKP is ac-coupled with a 0.01 µF
capacitor to the clock source, as shown in Figure 24.
49.9 Ω
0.22 µF
348 Ω
0.1 µF
0.1 µF
0.01 µF
ADS5411
Gain is a function of the source impedance, termination,
and 348 Ω feedback resistor. See the THS4509 data
sheet (SLOS454) for further component values to set
proper 50 Ω termination for other common gains.
Since
the
ADS5411
recommended
input
common-mode voltage is 2.4 V, the THS4509 is
operated from a single power supply input with
VS+ = 5 V and VS− = 0 V (ground). This maintains
maximum headroom on the internal transistors of the
THS4509.
CLK
0.1 µF
Clock
Source
1:4
CLK
ADS5411
Figure 25. Using the THS4509 With the ADS5411
MA3X71600LCT−ND
CLK
Figure 27. Differential Clock
Nevertheless, for jitter sensitive applications, the use of
a differential clock will have some advantages (as with
any other ADCs) at the system level. The first
advantage is that it allows for common-mode noise
rejection at the PCB level. A further analysis (see
Clocking High Speed Data Converters, SLYT075)
reveals one more advantage. The following formula
describes the different contributions to clock jitter:
(Jittertotal)2 = (EXT_jitter)2+ (ADC_jitter)2=
(EXT_jitter) 2 + (ADC_int)2 + (K/clock_slope)2
15
ADS5411
www.ti.com
SLAS487A − SEPTEMBER 2005 − REVISED JANUANRY 2010
APPLICATION INFORMATION
The first term would represent the external jitter, coming
from the clock source, plus noise added by the system
on the clock distribution, up to the ADC. The second
term is the ADC contribution, which can be divided in
two portions. The first does not depend directly on any
external factor. That is the best we can get out of our
ADC. The second contribution is a term inversely
proportional to the clock slope. The faster the slope, the
smaller this term will be. As an example, we could
compute the ADC jitter contribution from a sinusoidal
input clock of 3 Vpp amplitude and Fs = 80 MSPS:
Another possibility is the use of a logic based clock, as
PECL. In this case, the slew rate of the edges will most
likely be much higher than the one obtained for the
same clock amplitude based on a sinusoidal clock. This
solution would minimize the effect of the slope
dependent ADC jitter. Nevertheless, observe that for
the ADS5411, this term is small and has been
optimized. Using logic gates to square a sinusoidal
clock may not produce the best results as logic gates
may not have been optimized to act as comparators,
adding too much jitter while squaring the inputs.
ADC_jitter = sqrt ((150fs)2+ (5 x 10−5/(1.5 x 2 x PI x
80 x 106))2) = 164fs
The common-mode voltage of the clock inputs is set
internally to 2.4 V using internal 1 kΩ resistors. It is
recommended using an ac coupling, but if for any
reason, this scheme is not possible, due to, for
instance, asynchronous clocking, the ADS5411
presents a good tolerance to clock common-mode
variation.
The use of differential clock allows for the use of bigger
clock amplitudes without exceeding the absolute
maximum ratings. This, on the case of sinusoidal clock,
results on higher slew rates which minimizes the impact
of the jitter factor inversely proportional to the clock
slope.
Figure 27 shows this approach. The back-to-back
Schottky can be added to limit the clock amplitude in
cases where this would exceed the absolute maximum
ratings, even when using a differential clock.
100 nF
MC100EP16DT
100 nF
D
D
CLK
VBB Q
499 W
100 nF
Q
100 nF
ADS5411
CLK
499 W
50 Ω
50 Ω
100 nF
113 Ω
Figure 28. Differential Clock Using PECL Logic
16
Additionally, the internal ADC core uses both edges of
the clock for the conversion process. This means that,
ideally, a 50% duty cycle should be provided.
DIGITAL OUTPUTS
The ADC provides 11 data outputs (D10 to D0, with D10
being the MSB and D0 the LSB), a data-ready signal
(DRY, pin 52), and an out-of-range indicator (OVR, pin
32) that equals 1 when the output reaches the full-scale
limits.
The output format is two’s complement. When the input
voltage is at negative full scale (around −1.1 V
differential), the output will be, from MSB to LSB,
100 0000 0000. Then, as the input voltage is increased,
the output switches to 100 0000 0001, 100 0000 0010
and so on unit 111 1111 1111 right before mid-scale
(when both inputs are tight together if we neglect offset
errors). Further increase on input voltage outputs the
word 000 0000 0000, to be followed by 000 0000 0001,
000 0000 0010, and so on until reaching 111 1111 1111
at full-scale input (1.1 V differential).
ADS5411
www.ti.com
SLAS487A − SEPTEMBER 2005 − REVISED JANUANRY 2010
APPLICATION INFORMATION
Although the output circuitry of the ADS5411 has been
designed to minimize the noise produced by the
transients of the data switching, care must be taken
when designing the circuitry reading the ADS5411
outputs. Output load capacitance should be minimized
by minimizing the load on the output traces, reducing
their length and the number of gates connected to them,
and by the use of a series resistor with each pin. Typical
numbers on the data sheet tables and graphs are
obtained with 100 Ω series resistor on each digital
output pin, followed by a 74AVC16244 digital buffer as
the one used in the evaluation board.
POWER SUPPLIES
The use of low noise power supplies with adequate
decoupling is recommended, being the linear supplies
the first choice vs switched ones, which tend to
generate more noise components that can be coupled
to the ADS5411.
The ADS5411 uses two power supplies. For the analog
portion of the design, a 5 V AVDD is used, while for the
digital outputs supply (DRVDD), we recommend the use
of 3.3 V. All the ground pins are marked as GND,
although AGND pins and DRGND pins are not tied
together inside the package. Customers willing to
experiment with different grounding schemes should
know that AGND pins are 4, 7, 10, 13, 15, 17, 19, 21,
23, 25, 27, and 29, while DRGND pins are 2, 34, and 42.
Nevertheless, we recommend that both grounds are
tied together externally, using a common ground plane.
That is the case on the production test boards and
modules provided to customer for evaluation. In order
to obtain the best performance, user should layout the
board to guarantee that the digital return currents do not
flow under the analog portion of the board. This can be
achieved without the need to split the board and just
with careful component placing and increasing the
number of vias and ground planes.
Finally, notice that the metallic heat sink under the
package is also connected to analog ground.
LAYOUT INFORMATION
The evaluation board represents a good guideline of
how to layout the board to obtain the maximum
performance out of the ADS5411. General design rules
as the use of multilayer boards, single ground plane for
both, analog and digital ADC ground connections and
local decoupling ceramic chip capacitors should be
applied. The input traces should be isolated from any
external source of interference or noise, including the
digital outputs as well as the clock traces. Clock should
also be isolated from other signals, especially on
applications where low jitter is required, as high IF
sampling.
Besides performance oriented rules, special care has
to be taken when considering the heat dissipation out
of the device. The thermal heat sink (octagonal, with
2,5 mm on each side) should be soldered to the board,
and provision for more than 16 ground vias should be
made. The thermal package information describes the
TJA values obtained on the different configurations.
17
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS5411IPGP
ACTIVE
HTQFP
PGP
52
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS5411IPGP
ADS5411IPGPR
ACTIVE
HTQFP
PGP
52
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS5411IPGP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADS5411IPGPR
Package Package Pins
Type Drawing
HTQFP
PGP
52
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
13.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.0
1.5
16.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS5411IPGPR
HTQFP
PGP
52
1000
350.0
350.0
43.0
Pack Materials-Page 2
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