Texas Instruments | Tandem 64 Tap Digital Potentiometer | Datasheet | Texas Instruments Tandem 64 Tap Digital Potentiometer Datasheet

Texas Instruments Tandem 64 Tap Digital Potentiometer Datasheet
TPL8002-25
www.ti.com
SLIS133 – NOVEMBER 2009
TANDEM 64-TAP DIGITAL POTENTIOMETER
Check for Samples: TPL8002-25
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
1
•
Adjustable Gain From 23.25 dB to –24 dB
64-Tap Positions With 0.75 dB Per Step
Supports 8-MHz Analog Bandwidth
Operating Range up to –4-V VEE/+4-V VDD
100-μA Maximum Static Supply Current
±30% End-to-End Resistance Tolerance
Absolute Tolerance of ±0.3 dB
Operating Temperature Range From
–40°C to 85°C
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B,Class II)
Tandem Adjustable Feedback and Gain
Resistors for Operational Amplifers
PW PACKAGE
(TOP VIEW)
RG1
RF1
RSW1
VDD
VEE
RSW2
RF2
RG2
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
GND
A
B
C
D
E
F
GND
DESCRIPTION/ORDERING INFORMATION
The TPL8002-25 is a programmable resistor device implementing two digital potentiometers with 64 wiper
positions each that are tandem controlled through a 6-bit parallel interface. The device has fixed wiper
resistances at the respective wiper contacts that tap the potentiometer resistors at a point determined by the
binary code present at its digital inputs.
The resistive wiper tap terminals, RSW, of the TPL8002-25 are typically connected to the inverting inputs (–) of
an external differential path inverting operational amplifier configuration, with the non-inverting inputs (+)
connected through to ground. The application's differential input to the configuration is the device's RG terminals.
The differential output of the external operational amplifiers is connected to the device's RF terminals, and thus
becomes the differential output of the application configuration.
The resistance between the wiper contacts and the end points RG and RF of the TPL8002-25 provides a
logarithmic gain/attenuation response of the configuration. With a digital code of decimal 0 (b000000) the
configuration has an inverting maximum attenuation of –24 dB. With a digital code of decimal 32 (b100000) the
configuration has inverting unity gain of 0.00 dB. With a digital code of decimal 63 (b111111) the configuration
has an inverting maximum gain of +23.25 dB. The response of the configuration with respect to the digital code
varies in fixed steps of 0.75 dB.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
(2)
TSSOP – PW
(2)
Tape and reel
ORDERABLE PART NUMBER TOP-SIDE MARKING
TPL8002-25PWR
PHY03A
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPL8002-25
SLIS133 – NOVEMBER 2009
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
RG1
RF1
RSW1
1
Position
Decoder
2
3
15
14
13
Control
Circuitry
RSW2
RF2
RG2
6
12
11
10
7
Position
Decoder
8
A
B
C
D
E
F
TYPICAL APPLICATION CIRCUIT
RF
RG
+IN
–
RSW
+VOUT
+
½ OPA2889
RF
RG
–IN
–
RSW
–VOUT
+
2
½ OPA2889
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Product Folder Link(s): TPL8002-25
TPL8002-25
www.ti.com
SLIS133 – NOVEMBER 2009
FUNCTION TABLE
Table 1. Switch Truth Table
DECIMAL
CONTROL
FEDCBA
GAIN/ATTN (dB)
RG (Ω)
RF (Ω)
63
111111
23.25
161
2339
62
111110
22.5
174
2326
61
111101
21.75
189
2311
60
111100
21
205
2295
59
111011
20.25
221
2279
58
111010
19.5
239
2261
57
111001
18.75
259
2241
56
111000
18
280
2220
55
110111
17.25
302
2198
54
110110
16.5
325
2175
53
110101
15.75
351
2149
52
110100
15
377
2123
51
110011
14.25
406
2094
50
110010
13.5
436
2064
49
110001
12.75
468
2032
48
110000
12
502
1998
47
101111
11.25
537
1963
46
101110
10.5
575
1925
45
101101
9.75
614
1886
44
101100
9
655
1845
43
101011
8.25
697
1803
42
101010
7.5
742
1758
41
101001
6.75
787
1713
40
101000
6
835
1665
39
100111
5.25
883
1617
38
100110
4.5
933
1567
37
100101
3.75
984
1516
36
100100
3
1036
1464
35
100011
2.25
1089
1411
34
100010
1.5
1142
1358
33
100001
0.75
1196
1304
32
100000
0
1250
1250
31
011111
-0.75
1304
1196
30
011110
-1.5
1358
1142
29
011101
-2.25
1411
1089
28
011100
-3
1464
1036
27
011011
-3.75
1516
984
26
011010
-4.5
1567
933
25
011001
-5.25
1617
883
24
011000
-6
1665
835
23
010111
-6.75
1713
787
22
010110
-7.5
1758
742
21
010101
-8.25
1803
697
20
010100
-9
1845
655
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Product Folder Link(s): TPL8002-25
3
TPL8002-25
SLIS133 – NOVEMBER 2009
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Table 1. Switch Truth Table (continued)
4
DECIMAL
CONTROL
FEDCBA
GAIN/ATTN (dB)
RG (Ω)
RF (Ω)
19
010011
-9.75
1886
614
18
010010
-10.5
1925
575
17
010001
-11.25
1963
537
16
010000
-12
1998
502
15
001111
-12.75
2032
468
14
001110
-13.5
2064
436
13
001101
-14.25
2094
406
12
001100
-15
2123
377
11
001011
-15.75
2149
351
10
001010
-16.5
2175
325
9
001001
-17.25
2198
302
8
001000
-18
2220
280
7
000111
-18.75
2241
259
6
000110
-19.5
2261
239
5
000101
-20.25
2279
221
4
000100
-21
2295
205
3
000011
-21.75
2311
189
2
000010
-22.5
2326
174
1
000001
-23.25
2339
161
0
000000
-24
2352
148
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPL8002-25
TPL8002-25
www.ti.com
SLIS133 – NOVEMBER 2009
ABSOLUTE MAXIMUM RATINGS (1)
(2)
over operating free-air temperature range (unless otherwise noted)
MIN
VDD – VEE
Power supply delta voltage (3)
(3)
MAX
UNIT
10
V
–0.3
5
V
0.3
–5
V
–0.3
VDD + 0.3
V
VEE – 0.3
VDD + 0.3
V
VDD
Positive supply voltage range
VEE
Negative supply voltage range (3)
VIN
Control input voltage range (2)
VI/O
Resistor I/O voltage range (2)
IIK
Control input clamp current
VIN < 0 and VI/O < 0
–18
mA
II/OK
I/O port clamp current
VIN < 0 and VI/O < 0
–18
mA
Tstg
Storage temperature range
85
°C
(1)
(2)
(3)
(4)
(3)
(3) (4)
–40
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
VDD – VEE
Power supply delta voltage
VDD
Positive supply voltage
VEE
Negative supply voltage
VIH
High-level control input voltage
VIL
Low-level control input voltage
VI
Control input voltage
VI/O
Resistor inputs/outputs
TA
Operating free-air temperature
TYP
MAX
UNIT
8
V
2.5
3.6
4
V
–2.5
–3.6
–4
V
VDD × 0.65
V
VDD × 0.35
V
GND
VDD
V
VEE
VDD
V
–40
85
°C
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Product Folder Link(s): TPL8002-25
5
TPL8002-25
SLIS133 – NOVEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS
Dual ±4-V Supply
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
Control inputs
IIN
MIN
TYP
VDD = 4 V, IIN = –18 mA
VDD = 4 V, VIN = VDD or GND
IDD + | IEE |
VDD = 4 V, VEE = –4 V, VIN = VDD or GND, II/O = 0
MAX
UNIT
–1.8
V
±1
μA
100
μA
CIN
Control capacitance (1)
VDD = 4 V, VIN = VDD or GND
3.2
pF
CRG
RG capacitance (1)
VIN = 0 V, frequency = 10 MHz
45
pF
CRF
RF capacitance (1)
VIN = 0 V, frequency = 10 MHz
45
pF
(1)
CW
Wiper capacitance
R
End-to-end resistance
RW
Wiper resistance
INL
Integral nonlinearity
DNL
Differential nonlinearity
(1)
VIN = 0 V, frequency = 10 MHz
45
1.75
2.5
pF
3.25
kΩ
420
Ω
–0.3
0.3
dB
–0.3
0.3
dB
The AC method is a frequency domain measurement. A 10-MHz ac voltage signal of known dc offset and amplitude of 82.5 mV are
applied to the pin under test. The imaginary component of the complex current is measured and used in the equation:
C = Iim / (2 × π × F × VIN) where Iim = imaginary component of input current, VIN = magnitude of input voltage, and F = frequency.
SWITCHING CHARACTERISTICS (1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
tPS
Contol to output step delay
BW
Analog signal bandwidth
(1)
6
TEST CONDITIONS
MIN
TYP
100
For a typical example, see Figure 2
8
MAX
UNIT
ns
MHz
Typical bandwidth shown in Figure 2 supports 6 MHz minimum.
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Product Folder Link(s): TPL8002-25
TPL8002-25
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SLIS133 – NOVEMBER 2009
PARAMETER MEASUREMENT INFORMATION
4V
–4 V
VDD
VEE
Absolute tolerance is used to compare
measured gain versus expected gain.
VIN
Rg
Rsw
Binary Control dBCALCULATED
Vsw
Rf
000000
BW
111111
Control
Circuitry
Position
Decoder
–24 dB
0.75 dB/step
VCTRL
23.25 dB
Absolute tolerance = dBCALCULATED – dBMEASURED
dBMEASURED = –20*LOG((VIN –VSW)/(VIN))
GND
Figure 1. Analog Signal Bandwidth and Absolute Tolerance
TPL8002-25
Rg
Rf
Ci
3.9 pF
–
Rsw
OPA2889
FB
+
Figure 2. Bandwidth Setup
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPL8002-25
7
PACKAGE OPTION ADDENDUM
www.ti.com
20-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPL8002-25PWR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TSSOP
PW
16
2000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
CU NIPDAU
Level-1-260C-UNLIM
(4/5)
-40 to 85
PHY03A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPL8002-25PWR
Package Package Pins
Type Drawing
TSSOP
PW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPL8002-25PWR
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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