Texas Instruments | 12-Bit 500-/550-MSPS Analog-to-Digital Converters (Rev. E) | Datasheet | Texas Instruments 12-Bit 500-/550-MSPS Analog-to-Digital Converters (Rev. E) Datasheet

Texas Instruments 12-Bit 500-/550-MSPS Analog-to-Digital Converters (Rev. E) Datasheet
ADS5463
ADS54RF63
AD
S5
463
www.ti.com ................................................................................................................................................... SLAS515E – NOVEMBER 2006 – REVISED JULY 2009
12-Bit, 500-/550-MSPS Analog-to-Digital Converters
•
•
FEATURES
1
•
•
•
•
•
•
•
•
•
•
23
•
•
12-Bit Resolution
On-Chip Analog Buffer
ADS5463: 500 MSPS
ADS5463 SFDR: 77dBc at 300 MHz fIN
ADS54RF63: 550 MSPS
ADS54RF63 SFDR: 70dBc at 900 MHz fIN
2.3-GHz Input Bandwidth
LVDS-Compatible Outputs
Very Low Latency: 3.5 Clock Cycles
High Analog Input Swing without Damage,
> 10 Vpp Differential-AC Signal
Total Power Dissipation: 2.2 W
80-Pin TQFP PowerPAD™ Package
(14-mm × 14-mm footprint)
Industrial Temperature Range: –40°C to 85°C
Pin-Similar/Compatible to 12-, 13-, and 14-Bit
Family: ADS5440/ADS5444/ADS5474
APPLICATIONS
•
•
•
•
•
•
Test and Measurement Instrumentation
Software-Defined Radio
Data Acquisition
Power Amplifier Linearization
Communication Instrumentation
Radar
DESCRIPTION
The ADS5463/ADS54RF63 is a 12-bit, 500-/550-MSPS analog-to-digital converter (ADC) that operates from both
a 5-V supply and 3.3-V supply, while providing LVDS-compatible digital outputs. This ADC is one of a family of
12-, 13-, and 14-bit ADCs that operate from 210 MSPS to 550 MSPS. The ADS5463/ADS54RF63 input buffer
isolates the internal switching of the onboard track and hold (T&H) from disturbing the signal source while
providing a high-impedance input.
The ADS54RF63 provides superior SFDR compared to the ADS5463 when the analog input frequency exceeds
~350 MHz or if operation up to 550 MSPS is required.
The ADS5463/ADS54RF63 is available in a TQFP-80 PowerPAD™ package. The ADS5463/ADS54RF63 is built
on the Texas Instrument complementary bipolar process (BiCom3) and specified over the full industrial
temperature range (–40°C to 85°C).
VIN
VIN
A1
TH1
+
TH2
S
+
TH3
A2
ADC1
A3
ADC3
–
–
VREF
S
DAC1
ADC2
DAC2
Reference
5
5
4
Digital Error Correction
CLK
CLK
Timing
OVR
OVR
DRY
DRY
D[11:0]
B0061-03
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2009, Texas Instruments Incorporated
ADS5463
ADS54RF63
SLAS515E – NOVEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
(1)
(2)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR (1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS5463
HTQFP-80 (2)
PowerPAD
PFP
–40°C to 85°C
ADS5463I
ADS54RF63
HTQFP-80 (2)
PowerPAD
PFP
–40°C to 85°C
ADS54RF63I
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
ADS5463IPFP
Tray, 96
ADS5463IPFPR
Tape and reel, 1000
ADS54RF63IPFP
Tray, 96
ADS54RF63IPFPR
Tape and reel, 1000
For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet.
Thermal pad size: 6.15 mm × 6.15 mm (min), 7.5 mm × 7.5 mm (maximum), see Thermal Pad Addendum located at the end of the data
sheet.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
ADS5463/ADS54RF63
Supply voltage
AVDD5 to GND
6
AVDD3 to GND
5
DVDD3 to GND
5
AC Signal
AIN, AIN to GND (2)
AIN to AIN
(2)
Voltage difference between pin and ground
Voltage difference between these pins
CLK, CLK to GND
CLK to CLK (2)
Data output to
GND (2)
Voltage difference between pin and ground
Voltage difference between these pins
0.4 to 4.4
DC signal, TJ = 125°C
1.0 to 3.8
AC Signal
-5.2 to 5.2
DC Signal, TJ = 105°C
-4.0 to 4.0
DC signal, TJ = 125°C
-2.8 to 2.8
DC signal, TJ = 105°C
1.1 to 3.7
AC Signal
-3.3 to 3.3
DC signal, TJ = 105°C
-3.3 to 3.3
DC signal, TJ = 125°C
-2.6 to 2.6
LVDS digital outputs
Storage temperature range
ESD, human-body model (HBM)
2
V
0.1 to 4.7
DC signal, TJ = 125°C
Maximum junction temperature (max TJ)
(2)
V
–0.3 to (AVDD5 + 0.3)
Operating temperature range
(1)
V
–0.3 to (AVDD5 + 0.3)
DC signal, TJ = 105°C
AC signal
(2)
UNIT
V
V
–0.3 to (DVDD3 + 0.3)
V
–40 to 85
°C
150
°C
–65 to 150
°C
2
kV
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied. Kirkendall voidings and current density information for calculation of expected lifetime is available upon
request.
Valid when supplies are within recommended operating range.
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THERMAL CHARACTERISTICS (1)
PARAMETER
RθJA (2)
RθJP (3)
(1)
(2)
(3)
TEST CONDITIONS
TYP
Soldered thermal pad, no airflow
23.7
Soldered thermal pad, 150-LFM airflow
17.8
Soldered thermal pad, 250-LFM airflow
16.4
Bottom of package (thermal pad)
2.99
UNIT
°C/W
°C/W
Using 36 thermal vias (6 × 6 array). See PowerPAD Package in the Application Information section.
RθJA is the thermal resistance from the junction to ambient.
RθJP is the thermal resistance from the junction to the thermal pad.
RECOMMENDED OPERATING CONDITIONS
ADS54RF63
MIN
TA
Open free-air temperature
NOM
–40
ADS5463
MAX
MIN
85
–40
NOM
MAX
UNIT
85
°C
SUPPLIES
AVDD5 Analog supply voltage
4.75
5
5.25
4.75
5
5.25
V
AVDD3 Analog supply voltage
3.0
3.3
3.6
3.0
3.3
3.6
V
DVDD3 Output driver supply voltage
3.0
3.3
3.6
3.0
3.3
3.6
V
ANALOG INPUT
VCM
Differential input range
2.2
2.2
Vpp
Input common mode
2.4
2.4
V
10
10
pF
DIGITAL OUTPUT (DRY, DATA, OVR)
Maximum differential output load
CLOCK INPUT (CLK)
CLK input sample rate (sine wave)
40
550
20
500
MSPS
Clock amplitude, differential sine wave, see
Figure 59
0.5
3.5
0.5
3.5
Vpp
60%
40%
Clock duty cycle, see Figure 64
40%
50%
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50%
60%
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ADS54RF63
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ELECTRICAL CHARACTERISTICS
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
ADS5463 sampling rate = 500 MSPS, ADS54RF63 sampling rate = 550 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3
= 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input, and 3-VPP differential clock, unless otherwise noted
PARAMETER
TEST CONDITIONS
Resolution
ADS54RF63
MIN
TYP
ADS5463
MAX
MIN
TYP
MAX
UNIT
12
12
Bits
2.2
2.2
VPP
ANALOG INPUTS
Differential input
VCM
CMRR
Common-mode
voltage
Self-biased
2.4
2.4
V
Input resistance
To VCM
500
500
Ω
Input capacitance
To ground (un-soldered
package)
2.3
2.3
pF
Input bandwidth
(–3 dB)
2.3
2.3
GHz
Common-mode
rejection ratio
Common mode signal = 10 MHz
90
90
dB
1000
1000
Ω
CLOCK INPUTS
Input resistance
To internal common-mode
Input capacitance
To ground (un-soldered
package)
1.5
1.5
pF
Common mode
Internally generated
2.4
2.4
V
2.4
2.4
V
INTERNAL REFERENCE VOLTAGE
VREF
4
Reference voltage
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
ADS5463 sampling rate = 500 MSPS, ADS54RF63 sampling rate = 550 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3
= 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input, and 3-VPP differential clock, unless otherwise noted
PARAMETER
TEST CONDITIONS
ADS54RF63
MIN
TYP
ADS5463
MAX
MIN
TYP
MAX
UNIT
DYNAMIC ACCURACY
No missing codes
DNL
Differential
linearity error
INL
Integral linearity
error
Specified
Specified
fIN = 10 MHz
–0.95
±0.5
0.95
–0.95
±0.25
0.95
LSB
500MSPS, fIN = 10 MHz
–2.5
±0.7
2.5
–2.5
+0.8/–0.3
2.5
LSB
550MSPS, fIN = 10 MHz
–4.5
±1.5
4.5
Offset error
–11
Offset
temperature
coefficient
11
NA
–11
0.0005
Gain error
–5
Gain temperature
coefficient
LSB
11
0.0005
5
–0.02
–5
mV
mV/°C
5
–0.02
%FS
%FS/°C
POWER SUPPLY
IAVDD5
5-V analog supply
current
IAVDD3
3.3-V analog
supply current
310
340
300
330
mA
140
155
125
138
mA
82
88
82
88
mA
Total power
dissipation
2.25
2.5
2.18
2.4
W
Power-up time
200
200
µs
85
85
dB
VIN = full scale, fIN = 10 MHz
3.3-V digital
IDVDD3 supply current
(includes LVDS)
PSRR
Power-supply
rejection ratio
Without 0.1-µF board supply
capacitors, with 100-kHz supply
noise
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ADS54RF63
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
ADS5463 sampling rate = 500 MSPS, ADS54RF63 sampling rate = 550 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3
= 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input, and 3-VPP differential clock, unless otherwise noted
PARAMETER
TEST CONDITIONS
ADS54RF63
MIN
TYP
ADS5463
MAX
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS
CLK
Maximum clock
frequency
RMS idle-channel noise
550
500
MHz
Inputs tied to common-mode
0.8
0.7
fIN = 10 MHz
64.7
65.4
fIN = 70 MHz
64.6
fIN = 100 MHz
64.6
fIN = 230 MHz
64.4
LSB
SNR, Signal-to-Noise Ratio
fS = 500MSPS
SNR
fS = 550MSPS
fIN = 300 MHz
62.5
65.4
63.5
65.3
65.1
64.3
63
65
fIN = 450 MHz
64.1
64.6
fIN = 650 MHz
63.5
63.9
fIN = 900 MHz
62.5
62.6
fIN = 1.3 GHz
61
59.3
fIN = 100 MHz
62.6
NA
61.9
NA
59.3
NA
fIN = 10 MHz
85
85
fIN = 70 MHz
83
fIN = 100 MHz
84
fIN = 230 MHz
81
fIN = 450 MHz
59
fIN = 1.3 GHz
dBFS
SFDR, Spurious-Free Dynamic Range
fS = 500MSPS
SFDR
fS = 550MSPS
fIN = 300 MHz
82
78
78
64
77
fIN = 450 MHz
80
75
fIN = 650 MHz
75
65
fIN = 900 MHz
70
56
fIN = 1.3 GHz
58
45
fIN = 100 MHz
76
NA
75
NA
57
NA
fIN = 450 MHz
fIN = 1.3 GHz
6
64
82
70
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62
dBc
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
ADS5463 sampling rate = 500 MSPS, ADS54RF63 sampling rate = 550 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3
= 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input, and 3-VPP differential clock, unless otherwise noted
PARAMETER
TEST CONDITIONS
ADS54RF63
MIN
TYP
ADS5463
MAX
MIN
TYP
MAX
UNIT
HD2, Second Harmonic
fS = 500MSPS
HD2
fS = 550MSPS
fIN = 10 MHz
87
fIN = 70 MHz
87
fIN = 100 MHz
85
fIN = 230 MHz
83
fIN = 300 MHz
64
79
87
82
70
80
81
64
77
fIN = 450 MHz
81
80
fIN = 650 MHz
75
77
fIN = 900 MHz
70
66
fIN = 1.3 GHz
58
50
fIN = 100 MHz
84
NA
78
NA
fIN = 1.3 GHz
63
NA
fIN = 10 MHz
90
85
fIN = 70 MHz
92
90
fIN = 100 MHz
89
fIN = 230 MHz
85
fIN = 450 MHz
62
dBc
HD3, Third Harmonic
fS = 500MSPS
HD3
fS = 550MSPS
fIN = 300 MHz
64
83
70
87
90
64
80
fIN = 450 MHz
90
75
fIN = 650 MHz
76
65
fIN = 900 MHz
78
56
fIN = 1.3 GHz
58
45
fIN = 100 MHz
76
NA
75
NA
57
NA
fIN = 10 MHz
86
86
fIN = 70 MHz
86
86
fIN = 100 MHz
86
86
fIN = 230 MHz
83
77
fIN = 300 MHz
82
81
fIN = 450 MHz
86
86
fIN = 650 MHz
85
85
fIN = 900 MHz
82
78
fIN = 1.3 GHz
78
67
fIN = 100 MHz
82
NA
fIN = 450 MHz
81
NA
fIN = 1.3 GHz
74
NA
fIN = 450 MHz
62
fIN = 1.3 GHz
dBc
Worst Harmonic/Spur (other than HD2 and HD3)
fS = 500MSPS
Worst
nonHD2/3
fS = 550MSPS
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dBc
7
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ADS54RF63
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
ADS5463 sampling rate = 500 MSPS, ADS54RF63 sampling rate = 550 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3
= 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input, and 3-VPP differential clock, unless otherwise noted
PARAMETER
TEST CONDITIONS
ADS54RF63
MIN
TYP
ADS5463
MAX
MIN
TYP
MAX
UNIT
THD, Total Harmonic Distortion
fS = 500MSPS
THD
fS = 550MSPS
fIN = 10 MHz
82
80
fIN = 70 MHz
82
79
fIN = 100 MHz
80
77
fIN = 230 MHz
78
75
fIN = 300 MHz
76
73
fIN = 450 MHz
77
73
fIN = 650 MHz
69
64
fIN = 900 MHz
64
55
fIN = 1.3 GHz
56
44
fIN = 100 MHz
74
NA
fIN = 450 MHz
72
NA
fIN = 1.3 GHz
56
NA
fIN = 10 MHz
63.6
64.2
fIN = 70 MHz
63.5
64.2
fIN = 100 MHz
63.5
fIN = 230 MHz
63.2
63.7
63.1
63.5
fIN = 450 MHz
62.9
63.1
fIN = 650 MHz
61.5
60.5
fIN = 900 MHz
59.6
54.4
fIN = 1.3 GHz
54.4
44.1
fIN = 100 MHz
61.3
NA
60.1
NA
54
NA
dBc
SINAD, Signal-to-Noise and Distortion
fS = 500MSPS
SINAD
fS = 550MSPS
fIN = 300 MHz
60
fIN = 450 MHz
57
fIN = 1.3 GHz
ENOB, Effective Number of Bits (from SINAD in dBc)
fS = 500MSPS
ENOB
fS = 550MSPS
(1)
8
64.1
10.3
10.4
10.4
fIN = 900 MHz
9.6
8.7
fIN = 1.3 GHz
8.7
7
9.7
NA
8.7
NA
fIN = 1.3 GHz
9.67
10
10.2
fIN = 450 MHz
dBc
(1)
fIN = 100 MHz
fIN = 300 MHz
62
9.18
Bits
ENOB = [SINAD(dBc) - 1.76] / 6.02
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
ADS5463 sampling rate = 500 MSPS, ADS54RF63 sampling rate = 550 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3
= 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input, and 3-VPP differential clock, unless otherwise noted
PARAMETER
ADS54RF63
TEST CONDITIONS
MIN
TYP
ADS5463
MAX
MIN
TYP
UNIT
MAX
Two-Tone SFDR
fS = 500MSPS
2-tone
SFDR
fS = 550MSPS
fIN1 = 65 MHz, fIN2 = 70 MHz,
each tone at –7 dBFS
90
90
fIN1 = 65 MHz, fIN2 = 70 MHz,
each tone at –16 dBFS
90
89
fIN1 = 350 MHz, fIN2 = 355 MHz,
each tone at –7 dBFS
90
82
fIN1 = 350 MHz, fIN2 = 355 MHz,
each tone at –16 dBFS
90
89
fIN1 = 397.5 MHz, fIN2 = 402.5
MHz, each tone at –7 dBFS
90
fIN1 = 647.5 MHz, fIN2 = 652.5
MHz, each tone at –7 dBFS
84
dBFS
NA
NA
LVDS DIGITAL OUTPUTS
VOD
Differential output
voltage (±)
VOC
Common-mode
output voltage
247
350
1.125
454
247
1.375
1.125
350
454
mV
1.375
V
Sample
N–1
N+4
N+2
ta
N
N+1
N+3
tCLKH
N+5
tCLKL
CLK
CLK
Latency = 3.5 Clock Cycles
tDRY
DRY
(1)
DRY
tDATA
D[11:0], OVR
N–1
N
N+1
D[11:0], OVR
T0158-01
(1)
Polarity of DRY is undetermined. For further information, see the Digital Outputs section.
Figure 1. Timing Diagram
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TIMING CHARACTERISTICS (1)
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
sampling rate = maximum rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential
clock (unless otherwise noted)
PARAMETER
ta
TEST CONDITIONS
ADS54RF63
MIN
TYP
ADS5463
MAX
MIN
TYP
MAX
UNIT
Aperture delay
200
200
ps
Aperture jitter, rms
150
150
fs
Latency
3.5
tCLK
Clock period
1.8181
tCLKH
Clock pulse duration, high
tCLKL
Clock pulse duration, low
(2)
3.5
50
2
cycles
50
ns
Assumes min 40%
duty cycle
0.727
0.8
ns
0.727
0.8
ns
tDRY
CLK to DRY delay
Zero crossing
1350
1750
950
1600
ps
tDATA
CLK to DATA/OVR
delay (2)
Zero crossing
1100
2000
750
2100
ps
tSKEW
DATA to DRY skew
tDATA – tDRY
–250
250
–350
650
ps
tRISE
DRY/DATA/OVR rise time
500
500
ps
tFALL
DRY/DATA/OVR fall time
500
500
ps
(1)
(2)
10
0
0
Timing parameters are specified by design or characterization, but not production tested. <10pF load on each output pin.
DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the overall propagation
delay.
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PIN CONFIGURATION
D4
D5
D4
D5
DGND
D6
DVDD3
D7
D6
D8
D7
D9
D8
D10
D9
D11 (MSB)
D10
DRY
D11 (MSB)
DRY
PFP PACKAGE
(TOP VIEW)
DVDD3
1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
DGND
2
59
D3
AVDD5
3
4
58
57
D2
NC
5
56
D1
VREF
6
55
D1
AGND
54
D0
AVDD5
7
8
53
D0
AGND
9
52
DGND
CLK
10
51
DVDD3
CLK
11
50
NC
NC
D3
D2
AGND
12
49
NC
AVDD5
13
48
NC
AVDD5
14
47
NC
AGND
15
46
NC
AIN
16
45
NC
AIN
17
44
NC
AGND
18
43
NC
AVDD5
19
42
OVR
AGND
20
41
OVR
AGND
AVDD3
AGND
AGND
AVDD3
AVDD3
AGND
AGND
RESERVED
AGND
AVDD5
AGND
RESERVED
AGND
AVDD5
AGND
AVDD5
AGND
AVDD5
AVDD5
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P0027-02
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Table 1. PIN FUNCTIONS
PIN
NAME
DESCRIPTION
NO.
AIN
16
Differential input signal (positive)
AIN
17
Differential input signal (negative)
AVDD5
3, 8, 13, 14, 19, 21,
23, 25, 27, 31
AVDD3
35, 37, 39
Analog power supply (3.3 V) (Suggestion for ≤250 MSPS: leave option to connect to 5 V for
ADS5440/4 13-bit compatibility)
DVDD3
1, 51, 66
Output driver power supply (3.3 V)
AGND
7, 9, 12, 15, 18, 20,
22, 24, 26, 28, 30,
32, 34, 36, 38, 40
(Power Pad)
DGND
(81)
2, 52, 65
CLK
CLK
Analog ground
Power pad for thermal relief, also analog ground
Digital ground
10
Differential input clock (positive). Conversion is initiated on rising edge.
11
Differential input clock (negative)
D0–D11
54, 56, 58, 60, 62,
64, 68, 70, 72, 74,
76, 78
D0–D11
53, 55, 57, 59, 61,
63, 67, 69, 71, 73,
75, 77
DRY, DRY
Analog power supply (5 V)
80, 79
LVDS digital output pairs (D0/D0 is LSB pair. D11/D11 is MSB pair.)
Data ready LVDS output pair
4, 5, 43–50
No connect (4 and 5 should be left floating, 43–50 are possible future bit additions for this pinout
and therefore can be connected to a digital bus or left floating)
OVR, OVR
42, 41
Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale
range.
RESERVED
29, 33
Pin 29 is reserved for possible future Vcm output for this pinout, like ADS5474; pin 33 is reserved for
possible future power-down control pin for this pinout, like ADS5474.
NC
VREF
12
6
Reference voltage input/output (2.4 V nominal). Connect 0.1-µF capacitor from VREF to AGND.
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ADS5463 TYPICAL CHARACTERISTICS
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
SPECTRAL PERFORMANCE
FFT FOR 30-MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 100-MHz INPUT SIGNAL
0
0
SFDR = 82.4 dBc
SINAD = 65.3 dBFS
SNR = 65.4 dBFS
THD = 79 dBc
−20
−20
−40
−40
Amplitude − dB
Amplitude − dB
SFDR = 80.6 dBc
SINAD = 65.1 dBFS
SNR = 65.3 dBFS
THD = 77.1 dBc
−60
−60
−80
−80
−100
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
25
50
f − Frequency − MHz
75 100 125 150 175 200 225 250
f − Frequency − MHz
G001
G002
Figure 2.
Figure 3.
SPECTRAL PERFORMANCE
FFT FOR 230-MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 300-MHz INPUT SIGNAL
0
0
SFDR = 77.5 dBc
SINAD = 64.7 dBFS
SNR = 65.2 dBFS
THD = 73.7 dBc
−20
−20
−40
Amplitude − dB
−40
Amplitude − dB
SFDR = 77.1 dBc
SINAD = 64.5 dBFS
SNR = 65 dBFS
THD = 73.1 dBc
−60
−60
−80
−80
−100
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
25
50
f − Frequency − MHz
75 100 125 150 175 200 225 250
f − Frequency − MHz
G003
Figure 4.
G004
Figure 5.
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ADS5463 TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
SPECTRAL PERFORMANCE
FFT FOR 450-MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 650-MHz INPUT SIGNAL
0
0
SFDR = 74.3 dBc
SINAD = 64.3 dBFS
SNR = 64.8 dBFS
THD = 73 dBc
−20
−20
−40
Amplitude − dB
−40
Amplitude − dB
SFDR = 65.5 dBc
SINAD = 61.8 dBFS
SNR = 64 dBFS
THD = 64.9 dBc
−60
−60
−80
−80
−100
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
25
50
f − Frequency − MHz
75 100 125 150 175 200 225 250
f − Frequency − MHz
G005
G006
Figure 6.
Figure 7.
SPECTRAL PERFORMANCE
FFT FOR 900-MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 1,300-MHz INPUT SIGNAL
0
0
SFDR = 55.5 dBc
SINAD = 55.3 dBFS
SNR = 62.8 dBFS
THD = 55.1 dBc
−20
−20
−40
−40
Amplitude − dB
Amplitude − dB
SFDR = 45.6 dBc
SINAD = 45.1 dBFS
SNR = 59.3 dBFS
THD = 44.3 dBc
−60
−60
−80
−80
−100
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
25
50
f − Frequency − MHz
75 100 125 150 175 200 225 250
f − Frequency − MHz
G007
G008
Figure 8.
14
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Figure 9.
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ADS5463 TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
TWO-TONE INTERMODULATION DISTORTION
(FFT FOR 65.1 MHz AND 70.1 MHz AT –7 dBFS)
TWO-TONE INTERMODULATION DISTORTION
(FFT FOR 65.1 MHz AND 70.1 MHz AT –16 dBFS)
0
0
fIN1 = 65.1 MHz, −7 dBFS
fIN2 = 70.1 MHz, −7 dBFS
IMD3 = 90.5 dBFS
SFDR = 90.3 dBFS
−20
−20
−40
Amplitude − dB
−40
Amplitude − dB
fIN1 = 65.1 MHz, −16 dBFS
fIN2 = 70.1 MHz, −16 dBFS
IMD3 = 96.1 dBFS
SFDR = 88.8 dBFS
−60
−60
−80
−80
−100
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
25
50
f − Frequency − MHz
75 100 125 150 175 200 225 250
f − Frequency − MHz
G009
G010
Figure 10.
Figure 11.
TWO-TONE INTERMODULATION DISTORTION
(FFT FOR 350 MHz AND 355 MHz AT –7 dBFS)
TWO-TONE INTERMODULATION DISTORTION
(FFT FOR 350 MHz AND 355 MHz AT –16 dBFS)
0
0
fIN1 = 350 MHz, −7 dBFS
fIN2 = 355 MHz, −7 dBFS
IMD3 = 81.6 dBFS
SFDR = 81.6 dBFS
−20
−20
−40
−40
Amplitude − dB
Amplitude − dB
fIN1 = 350 MHz, −16 dBFS
fIN2 = 355 MHz, −16 dBFS
IMD3 = 101.1 dBFS
SFDR = 88.9 dBFS
−60
−60
−80
−80
−100
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
25
50
f − Frequency − MHz
75 100 125 150 175 200 225 250
f − Frequency − MHz
G011
Figure 12.
G012
Figure 13.
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ADS5463 TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
0.3
1.0
fS = 500 MSPS
fIN = 10 MHz
INL − Integral Nonlinearity − LSB
0.2
Differential Nonlinearity − LSB
fS = 500 MSPS
fIN = 10 MHz
0.8
0.1
0.0
−0.1
−0.2
0.6
0.4
0.2
0.0
−0.2
−0.4
−0.6
−0.8
−0.3
−1.0
50
550
1050 1550 2050 2550 3050 3550 4050
50
550
1050 1550 2050 2550 3050 3550 4050
Code
Code
G014
G015
Figure 14.
Figure 15.
AC PERFORMANCE
vs
INPUT AMPLITUDE (100-MHz INPUT SIGNAL)
AC PERFORMANCE
vs
INPUT AMPLITUDE (300-MHz INPUT SIGNAL)
120
120
AC Performance − dB
80
SFDR (dBFS)
100
80
SNR (dBFS)
AC Performance − dB
100
60
40
SFDR (dBc)
20
0
SNR (dBc)
−20
SNR (dBFS)
60
40
SFDR (dBc)
20
0
SNR (dBc)
−20
−40
−60
−120
SFDR (dBFS)
−40
fS = 500 MSPS
fIN = 100.3 MHz
−100
−80
−60
−40
−20
−60
−120
0
fS = 500 MSPS
fIN = 301.1 MHz
−100
Input Amplitude − dBFS
−80
−60
G017
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−20
0
G018
Figure 16.
16
−40
Input Amplitude − dBFS
Figure 17.
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www.ti.com ................................................................................................................................................... SLAS515E – NOVEMBER 2006 – REVISED JULY 2009
ADS5463 TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
AC PERFORMANCE
vs
INPUT AMPLITUDE (350-MHz AND 355-MHz TWO-TONE
INPUT SIGNAL)
100
AC Performance − dB
SNR (dBFS)
60
Worst Spur (dBc)
40
20
SNR (dBc)
0
fS = 500 MSPS
fIN1 = 350 MHz
fIN2 = 355 MHz
−20
−80
−70
−60
−50
−40
−30
−20
−10
80
SFDR − Spurious-Free Dynamic Range − dBc
Worst Spur (dBFS)
80
SFDR
vs
AVDD5 ACROSS TEMPERATURE
75
70
TA = 0°C
TA = 40°C
65
TA = 65°C
TA = 25°C
TA = −40°C
TA = 85°C
60
fS = 500 MSPS
fIN = 100 MHz
TA = 100°C
55
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
0
AVDD − Supply Voltage − V
Input Amplitude − dBFS
G026
G020
Figure 18.
Figure 19.
SNR
vs
AVDD5 ACROSS TEMPERATURE
SFDR
vs
AVDD3 ACROSS TEMPERATURE
80
67.0
SFDR − Spurious-Free Dynamic Range − dBc
SNR − Signal-to-Noise Ratio − dBFS
66.5
TA = 40°C
fS = 500 MSPS
fIN = 100 MHz
TA = −40°C
66.0
TA = 0°C
65.5
TA = 25°C
65.0
TA = 40°C
64.5
TA = 65°C
64.0
TA = 85°C
TA = 100°C
63.5
63.0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
AVDD − Supply Voltage − V
TA = 25°C
78
TA = 0°C
76
TA = 65°C
74
72
TA = 85°C
TA = 100°C
70
TA = −40°C
68
2.7
2.9
G027
Figure 20.
fS = 500 MSPS
fIN = 100 MHz
3.1
3.3
3.5
AVDD − Supply Voltage − V
3.7
G028
Figure 21.
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ADS5463 TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
SNR
vs
AVDD3 ACROSS TEMPERATURE
SFDR
vs
DVDD3 ACROSS TEMPERATURE
80
66.0
SFDR − Spurious-Free Dynamic Range − dBc
SNR − Signal-to-Noise Ratio − dBFS
66.5
TA = −40°C
TA = 0°C
65.5
TA = 25°C
TA = 40°C
65.0
TA = 65°C
64.5
TA = 85°C
64.0
fS = 500 MSPS
fIN = 100 MHz
63.5
2.7
2.9
TA = 100°C
3.1
3.3
3.5
TA = 40°C
TA = 0°C
76
TA = 65°C
74
TA = 85°C
72
TA = −40°C
70
TA = 100°C
fS = 500 MSPS
fIN = 100 MHz
68
2.7
3.7
AVDD − Supply Voltage − V
TA = 25°C
78
2.9
3.1
3.3
DVDD − Supply Voltage − V
G029
Figure 22.
3.5
3.7
G030
Figure 23.
SNR
vs
DVDD3 ACROSS TEMPERATURE
SNR − Signal-to-Noise Ratio − dBFS
66.5
fS = 500 MSPS
fIN = 100 MHz
66.0
TA = −40°C
TA = 0°C
65.5
TA = 25°C
TA = 40°C
65.0
TA = 65°C
64.5
TA = 85°C
64.0
TA = 100°C
63.5
2.7
2.9
3.1
3.3
3.5
3.7
DVDD − Supply Voltage − V
G031
Figure 24.
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ADS5463 TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
SNR vs INPUT FREQUENCY AND SAMPLING FREQUENCY (ADS5463 Only)
550
63
64
61
62
64
65
63
fS – Sampling Frequency – MHz
500
450
65
64
400
63
62
350
300
65
64
63
62
250
61
200
58
59
65
170
10
100
300
200
400
500
600
700
800
900
1000
64
65
66
67
fIN – Input Frequency – MHz
58
57
61
60
59
62
63
SNR – dBFS
M0048-09
Figure 25.
SFDR vs INPUT FREQUENCY AND SAMPLING FREQUENCY (ADS5463 Only)
550
70
75
80
500
fS – Sampling Frequency – MHz
60
75
55
65
80
80
450
400
70
75
350
65
80
55
60
80
300
85
250
70
75
85
60
55
200
170
10
65
80
100
300
200
400
500
600
700
800
900
1000
fIN – Input Frequency – MHz
45
50
60
55
65
70
75
SFDR – dBc
80
85
90
M0049-09
Figure 26.
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ADS54RF63 TYPICAL CHARACTERISTICS
Typical plots at TA = 25°C, sampling rate = 550 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
SPECTRAL PERFORMANCE
FFT FOR 450-MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 650-MHz INPUT SIGNAL
0
0
SFDR = 79.4 dBc
SINAD = 63.1 dBFS
SNR = 63.2 dBFS
THD = 76.6 dBc
−20
−20
−40
Amplitude − dB
−40
Amplitude − dB
SFDR = 78.2 dBc
SINAD = 63 dBFS
SNR = 63.2 dBFS
THD = 76.5 dBc
−60
−60
−80
−80
−100
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250 275
0
25
50
f − Frequency − MHz
75 100 125 150 175 200 225 250 275
f − Frequency − MHz
G034
G035
Figure 27.
Figure 28.
SPECTRAL PERFORMANCE
FFT FOR 900-MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 1,300-MHz INPUT SIGNAL
0
0
SFDR = 71.6 dBc
SINAD = 61.3 dBFS
SNR = 62 dBFS
THD = 68.7 dBc
−20
−20
−40
Amplitude − dB
−40
Amplitude − dB
SFDR = 52.7 dBc
SINAD = 52.2 dBFS
SNR = 60.4 dBFS
THD = 51.9 dBc
−60
−60
−80
−80
−100
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250 275
0
25
50
75 100 125 150 175 200 225 250 275
f − Frequency − MHz
f − Frequency − MHz
G037
G036
Figure 29.
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Figure 30.
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ADS54RF63 TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 550 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
TWO-TONE INTERMODULATION DISTORTION
FFT FOR 397.5 MHz AND 402.5 MHz AT –7 dBFS
TWO-TONE INTERMODULATION DISTORTION
FFT FOR 647.5 MHz AND 652.5 MHz AT –7 dBFS
0
0
fIN1 = 397.5 MHz, −7 dBFS
fIN2 = 402.5 MHz, −7 dBFS
IMD3 = 87.4 dBFS
SFDR = 83.7 dBc
−20
−20
−40
Amplitude − dB
−40
Amplitude − dB
fIN1 = 647.5 MHz, −7 dBFS
fIN2 = 652.5 MHz, −7 dBFS
IMD3 = 77 dBFS
SFDR = 77 dBc
−60
−60
−80
−80
−100
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250 275
0
25
50
f − Frequency − MHz
75 100 125 150 175 200 225 250 275
f − Frequency − MHz
G038
G039
Figure 31.
Figure 32.
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
0.3
1.0
fS = 550 MSPS
fIN = 10 MHz
INL − Integral Nonlinearity − LSB
0.2
Differential Nonlinearity − LSB
fS = 550 MSPS
fIN = 10 MHz
0.8
0.1
0.0
−0.1
−0.2
0.6
0.4
0.2
0.0
−0.2
−0.4
−0.6
−0.8
−0.3
−1.0
0
512
1024 1536 2048 2560 3072 3584 4096
0
512
1024 1536 2048 2560 3072 3584 4096
Code
Code
G041
G040
Figure 33.
Figure 34.
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ADS54RF63 TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 550 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
AC PERFORMANCE
vs
INPUT AMPLITUDE (397.5-MHz AND 402.5-MHz TWO-TONE
INPUT SIGNAL)
130
AC PERFORMANCE
vs
INPUT AMPLITUDE (647.5-MHz AND 652.5-MHz TWO-TONE
INPUT SIGNAL)
130
2F2−F1 (dBFS)
2F1−F2 (dBFS)
90
2F1−F2 (dBFS)
110
2F2−F1 (dBFS)
AC Performance − dB
AC Performance − dB
110
Worst Spur (dBFS)
70
Worst Spur (dBc)
50
30
10
−80
−60
−50
−40
−30
−20
−10
Worst Spur (dBFS)
70
Worst Spur (dBc)
50
30
fS = 550 MSPS
fIN1 = 397.5 MHz
fIN2 = 402.5 MHz
−70
90
10
−80
0
fS = 550 MSPS
fIN1 = 647.5 MHz
fIN2 = 652.5 MHz
−70
−60
Input Amplitude − dBFS
−50
−40
−30
−20
−10
G043
G044
Figure 35.
Figure 36.
SFDR
vs
AVDD5 ACROSS TEMPERATURE
SNR
vs
AVDD5 ACROSS TEMPERATURE
66.0
TA = 85°C
TA = 55°C
65.5
SNR − Signal-to-Noise Ratio − dBFS
SFDR − Spurious-Free Dynamic Range − dBc
90
85
TA = 25°C
80
75
TA = 0°C
TA = −20°C
70
TA = −40°C
65
TA = 100°C
AVDD − Supply Voltage − V
fS = 550 MSPS
fIN = 100 MHz
65.0
TA = −20°C
64.5
TA = 25°C
64.0
TA = 55°C
TA = 85°C
63.5
63.0
TA = 100°C
62.0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
AVDD − Supply Voltage − V
G045
Figure 37.
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TA = 0°C
TA = −40°C
62.5
fS = 550 MSPS
fIN = 100 MHz
60
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
22
0
Input Amplitude − dBFS
G046
Figure 38.
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ADS54RF63 TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 550 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
SFDR
vs
AVDD3 ACROSS TEMPERATURE
SNR
vs
AVDD3 ACROSS TEMPERATURE
66.0
TA = 0°C
TA = 85°C
82
TA = 100°C
80
TA = 55°C
TA = 25°C
78
76
TA = 0°C
TA = −20°C
74
TA = −40°C
72
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
AVDD − Supply Voltage − V
63.0
TA = 100°C
fS = 550 MSPS
fIN = 100 MHz
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
G047
Figure 40.
SFDR
vs
DVDD3 ACROSS TEMPERATURE
SNR
vs
DVDD3 ACROSS TEMPERATURE
3.6
G048
66.0
TA = 85°C
TA = 55°C
81
TA = 100°C
79
TA = 25°C
78
TA = −40°C
77
TA = 0°C
TA = −20°C
74
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
TA = −40°C
65.0
64.5
TA = −20°C
64.0
TA = 25°C
TA = 55°C
TA = 85°C
63.5
63.0
62.5
fS = 550 MSPS
fIN = 100 MHz
DVDD − Supply Voltage − V
TA = 0°C
65.5
SNR − Signal-to-Noise Ratio − dBFS
SFDR − Spurious-Free Dynamic Range − dBc
TA = 85°C
63.5
AVDD − Supply Voltage − V
82
75
TA = 55°C
64.0
Figure 39.
83
76
TA = 25°C
64.5
62.0
2.7
3.6
84
80
65.0
62.5
fS = 550 MSPS
fIN = 100 MHz
TA = −20°C
TA = −40°C
65.5
SNR − Signal-to-Noise Ratio − dBFS
SFDR − Spurious-Free Dynamic Range − dBc
84
TA = 100°C
fS = 550 MSPS
fIN = 100 MHz
62.0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
DVDD − Supply Voltage − V
G049
Figure 41.
G050
Figure 42.
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ADS54RF63 TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 550 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
SNR vs INPUT FREQUENCY AND SAMPLING FREQUENCY (ADS54RF63 Only)
600
62
60
63
61
58
60
64
fS – Sampling Frequency – MHz
500
59
62
63
400
60
61
59
300
64
58
200
63
62
59
60
61
57
64
100
200
600
400
59
60
61
62
63
40
10
56
58
800
1000
57
1200
1400
56
1600
1800
55
54
2000 2100
fIN – Input Frequency – MHz
52
56
54
58
60
62
64
SNR – dBFS
M0048-21
Figure 43.
SFDR vs INPUT FREQUENCY AND SAMPLING FREQUENCY (ADS54RF63 Only)
600
60
70
80
500
fS – Sampling Frequency – MHz
55
75
75
70
65
75
65
50
45
80
80
85
400
55
45
60
85
50
300
70
85
200
80
75
100
55
75
80
40
10
65
85
200
400
70
50
45
60
75
600
800
1000
1200
1400
1600
1800
2000 2100
fIN – Input Frequency – MHz
40
50
60
70
80
SFDR – dBc
90
M0049-21
Figure 44.
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ADS5463 AND ADS54RF63 TYPICAL CHARACTERISTICS
Typical plots at TA = 25°C, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock,
(unless otherwise noted)
NORMALIZED GAIN RESPONSE
vs
INPUT FREQUENCY
NOISE HISTOGRAM WITH INPUTS SHORTED
3
60
55
fS = 500 MSPS
0
−3
45
ADS5463
ADS54RF63
Percentage − %
Normalized Gain Response − dB
50
−6
−9
−12
40
35
30
25
20
−15
−18
−21
10M
15
10
fS= 500 MSPS
AIN = ±0.4 VPP
5
0
100M
1G
5G
fI − Input Frequency − Hz
2050
2049
2048
2047
2046
Code Number
G013
G016
Figure 45.
Figure 46.
CMRR
vs
COMMON-MODE INPUT FREQUENCY
CMRR − Common-Mode Rejection Ratio − dB
0
fS = 500 MSPS
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0.1
1
10
100
1k
10k
Common-Mode Input Frequency − MHz
G033
Figure 47.
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APPLICATION INFORMATION
Theory of Operation
The ADS5463/ADS54RF63 is a 12-bit, 500/550-MSPS, monolithic pipeline ADC. Its bipolar analog core operates
from 5-V and 3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs. The
conversion process is initiated by the rising edge of the external input clock. At that instant, the differential input
signal is captured by the input track-and-hold (T&H), and the input sample is sequentially converted by a series
of lower resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the
falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process
results in a data latency of 3.5 clock cycles, after which the output data is available as a 12-bit parallel word,
coded in offset binary format.
The ADS5463 and ADS54RF63 are identical in the way they are used on a board. They differ in their maximum
sample rate and spectral performance versus frequency. A good study of the contour plots in Figure 25,
Figure 26, Figure 43, and Figure 44 demonstrate the spectral differences. The digital output characteristics are
the same except the ADS54RF63 has less restrictive timing parameters.
Input Configuration
The analog input for the ADS5463/ADS54RF63 consists of an analog pseudo-differential buffer followed by a
bipolar transistor track-and-hold (see Figure 48). The analog buffer isolates the source driving the input of the
ADC from any internal switching and presents a high impedance to drive at high input frequencies, as compared
to an ADC without a buffered input. The input common mode is set internally through a 500-Ω resistor connected
from 2.4 V to each of the inputs. This results in a differential input impedance of 1 kΩ. The 0.5 pF of parasitic
package capacitance is before soldering.
ADS5463/5474/54RF63
AVDD5
~ 2.5 nH Bond Wire
Buffer
AIN
~ 200 fF
Bond Pad
~ 0.5 pF
Package
500 W
GND
1.6 pF
VCM
AVDD5
1.6 pF
500 W
~ 2.5 nH Bond Wire
GND
AIN
~ 0.5 pF
Package
~ 200 fF
Bond Pad
Buffer
GND
S0293-01
Figure 48. Analog Input Equivalent Circuit (unsoldered)
For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swing
symmetrically between 2.4 V + 0.55 V and 2.4 V – 0.55 V. This means that each input has a maximum signal
swing of 1.1 VPP for a total differential input signal swing of 2.2 VPP. Operation below 2.2 VPP is allowable, with
the characteristics of performance versus input amplitude demonstrated in Figure 16 and Figure 17. For
instance, for performance at 1.1 VPP rather than 2.2 VPP, see the SNR and SFDR at -6 dBFS (0 dBFS = 2.2 VPP).
The maximum swing is determined by the internal reference voltage generator, eliminating the need for any
external circuitry for this purpose.
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The ADS5463/ADS54RF63 obtains optimum performance when the analog inputs are driven differentially. The
circuit in Figure 49 shows one possible configuration using an RF transformer with termination either on the
primary or on the secondary of the transformer. In addition, the evaluation module is configured with two
back-to-back transformers, which also demonstrates good performance. If voltage gain is required, a step-up
transformer can be used.
Z0
50 W
R0
50 W
AIN
R
200 W
AC Signal
Source
ADS5463
AIN
Mini-Circuits
JTX-4-10T
S0176-03
Figure 49. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer
In addition to the transformer configurations, an RF gain-block amplifier, such as the Texas Instruments
THS9001, can also be used for high-input-frequency applications. For large voltage gains at intermediate
frequencies in the 50-MHz – 350-MHz range, the configuration shown in Figure 50 can be used. The component
values can be tuned for different intermediate frequencies. The example shown is located on the evaluation
module and is tuned for an IF of 170 MHz. More information regarding this configuration can be found in the
ADS5463 EVM User Guide (SLAU194) and the THS9001 50 MHz to 350 MHz Cascadeable Amplifier data sheet
(SLOS426).
1000 pF
VIN
1000 pF
AIN
THS9001
50 W
18 mH
39 pF
ADS5463
50 W
VIN
0.1 mF
AIN
THS9001
1000 pF
1000 pF
S0177-03
Figure 50. Using the THS9001 IF Amplifier with the ADS5463/ADS54RF63
From
50 W
Source
VIN
100 W
78.9 W
348 W
+5V
49.9 W
0.22 mF
100 W
AIN
THS4509
ADS5463
49.9 W 18 pF
AIN
VREF
CM
49.9 W
0.22 mF
78.9 W
49.9 W
0.22 mF
0.1 mF
0.1 mF
348 W
S0193-02
Figure 51. Using the THS4509 with the ADS5463/ADS54RF63
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For applications requiring dc-coupling with the signal source, a differential input/differential output amplifier like
the THS4509 (see Figure 51) provides good harmonic performance and low noise over a wide range of
frequencies. Notice that VREF is used for the common mode with the ADS5463/ADS54RF63 and
ADS5444/5440, whereas VCM must be used with the ADS5474.
In this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to
differential, and sets the proper input common-mode voltage to the ADS5463/ADS54RF63 by using the VREF
pin from the ADC. The 50-Ω resistors and 18-pF capacitor between the THS4509 outputs and
ADS5463/ADS54RF63 inputs (along with the input capacitance of the ADC) limit the bandwidth of the signal to
about 70 MHz (–3 dB). Input termination is accomplished via the 78.9-Ω resistor and 0.22-µF capacitor to
ground, in conjunction with the input impedance of the amplifier circuit. A 0.22-µF capacitor and 49.9-Ω resistor
are inserted to ground across the 78.9-Ω resistor and 0.22-µF capacitor on the alternate input to balance the
circuit. Gain is a function of the source impedance, termination, and 348-Ω feedback resistor. See the THS4509
data sheet for further component values to set proper 50-Ω termination for other common gains. Because the
ADS5463/ADS54RF63 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a
single power supply input with Vs+ = 5 V and Vs– = 0 V (ground). This maintains maximum headroom on the
internal transistors of the THS4509.
Over-Range Analog Input Recovery Error
An over-range condition occurs if the analog input voltage exceeds the full-scale range of the converter (0dBFS,
nominally 2.2 Vpp). To test recovery from an over-range, the ADC analog input is injected with a sinusoidal input
frequency exactly at CLKIN/4 (a four-point sinusoid). The four sample points of each period theoretically occur at
the top, mid-scale, bottom and mid-scale of the sinusoid. Once the amplitude exceeds 0dBFS, the top and
bottom of the sinusoidal input becomes out of range, while the mid-scale points are always in-range and
therefore measureable. The graph in Figure 52 indicates the amount of error from the expected mid-scale value
of 2048 that occurs after negative over-range (bottom of sinusoid went out of range) and positive over-range (top
of sinusoid went out of range). Due to the four point sinusoid, this equates to the amount of error in a valid
sample 1 clock cycle after an over-range occurs as a function of amplitude. The errors generally increase as a
function of input over-range amplitude, though non-monotonically.
R
R
R
OVER-RANGE RECOVERY ERROR
vs
ANALOG INPUT AMPLITUDE
4
Test fIN = Fclkmax/4 Sinusoid
Expected In-Range Code is 2048 (Mid-Scale)
Input Amplitude Values >0 dBFS are
Over-Ranging the ADC
Mid-Scale Code Error − %
3
2
Error After Positive Over-Range
1
0
−1
Error After Negative Over-Range
−2
−3
−4
−1
0
1
2
3
4
5
6
Analog Input Amplitude − dBFS
G055
Figure 52.
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External Voltage Reference
For systems that require the analog signal gain to be adjusted or calibrated, this can be performed by using an
external reference. The dependency on the signal amplitude to the value of the external reference voltage is
characterized typically by Figure 53 (VREF = 2.4 V is normalized to 0 dB as this is the internal reference
voltage). (This figure is the average gain adjustment from the data collected from -1dBFS to -6dBFS in 1 dB
steps.) As can be seen in the linear fit, this equates to approximately –0.3 dB of signal adjustment per 100 mV of
reference adjustment. The range of allowable variation depends on the analog input amplitude that is applied to
the inputs and the desired spectral performance, as can be seen in the performance versus external reference
graphs in Figure 54 and Figure 55. As the applied analog signal amplitude is reduced, more variation in the
reference voltage is allowed in the positive direction (which equates to a reduction in signal amplitude), whereas
an adjustment in reference voltage below the nominal 2.4 V (which equates to an increase in signal amplitude) is
not recommended below approximately 2.35 V. The power consumption versus reference voltage and operating
temperature should also be considered, especially at high ambient temperatures, because the lifetime of the
device is affected by internal junction temperature, see Figure 68.
The ADS5463/ADS54RF63 does not have a VCM output pin and uses the VREF pin to provide the
common-mode voltage in dc-coupled applications. The ADS5463/ADS54RF63 (VCM = 2.4 V) and ADS5474
(VCM = 3.1 V) do not have the same common-mode voltage, but they do share the same approximate VREF
(2.4 V). To create a board layout that may accommodate both devices in dc-coupled applications, route the VCM
of the ADS5474 and the VREF of the ADS5463/ADS54RF63 both to a common point that can be selected via a
switch, jumper, or a 0-Ω resistor to be used as the common-mode voltage of the driving circuit.
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90
1.0
Normalized Gain Adjustment − dB
0.5
0.0
SFDR − Spurious-Free Dynamic Range − dBc
fS = 500 MSPS
fIN = 230 MHz
AIN = < −1 dBFS
Best Fit:
y = −3.06x + 7.33
−0.5
−1.0
Normalized
Amplitude
−1.5
−2.0
Linear
(Normalized Amplitude)
−2.5
AIN = −5 dBFS
AIN = −6 dBFS
80
70
AIN = −4 dBFS
50
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
AIN = −1 dBFS
AIN = −2 dBFS
fS = 500 MSPS
fIN = 230 MHz
Normalized to 0 dB at Nominal VREF = 2.4 V
−3.0
2.2
AIN = −3 dBFS
60
40
2.05 2.15 2.25 2.35 2.45 2.55 2.65 2.75 2.85 2.95 3.05 3.15
3.1
External VREF Applied − V
External VREF Applied − V
G042
G019
Figure 53. ADS5463 Signal Gain Adjustment versus
External Reference (VREF)
Figure 54. ADS5463 SFDR versus External VREF and AIN
3.0
70
2.9
65
fS = 500 MSPS
fIN = 230 MHz
2.8
2.7
60
P − Power − W
SNR − Signal-to-Noise Ratio − dBFS
AIN = −6 dBFS
AIN = −2 dBFS
55
AIN = −3 dBFS
50
AIN = −4 dBFS
2.5
2.4
2.3
AIN = −1 dBFS
45
2.6
2.2
AIN = −5 dBFS
2.1
fS = 500 MSPS
fIN = 230 MHz
40
2.05 2.15 2.25 2.35 2.45 2.55 2.65 2.75 2.85 2.95 3.05 3.15
2.0
2.05 2.15 2.25 2.35 2.45 2.55 2.65 2.75 2.85 2.95 3.05 3.15
External VREF Applied − V
External VREF Applied − V
G052
G051
Figure 55. ADS5463 SNR versus External VREF and AIN
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Figure 56. Total Power Consumption versus External
VREF
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Clock Inputs
The ADS5463/ADS54RF63 clock input can be driven with either a differential clock signal or a single-ended clock
input. The equivalent clock input circuit can be seen in Figure 57. The 0.5 pF of parasitic package capacitance is
before soldering. When jitter may not be a big concern, the use of a single-ended clock (as shown in Figure 58)
could save cost and board space without much performance tradeoff. When clocked with this configuration, it is
best to connect CLK to ground with a 0.01-µF capacitor, while CLK is ac-coupled with a 0.01-µF capacitor to the
clock source, as shown in Figure 58.
ADS5463/5474/54RF63
AVDD5
~ 2.5 nH Bond Wire
CLK
~ 200 fF
Bond Pad
~ 0.5 pF
Package
Parasitic
~ 0.8 pF
1000 W
GND
AVDD5
Internal
Clock
Buffer
~ 2.4 V
GND
Parasitic
~ 0.8 pF
1000 W
~ 2.5 nH Bond Wire
CLK
~ 0.5 pF
Package
~ 200 fF
Bond Pad
GND
S0292-01
Figure 57. Clock Input Circuit (unsoldered package)
Square Wave or
Sine Wave
CLK
0.01 mF
ADS5463
CLK
0.01 mF
S0168-05
Figure 58. Single-Ended Clock
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66.0
79
fIN = 100 MHz
SNR − Signal-to-Noise Ratio − dBFS
SFDR − Spurious-Free Dynamic Range − dBc
80
78
77
fIN = 300 MHz
76
75
74
73
fIN = 100 MHz
65.5
65.0
fIN = 300 MHz
64.5
64.0
63.5
63.0
72
fS = 500 MSPS
fS = 500 MSPS
62.5
71
0
1
2
3
4
0
5
Clock Amplitude − VP−P
1
G022
Figure 59. ADS5463 SFDR versus Differential Clock
Level
2
3
Clock Amplitude − VP−P
4
5
G023
Figure 60. ADS5463 SNR versus Differential Clock Level
The characterization of the ADS5463/ADS54RF63 is typically performed with a 3-VPP differential clock, but the
ADC performs well with a differential clock amplitude down to ~0.5 VPP (250-mV swing on both CLK and CLK),
as shown in Figure 59 and Figure 60. For jitter-sensitive applications, the use of a differential clock has some
advantages at the system level. The differential clock allows for common-mode noise rejection at the printed
circuit board (PCB) level. With a differential clock, the signal-to-noise ratio of the ADC is better for jitter-sensitive,
high-frequency applications because the board level clock jitter is superior.
Larger clock amplitude levels are recommended for high analog input frequencies or slow clock frequencies. At
high analog input frequencies, the sampling process is sensitive to jitter. At slow clock frequencies, a small
amplitude sinusoidal clock has a lower slew rate and can create jitter-related SNR degradation due to the
uncertainty in the sampling point associated with a slow slew rate. Figure 61 demonstrates a recommended
method for converting a single-ended clock source into a differential clock; it is similar to the configuration found
on the evaluation board and was used for much of the characterization. See also Clocking High Speed Data
Converters (SLYT075) for more details.
0.1 mF
Clock
Source
CLK
ADS5463
CLK
S0194-02
Figure 61. Differential Clock
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩ resistors (see
Figure 57). It is recommended to use ac coupling, but if this scheme is not possible, the ADS5463 features good
tolerance to clock common-mode variation, as shown in Figure 62 and Figure 63 (the ADS54RF63 behaves
similarly). The internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50%
duty-cycle clock signal should be provided, though even 40/60 is good enough for many applications.
Performance degradation as a result of duty cycle can be seen in Figure 64.
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66
fIN = 100 MHz
SNR − Signal-to-Noise Ratio − dBFS
SFDR − Spurious-Free Dynamic Range − dBc
85
fIN = 100 MHz
80
fIN = 300 MHz
75
70
65
65
fIN = 300 MHz
64
63
62
61
fS = 500 MSPS
fS = 500 MSPS
60
60
0
1
2
3
4
5
0
1
Clock Common Mode − V
2
3
4
5
Clock Common Mode − V
G024
G025
Figure 62. ADS5463 SFDR versus Clock Common Mode
Figure 63. ADS5463 SNR versus Clock Common Mode
SFDR − Spurious-Free Dynamic Range − dBc
85
fIN = 100 MHz
80
75
fIN = 300 MHz
70
65
60
55
fS = 500 MSPS
50
20
30
40
50
60
70
80
Duty Cycle − %
G021
Figure 64. ADS5463 SFDR vs Clock Duty Cycle
To understand how to determine the required clock jitter, an example is useful. The ADS5463 is capable of
achieving 63.6 dBFS SNR at 450 MHz of analog input frequency. In order to achieve this SNR at 450 MHz the
clock source rms jitter must be at least 181 fsec when combined with the 150 fsec of internal aperture jitter in
order for the total rms jitter to be 234 fsec. A summary of maximum recommended rms clock jitter as a function
of analog input frequency is provided in Table 2 (using 150 fsec of internal aperture jitter). The equations used to
create the table are also presented.
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Table 2. Recommended RMS Clock Jitter
INPUT FREQUENCY
(MHz)
MEASURED SNR
(dBc)
TOTAL JITTER
(fsec rms)
MAXIMUM CLOCK JITTER
(fsec rms)
10
64.4
9590
9589
70
64.4
1370
1362
100
64.3
970
959
230
64.1
432
405
300
64
335
300
450
63.6
234
181
650
62.9
175
94
1300
58.3
149
16
Equation 1 and Equation 2 are used to estimate the required clock source jitter.
SNR (dBc) = -20 x LOG10 (2 x p x fIN x jTOTAL)
jTOTAL = (jADC2 + jCLOCK2)1/2
(1)
(2)
where:
jTOTAL = the rms summation of the clock and ADC aperture jitter;
jADC = the ADC internal aperture jitter which is located in the data sheet;
jCLOCK = the rms jitter of the clock at the clock input pins to the ADC; and
fIN = the analog input frequency.
Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the
clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.
For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not
required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see
application note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC
Devices. Recommended clock distribution chips (CDCs) are the TI CDC7005, the CDCM7005, and the
CDCE72010. Depending on the jitter requirements, a band pass filter (BPF) is sometimes required between the
CDC and the ADC. If the insertion loss of the BPF causes the clock amplitude to be too low for the ADC, or the
clock source amplitude is too low to begin with, an inexpensive amplifier can be placed between the CDC and
the BPF.
Figure 65 represents a scenario where an LVCMOS single-ended clock output is used from a TI CDCM7005 with
the clock signal path optimized for maximum amplitude and minimum jitter. This type of conditioning might
generally be well-suited for use with greater than 250 MHz of input frequency. The jitter of this setup is difficult to
estimate and requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost
amplifier because of insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter
provided by the CDC is still not adequate. The total jitter at the CDCM7005 output depends largely on the phase
noise of the VCXO selected, as well as the CDCM7005, and typically has 50 fs – 100 fs of rms jitter. If it is
determined that the jitter from the CDCM7005 with a VCXO is sufficient without further conditioning, it is possible
to clock the ADS5463/ADS54RF63 directly from the CDCM7005 using differential LVPECL outputs, as illustrated
in Figure 66 (see the CDCM7005 data sheet for the exact schematic). This scenario may be more suitable for
less than 150 MHz of input frequency where jitter is not as critical. A careful analysis of the required jitter and of
the components involved is recommended before determining the proper approach.
34
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www.ti.com ................................................................................................................................................... SLAS515E – NOVEMBER 2006 – REVISED JULY 2009
Low-Jitter Clock Distribution
AMP and/or BPF are Optional
Board Master
Reference Clock
(High or Low Jitter)
10 MHz
REF
LVCMOS
CLKIN
BPF
AMP
XFMR
500 MHz
CLKIN
ADC
1000 MHz (to Transmit DAC)
ADS5463
125 MHz (to DSP)
LVPECL
or
LVCMOS
Low-Jitter Oscillator
1000 MHz
VCO
.
.
.
250 MHz (to FPGA)
To Other
CDC
(Clock Distribution Chip)
CDCM7005
This is an Example Block Diagram.
B0268-03
Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output
frequency and amplitude ranges.
Figure 65. Optimum Jitter Clock Circuit
Low-Jitter Clock Distribution
Board Master
Reference Clock
(High or Low Jitter)
10 MHz
500 MHz
CLKIN
LVPECL
REF
CLKIN
ADC
1000 MHz (to Transmit DAC)
ADS5463
125 MHz (to DSP)
Low-Jitter Oscillator
1000 MHz
VCO
LVPECL
or
LVCMOS
.
.
.
250 MHz (to FPGA)
To Other
CDC
(Clock Distribution Chip)
CDCM7005
This is an Example Block Diagram.
B0343-01
Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output
frequency and amplitude ranges.
Figure 66. Acceptable Jitter Clock Circuit
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS5463 ADS54RF63
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ADS5463
ADS54RF63
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Digital Outputs
The ADC provides 12 LVDS-compatible, offset binary data outputs (D11 to D0; D11 is the MSB and D0 is the
LSB), a data-ready signal (DRY), and an over-range indicator (OVR). It is recommended to use the DRY signal
to capture the output data of the ADS5463/ADS54RF63. DRY is source-synchronous to the DATA/OVR outputs
and operates at the same frequency, creating a half-rate DDR interface that updates data on both the rising and
falling edges of DRY. It is recommended that the capacitive loading on the digital outputs be minimized. Higher
capacitance shortens the data-valid timing window. The values given for timing (see Figure 1) were obtained with
a measured 10-pF parasitic board capacitance to ground on each LVDS line (or 5-pF differential parasitic
capacitance). When setting the time relationship between DRY and DATA at the receiving device, it is generally
recommended that setup time be maximized, but this partially depends on the setup and hold times of the device
receiving the digital data (like an FPGA, Field Programmable Gate Array). Since DRY and DATA are coincident,
it will likely be necessary to delay either DRY or DATA such that setup time is maximized.
Referencing Figure 1, the polarity of DRY with respect to the sample N data output transition is undetermined
because of the unknown startup logic level of the clock divider that generates the DRY signal (DRY is a
frequency divide-by-two of CLK). Either the rising or the falling edge of DRY will be coincident with sample N and
the polarity of DRY could invert when power is cycled off/on. Data capture from the transition and not the polarity
of DRY is recommended, but not required. If the synchronization of multiple ADS5463/ADS54RF63 devices is
required, it might be necessary to use a form of the CLKIN signal rather than DRY to capture the data. Studying
the timing characteristics, it can be seen that the ADS54RF63 offers more tightly controlled timing parameters
than the ADS5463. Depending on the setup/hold requirements of the FPGA in use, it may be possible to use the
DRY from a single ADS54RF63 to latch data into the FPGA from multiple ADS54RF63. This would prove much
more difficult with the ADS5463 at full clock speed due to more restrictive timing parameters.
The DRY frequency is identical on the ADS5463/ADS54RF63 to the ADS5474 (where DRY equals half of the
CLK frequency), but different to the pin-similar ADS5444/ADS5440 (where DRY equals the CLK frequency). The
LVDS outputs all require an external 100-Ω load between each output pair in order to meet the expected LVDS
voltage levels. For long trace lengths, it may be necessary to place a 100-Ω load on each digital output as close
to the ADC as possible and another 100-Ω differential load at the end of the LVDS transmission line to provide
matched impedance and avoid signal reflections. The effective load in this case reduces the LVDS voltage levels
by half.
The OVR output equals a logic high when the 12-bit output word attempts to exceed either all 0s or all 1s. The
digital outputs will clip to all 0s or all 1s if the input is out of range. The OVR signal is provided as an indicator
that the analog input signal exceeded the full-scale input limit of approximately 2.2 VPP (± gain error). The OVR
indicator is provided for systems that use gain control to keep the analog input signal within acceptable limits.
36
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ADS5463
ADS54RF63
www.ti.com ................................................................................................................................................... SLAS515E – NOVEMBER 2006 – REVISED JULY 2009
Power Supplies
The ADS5463/ADS54RF63 uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V
supply (AVDD5 and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). The use of
low-noise power supplies with adequate decoupling is recommended. Linear supplies are preferred to switched
supplies; switched supplies tend to generate more noise components that can be coupled to the
ADS5463/ADS54RF63. However, the PSRR value and the plot shown in Figure 67 were obtained without bulk
supply decoupling capacitors. When bulk (0.1 µF) decoupling capacitors are used, the board-level PSRR is much
higher than the stated value for the ADC. The user may be able to supply power to the device with a
less-than-ideal supply and still achieve good performance. It is not possible to make a single recommendation for
every type of supply and level of decoupling for all systems. If the noise characteristics of the available supplies
are understood, a study of the PSRR data for the ADS5463/ADS54RF63 may provide the user with enough
information to select noisy supplies if the performance is still acceptable within the frequency range of interest.
The power consumption of the ADS5463/ADS54RF63 does not change substantially over clock rate or input
frequency as a result of the architecture and process. The DVDD3 PSRR is superior to both the AVDD5 and
AVDD3 so was not graphed.
Because there are two diodes connected in reverse between AVDD3 and DVDD3 internally, a power-up
sequence is recommended. When there is a delay in power up between these two supplies, the one that lags
could have current sinking through an internal diode before it powers up. The sink current can be large or small
depending on the impedance of the external supply and could damage the device or affect the supply source.
The best power up sequence is one of the following options (regardless of when AVDD5 powers up):
• Power up both AVDD3 and DVDD3 at the same time (best scenario), OR
• Keep the voltage difference less than 0.8 V between AVDD3 and DVDD3 during the power up (0.8 V is not a
hard specification - a smaller delta between supplies is safer).
If the above sequences are not practical then the sink current from the supply needs to be controlled or
protection added externally. The max transient current (on the order of µsec) for the DVDD3 or AVDD3 pin is 500
mA to avoid potential damage to the device or reduce its lifetime.
The values for the analog and clock inputs given in the Absolute Maximum Ratings are valid when the supplies
are on. When the power supplies are off and the clock or analog inputs are still being actively driven, the input
voltage and current need to be limited to avoid device damage. If the ADC supplies are off, max/min continuous
dc voltage is ±0.95 V and max dc current is 20 mA for each input pin (clock or analog), relative to ground.
PSRR − Power Supply Rejection Ratio − dB
100
AVDD3
90
80
AVDD5
70
60
50
fS = 500 MSPS
fIN = None
40
0.01
0.1
1
10
100
f − Frequency − MHz
G032
Figure 67. PSRR versus Supply Injected Frequency
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS5463 ADS54RF63
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ADS5463
ADS54RF63
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Operational Lifetime
It is important for applications that anticipate running continuously for long periods of time near the
maximum-rated ambient temperature of +85°C to consider the data shown in Figure 68 and Figure 69. Referring
to the Thermal Characteristics table, the worst-case operating condition with no airflow has a thermal rise of
23.7°C/W. At approximately 2.2 W of normal power dissipation, at a maximum ambient of +85°C with no airflow,
the junction temperature of the ADS5463 reaches approximately +85°C + 23.7°C/W × 2.2 W = +137°C and
therefore the expected lifetime is approximately 8 years due to an electro migration failure and 18 years due to a
wirebonding failure. Being even more conservative and accounting for the maximum possible power dissipation
that is ensured (2.4 W), the junction temperature becomes nearly +142°C. As Figure 68 and Figure 69 show, this
operating condition limits the expected lifetime of the ADS5463 even more. Operation at +85°C continuously may
require airflow or an additional heatsink in order to decrease the internal junction temperature and increase the
expected lifetime. An airflow of 250 LFM (linear feet per minute) reduces the thermal resistance to 16.4°C/W, the
maximum junction temperature to +124°C and the expected lifetime to over 10 years, assuming a worst-case of
2.4 W and +85°C ambient. Of course, operation at lower ambient temperatures greatly increases the expected
lifetime.
The ADS5463/ADS54RF63 performance over temperature is quite good and can be seen starting in Figure 19.
Although the typical plots show good performance at +100°C, the device is only rated from –40°C to +85°C. For
continuous operation at temperatures near or above the maximum, aside from performance degradation, the
expected primary negative effect is a shorter device lifetime.
100
Estimated Life − Years
Estimated Life − Years
1k
100
10
1
80
90 100 110 120 130 140 150 160 170 180
TJ − Continuous Junction Temperature − °C
Figure 68. Operating Life Derating Chart, Electro
Migration Fail Mode
38
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G053
10
1
0.1
130
140
150
160
170
180
190
TJ − Continuous Junction Temperature − °C
200
G054
Figure 69. Operating Life Derating Chart, Wirebound
Voiding Fail Mode
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS5463 ADS54RF63
ADS5463
ADS54RF63
www.ti.com ................................................................................................................................................... SLAS515E – NOVEMBER 2006 – REVISED JULY 2009
Layout Information
The evaluation board represents a good guideline of how to lay out the board to obtain maximum performance
from the ADS5463/ADS54RF63. General design rules, such as the use of multilayer boards, single ground plane
for ADC ground connections, and local decoupling ceramic chip capacitors, should be applied. The input traces
should be isolated from any external source of interference or noise, including the digital outputs as well as the
clock traces. The clock signal traces should also be isolated from other signals, especially in applications where
low jitter is required like high IF sampling. Besides performance-oriented rules, care must be taken when
considering the heat dissipation of the device. The thermal heat sink should be soldered to the board as
described in the PowerPAD Package section. See ADS5463 EVM User Guide (SLAU194) on the TI web site for
the evaluation board schematic.
PowerPAD Package
The PowerPAD package is a thermally enhanced standard-size IC package designed to eliminate the use of
bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using
standard printed circuit board (PCB) assembly techniques and can be removed and replaced using standard
repair procedures.
The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of
the IC. This provides an extremely low thermal resistance path between the die and the exterior of the package.
The thermal pad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using
the PCB as a heatsink.
Assembly Process
1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in
the Mechanical Data section.
2. Place a 6-by-6 array of thermal vias in the thermal pad area. These holes should be 13 mils in diameter. The
small size prevents wicking of the solder through the holes.
3. It is recommended to place a small number of 25-mil-diameter holes under the package, but outside the
thermal pad area, to provide an additional heat path.
4. Connect all holes (both inside and outside the thermal pad area) to an internal copper plane (such as a
ground plane).
5. Do not use the typical web or spoke via-connection pattern when connecting the thermal vias to the ground
plane. The spoke pattern increases the thermal resistance to the ground plane.
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.
7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.
8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
For more detailed information regarding the PowerPAD package and its thermal properties, see either the
PowerPAD Made Easy application brief (SLMA004) or the PowerPAD Thermally Enhanced Package application
report (SLMA002).
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS5463 ADS54RF63
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ADS5463
ADS54RF63
SLAS515E – NOVEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the
low-frequency value
Aperture Delay
The delay in time between the rising edge of the input
sampling clock and the actual time at which the
sampling occurs
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay
Clock Pulse Duration/Duty Cycle
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse
duration) to the period of the clock signal, expressed
as a percentage.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input
values spaced exactly 1 LSB apart. DNL is the
deviation of any single step from this ideal value,
measured in units of LSB.
Common-Mode Rejection Ratio (CMRR)
CMRR measures the ability to reject signals that are
presented to both analog inputs simultaneously. The
injected common-mode frequency level is translated
into dBFS, the spur in the output FFT is measured in
dBFS, and the difference is the CMRR in dB.
Effective Number of Bits (ENOB)
ENOB is a measure in units of bits of a converter's
performance as compared to the theoretical limit
based on quantization noise
ENOB = (SINAD – 1.76)/6.02
Gain Error
Gain error is the deviation of the ADC actual input
full-scale range from its ideal value, given as a
percentage of the ideal input full-scale range.
PSRR is a measure of the ability to reject frequencies
present on the power supply. The injected frequency
level is translated into dBFS, the spur in the output
FFT is measured in dBFS, and the difference is the
PSRR in dB. The measurement calibrates out the
benefit of the board supply decoupling capacitors.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and in the first five harmonics.
P
SNR + 10log 10 S
PN
(4)
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter’s full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding
dc.
PS
SINAD + 10log 10
PN ) PD
(5)
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter’s full-scale range.
Temperature Drift
Temperature drift (with respect to gain error and
offset error) specifies the change from the value at
the nominal temperature to the value at TMIN or TMAX.
It is computed as the maximum variation the
parameters over the whole temperature range divided
by TMIN – TMAX.
Integral Nonlinearity (INL)
INL is the deviation of the ADC transfer function from
a best-fit line determined by a least-squares curve fit
of that transfer function. The INL at each analog input
value is the difference between the actual transfer
function and this best-fit line, measured in units of
LSB.
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS)
to the power of the first five harmonics (PD).
P
THD + 10log 10 S
PD
(6)
Offset Error
Offset error is the deviation of output code from
mid-code when
both
inputs are tied
to
common-mode.
Two-Tone Intermodulation Distortion (IMD3)
IMD3 is the ratio of the power of the fundamental (at
frequencies f1, f2) to the power of the worst spectral
component at either frequency 2f1 – f2 or 2f2 – f1).
IMD3 is given in units of either dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter’s full-scale range.
Power-Supply Rejection Ratio (PSRR)
40
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THD is typically given in units of dBc (dB to carrier).
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS5463 ADS54RF63
ADS5463
ADS54RF63
www.ti.com ................................................................................................................................................... SLAS515E – NOVEMBER 2006 – REVISED JULY 2009
REVISION HISTORY
Changes from Revision D (FEBRUARY 2009) to Revision E ......................................................................................... Page
•
•
Added AC to High Analog Input Swing feature description ................................................................................................... 1
Changed clock and analog inputs and data outputs in ABSOLUTE MAXIMUM RATINGS table ......................................... 2
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS5463 ADS54RF63
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Feb-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS5463IPFP
ACTIVE
HTQFP
PFP
80
96
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-40 to 85
ADS5463I
ADS5463IPFPR
ACTIVE
HTQFP
PFP
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-40 to 85
ADS5463I
ADS54RF63IPFP
ACTIVE
HTQFP
PFP
80
96
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-40 to 85
ADS54RF63I
ADS54RF63IPFPR
ACTIVE
HTQFP
PFP
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-40 to 85
ADS54RF63I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Feb-2017
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS5463 :
• Enhanced Product: ADS5463-EP
• Space: ADS5463-SP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS5463IPFPR
HTQFP
PFP
80
1000
330.0
24.4
15.0
15.0
1.5
20.0
24.0
Q2
ADS54RF63IPFPR
HTQFP
PFP
80
1000
330.0
24.4
15.0
15.0
1.5
20.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS5463IPFPR
HTQFP
PFP
80
1000
350.0
350.0
43.0
ADS54RF63IPFPR
HTQFP
PFP
80
1000
350.0
350.0
43.0
Pack Materials-Page 2
www.ti.com
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