Texas Instruments | Quad Channel 12-Bit 125-MSPS ADC W/Serial LVDS Interface (Rev. B) | Datasheet | Texas Instruments Quad Channel 12-Bit 125-MSPS ADC W/Serial LVDS Interface (Rev. B) Datasheet

Texas Instruments Quad Channel 12-Bit 125-MSPS ADC W/Serial LVDS Interface (Rev. B) Datasheet
ADS6425
www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009
QUAD CHANNEL, 12-BIT, 125-MSPS ADC WITH SERIAL LVDS INTERFACE
FEATURES
APPLICATIONS
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Maximum Sample Rate: 125 MSPS
12-Bit Resolution with No Missing Codes
1.65-W Total Power
Simultaneous Sample and Hold
70.3 dBFS SNR at Fin = 50 MHz
83 dBc SFDR at Fin = 50 MHz, 0 dB Gain
79 dBc SFDR at Fin = 170 MHz, 3.5 dB Gain
3.5 dB Coarse Gain and up to 6 dB
Programmable Fine Gain for SFDR/SNR
Trade-Off
Serialized LVDS Outputs with Programmable
Internal Termination Option
Supports Sine, LVCMOS, LVPECL, LVDS Clock
Inputs and Amplitude Down to 400 mVpp
Differential
Internal Reference with External Reference
Support
No External Decoupling Required for
References
3.3-V Analog and Digital Supply
64 QFN Package (9 mm × 9 mm)
Pin Compatible 14-Bit Family (ADS644X SLAS532)
Base-Station IF Receivers
Diversity Receivers
Medical Imaging
Test Equipment
DESCRIPTION
The ADS6425 is a high performance 12-bit,
125-MSPS quad channel ADC. Serial LVDS data
outputs reduce the number of interface lines, resulting
in a compact 64-pin QFN package (9 mm × 9 mm)
that allows for high system integration density. The
device includes a 3.5 dB coarse gain option that can
be used to improve SFDR performance with little
degradation in SNR. In addition to the coarse gain,
fine gain options also exist, programmable in 1dB
steps up to 6dB.
The output interface is 2-wire, where each ADC's
data is serialized and output over two LVDS pairs.
This makes it possible to halve the serial data rate
(compared to a 1-wire interface) and restrict it to less
than 1Gbps easing receiver design. The ADS6425
also includes the traditional 1-wire interface that can
be used at lower sampling frequencies.
An internal phase locked loop (PLL) multiplies the
incoming ADC sampling clock to derive the bit clock.
The bit clock is used to serialize the 12-bit data from
each channel. In addition to the serial data streams,
the frame and bit clocks are also transmitted as
LVDS outputs. The LVDS output buffers have
features such as programmable LVDS currents,
current doubling modes, and internal termination
options. These can be used to widen eye-openings
and improve signal integrity, easing capture by the
receiver.
The ADC channel outputs can be transmitted either
as MSB or LSB first and 2s complement or straight
binary.
The ADS6425 has internal references, but can also
support an external reference mode. The device is
specified over the industrial temperature range
(–40°C to 85°C).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated
ADS6425
SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com
LVDD
LGND
CAP
AVDD
AGND
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
CLKP
CLKM
BIT Clock
DCLKP
DCLKM
FRAME Clock
FCLKP
FCLKM
PLL
SHA
12-Bit
ADC
Digital
Encoder
and
Serializer
SHA
12-Bit
ADC
Digital
Encoder
and
Serializer
SHA
12-Bit
ADC
Digital
Encoder
and
Serializer
SHA
12-Bit
ADC
Digital
Encoder
and
Serializer
INA_P
INA_M
INB_P
INB_M
INC_P
INC_M
IND_P
VCM
DA1_P
DA1_M
DB0_P
DB0_M
DB1_P
DB1_M
DC0_P
DC0_M
DC1_P
DC1_M
DD0_P
DD0_M
DD1_P
DD1_M
REFM
REFP
IND_M
DA0_P
DA0_M
Reference
Parallel
Interface
Serial
Interface
SCLK
RESET
SEN
SDATA
CFG4
CFG3
CFG1
CFG2
PDN
ADS6425
B0199-02
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS6425
QFN-64 (2)
RGC
–40°C to 85°C
AZ6425
(1)
(2)
2
ORDERING NUMBER
TRANSPORT
MEDIA,
QUANTITY
ADS6425IRGCT
250, Tape/reel
ADS6425IRGCR
2000, Tape/reel
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 23.17 °C/W (0 LFM air flow), θJC
= 22.1 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in. x 3 in. PCB.
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ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
AVDD
Supply voltage range
–0.3 to 3.9
V
LVDD
Supply voltage range
–0.3 to 3.9
V
Voltage between AGND and DGND
–0.3 to 0.3
V
Voltage between AVDD to LVDD
–0.3 to 3.3
V
Voltage applied to external pin, VCM
–0.3 to 2.0
V
Voltage applied to analog input pins
–0.3V to minimum ( 3.6, AVDD + 0.3V)
V
TA
Operating free-air temperature range
–40 to 85
°C
TJ
Operating junction temperature range
125
°C
Tstg
Storage temperature range
–65 to 150
°C
220
°C
Lead temperature 1,6 mm (1/16") from the case for 10 seconds
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
AVDD Analog supply voltage
3.0
3.3
3.6
V
LVDD
3.0
3.3
3.6
V
SUPPLIES
LVDS Buffer supply voltage
ANALOG INPUTS
Differential input voltage range
2
Vpp
1.5
±0.1
Input common-mode voltage
Voltage applied on VCM in external reference mode
1.45
1.50
V
1.55
V
125
MSPS
CLOCK INPUT
Input clock sample rate
5
Sine wave, ac-coupled
Input clock amplitude differential (VCLKP – VCLKM)
0.4
LVPECL, ac-coupled
1.5
± 0.8
LVDS, ac-coupled
Vpp
± 0.35
LVCMOS, ac-coupled
3.3
Input Clock duty cycle
35%
50%
65%
DIGITAL OUTPUTS
Without internal termination
CLOAD
Maximum external load capacitance from each output pin to
DGND
RLOAD
Differential load resistance (external) between the LVDS output pairs
TA
Operating free-air temperature
5
With internal termination
pF
10
Ω
100
–40
85
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°C
3
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ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3V, sampling rate = 125MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
RESOLUTION
TYP
MAX
UNIT
12
Bits
2.0
Vpp
ANALOG INPUT
Differential input voltage range
Differential input capacitance
7
pF
Analog input bandwidth
500
MHz
Analog input common mode current
(per input pin of each ADC)
155
µA
REFERENCE VOLTAGES
VREFB
Internal reference bottom voltage
1.0
V
VREFT
Internal reference top voltage
2.0
V
VCM
Common mode output voltage
1.5
V
VCM Output current capability
±4
mA
DC ACCURACY
No missing codes
EO
Assured
Offset error
-15
±2
+15
mV
Offset error temperature coefficient
0.05
Offset error temperature coefficient,
channel-channel
Internal reference error
(VREFT-VREFB)
-15
Internal reference error temperature
coefficient
EG
Gain error
(1)
±5
mV/°C
15
0.25
Does not include gain error caused due to
internal reference error
-1
0.3
mV
mV/°C
+1
% FS
Gain error temperature coefficient
Δ%/°C
0.005
Gain error temperature coefficient,
channel-channel
DNL
Differential nonlinearity
-0.9
INL
Integral nonlinearity
-2.5
PSRR
DC Power supply rejection ratio
0.5
2.0
1.0
2.5
LSB
LSB
–0.5
mV/V
POWER SUPPLY
ICC
Total supply current
502
mA
IAVDD
Analog supply current
412
mA
ILVDD
LVDS supply current
90
mA
Total power
Power down
(1)
4
Input clock running
1.65
1.8
W
77
150
mW
This is specified by design and characterization. It is not tested in production.
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ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3V, sampling rate = 125MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS
Fin = 10 MHz
70.9
Fin = 50 MHz
67.5
Fin = 100 MHz
SNR
Signal to noise ratio
Fin = 170 MHz
Fin = 230 MHz
69.9
0 dB Gain
68.5
3.5 dB Coarse gain
68.1
0 dB Gain
67.4
3.5 dB Coarse gain
67.1
Fin = 10 MHz
67
Fin = 100 MHz
Signal to noise and distortion ratio
Fin = 170 MHz
Fin = 230 MHz
RMS Output noise
69.7
66.9
3.5 dB Coarse gain
67.4
0 dB Gain
66.5
Inputs tied to common-mode
0.407
Fin = 230 MHz
73
87
75
3.5 dB Coarse gain
79
0 dB Gain
74
3.5 dB Coarse gain
78
73
Fin = 100 MHz
Fin = 170 MHz
Fin = 230 MHz
90
85
3.5 dB Coarse gain
88
0 dB Gain
82
3.5 dB Coarse gain
85
73
Fin = 100 MHz
Fin = 170 MHz
Fin = 230 MHz
Worst harmonic (other than HD2,
HD3)
dBc
90
Fin = 50 MHz
Third harmonic
91
0 dB Gain
Fin = 10 MHz
HD3
dBc
93
Fin = 50 MHz
Second harmonic
83
0 dB Gain
Fin = 10 MHz
HD2
LSB
90
Fin = 100 MHz
Fin = 170 MHz
dBFS
66
3.5 dB Coarse gain
Fin = 50 MHz
Spurious free dynamic range
70
0 dB Gain
Fin = 10 MHz
SFDR
dBFS
70.7
Fin = 50 MHz
SINAD
70.5
83
87
0 dB Gain
75
3.5 dB Coarse gain
79
0 dB Gain
74
3.5 dB Coarse gain
78
Fin = 10 MHz
95
Fin = 50 MHz
94
Fin = 100 MHz
91
Fin = 170 MHz
88
Fin = 230 MHz
86
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dBc
5
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ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3V, sampling rate = 125MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
Fin = 10 MHz
Total harmonic distortion
70
81
Fin = 100 MHz
84
Fin = 170 MHz
73
Fin = 230 MHz
ENOB
IMD
Effective number of bits
Cross-talk
dBc
72
Fin = 50 MHz
Two-tone intermodulation distortion
UNIT
88
Fin = 50 MHz
THD
MAX
10.8
11.4
F1= 46.09 MHz, F2 = 50.09 MHz
90
F1= 185.09 MHz, F2 = 190.09 MHz
82
Near channel, Frequency of interfering signal
= 10 MHz
92
Bits
dBFS
dBFS
Far channel, Frequency of interfering signal
= 10 MHz
105
DIGITAL CHARACTERISTICS
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 AVDD = LVDD = 3.3V, IO = 3.5mA, RLOAD = 100Ω (1).
All LVDS specifications are characterized, but not tested at production.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS
High-level input voltage
2.4
V
Low-level input voltage
0.8
V
High-level input current
10
µA
Low-level input current
10
µA
4
pF
High-level output voltage
1375
mV
Low-level output voltage
1025
mV
Input capacitance
DIGITAL OUTPUTS
|VOD|
Output differential voltage
VOS
Output offset voltage
Common-mode voltage of OUTP and OUTM
Output capacitance
Output capacitance inside the device, from either output to ground
(1)
6
250
350
450
mV
1200
mV
2
pF
IO refers to the LVDS buffer current setting, RLOAD is the external differential load resistance between the LVDS output pair
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TIMING SPECIFICATIONS (1)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA,
RL = 100 Ω (3), no internal termination, unless otherwise noted.
PARAMETER
tJ
TEST CONDITIONS
Aperture jitter
MIN
Uncertainty in the sampling instant
Interface: 2-wire, DDR bit clock, 12x serialization
TYP
MAX
UNIT
250
fs rms
(4)
Measured from zero crossing of data transitions to
zero crossing of bit clock
0.4
0.6
ns
Measured from zero crossing of bit clock to zero
crossing of data transitions
0.5
0.7
ns
Frame setup time
Measured from zero-cross of frame clock rising
edge to zero-cross of bit clock rising edge
0.4
0.6
ns
th
Frame hold time
Measured from zero-cross of bit clock falling edge
to zero-cross of frame clock falling edge
0.5
0.7
ns
tpd_clk
Clock propagation delay (4)
Input clock rising edge cross-over to frame clock
rising edge cross-over
3.6
4.4
tsu
Data setup time (5)
th
Data hold time (5)
tsu
(6)
(6)
Bit clock cycle-cycle jitter
(6)
Frame clock cycle-cycle jitter
(6)
5.2
ns
350
ps pp
75
ps pp
Below specifications apply for 5 MSPS ≤ Fs ≤125 MSPS and all interface options.
tA
Aperture delay
Delay from rising edge of input clock to the actual
sampling instant
Aperture delay variation,
channel-channel
Within the same device
ADC Latency
(7)
Wake up time
1
2
-250
Time for a sample to propagate to the ADC output
Figure 1
3
ns
250
ps
Clock
cycles
12
Time to valid data after coming out of global power
down
100
Time to valid data after input clock is re-started
100
µs
200
clock
cycles
Time to valid data after coming out of channel
standby
µs
tRISE
Data rise time
Data rise time measured from –100 mV to +100
mV
50
100
200
ps
tFALL
Data fall time
Data fall time measured from +100 mV to –100 mV
50
100
200
ps
tRISE
Bit clock and frame clock rise time
Rise time measured from –100mV to +100mV
50
100
200
ps
tFALL
Bit clock and frame clock fall time
Fall time measured from +100mV to –100mV
50
100
200
ps
LVDS Bit clock duty cycle
45%
50%
55%
LVDS Frame clock duty cycle
47%
50%
53%
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Timing parameters are ensured by design and characterization and not tested in production.
CL is the external single-ended load capacitance between each output pin and ground.
Io refers to the LVDS buffer current setting; RL is the external differential load resistance between the LVDS output pair.
Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options.
Timing parameters are measured at the end of a 2 inch pcb trace (100-Ω characteristic impedance) terminated by RLand CL.
Setup and hold time specifications take into account the effect of jitter on the output data and clock.
Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as
shown in Table 25
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Sample
N+13
Sample
N+12
Sample
N+11
Sample
N
Input
Signal
tA
Input
Clock
CLKM
CLKP
tPD_CLK
Latency 12 Clocks
DCLKP
Bit
Clock
DCLKM
Output
Data
DOM
DOP
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 D11 D10 D9
Sample N–1
Frame
Clock
D8
D7
D6
D5
D4
D3
D2
D1
D0
Sample N
FCLKM
FCLKP
T0105-03
Figure 1. Latency
DCLKP
Bit Clock
DCLKM
tsu
th
tsu
Output Data P
(differential)
DA, DB, DC, DD M
th
Dn+1
Dn
tsu
th
FCLKP
Frame Clock
FCLKM
Figure 2. LVDS Timings
8
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DEVICE PROGRAMMING MODES
The ADS6425 offers flexibility with several programmable features that are easily configured.
The device can be configured independently using either parallel interface control or serial interface
programming.
In addition, the device supports a third configuration mode, where both the parallel interface and the serial control
registers are used. In this mode, the priority between the parallel and serial interfaces is determined by a priority
table (Table 2). If this additional level of flexibility is not required, the user can select either the serial interface
programming or the parallel interface control.
USING PARALLEL INTERFACE CONTROL ONLY
To control the device using parallel interface, keep RESET tied to high (LVDD). Pins CFG1, CFG2, CFG3,
CFG4, PDN, SEN, SCLK, and SDATA are used to directly control certain functions of the ADC. After power-up,
the device will automatically get configured as per the parallel pin voltage settings (Table 3 to Table 6) and no
reset is required. In this mode, SEN, SCLK, and SDATA function as parallel interface control pins.
Frequently used functions are controlled in this mode—output data interface and format, power down modes,
coarse gain and internal/external reference. The parallel pins can be configured using a simple resistor string
(with 10% tolerance resistors) as illustrated in Figure 3.
Table 1 briefly describes the modes controlled by the parallel pins.
Table 1. Parallel Pin Definition
PIN
SEN
SCLK, SDATA
CONTROL FUNCTIONS
Coarse gain and internal/external reference.
Sync, deskew patterns and global power down.
PDN
Dedicated pin for global power down
CFG1
1-Wire/2-wire and DDR/SDR bit clock
CFG2
12x/14x Serialization and SDR bit clock capture edge
CFG3
Reserved function. Tie CFG3 to Ground.
CFG4
MSB/LSB First and data format.
USING SERIAL INTERFACE PROGRAMMING ONLY
In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal
registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET
pin or by a high setting on the <RST> bit (in register ). After reset, the RESET pin must be kept low.
The Serial Interface section describes the register programming and register reset in more detail.
Since the parallel pins (CFG1-4 and PDN) are not used in this mode, they must be tied to ground. The register
override bit <OVRD> - D10 in register 0x0D has to be set high to disable the control of parallel interface pins in
this serial interface control ONLY mode.
USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (CFG1-4 and PDN)
can also be used to configure the device.
The parallel interface control pins CFG1 to CFG4 and PDN are available. After power-up, the device will
automatically get configured as per the parallel pin voltage settings (Table 3 to Table 9) and no reset is required.
A simple resistor string can be used as illustrated in Figure 3.
SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC.
The registers must first be reset to their default values either by applying a pulse on RESET pin or by a high
setting on the <RST> bit (in register ). After reset, the RESET pin must be kept low.
The Serial Interface section describes the register programming and register reset in more detail.
Since some functions are controlled using both the parallel pins and serial registers, the priority between the two
is determined by a priority table (Table 2).
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Table 2. Priority Between Parallel Pins and Serial Registers
PIN
FUNCTIONS SUPPORTED
CFG1 to
CFG4
PRIORITY
As described in Table 6 to
Table 9
Register bits can control the modes ONLY if the <OVRD> bit is high. If the <OVRD> bit is
LOW, then the control voltage on these parallel pins determines the function as per Tables
PDN
Global Power Down
D0 bit in register 0x00 controls global power down ONLY if PDN pin is LOW. If PDN is high,
device is in global power down mode.
SEN
Serial Interface Enable
3.5 dB coarse gain setting is controlled by bit D5 in register 0x0D ONLY if the <OVRD> bit is
high. Else, it is in default setting of 0 dB coarse gain.
Internal/External reference setting is determined by bit D5 in register 0x00.
SCLK,
SDATA
Bits D5-D7 in register 0x0A control the SYNC and DESKEW output patterns.
Serial Interface Clock and
Serial Interface Data
Power down is determined by bit D0 in 0x00 register.
LVDD
LVDD
(5/6) LVDD
R
(5/8) LVDD
GND
2R
(5/8) LVDD
3R
(5/6) LVDD
LVDD
GND
2R
LVDD
(3/8) LVDD
(3/6) LVDD
(3/8) LVDD
(3/6) LVDD
3R
3R
To SEN Pin
To CFGx Pins
GND
GND
Figure 3. Simple Scheme to Configure Parallel Pins
10
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DESCRIPTION OF PARALLEL PINS
Table 3. SCLK, SDATA Control Pins
SCLK
SDATA
LOW
LOW
NORMAL conversion.
DESCRIPTION
LOW
HIGH
SYNC - ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the
deserialized data to the frame boundary. See Capture Test Patterns for details.
HIGH
LOW
POWER DOWN –Global power down, all channels of the ADC are powered down, including internal references,
PLL and output buffers.
HIGH
HIGH
DESKEW - ADC outputs deskew pattern on all channels. This pattern can be used by the receiver to ensure
deserializer uses the right clock edge. See Capture Test Patterns for details.
Table 4. SEN Control Pin
SEN
0
DESCRIPTION
External reference and 0 dB coarse gain (full-scale = 2V pp)
(3/8)LVDD
External reference and 3.5 dB coarse gain (full-scale = 1.34V pp)
(5/8)LVDD
Internal reference and 3.5 dB coarse gain (full-scale = 1.34V pp)
LVDD
Internal reference and 0 dB coarse gain (full-scale = 2V pp)
Independent of the programming mode used, after power-up the parallel pins PDN, CFG1 to CFG4 will
automatically configure the device as per the voltage applied (Table 5 to Table 9).
Table 5. PDN Control Pin
PDN
0
AVDD
DESCRIPTION
Normal operation
Power down global
Table 6. CFG1 Control Pin
CFG1
DESCRIPTION
0 (default)
+200mV
DDR Bit clock and 1-wire interface
(3/6)LVDD
±200mV
Not used
(5/6)LVDD
±200mV
SDR Bit clock and 2-wire interface
LVDD
- 200mV
DDR Bit clock and 2-wire interface
Table 7. CFG2 Control Pin
CFG2
DESCRIPTION
0 (default)
+200mV
12x Serialization and capture at falling edge of bit clock (only with SDR bit clock)
(3/6)LVDD
±200mV
14x Serialization and capture at falling edge of bit clock (only with SDR bit clock)
(5/6)LVDD
±200mV
14x Serialization and capture at rising edge of bit clock (only with SDR bit clock)
LVDD
- 200mV
12x Serialization and capture at rising edge of bit clock (only with SDR bit clock)
Table 8. CFG3 Control Pin
CFG3
RESERVED - TIE TO GROUND
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Table 9. CFG4 Control Pin
CFG4
DESCRIPTION
0 (default)
+200mV
MSB First and 2s complement
(3/6)LVDD
±200mV
MSB First and Offset binary
(5/6)LVDD
±200mV
LSB First and Offset binary
LVDD
- 200mV
LSB First and 2s complement
SERIAL INTERFACE
The ADC has a serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock),
SDATA (serial interface data) and RESET. Serial shift of bits into the device is enabled when SEN is low. Serial
data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the
register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits,
the excess bits are ignored. Data can be loaded in multiple of 16-bit words within a single active SEN pulse. The
interface can work with SCLK frequency from 20 MHz down to very low speeds (few hertz) and even with
non-50% duty cycle SCLK.
The first 5-bits of the 16-bit word are the address of the register while the next 11 bits are the register data.
Register Reset
After power-up, the internal registers must be reset to their default values. This can be done in one of two ways:
1. Either by applying a high-going pulse on RESET (of width greater than 10ns) OR
2. By applying software reset. Using the serial interface, set the <RST> bit in register 0x00 to high – this resets
the registers to their default values and then self-resets the <RST> bit to LOW.
When RESET pin is not used, it must be tied to LOW.
12
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Register Address
SDATA
A4
A3
A2
A1
Register Data
A0
D10
D9
D8
D7
D6
t(SCLK)
D5
D4
D3
D2
D1
D0
t(DH)
t(DSU)
SCLK
t(SLOADH)
t(SLOADS)
SEN
RESET
T0109-03
Figure 4. Serial Interface Timing
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SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD =
3.3V, unless otherwise noted.
PARAMETER
MIN
TYP
> dc
MAX
UNIT
20
MHz
fSCLK
SCLK Frequency, fSCLK = 1/tSCLK
tSLOADS
SEN to SCLK Setup time
25
ns
tSLOADH
SCLK to SEN Hold time
25
ns
tDSU
SDATA Setup time
25
ns
tDH
SDATA Hold time
25
ns
100
ns
Time taken for register write to take effect after 16th SCLK falling edge
RESET TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = LVDD =
3.3V, unless otherwise noted.
PARMATER
CONDITIONS
MIN
t1
Power-on delay time
Delay from power-up of AVDD and LVDD to RESET pulse
active
t2
Reset pulse width
Pulse width of active RESET signal
t3
Register write delay time Delay from RESET disable to SEN active
tPO
Power-up delay time
TYP
UNIT
5
ms
10
ns
25
Delay from power-up of AVDD and LVDD to output stable
MAX
ns
6.5
ms
Power Supply
AVDD, LVDD
t1
RESET
t2
t3
SEN
T0108-03
Figure 5. Reset Timing
14
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SERIAL REGISTER MAP
Table 10. Summary of Functions Supported By Serial Interface
REGISTER
ADDRESS
A4 - A0
REGISTER FUNCTIONS (1) (2) (3)
D10
D9
D8
D7
00
<RST>
S/W RESET
0
0
0
04
0
0
0
0
0
<DF>
DATA
FORMAT 2S
COMP OR
STRAIGHT
BINARY
0
0A
D6
0
0D
10
11
(1)
(2)
(3)
<REF>
INTERNAL
OR
EXTERNAL
D4
D3
<PDN CHD>
POWER
DOWN CH D
<PDN CHC>
POWER
DOWN CHC
D2
<PDN CHB>
POWER
DOWN CH B
<CLKIN GAIN>
INPUT CLOCK BUFFER GAIN CONTROL
<PATTERNS>
TEST PATTERNS
0
0
0
D1
D0
<PDN CHA>
POWER
DOWN CH A
<PDN
GLOBAL>
GLOBAL
POWER
DOWN
0
0
0
0
<CUSTOM A>
CUSTOM PATTERN (LOWER 11 BITS)
0B
0C
D5
0
0
0
0
0
0
0
<CUSTOM
B>
CUSTOM
PATTERN
(MSB BIT)
BYTE-WISE
OR
BIT-WISE
MSB OR
LSB FIRST
<COARSE
GAIN>
COURSE
GAIN
ENABLE
FALLING OR
RISING BIT
CLOCK
CAPTURE
EDGE
0
12-BIT OR
14-BIT
SERIALIZE
DDR OR
SDR BIT
CLOCK
1-WIRE OR
2-WIRE
INTERFACE
<FINE GAIN>
FINE GAIN CONTROL (1dB to 6 dB)
<OVRD>
OVERRIDE
BIT
0
0
<TERM CLK>
LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS
WORD-WISE CONTROL
0
0
<LVDS CURR>
LVDS CURRENT SETTINGS
0
0
<CURR DOUBLE>
LVDS CURRENT DOUBLE
<TERM DATA>
LVDS INTERNAL TERMINATION - DATA OUTPUTS
The unused bits in each register (shown by blank cells in above table) must be programmed as 0.
Multiple functions in a register can be programmed in a single write operation.
After a hardware or software reset, all register bits are cleared to 0.
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DESCRIPTION OF SERIAL REGISTERS
Table 11. Serial Register A (1)
REGISTER
ADDRESS
A4 - A0
D10
<RST>
S/W RESET
00
(1)
BITS
D9
0
D8
0
D7
0
D6
D5
D4
D3
D2
D1
D0
0
<REF>
INTERNAL
OR
EXTERNAL
<PDN CHD>
POWER
DOWN CH D
<PDN CHC>
POWER
DOWN CHC
<PDN CHB>
POWER
DOWN CH B
<PDN CHA>
POWER
DOWN CH A
<PDN>
GLOBAL
POWER
DOWN
After a hardware or software reset, all register bits are cleared to 0.
D0 - D4
Power down modes
D0
<PDN GLOBAL>
0
Normal operation
1
Global power down, including all channels ADCs, internal references, internal PLL and output
buffers
D1
<PDN CHA>
0
CH A Powered up
1
CH A ADC Powered down
D2
<PDN CHB>
0
CH B Powered up
1
CH B ADC Powered down
D3
<PDN CHC>
0
CH C Powered up
1
CH C ADC Powered down
D4
<PDN CHD>
0
CH D Powered up
1
CH D ADC Powered down
D5
<REF> Reference
0
Internal reference enabled
1
External reference enabled
D10
<RST>
1
Software reset applied – resets all internal registers and self-clears to 0
16
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Table 12. Serial Register B (1)
REGISTER
ADDRESS
A4 - A0
04
(1)
BITS
D10
0
D9
0
D8
D7
0
D6
D5
D4
D3
D2
<CLKIN GAIN>
INPUT CLOCK BUFFER GAIN CONTROL
0
D1
D0
0
0
After a hardware or software reset, all register bits are cleared to 0.
D6 - D2
<CLKIN GAIN> Input clock buffer gain control
11000
Gain 0, minimum gain
00000
Gain 1, default gain after reset
01100
Gain 2
01010
Gain 3
01001
Gain 4
01000
Gain 5, maximum gain
Table 13. Serial Register C (1)
REGISTER
ADDRESS
A4 - A0
00
(1)
BITS
D10
D9
D8
0
<DF>
DATA
DORMAT 2S
COMP OR
STRAIGHT
BINARY
0
D7
D6
D5
<PATTERNS>
TEST PATTERNS
D4
D3
D2
D1
D0
0
0
0
0
0
After a hardware or software reset, all register bits are cleared to 0.
D7 - D5
<PATTERNS> Capture test patterns
000
Normal ADC operation
001
Output all zeros
010
Output all ones
011
Output toggle pattern
100
Unused
101
Output custom pattern (contents of CUSTOM pattern registers 0x0B and 0x0C)
110
Output DESKEW pattern (serial stream of 1010..)
111
Output SYNC pattern
D9
<DF> Data format selection
0
2s Complement format
1
Straight binary format
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Table 14. Serial Register D (1)
REGISTER
ADDRESS
A4 - A0
BITS
D10
D9
D8
D7
D6
0B
(1)
D5
D4
D3
D2
D1
D0
D2
D1
D0
<CUSTOM A>
CUSTOM PATTERN (LOWER 11 BITS)
After a hardware or software reset, all register bits are cleared to 0.
D10 - D0
<CUSTOM A> Lower 11 bits of custom pattern <D10>…<D0>
Table 15. Serial Register E (1)
REGISTER
ADDRESS
A4 - A0
D9
D8
<FINE GAIN>
FINE GAIN CONTROL (1 dB to 6 dB)
0C
(1)
BITS
D10
D7
D6
0
D5
0
D4
0
D3
0
0
0
0
<CUSTOM
B>
CUSTOM
PATTERN
(MSB BIT)
After a hardware or software reset, all register bits are cleared to 0.
D4 - D0
<CUSTOM B> MSB bit of custom pattern <D11>
D10-D8
<FINE GAIN> Fine gain control
000
0 dB Gain (full-scale range = 2.00 VPP)
001
1 dB Gain (full-scale range = 1.78 VPP)
010
2 dB Gain (full-scale range = 1.59 VPP)
011
3 dB Gain (full-scale range = 1.42 VPP)
100
4 dB Gain (full-scale range = 1.26 VPP)
101
5 dB Gain (full-scale range = 1.12 VPP)
110
6 dB Gain (full-scale range = 1.00 VPP)
Table 16. Serial Register F (1)
REGISTER
ADDRESS
A4 - A0
0D
(1)
BITS
D10
<OVRD>
OVER-RIDE
BITE
D9
D8
0
0
D7
D6
BYTE-WISE
OR
BIT-WISE
MSB OR
LSB FIRST
D5
D4
D3
D2
D1
D0
<COARSE
GAIN>
COARSE
GAIN
ENABLE
FALLING OR
RISING BIT
CLOCK
CAPTURE
EDGE
0
14-BIT OR
16-BIT
SERIALIZE
DDR OR
SDR BIT
CLOCK
1-WIRE OR
2-WIRE
INTERFACE
After a hardware or software reset, all register bits are cleared to 0.
D0
Interface selection
0
1 Wire interface
1
2 Wire interface
D1
Bit clock selection (only in 2-wire interface)
0
DDR Bit clock
1
SDR Bit clock
D2
Serialization selection
0
12x Serialization
1
14x Serialization
18
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D4
Bit clock capture edge (only when SDR bit clock is selected, D1 = 1)
0
Capture data with falling edge of bit clock
1
Capture data with rising edge of bit clock
D5
<COARSE GAIN> Coarse gain control
0
0 dB coarse gain
1
3.5dB coarse gain (full-scale range = 1.34 VPP)
D6
MSB or LSB first selection
0
MSB First
1
LSB First
D7
Byte/bit wise outputs (only when 2-wire is selected)
0
Byte wise
1
Bit wise
D10
<OVRD> Over-ride bit. All the functions in register 0x0D can also be controlled using the
parallel control pins. By setting bit <OVRD> = 1, the contents of register 0x0D will over-ride
the settings of the parallel pins.
0
Disable over-ride
1
Enable over-ride
Table 17. Serial Register G (1)
REGISTER
ADDRESS
A4 - A0
10
(1)
BITS
D10
D9
D8
D7
D6
D5
<TERM CLK>
LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS
D4
D3
D2
<LVDS CURR>
LVDS CURRENT SETTINGS
D1
D0
<LVDS DOUBLE>
LVDS CURRENT DOUBLE
After a hardware or software reset, all register bits are cleared to 0.
D0
<CURR DOUBLE> LVDS current double for data outputs
0
Nominal LVDS current, as set by <D5…D2>
1
Double the nominal value
D1
<CURR DOUBLE> LVDS current double for bit and word clock outputs
0
Nominal LVDS current, as set by <D5…D2>
1
Double the nominal value
D3-D2
<LVDS CURR> LVDS current setting for data outputs
00
3.5 mA
01
4 mA
10
2.5 mA
11
3 mA
D5-D4
<LVDS CURR> LVDS current setting for bit and word clock outputs
00
3.5 mA
01
4 mA
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10
2.5 mA
11
3 mA
D10-D6
<TERM CLK> LVDS internal termination for bit and word clock outputs
00000
No internal termination
00001
166 Ω
00010
200 Ω
00100
250 Ω
01000
333 Ω
10000
500 Ω
Any combination of above bits can also be programmed, resulting in a parallel combination of
the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω
100 Ω
00101
Table 18. Serial Register H (1)
REGISTER
ADDRESS
A4 - A0
D10
11
(1)
BITS
D9
WORD-WISE CONTROL
D8
0
D7
0
D6
D5
0
0
D4
D3
D2
D1
D0
<TERM DATA>
LVDS INTERNAL TERMINATION - DATA OUTPUTS
After a hardware or software reset, all register bits are cleared to 0.
D4-D0
<TERM DATA> LVDS internal termination for data outputs
00000
No internal termination
00001
166 Ω
00010
200 Ω
00100
250 Ω
01000
333 Ω
10000
500 Ω
Any combination of above bits can also be programmed, resulting in a parallel combination
of the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω
00101
100 Ω
D10-D9
Only when 2-wire interface is selected
00
Byte-wise or bit-wise output, 1x frame clock
11
Word-wise output enabled, 0.5x frame clock
01,10
Do not use
20
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PIN CONFIGURATION (2-WIRE INTERFACE)
LVDD
DC1_P
DC1_M
DC0_P
DC0_M
LGND
FCLKP
FCLKM
DCLKP
DCLKM
LGND
DB1_P
DB1_M
DB0_P
DB0_M
LVDD
RGC PACKAGE
(TOP VIEW)
DA1_P
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
DD0_M
DA1_M
2
47
DD0_P
DA0_P
3
46
DD1_M
DA0_M
4
45
DD1_P
CAP
5
44
SCLK
RESET
6
43
SDATA
LVDD
7
42
SEN
AGND
8
41
PDN
ADS6425
AGND
13
36
AGND
INB_M
14
35
INC_M
INB_P
15
34
INC_P
AGND
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AGND
AVDD
IND_P
AGND
37
CFG1
12
CFG2
INA_P
CFG3
IND_M
AVDD
38
AGND
11
CLKM
INA_M
CLKP
AGND
AGND
39
VCM
10
CFG4
AGND
NC
AVDD
AVDD
40
AGND
9
AVDD
AVDD
P0056-02
PIN ASSIGNMENTS (2-WIRE INTERFACE)
PINS
NAME
NO.
I/O
NO. OF
PINS
DESCRIPTION
SUPPLY AND GROUND PINS
AVDD
9,17,19,27,32,40,
6
Analog power supply
AGND
8,10,13,16,18,23,26,
31,33
36,39,
11
Analog ground
LVDD
7,49,64
3
Digital power supply
LGND
54,59
2
Digital ground
INPUT PINS
CLKP, CLKM
24,25
I
2
Differential input clock pair
INA_P, INA_M
12,11
I
2
Differential input signal pair, channel A. If unused, the pins should be tied to
VCM and not floated.
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PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued)
PINS
NAME
NO.
I/O
NO. OF
PINS
DESCRIPTION
INB_P, INB_M
15,14
I
2
Differential input signal pair, channel B. If unused, the pins should be tied to
VCM and not floated.
INC_P, INC_M
34,35
I
2
Differential input signal pair, channel C. If unused, the pins should be tied to
VCM and not floated.
IND_P, IND_M
37,38
I
2
Differential input signal pair, channel D. If unused, the pins should be tied to
VCM and not floated.
1
Connect 2nF capacitor from pin to ground
CAP
5
SCLK
44
I
1
This pin functions as serial interface clock input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN
modes (along with SDATA). See Table 3 for description.
This pin has an internal pull-down resistor.
SDATA
43
I
1
This pin functions as serial interface data input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN
modes (along with SCLK). See Table 3 for description.
This pin has an internal pull-down resistor.
SEN
42
I
1
This pin functions as serial interface enable input when RESET is low.
When RESET is high, it controls coarse gain and internal/external reference
modes. See Table 4 for description.
This pin has an internal pull-up resistor.
Serial interface reset input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin or by using
software reset option. Refer to the Serial Interface section. In parallel interface
mode, tie RESET permanently high. (SCLK, SDATA and SEN function as
parallel control pins in this mode).
RESET
6
I
1
PDN
41
I
1
Global power down control pin.
CFG1
30
I
1
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock
selection. See Table 6 for description.
Tie to AVDD for 2-wire interface with DDR bit clock.
CFG2
29
I
1
Parallel input pin. It controls 12x or 14x serialization and SDR bit clock capture
edge. See Table 7 for description.
For 12x serialization with DDR bit clock, tie to ground or AVDD.
CFG3
28
I
1
RESERVED pin - Tie to ground.
CFG4
21
I
1
Parallel input pin. It controls data format and MSB or LSB first modes. See
Table 9 for description.
VCM
22
I/O
1
Internal reference mode – common-mode voltage output
External reference mode – reference input. The voltage forced on this pin sets
the internal reference.
DA0_P,DA0_M
3,4
O
2
Channel A differential LVDS data output pair, wire 0
DA1_P,DA1_M
1,2
O
2
Channel A differential LVDS data output pair, wire 1
DB0_P,DB0_M
62,63
O
2
Channel B differential LVDS data output pair, wire 0
DB1_P,DB1_M
60,61
O
2
Channel B differential LVDS data output pair, wire 1
DC0_P,DC0_M
52,53
O
2
Channel C differential LVDS data output pair, wire 0
DC1_P,DC1_M
50,51
O
2
Channel C differential LVDS data output pair, wire 1
DD0_P,DD0_M
47,48
O
2
Channel D differential LVDS data output pair, wire 0
DD1_P,DD1_M
45,46
O
2
Channel D differential LVDS data output pair, wire 1
DCLKP,DCLKM
57,58
O
2
Differential bit clock output pair
FCLKP,FCLKM
55,56
O
2
Differential frame clock output pair
1
Do Not Connect
The pin has an internal pull-down resistor to ground.
OUTPUT PINS
NC
22
20
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PIN CONFIGURATION (1-WIRE INTERFACE)
LVDD
DD_P
DD_M
DC_P
DC_M
LGND
FCLKP
FCLKM
DCLKP
DCLKM
LGND
DB_P
DB_M
DA_P
DA_M
LVDD
RGC PACKAGE
(TOP VIEW)
UNUSED
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
UNUSED
UNUSED
2
47
UNUSED
UNUSED
3
46
UNUSED
UNUSED
4
45
UNUSED
CAP
5
44
SCLK
RESET
6
43
SDATA
LVDD
7
42
SEN
AGND
8
41
PDN
ADS6425
IND_P
AGND
13
36
AGND
INB_M
14
35
INC_M
INB_P
15
34
INC_P
AGND
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AGND
AGND
AVDD
37
CFG1
12
CFG2
INA_P
CFG3
IND_M
AVDD
38
AGND
11
CLKM
INA_M
CLKP
AGND
AGND
39
VCM
10
CFG4
AGND
NC
AVDD
AVDD
40
AGND
9
AVDD
AVDD
P0056-03
PIN ASSIGNMENTS (1-WIRE INTERFACE)
PINS
NAME
NO.
I/O
NO. OF
PINS
DESCRIPTION
SUPPLY AND GROUND PINS
AVDD
9,17,19,27,32,40,
6
Analog power supply
AGND
8,10,13,16,18,23,26,
31,33
36,39,
11
Analog ground
LVDD
7,49,64
3
Digital power supply
LGND
54,59
2
Digital ground
INPUT PINS
CLKP, CLKM
24,25
I
2
Differential input clock pair
INA_P, INA_M
12,11
I
2
Differential input signal pair, channel A. If unused, the pins should be tied to
VCM and not floated.
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PIN ASSIGNMENTS (1-WIRE INTERFACE) (continued)
PINS
NAME
NO.
I/O
NO. OF
PINS
DESCRIPTION
INB_P, INB_M
15,14
I
2
Differential input signal pair, channel B. If unused, the pins should be tied to
VCM and not floated.
INC_P, INC_M
34,35
I
2
Differential input signal pair, channel C. If unused, the pins should be tied to
VCM and not floated.
IND_P, IND_M
37,38
I
2
Differential input signal pair, channel D. If unused, the pins should be tied to
VCM and not floated.
1
Connect 2nF capacitance from pin to ground
CAP
5
SCLK
44
I
1
This pin functions as serial interface clock input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN
modes (along with SDATA). See Table 3 for description.
This pin has an internal pull-down resistor.
SDATA
43
I
1
This pin functions as serial interface data input when RESET is low.
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN
modes (along with SCLK). See Table 3 for description.
This pin has an internal pull-down resistor.
SEN
42
I
1
This pin functions as serial interface enable input when RESET is low.
When RESET is high, it controls coarse gain and internal/external reference
modes. See Table 4 for description.
This pin has an internal pull-up resistor.
Serial interface reset input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin or by using
software reset option. Refer to the Serial Interface section. In parallel interface
mode, tie RESET permanently high. (SCLK, SDATA and SEN function as
parallel control pins in this mode).
RESET
6
I
1
PDN
41
I
1
Global power down control pin.
CFG1
30
I
1
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock
selection. See Table 6 for description.
Tie to ground for 1-wire interface with DDR bit clock.
CFG2
29
I
1
Parallel input pin. It controls 12x or 14x serialization and SDR bit clock capture
edge. See Table 7 for description.
For 12x serialization with DDR bit clock, tie to ground or AVDD.
CFG3
28
I
1
RESERVED pin - Tie to ground.
CFG4
21
I
1
Parallel input pin. It controls data format and MSB or LSB first modes. See
Table 9 for description.
VCM
22
I/O
1
Internal reference mode – common-mode voltage output
External reference mode – reference input. The voltage forced on this pin sets
the internal reference.
DA_P,DA_M
62,63
O
2
Channel A differential LVDS data output pair
DB_P,DB_M
60,61
O
2
Channel B differential LVDS data output pair
DC_P,DC_M
52,53
O
2
Channel C differential LVDS data output pair
DD_P,DD_M
50,51
O
2
Channel D differential LVDS data output pair
DCLKP,DCLKM
57,58
O
2
Differential bit clock output pair
FCLKP,FCLKM
55,56
O
2
Differential frame clock output pair
1-4,45-48
8
These pins are unused in the 1-wire interface. Do not connect
20
1
Do not connect
The pin has an internal pull-down resistor to ground.
OUTPUT PINS
UNUSED
NC
24
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TYPICAL CHARACTERISTICS
All plots are at 25°C, AVDD = LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32K point FFT
(unless otherwise noted)
FFT for 10 MHz INPUT SIGNAL
FFT for 50 MHz INPUT SIGNAL
0
SFDR = 91 dBc
SINAD = 71.35 dBFS
SNR = 71.41 dBFS
THD = 89.5 dBc
−20
SFDR = 85.8 dBc
SINAD = 70.7 dBFS
SNR = 70.9 dBFS
THD = 84.4 dBc
−20
−40
Amplitude − dB
−40
Amplitude − dB
0
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
50
60
f − Frequency − MHz
0
10
20
30
G001
Figure 6.
FFT for 100 MHz INPUT SIGNAL
60
G002
FFT for 170 MHz INPUT SIGNAL
0
SFDR = 86.7 dBc
SINAD = 69.9 dBFS
SNR = 70.1 dBFS
THD = 82.7 dBc
−20
SFDR = 79.9 dBc
SINAD = 68.2 dBFS
SNR = 68.8 dBFS
THD = 78.2 dBc
−20
−40
Amplitude − dB
−40
Amplitude − dB
50
Figure 7.
0
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
50
60
f − Frequency − MHz
0
10
20
30
40
50
60
f − Frequency − MHz
G003
G004
Figure 8.
Figure 9.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
0
SFDR = 79.2 dBc
SINAD = 67.4 dBFS
SNR = 68 dBFS
THD = 77.9 dBc
−20
fIN1 = 46.1 MHz, –7 dBFS
fIN2 = 50.1 MHz, –7 dBFS
2-Tone IMD = –90.2 dBFS
SFDR = –98.8 dBFS
−20
−40
Amplitude − dB
−40
Amplitude − dB
40
f − Frequency − MHz
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
f − Frequency − MHz
50
60
0
G005
Figure 10.
10
20
30
40
50
f − Frequency − MHz
60
G006
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32K point FFT
(unless otherwise noted)
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
SFDR vs INPUT FREQUENCY
90
0
fIN1 = 185.1 MHz, –7 dBFS
fIN2 = 190.1 MHz, –7 dBFS
2-Tone IMD = –81 dBFS
SFDR = –91 dBFS
−20
86
84
SFDR − dBc
Amplitude − dB
−40
88
−60
−80
−100
82
Gain = 3.5 dB
80
78
−120
76
−140
74
−160
72
0
10
20
30
40
50
0
60
f − Frequency − MHz
Gain = 0 dB
50
100
150
200
250
fIN − Input Frequency − MHz
G021
Figure 12.
G007
Figure 13.
SNR vs INPUT FREQUENCY
SFDR vs INPUT FREQUENCY ACROSS GAINS
72
92
Input adjusted to get −1dBFS input
3 dB
90
71
70
Gain = 0 dB
69
68
5 dB
86
SFDR − dBc
SNR − dBFS
88
4 dB
84
82
80
Gain = 3.5 dB
6 dB
2 dB
78
67
76
66
0 dB
0
50
100
150
200
250
fIN − Input Frequency − MHz
10
30
50
70
SINAD vs INPUT FREQUENCY ACROSS GAINS
4 dB
88
76
86
75
SFDR
84
74
69
3 dB
3.5 dB
1 dB
68
67
82
73
80
72
SNR
78
71
76
66
70
fIN = 50.1 MHz
LVDD = 3.3 V
74
6 dB
5 dB
65
20
40
60
80
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
72
3.0
SNR − dBFS
2 dB
SFDR − dBc
SINAD − dBFS
G009
PERFORMANCE vs AVDD
0 dB
70
110 130 150 170 190 210 230
Figure 15.
72
71
90
fIN − Input Frequency − MHz
G008
Figure 14.
3.1
G010
Figure 16.
26
1 dB
74
3.2
3.3
3.4
AVDD − Supply Voltage − V
3.5
69
68
3.6
G011
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32K point FFT
(unless otherwise noted)
PERFORMANCE vs LVDD
PERFORMANCE vs TEMPERATURE
98
86
73
fIN = 50.1 MHz
AVDD = 3.3 V
94
74
84
72
73
86
70
SFDR
82
69
82
72
80
SNR − dBFS
71
SFDR − dBc
SNR
90
SNR − dBFS
SFDR − dBc
SFDR
71
SNR
78
70
76
69
fIN = 50.1 MHz
3.1
3.2
3.3
3.4
68
3.6
3.5
LVDD − Supply Voltage − V
74
−40
68
−20
0
20
PERFORMANCE vs INPUT AMPLITUDE
75
90
74
88
73
SNR (dBFS)
72
60
71
50
30
−60
−50
−40
fIN = 20 MHz
−30
−20
−10
SFDR − dBc
80
92
SNR − dBFS
SFDR − dBc, dBFS
SFDR (dBFS)
90
SFDR (dBc)
G013
PERFORMANCE vs CLOCK AMPLITUDE
76
40
80
Figure 19.
110
70
60
T − Temperature − °C
G012
Figure 18.
100
40
74
fIN = 50.1 MHz
72
SNR
86
70
82
69
SFDR
80
69
78
68
76
0.5
Input Amplitude − dBFS
71
84
70
0
73
SNR − dBFS
78
3.0
68
67
1.0
1.5
2.0
66
3.0
2.5
Input Clock Amplitude − VPP
G014
Figure 20.
G015
Figure 21.
PERFORMANCE vs CLOCK DUTY CYCLE
POWER DISSIPATION vs SAMPLING FREQUENCY
90
77
89
75
2.0
88
73
87
71
86
69
SNR
85
SNR − dBFS
SFDR − dBc
SFDR
67
1.4
1.2
1.0
AVDD
0.8
0.6
LVDD
0.4
0.0
65
40
1.6
0.2
fIN = 20.1 MHz
84
35
PD − Power Dissipation − W
1.8
45
50
55
Input Clock Duty Cycle − %
60
0
65
G020
Figure 22.
25
50
75
100
fS − Sampling Frequency − MSPS
125
G016
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32K point FFT
(unless otherwise noted)
OUTPUT NOISE HISTOGRAM WITH
INPUTS TIED TO COMMON-MODE
PERFORMANCE IN EXTERNAL REFERENCE MODE
80
94
73
fIN = 50.1 MHz
External Reference Mode
RMS (LSB) = 0.407
70
SFDR − dBc
Occurence − %
50
40
30
72
90
71
SNR
88
70
SNR − dBFS
92
60
SFDR
20
86
69
10
0
2044
2045
2046
2047
2048
2049
84
1.30
2050
Output Code
1.35
1.40
1.45
1.50
1.55
VVCM − VCM Voltage − V
G017
Figure 24.
1.60
1.65
68
1.70
G018
Figure 25.
CMRR − Common−Mode Rejection Ratio − dBc
CMRR
vs
FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
50
100
150
200
f − Frequency − MHz
250
300
G019
Figure 26.
28
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32K point FFT
(unless otherwise noted)
125
120
fS - Sampling Frequency - MSPS
110
70
69.5
69
68.5
70.5
71
100
70.5
71
90
70.5
70
80
69.5
69
70
68.5
60
67.5
50
71
40
10
20
40
68
70.5
60
80
100
69
69.5
70
120
140
160
68.5
180
200
220 230
fIN - Input Frequency - MHz
66
67
68
69
70
71
72
73
74
SNR - dBFS
75
M0048-12
Figure 27. SNR Contour
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = LVDD = 3.3 V, sampling frequency = 125 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, 32K point FFT
(unless otherwise noted)
125
77
120
83
80
fS - Sampling Frequency - MSPS
110
100
89
90
86
86
86
83
80
89
92
83
70
60
86
89
50
83
92
40
10
20
40
80
60
100
120
140
160
180
200
220 230
92
94
fIN - Input Frequency - MHz
74
76
78
80
82
84
86
SFDR - dBc
88
90
95
M0049-12
Figure 28. SFDR Contour
30
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS6425 is a quad channel, 12-bit, 125-MSPS, pipeline ADC, based on switched capacitor architecture in
CMOS technology.
The conversion is initiated simultaneously by all the four channels at the rising edge of the external input clock.
After the input signals are captured by the sample and hold circuit of each channel, the samples are sequentially
converted by a series of low resolution stages. The stage outputs are combined in a digital correction logic block
to form the final 12-bit word with a latency of 12 clock cycles. The 12-bit word of each channel is serialized and
output as LVDS levels. In addition to the data streams, a bit clock and a frame clock are also output. The frame
clock is aligned with the 12-bit word boundary.
ANALOG INPUT
The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in
Figure 29. This differential topology results in very good AC performance even for high input frequencies. The
INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V, available on VCM pin
13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5 V
and VCM – 0.5 V, resulting in a 2-Vpp differential input swing. The maximum swing is determined by the internal
reference voltages REFP (2.0V nominal) and REFM (1.0 V, nominal). The sampling circuit has a 3 dB bandwidth
that extends up to 500 MHz (Figure 30, shown by the transfer function from the analog input pins to the voltage
across the sampling capacitors TF_ADC).
Sampling
Switch
Lpkg
3 nH
25 W
Sampling
Capacitor
RCR Filter
INP
Cbond
2 pF
50 W
Resr
200 W
Lpkg
3 nH
3.2 pF
Cpar2 Ron
1 pF 15 W
Csamp
4.0 pF
Cpar1
0.8 pF
Ron
10 W
50 W
Csamp
4.0 pF
Ron
15 W
25 W
INM
Cpar2
1 pF
Cbond
2 pF
Resr
200 W
Sampling
Capacitor
Sampling
Switch
S0237-01
Figure 29. Input Sampling Circuit
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1
0
Magnitude − dB
−1
−2
−3
−4
−5
−6
0
100
200
300
400
500
600
fIN − Input Frequency − MHz
700
G022
Figure 30. Analog Input Bandwidth (represented by magnitude of TF_ADC, see Figure 31)
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection.
A 5-Ω resistor in series with each input pin is recommended to damp out ringing caused by the package
parasitics. It is also necessary to present low impedance (< 50 Ω) for the common mode switching currents. For
example, this is achieved by using two resistors from each input terminated to the common mode voltage (VCM).
Using RF-Transformer Based Drive Circuits
Figure 31 shows a configuration using a single 1:1 turns ratio transformer (for example, WBC1-1) that can be
used for low input frequencies up to 100MHz.
The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated on the
secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by the
sampling circuit from the RF transformer’s leakage inductances. The termination is accomplished by two resistors
connected in series, with the center point connected to the 1.5 V common mode (VCM pin). The value of the
termination resistors (connected to common mode) has to be low (< 100 Ω) to provide a low-impedance path for
the ADC common-mode switching current.
TF_ADC
0.1 mF
ADS6xxx
5W
INP
0.1 mF
25 W
25 W
INM
1:1
5W
VCM
S0256-01
Figure 31. Single Transformer Drive Circuit
At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results
32
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in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps
minimize this mismatch, and good performance is obtained for high frequency input signals. Figure 32 shows an
example using two transformers (Coilcraft WBC1-1). An additional termination resistor pair (enclosed within the
shaded box in Figure 32) may be required between the two transformers to improve the balance between the P
and M sides. The center point of this termination must be connected to ground.
ADS6xxx
0.1 mF
5W
INP
50 W
0.1 mF
50 W
50 W
50 W
INM
1:1
1:1
5W
VCM
S0164-04
Figure 32. Two Transformer Drive Circuit
INPUT COMMON MODE
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-µF low-inductance capacitor
connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC
sinks a common-mode current in the order of 155 µA at 125 MSPS (per input pin). Equation 1 describes the
dependency of the common-mode current and the sampling frequency.
155 mAxFs
125 MSPS
(1)
This equation helps to design the output capability and impedance of the CM driving circuit accordingly.
REFERENCE
The ADS6425 has built-in internal references REFP and REFM, requiring no external components. Design
schemes are used to linearize the converter load seen by the references; this and the on-chip integration of the
requisite reference capacitors eliminates the need for external decoupling. The full-scale input range of the
converter can be controlled in the external reference mode as explained below. The internal or external reference
modes can be selected by programming the register bit <REF> (Table 11).
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INTREF
Internal
Reference
VCM
1 kW
INTREF
4 kW
EXTREF
REFM
REFP
ADS6xxx
S0165-04
Figure 33. Reference Section
Internal Reference
When the device is in internal reference mode, the REFP and REFM voltages are generated internally.
Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog
input pins.
External Reference
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the
VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential
input voltage corresponding to full-scale is given by Equation 2.
Full−scale differential input pp + (Voltage forced on VCM) 1.33
(2)
In this mode, the range of voltage applied on VCM pin should be 1.45 to 1.55V. The 1.5-V common-mode
voltage to bias the input pins has to be generated externally.
COARSE GAIN AND PROGRAMMABLE FINE GAIN
The ADS6425 includes gain settings that can be used to get improved SFDR performance (compared to 0 dB
gain mode). The gain settings are 3.5 dB coarse gain and programmable fine gain from 0 dB to 6 dB. For each
gain setting, the analog input full-scale range scales proportionally, as shown in Table 19.
The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR (as
seen in Figure 13 andFigure 14). The fine gain is programmable in 1 dB steps from 0 to 6 dB. With the fine gain
also, SFDR improvement is achieved, but at the expense of SNR (there will be about 1dB SNR degradation for
every 1dB of fine gain).
So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get
best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the
SFDR improvement is significant with marginal degradation in SINAD.
The gains can be programmed using the register bits <COARSE GAIN> (Table 16) and <FINE GAIN>
(Table 15). Note that the default gain after reset is 0 dB.
34
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Table 19. Full-Scale Range Across Gains
GAIN, dB
TYPE
0
Default (after reset)
FULL-SCALE, Vpp
2
3.5
Coarse setting (fixed)
1.34
1
1.78
2
1.59
3
1.42
Fine setting
(programmable)
4
1.26
5
1.12
6
1.00
CLOCK INPUT
The ADS6425 clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
VCM using internal 5-kΩ resistors as shown in Figure 34. This allows using transformer-coupled drive circuits for
sine wave clock or ac-coupling for LVPECL, LVDS clock sources (see Figure 35 and Figure 37).
VCM
VCM
5 kW
5 kW
CLKP
CLKM
ADS6xxx
S0166-04
Figure 34. Internal Clock Buffer
0.1 mF
CLKP
Differential Sine-Wave
or PECL or LVDS Clock Input
0.1 mF
CLKM
ADS6xxx
S0167-05
Figure 35. Differential Clock Driving Circuit
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Figure 36 shows a typical scheme using PECL clock drive from a CDCM7005 clock driver. SNR performance
with this scheme is comparable with that of a low jitter sine wave clock source.
VCC
Reference Clock
REF_IN
VCC
Y0
CLKP
Y0B
CLKM
CDCM7005
VCXO_INP
OUTM
VCXO_INM
CP_OUT
ADS6xxx
VCXO
OUTP
CTRL
S0238-02
Figure 36. PECL Clock Drive Using CDCM7005
Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin) connected to ground with a
0.1-µF capacitor, as shown in Figure 37.
0.1 mF
CMOS Clock Input
CLKP
0.1 mF
CLKM
ADS6xxx
S0168-07
Figure 37. Single-Ended Clock Driving Circuit
For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode
noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a
non-50% duty cycle clock input.
CLOCK BUFFER GAIN
When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is
increased. Hence, it is recommended to use large clock amplitude. As shown by Figure 21, use clock amplitude
greater than 1V pp to avoid performance degradation.
In addition, the clock buffer has programmable gain to amplify the input clock to support very low clock
amplitude. The gain can be set by programming the register bits <CLKIN GAIN> (Table 12) and increases
monotonically from Gain 0 to Gain 5 settings. Table 20 shows the minimum clock amplitude supported for each
gain setting.
36
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Table 20. Minimum Clock Amplitude Across Gains
CLOCK BUFFER GAIN
MINIMUM CLOCK AMPLITUDE SUPPORTED, mV (pp differential)
Gain 0 (minimum gain)
800
Gain 1 (default gain)
400
Gain 2
300
Gain 3
200
Gain 4
150
Gain 5 (highest gain)
100
POWER DOWN MODES
The ADS6425 has three power down modes – global power down, channel standby and input clock stop.
Global Power Down
This is a global power down mode in which almost the entire chip is powered down, including the four ADCs,
internal references, PLL and LVDS buffers. As a result, the total power dissipation falls to about 77 mW typical
(with input clock running). This mode can be initiated by setting the register bit <PDN GLOBAL> (Table 11). The
output data and clock buffers are in high impedance state.
The wake-up time from this mode to data becoming valid in normal mode is 100 µs.
Channel Standby
In this mode, only the ADC of each channel is powered down and this helps to get very fast wake-up times. Each
of the four ADCs can be powered down independently using the register bits <PDN CH> (Table 11). The analog
power dissipation varies from 1115 mW (only one channel in standby) to 245 mW (all four channels in standby).
The output LVDS buffers remain powered up.
The wake-up time from this mode to data becoming valid in normal mode is 200 clock cycles.
Input Clock Stop
The converter enters this mode:
• If the input clock frequency falls below 1 MSPS or
• If the input clock amplitude is less than 400 mV (pp, differential with default clock buffer gain setting) at any
sampling frequency.
All ADCs and LVDS buffers are powered down and the power dissipation is about 235 mW. The wake-up time
from this mode to data becoming valid in normal mode is 100 µs.
Table 21. Power Down Modes Summary
POWER DOWN MODE
AVDD POWER
(mW)
LVDD POWER
(mW)
WAKE UP TIME
In power-up
1360
297
–
Global power down
65
12
100 µs
1 Channel in standby
1115
297
200 Clocks
2 Channels in standby
825
297
200 Clocks
3 Channels in standby
532
297
200 Clocks
4 Channels in standby
245
297
200 Clocks
Input clock stop
200
35
100 µs
POWER SUPPLY SEQUENCING
During power-up, the AVDD and LVDD supplies can come up in any sequence. The two supplies are separated
inside the device. Externally, they can be driven from separate supplies or from a single supply.
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DIGITAL OUTPUT INTERFACE
The ADS6425 offers several flexible output options making it easy to interface to an ASIC or an FPGA. These
options can be easily programmed using either parallel pins and/or the serial interface.
The output interface options are:
• 1-wire, 1× frame clock, 12× and 14× serialization with DDR bit clock
• 2-wire, 1× frame clock, 12× serialization, with DDR and SDR bit clock, byte wise/bit wise/word wise
• 2-wire, 1× word clock, 14× serialization, with SDR bit clock, byte wise/bit wise/word wise
• 2-wire, (0.5 x) frame clock, 14× serialization, with DDR bit clock, byte wise/bit wise/word wise.
The maximum sampling frequency, bit clock frequency and output data rate will vary depending on the interface
options selected (refer to Table 12).
Table 22. Maximum Recommended Sampling Frequency for Different Output Interface Options
INTERFACE OPTIONS
MAXIMUM
RECOMMENDED
SAMPLING
FREQUENCY,
MSPS
BIT CLOCK
FREQUENCY,
MHZ
FRAME CLOCK
FREQUENCY, MHZ
SERIAL DATA RATE,
Mbps
1-Wire
DDR Bit
clock
12× Serialization
65
390
65
780
14× Serialization
65
455
65
910
2-Wire
DDR Bit
clock
12× Serialization
125
375
125
750
14× Serialization
125
437.5
62.5
875
SDR Bit
clock
12× Serialization
65
390
65
390
14× Serialization
65
455
65
455
2-Wire
Each interface option is described in detail below.
1-WIRE INTERFACE - 12× AND 14× SERIALIZATION WITH DDR BIT CLOCK
Here the device outputs the data of each ADC serially on a single LVDS pair (1-wire). The data is available at the
rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at the rising edge of every
frame clock, starting with the MSB. Optionally, it can also be programmed to output the LSB first. The data rate is
12 × Sample frequency (12× serialization) and 14 × Sample frequency (14× serialization).
38
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Input Clock,
CLK
Freq = Fs
14-Bit Serialization
(1)
12-Bit Serialization
Frame Clock,
FCLK
Freq = 1 ´ Fs
Bit Clock,
DCLK
Freq = 6 ´ Fs
Output Data
DA, DB, DC, DD
Data Rate = 12 ´ Fs
D11
(D0)
D10
(D1)
D9
(D2)
D8
(D3)
D7
(D4)
D6
(D5)
D5
(D6)
D7
(D6)
D6
(D7)
D4
(D7)
D3
(D8)
D2
(D9)
D1
(D10)
D0
(D11)
D11
(D0)
D0
(0)
0
(D0)
D10
(D1)
Bit Clock,
DCLK
Freq = 7 ´ Fs
Output Data
DA, DB, DC, DD
Data Rate = 14 ´ Fs
0
(D0)
0
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D5
(D8)
D4
(D9)
D3
D2
(D10) (D11)
D1
(0)
Sample N
0
(D1)
Sample N + 1
Data Bit in MSB First Mode
D13
(D2)
Data Bit in LSB First Mode
(1)
In 14-Bit serialization, two zero bits are padded to the 12-bit ADC data on the MSB side.
T0225-01
Figure 38. 1-Wire Interface
2-WIRE INTERFACE - 12× SERIALIZATION WITH DDR/SDR BIT CLOCK
The 2-wire interface is recommended for sampling frequencies above 65 MSPS. The device outputs the data of
each ADC serially on two LVDS pairs (2-wire). The data rate is 6 × Sample frequency since 6 bits are sent on
each wire every clock cycle. The data is available along with DDR bit clock or optionally with SDR bit clock. Each
ADC sample is sent over the 2 wires as byte-wise or bit-wise or word-wise.
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Input Clock,
CLK
Freq = Fs
Frame Clock,
FCLK
Freq = 1 ´ Fs
Bit Clock – SDR,
DCLK
Freq = 6 ´ Fs
In Byte-Wise Mode
Bit Clock – DDR,
DCLK
Freq = 3 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D5
(D0)
D4
(D1)
D3
(D2)
D2
(D3)
D1
(D4)
D0
(D5)
D5
(D0)
D4
(D1)
D3
(D2)
D2
(D3)
D1
(D4)
D0
(D5)
Output Data
DA1, DB1, DC1, DD1
D11
(D6)
D10
(D7)
D9
(D8)
D8
(D9)
D7
D6
D11
(D6)
D10
(D7)
D9
(D8)
D8
(D9)
D7
D6
(D10) (D11)
(D10) (D11)
D10
(D0)
D8
(D2)
D6
(D4)
D4
(D6)
D2
(D8)
(D10)
In Word-Wise Mode
In Bit-Wise Mode
Data Rate = 6 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D10
(D0)
D8
(D2)
D6
(D4)
D4
(D6)
D2
(D8)
(D10)
Output Data
DA1, DB1, DC1, DD1
D11
(D1)
D9
(D3)
D7
(D5)
D5
(D7)
D3
(D9)
(D11)
D11
(D1)
D9
(D3)
D7
(D5)
D5
(D7)
D3
(D9)
(D11)
Output Data
DA0, DB0, DC0, DD0
D11
(D0)
D10
(D1)
D9
(D2)
D8
(D3)
D7
(D4)
D6
(D5)
D5
(D6)
D4
(D7)
D3
(D8)
D2
(D9)
D1
D0
(D10) (D11)
Output Data
DA1, DB1, DC1, DD1
D11
(D0)
D10
(D1)
D9
(D2)
D8
(D3)
D7
(D4)
D6
(D5)
D5
(D6)
D4
(D7)
D3
(D8)
D2
(D9)
(D10) (D11)
D0
D1
Data Bit in MSB First Mode
D1
D0
D1
D0
White Cells – Sample N
D5
(D0)
Data Bit in LSB First Mode
Grey Cells – Sample N + 1
T0226-01
A.
40
In the byte-wise and bit-wise modes, the frame clock frequency is 1 x Fs. In the word-wise mode, the frame clock
frequency is 0.5 x Fs.
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Figure 39. 2-Wire Interface 12× Serialization
2-WIRE INTERFACE - 14× SERIALIZATION
In 14× serialization, two zero bits are padded to the 12-bit ADC data on the MSB side and the combined 14-bit
data is serialized and output over two LVDS pairs. A frame clock at 1× sample frequency is also available with an
SDR bit clock. With DDR bit clock option, the frame clock frequency is 0.5× sample frequency. The output data
rate will be 7 × Sample frequency as 7 data bits are output every clock cycle on each wire. Each ADC sample is
sent over the 2 wires as byte-wise or bit-wise or word-wise.
Using the 14× serialization makes it possible to upgrade to a 14-bit ADC in the 64xx family in the future
seamlessly, without requiring any modification to the receiver capture logic design.
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Input Clock,
CLK
Freq = Fs
Frame Clock,
FCLK
Freq = 1 ´ Fs
In Byte-Wise Mode
Bit Clock – SDR,
DCLK
Freq = 7 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D6
(D0)
D5
(D1)
D4
(D2)
D3
(D3)
D2
(D4)
D1
(D5)
D0
(D6)
D6
(D0)
D5
(D1)
D4
(D2)
D3
(D3)
D2
(D4)
D1
(D5)
D0
(D6)
D6
(D0)
D5
(D1)
Output Data
DA1, DB1, DC1, DD1
0
(D7)
0
(D8)
D11
(D9)
D10
D9
D8
(0)
D7
(0)
0
(D7)
0
(D8)
D11
(D9)
D10
D9
(D10) (D11)
(D10) (D11)
D8
(0)
D7
(0)
0
(D7)
0
(D8)
D2
D0
(0)
0
(D0)
D10
(D2)
D8
(D4)
D6
(D6)
D4
(D8)
D2
(D10)
D0
(0)
0
(D0)
D10
(D2)
(D11)
D1
(0)
0
(D1)
D11
(D3)
D1
(0)
D0
(0)
0
(D0)
0
(D1)
D1
(0)
D0
(0)
0
(D0)
0
(D1)
In Word-Wise Mode
In Bit-Wise Mode
Data Rate = 7 ´ Fs
Output Data
DA0, DB0, DC0, DD0
0
(D0)
D10
(D2)
D8
(D4)
D6
(D6)
D4
(D8)
(D10)
Output Data
DA1, DB1, DC1, DD1
0
(D1)
D11
(D3)
D9
(D5)
D7
(D7)
D5
(D9)
(D11)
D1
(0)
0
(D1)
D11
(D3)
D9
(D5)
D7
(D7)
D5
(D9)
Output Data
DA0, DB0, DC0, DD0
0
(D0)
0
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D5
(D8)
D4
(D9)
D3
D2
(D10) (D11)
Output Data
DA1, DB1, DC1, DD1
0
(D0)
0
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D5
(D8)
D4
(D9)
(D10) (D11)
D3
Data Bit in MSB First Mode
D3
D2
D3
White Cells – Sample N
D6
(D0)
Data Bit in LSB First Mode
Grey Cells – Sample N + 1
T0227-01
Figure 40. 2-Wire Interface 14× Serialization - SDR Bit Clock
42
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Input Clock,
CLK
Freq = Fs
Frame Clock,
FCLK
Freq = 0.5 ´ Fs
In Byte-Wise Mode
Bit Clock – DDR,
DCLK
Freq = 3.5 ´ Fs
Output Data
DA0, DB0, DC0, DD0
D6
(D0)
D5
(D1)
D4
(D2)
D3
(D3)
D2
(D4)
D1
(D5)
D0
(D6)
D6
(D0)
D5
(D1)
D4
(D2)
D3
(D3)
D2
(D4)
D1
(D5)
D0
(D6)
D6
(D0)
D5
(D1)
Output Data
DA1, DB1, DC1, DD1
0
(D7)
0
(D8)
D11
(D9)
D10
D9
D8
(0)
D7
(0)
0
(D7)
0
(D8)
D11
(D9)
D10
D9
(D10) (D11)
(D10) (D11)
D8
(0)
D7
(0)
0
(D7)
0
(D8)
D2
D0
(0)
0
(D0)
D10
(D2)
D8
(D4)
D6
(D6)
D4
(D8)
D2
(D10)
D0
(0)
0
(D0)
D10
(D2)
(D11)
D1
(0)
0
(D1)
D11
(D3)
D1
(0)
D0
(0)
0
(D0)
0
(D1)
D1
(0)
D0
(0)
0
(D0)
0
(D1)
In Word-Wise Mode
In Bit-Wise Mode
Data Rate = 7 ´ Fs
Output Data
DA0, DB0, DC0, DD0
0
(D0)
D10
(D2)
D8
(D4)
D6
(D6)
D4
(D8)
(D10)
Output Data
DA1, DB1, DC1, DD1
0
(D1)
D11
(D3)
D9
(D5)
D7
(D7)
D5
(D9)
(D11)
D1
(0)
0
(D1)
D11
(D3)
D9
(D5)
D7
(D7)
D5
(D9)
Output Data
DA0, DB0, DC0, DD0
0
(D0)
0
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D5
(D8)
D4
(D9)
D3
D2
(D10) (D11)
Output Data
DA1, DB1, DC1, DD1
0
(D0)
0
(D1)
D11
(D2)
D10
(D3)
D9
(D4)
D8
(D5)
D7
(D6)
D6
(D7)
D5
(D8)
D4
(D9)
(D10) (D11)
D3
Data Bit in MSB First Mode
D3
D2
D3
White Cells – Sample N
D6
(D0)
Data Bit in LSB First Mode
Grey Cells – Sample N + 1
T0228-01
Figure 41. 2-Wire Interface 14× Serialization - DDR Bit Clock
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OUTPUT BIT ORDER
In the 2-wire interface, three types of bit order are supported - byte-wise, bit-wise and word-wise.
Byte-wise: Each 12-bit sample is split across the 2 wires. Wires DA0, DB0, DC0 and DD0 carry the 6 LSB bits
D5-D0 and wires DA1, DB1, DC1 and DD1 carry the 6 MSB bits.
Bit-wise: Each 12-bit sample is split across the 2 wires. Wires DA0, DB0, DC0 and DD0 carry the 6 even bits
(D0,D2,D4..) and wires DA1, DB1, DC1 and DD1 carry the 6 odd bits (D1,D3,D5...).
Word-wise: In this case, all 12-bits of a sample are sent over a single wire. Successive samples are sent over
the 2 wires. For example sample N is sent on wires DA0, DB0, DC0 and DD0, while sample N+1 is sent over
wires DA1, DB1, DC1 and DD1. The frame clock frequency is 0.5x sampling frequency, with the rising edge
aligned with the start of each word.
MSB/LSB FIRST
By default after reset, the 12-bit ADC data is output serially with the MSB first (D11,D10,...D1,D0). The data can
be output LSB first also by programming the register bit <MSB_LSB_First>. In the 2-wire mode, the bit order in
each wire is flipped in the LSB first mode.
OUTPUT DATA FORMATS
Two output data formats are supported – 2s complement (default after reset) and offset binary. They can be
selected using the serial interface register bit <DF>. In the event of an input voltage overdrive, the digital outputs
go to the appropriate full-scale level. For a positive overdrive, the output code is 0xFFF in offset binary output
format, and 0x7FF in 2s complement output format. For a negative input overdrive, the output code is 0x000 in
offset binary output format and 0x800 in 2s complement output format.
LVDS CURRENT CONTROL
The default LVDS buffer current is 3.5 mA. With an external 100-Ω termination resistance, this develops
±350-mV logic levels at the receiver. The LVDS buffer currents can also be programmed to 2.5 mA, 3.0 mA and
4.5 mA using the register bits <LVDS CURR>. In addition, there exists a current double mode, where the LVDS
nominal current is doubled (register bits <CURR DOUBLE>, Table 17).
LVDS INTERNAL TERMINATION
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. Five termination resistances are available – 166, 200, 250, 333, and 500 Ω
(nominal with ±20% variation). Any combination of these terminations can be programmed; the effective
termination will be the parallel combination of the selected resistances. The terminations can be programmed
separately for the clock and data buffers (bits <TERM CLK> and <TERM DATA>, Table 18).
The internal termination helps to absorb any reflections from the receiver end, improving the signal integrity. This
makes it possible to drive up to 10 pF of load capacitance, compared to only 5 pF without the internal
termination.Figure 42 and Figure 43 show the eye diagram with 5 pF and 10 pF load capacitors (connected from
each output pin to ground).
With 100-Ω internal and 100-Ω external termination, the voltage swing at the receiver end will be halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode (bits <CURR DOUBLE>, Table 17).
44
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C001
Figure 42. LVDS Data Eye Diagram with 5-pF Load Capacitance (No Internal Termination)
C002
Figure 43. LVDS Data Eye Diagram with 10-pF Load Capacitance (100 Ω Internal Termination)
CAPTURE TEST PATTERNS
The ADS6425 outputs the bit clock (DCLK), positioned nearly at the center of the data transitions. It is
recommended to route the bit clock, frame clock and output data lines with minimum relative skew on the PCB.
This ensures sufficient setup/hold times for a reliable capture by the receiver.
The DESKEW is a 1010... or 0101... pattern output on the serial data lines that can be used to verify if the
receiver capture clock edge is positioned correctly. This may be useful in case there is some skew between
DCLK and serial data inside the receiver. Once deserialized, it is required to ensure that the parallel data is
aligned to the frame boundary. The SYNC test pattern can be used for this. For example, in the 1-wire interface,
the SYNC pattern is 6 '1's followed by 6 '0's (from MSB to LSB). This information can be used by the receiver
logic to shift the deserialized data till it matches the SYNC pattern.
In addition to DESKEW and SYNC, the ADS6425 includes other test patterns to verify correctness of the capture
by the receiver such as all zeros, all ones and toggle. These patterns are output on all four channel data lines
simultaneously. Some patterns like custom and sync are affected by the type of interface selected, serialization
and bit order.
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Table 23. Test Patterns
PATTERN
DESCRIPTION
All zeros
Outputs logic low.
All ones
Outputs logic high.
Toggle
Outputs toggle pattern - <D11-D0> alternates between 101010101010 and 010101010101 every clock cycle.
Custom
Outputs a 12-bit custom pattern. The 12-bit custom pattern can be specified into two serial interface registers.
In the 2-wire interface, each code is sent over the 2 wires depending on the serialization and bit order.
Sync
Deskew
Outputs a sync pattern.
Outputs deskew pattern. Either <D11-D0> = 101010101010 OR <D11-D0> = 010101010101 every clock cycle.
Table 24. SYNC Pattern
INTERFACE OPTION
1-Wire
2-Wire
46
SERIALIZATION
SYNC PATTERN ON EACH WIRE
12 X
MSB-111111000000-LSB
14 X
MSB-11111110000000-LSB
12 X
MSB-111000-LSB
14 X
MSB-1111000-LSB
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OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES
Setup, hold and other timing parameters are specified across sampling frequencies and for each type of output
interface in the tables below.
Table 26 to Table 29: Typical values are at 25°C, min and max values are across the full temperature range TMIN
= –40°C to TMAX = 85°C, AVDD = LVDD = 3.3 V, CL = 5 pF , IO = 3.5 mA, RL = 100 Ω , no internal termination,
unless otherwise noted.
Timing parameters are ensured by design and characterization and not tested in production.
Ts = 1/ Sampling frequency = 1/Fs
Table 25. Clock Propagation Delay and Serializer Latency for Different Interface Options
INTERFACE
SERIALIZATION
1-Wire with DDR bit clock
2-Wire with DDR bit clock
2-Wire with SDR bit clock
2-Wire with DDR bit clock
12X
tpd_clk = 0.5xTs + tdelay
14X
tpd_clk = 0.428xTs + tdelay
12X
(1)
0
tpd_clk = tdelay
1
tpd_clk = 0.5xTs + tdelay
0
2
(when tpd_clk ≥ Ts)
tpd_clk = 0.857xTs + tdelay
14X
2-Wire with SDR bit clock
(1)
SERIALIZER LATENCY
clock cycles
CLOCK PROPAGATION DELAY, tpd_clk
1
(when tpd_clk < Ts)
tpd_clk = 0.428xTs + tdelay
0
Note that the total latency = ADC latency + serializer latency. The ADC latency is 12 clocks.
Table 26. Timings for 1-Wire Interface
SERIALIZATION
12×
14×
DATA SETUP TIME, tsu
ns
DATA HOLD TIME, th
ns
SAMPLING
FREQUENCY
MSPS
MIN
TYP
MIN
TYP
65
0.4
0.6
0.5
0.7
40
0.8
1.0
0.9
1.1
20
1.6
2.0
1.8
2.2
10
3.5
4.0
3.5
4.2
MAX
65
0.3
0.5
0.4
0.6
40
0.65
0.85
0.7
0.9
20
1.3
1.65
1.6
1.9
10
3.2
3.5
3.2
3.6
tdelay
ns
MAX
MIN
TYP
MAX
Fs ≥ 40 MSPS
3
4
5
Fs < 40 MSPS
3
4.5
6
Fs ≥ 40 MSPS
3
4
5
Fs < 40 MSPS
3
4.5
6
Table 27. Timings for 2-Wire Interface, DDR Bit Clock
SERIALIZATION
12×
14×
DATA SETUP TIME, tsu
ns
DATA HOLD TIME, th
ns
SAMPLING
FREQUENCY
MSPS
MIN
TYP
MIN
TYP
105
0.55
0.75
0.6
0.8
92
0.65
0.85
0.7
0.9
80
0.8
1.0
0.8
1.05
65
0.9
1.2
1.0
1.3
40
1.7
2.0
1.1
2.1
105
0.45
0.65
0.5
0.7
92
0.55
0.75
0.6
0.8
80
0.65
0.85
0.7
0.9
65
0.8
1.1
0.8
1.1
40
1.4
1.7
1.5
1.9
MAX
tdelay
ns
MAX
MIN
TYP
3.4
4.4
Product Folder Link(s): ADS6425
5.4
Fs < 45 MSPS
3.7
5.2
6.7
Fs ≥ 45 MSPS
3
4
5
Fs < 45 MSPS
3
4.5
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MAX
Fs ≥ 45 MSPS
6
47
ADS6425
SLWS197B – MARCH 2007 – REVISED JUNE 2009 ......................................................................................................................................................... www.ti.com
Table 28. Timings for 2-Wire Interface, SDR Bit Clock
SERIALIZATION
12×
14×
DATA SETUP TIME, tsu
ns
DATA HOLD TIME, th
ns
SAMPLING
FREQUENCY
MSPS
MIN
TYP
MIN
TYP
65
1.0
1.2
1.1
1.3
40
1.8
2.0
1.9
2.1
20
3.9
4.1
3.8
4.1
10
8.2
8.4
7.8
8.2
65
0.8
1.0
1.0
1.2
40
1.5
1.7
1.6
1.8
20
3.4
3.6
3.3
3.5
10
6.9
7.2
6.6
6.9
MAX
tdelay
ns
MAX
MIN
TYP
MAX
Fs ≥ 40 MSPS
3.4
4.4
5.4
Fs < 40 MSPS
3.7
5.2
6.7
Fs ≥ 40 MSPS
3.4
4.4
5.4
Fs < 40 MSPS
3.7
5.2
6.7
Table 29. Output Jitter (applies to all interface options)
SAMPLING FREQUENCY
MSPS
BIT CLOCK JITTER, CYCLE-CYCLE
ps, peak-peak
MIN
≥ 65
48
TYP
MAX
350
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FRAME CLOCK JITTER, CYCLE-CYCLE
ps, peak-peak
MIN
TYP
MAX
75
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Product Folder Link(s): ADS6425
ADS6425
www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009
DEFINITION OF SPECIFICATIONS
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs.
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate – The maximum sampling rate at which certified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly
1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – The INL is the deviation of the ADC's transfer function from a best fit line
determined by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – The gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The
gain error is given as a percentage of the ideal input full-scale range.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC's actual average
idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation
of the parameter across the TMIN to TMAX range by the difference TMAX–TMIN.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),
excluding the power at DC and the first nine harmonics.
P
SNR + 10Log10 S
PN
(3)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
PS
SINAD + 10Log10
PN ) PD
(4)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's
full-scale range.
Effective Number of Bits (ENOB) – The ENOB is a measure of a converter’s performance as compared to the
theoretical limit based on quantization noise.
ENOB + SINAD * 1.76
6.02
(5)
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the
first nine harmonics (PD).
P
THD + 10Log10 S
PD
(6)
THD is typically given in units of dBc (dB to carrier).
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Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1
and f2) to the power of the worst spectral component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in
units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to
full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range.
DC Power Supply Rejection Ratio (DC PSRR) – The DC PSSR is the ratio of the change in offset error to a
change in analog supply voltage. The DC PSRR is typically given in units of mV/V.
AC Power Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the
supply voltage by the ADC. If ΔVsup is the change in supply voltage and ΔVout is the resultant change of the
ADC output code (referred to the input), then
PSRR + 20Log10 DVout , expressed in dBc
DVsup
(7)
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error for a 6 dB
overload on the analog inputs. A 6 dBFS sine wave input at Nyquist frequency is used as the test stimulus.
Common Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variations in the analog input
common-mode by the ADC. If ΔVcm_in is the change in the common-mode voltage of the input pins and ΔVout
is the resultant change of the ADC output code (referred to the input), then
CMRR + 20Log10 DVout , expressed in dBc
DVcm_in
(8)
50
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ADS6425
www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009
Changes from Revision A (October 2007) to Revision B ............................................................................................... Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Added Frame setup time to timing specifications .................................................................................................................. 7
Added Frame hold time to timing specifications .................................................................................................................... 7
Changed Figure 2 ................................................................................................................................................................. 8
Added (with 10% tolerance resistors) to USING PARALLEL INTERFACE CONTROL ONLY section................................. 9
Changed Figure 3 ............................................................................................................................................................... 10
Added voltage values to Table 6 ......................................................................................................................................... 11
Added voltage values to Table 7 ......................................................................................................................................... 11
Added voltage values to Table 9 ......................................................................................................................................... 12
Added note to Table 10 ....................................................................................................................................................... 15
Added 32K point FFT to typical characteristics conditions .................................................................................................. 25
Added 32K point FFT to typical characteristics conditions .................................................................................................. 26
Added 32K point FFT to typical characteristics conditions .................................................................................................. 27
Added 32K point FFT to typical characteristics conditions .................................................................................................. 28
Added 32K point FFT to typical characteristics conditions .................................................................................................. 29
Added 32K point FFT to typical characteristics conditions .................................................................................................. 30
Changed Gain 4 to Gain 5 in CLOCK BUFFER GAIN section............................................................................................ 36
Added Gain 5 to Table 20.................................................................................................................................................... 37
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
ADS6425IRGCT
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VQFN
RGC
64
250
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
AZ6425
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Sep-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADS6425IRGCT
Package Package Pins
Type Drawing
VQFN
RGC
64
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
16.4
Pack Materials-Page 1
9.3
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.3
1.5
12.0
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Sep-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS6425IRGCT
VQFN
RGC
64
250
213.0
191.0
55.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGC 64
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
9 x 9, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGC0064A
PLASTIC QUADFLAT PACK- NO LEAD
9.15
8.85
B
A
9.15
8.85
PIN 1 INDEX AREA
(0.1)TYP
DETAIL 'A'
OPTION1
1 MAX
(0.2)TYP
DETAIL 'A'
OPTION2
C
SEATING PLANE
0.05
0.00
EXPOSED
THERMAL PAD
0.08 C
2X
7.5
7.25±0.1
32
17
16
33
SEE DETAIL 'A'
60X
0.5
2X
7.5
SYMM
65
64X0.3
0.18
48
1
PIN1 ID
(OPTIONAL)
64
0.1
0.05
C A B
C
49
SYMM
64X0.5
0.3
4219009/A 10/2018
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGC0064A
PLASTIC QUADFLAT PACK- NO LEAD
2X(8.8)
2X(7.5)
64X(0.6)
(
SEE SOLDER MASK
DETAIL
7.25)
64
49
1
48
64X(0.24)
60X(0.5)
SYMM
65
2X(7.5)
4X
(1.14)
2X
(8.8)
2X
(1.1)
(0.05)
(TYP)
33
16
45X (Ø0.2)
(TYP) VIA
4X
(1.14)
17
SYMM
32
2X
(1.1)
LAND PATTERN EXAMPLE
SCALE: 10X
0.07 MAX
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
METAL UNDER
SOLDER MASK
4219009/A 10/2018
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGC0064A
PLASTIC QUADFLAT PACK- NO LEAD
2X (8.8)
2X(7.5)
36X
(0.94)
SYMM
64x(0.6)
64
49
1
48
65
64X(0.24)
60X(0.5)
2X(0.57)
SYMM
2X(7.5)
2X(8.8)
4X(1.14)
(R0.05)
TYP
33
16
EXPOSED METAL
32
17
2X(0.57)
4X(1.14)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
60% PRINTED COVERAGE BY AREA
SCALE: 12X
4219009/A 10/2018
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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