Texas Instruments | 16-Bit 200-kSPS Low-Power Sampling ADC w/Int Ref and Par/Serial Interface (Rev. A) | Datasheet | Texas Instruments 16-Bit 200-kSPS Low-Power Sampling ADC w/Int Ref and Par/Serial Interface (Rev. A) Datasheet

Texas Instruments 16-Bit 200-kSPS Low-Power Sampling ADC w/Int Ref and Par/Serial Interface (Rev. A) Datasheet
ADS8517
AD
S8
517
AD
S8
517
www.ti.com ................................................................................................................................................. SLAS527A – SEPTEMBER 2008 – REVISED JUNE 2009
16-Bit, 200-kSPS, Low-Power, Sampling ANALOG-TO-DIGITAL CONVERTER
with Internal Reference and Parallel/Serial Interface
FEATURES
APPLICATIONS
• 200-kHz Minimum Sampling Rate
• 4-V, 5-V, and ±10-V Input Ranges with
High-Impedance Input
• ±1.5 LSB Max INL
• +1.5/–1 LSB Max/Min DNL, 16 Bits NMC
• ±2-mV Max BPZ, ±0.6 ppm/°C BPZ Drift
• ±2-mV Max UPZ, ±0.15 ppm/°C UPZ Drift
• 88.8-dB SINAD with 10-kHz Input
• SPI™-Compatible Serial Output With
Daisy-Chain (TAG), SPI Master/Slave Feature
• Full Parallel Interface
• Binary Twos Complement or Straight Binary
Output Code Formats
• Single 4.5-V to 5.5-V Analog Supply, 1.65-V to
5.5-V Interface Supply
• Uses Internal 2.5-V or External Reference
• No External Precision Resistors Required
• Low Power Dissipation (ADC+REF+BUF):
– 47 mW Typ, 60 mW Max at 200 kSPS
• 50-µW Max Power-Down Mode
• Pin-Compatible with 16-Bit ADS7807 and
ADS8507, and 12-Bit ADS7806 and ADS8506
• SO-28 and TSSOP-28 Packages
•
•
•
•
•
•
1
23
Portable Test Equipment
USB Data Acquisition Module
Medical Equipment
Industrial Process Control
Digital Signal Processing
Instrumentation
DESCRIPTION
The ADS8517 is a complete low-power, single 5-V
supply, 16-bit sampling analog-to-digital (A/D)
converter.
It
contains
a
complete,
16-bit,
capacitor-based, successive approximation register
(SAR) A/D converter with sample-and-hold, clock,
reference, and data interface. The converter can be
configured for a variety of input ranges including
±10 V, 4 V, and 5 V. For most input ranges, the input
voltage can swing to 25 V or –25 V without damage
to the device.
An SPI-compatible serial interface allows data to be
synchronized to an internal or external clock. A full
parallel interface using the selectable BYTE pin is
also provided to allow the maximum system design
flexibility. The ADS8517 is specified at a 200-kHz
sampling rate over the industrial –40°C to +85°C
temperature range.
ADC
Parallel
Data
Successive Approximation Register (SAR)
Parallel
and
Serial
Data Out
and
Control
CDAC
40 kW
R1IN
10 kW
R2IN
20 kW
40 kW
Comparator
CAP
Clock
Ref
Buffer
PWRD
BYTE
BUSY
CS
R/C
SB/BTC
TAG
SDATA
DATACLK
EXT/INT
BUF
REF
REF
6 kW
2.5-V
Internal Reference
REFD
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2009, Texas Instruments Incorporated
ADS8517
SLAS527A – SEPTEMBER 2008 – REVISED JUNE 2009 ................................................................................................................................................. www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
ADS8517IB
NO
MISSING
CODE
±1.5
ADS8517I
±3
MINIMUM
SINAD
(dB)
16
SPECIFIED
TEMPERATURE
RANGE
87
15
PACKAGELEAD
PACKAGE
DESIGNATOR
SO-28
DW
TSSOP-28
PW
SO-28
DW
-40°C to +85°C
85
-40°C to +85°C
TSSOP-28
(1)
PW
ORDERING
NUMBER
TRANSPORT
MEDIA, QTY
ADS8517IBDW
Tube, 20
ADS8517IBDWR
Tape and Reel, 1000
ADS8517IBPW
Tube, 50
ADS8517IBPWR
Tape and Reel, 2000
ADS8517IDW
Tube, 20
ADS8517IDWR
Tape and Reel, 1000
ADS8517W
Tube, 50
ADS8517IPWR
Tape and Reel, 2000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1) (2)
Over operating free-air temperature range (unless otherwise noted).
UNIT
R1IN
Analog inputs
±25 V
R2IN
±25 V
REF
+VANA + 0.3 V to AGND2 – 0.3 V
DGND, AGND2
Ground voltage differences
±0.3 V
VANA
6V
VDIG to VANA
0.3 V
VDIG
6V
Digital inputs
-0.3 V to +VDIG + 0.3 V
Maximum junction temperature
+165°C
Storage temperature range
–65°C to +150°C
Internal power dissipation
(1)
(2)
700 mW
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
ELECTRICAL CHARACTERISTICS
At TA = -40°C to +85°C, fS = 200 kHz, VDIG = VANA = 5 V, using internal reference (see Figure 39), unless otherwise noted.
ADS8517IB (1)
ADS8517I
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Resolution
MIN
TYP
16
MAX
16
UNIT
Bits
ANALOG INPUT
Voltage ranges
See Table 1
–10
10
–10
10
0
5
0
5
0
4
0
4
Impedance
Capacitance
(1)
2
V
See Table 1
45
45
pF
Shaded cells indicate different specifications for high-grade version of the device.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = -40°C to +85°C, fS = 200 kHz, VDIG = VANA = 5 V, using internal reference (see Figure 39), unless otherwise noted.
ADS8517IB (1)
ADS8517I
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
THROUGHPUT SPEED
Conversion time
Complete cycle
Acquire and convert
Throughput rate
2.5
2.5
5
5
200
200
µs
µs
kHz
DC ACCURACY
INL
Integral linearity error
–3
3
–1.5
1.5
LSB (2)
DNL
Differential linearity error
–2
3
–1
1.5
LSB
No missing codes
15
Transition noise (3)
0.9
Gain error
Full-scale error (4)
Full-scale error drift
BPZ
UPZ
Bits
0.8
±0.2
LSB
±0.1
%
Internal reference
–0.75
0.75
–0.75
0.75
External 2.5-V reference
–0.75
0.75
–0.75
0.75
Internal reference
±9
External 2.5-V reference
Bipolar zero error
±10 V range
Bipolar zero error drift
±10 V range
Unipolar zero error
0 V to 5 V, 0 V to 4 V ranges
Unipolar zero error drift
0 V to 5 V, 0 V to 4 V ranges
Recovery time to rated accuracy
from power down (5)
2.2-µF capacitor to CAP
Power-supply sensitivity
(VDIG = VANA = VS)
16
±9
±1
–5
±1
–2
±0.6
–3
±0.1
±1
ppm/°C
2
±0.6
3
–2
±0.1
±0.15
±0.15
1
1
%
ppm/°C
±1
5
%
mV
ppm/°C
2
mV
ppm/°C
ms
+4.75 V < VANA < +5.25 V
–8
+8
–6
+6
+4.5 V < VANA < +5.5 V
–20
+20
–12
+12
92
LSB
AC ACCURACY
SFDR
Spurious-free dynamic range
fIN = 10 kHz, ±10 V
THD
Total harmonic distortion
fIN = 10 kHz, ±10 V
fIN = 10 kHz, ±10 V
100
–97
85
96
101
87
88.5
–92
88
–98
dB (6)
–95
dB
SINAD
Signal-to-(noise+distortion)
SNR
Signal-to-noise ratio
fIN = 10 kHz, ±10 V
89
dB
SNR usable bandwidth (7)
fIN = 10 kHz, ±10 V
130
130
kHz
SNR full-power bandwidth (–3 dB)
fIN = 10 kHz, ±10 V
600
600
kHz
Aperture delay
40
40
ns
Aperture jitter
20
20
–60 dB Input
29
85
dB
29
88
88
SAMPLING DYNAMICS
Transient response
FS step
Overvoltage recovery (8)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
5
750
ps
5
750
µs
ns
LSB means Least Significant Bit. One LSB for the ±10 V input range is 305 µV.
Typical rms noise at worst-case transitions.
Full-scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by
the transition voltage (not divided by the full-scale range) and includes the effect of offset error.
This is the time delay after the ADS8517 is brought out of Power-Down mode until all internal settling occurs and the analog input is
acquired to rated accuracy. A Convert command after this delay will yield accurate results.
All specifications in dB are referred to a full-scale input.
Usable bandwidth defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60 dB.
Recovers to specified performance after 2 x FS input overvoltage.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = -40°C to +85°C, fS = 200 kHz, VDIG = VANA = 5 V, using internal reference (see Figure 39), unless otherwise noted.
ADS8517IB (1)
ADS8517I
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
2.48
2.5
2.52
2.48
2.5
2.52
V
REFERENCE
Internal reference voltage
No load
Internal reference source current
(must use external buffer)
1
1
µA
Internal reference drift
8
8
ppm/°C
External reference voltage range
for specified linearity
External reference current drain
2.3
2.5
2.7
External 2.5-V reference
2.3
2.5
100
2.7
V
100
µA
V
DIGITAL INPUTS
VIL
Low-level input voltage (9)
VDIG = 1.65 V to 5.5 V
–0.3
0.6
–0.3
0.6
VIH
High-level input voltage (9)
VDIG = 1.65 V to 5.5 V
0.5 x VDIG
VDIG + 0.3
0.5 x VDIG
VDIG + 0.3
V
IIL
Low-level input current
VIL = 0 V
±10
±10
µA
IIH
High-level input current
VIH = 5 V
±10
±10
µA
0.45
0.45
V
DIGITAL OUTPUTS
Data format - Parallel 16-bits in 2-bytes, Serial
Data coding - Binary twos complement or straight binary
VOL
Low-level output voltage
ISINK = 1.6mA,
VDIG = 1.65V to 5.5V
VOH
High-level output voltage
ISOURCE = 500µA,
VDIG = 1.65V to 5.5V
Leakage current
High-Z state,
VOUT = 0 V to VDIG
±5
±5
µA
Output capacitance
High-Z state
15
15
pF
Bus access time
RL = 3.3 kΩ, CL = 50 pF
83
83
ns
Bus relinquish time
RL = 3.3 kΩ, CL = 10 pF
83
83
ns
V
VDIG – 0.45
VDIG – 0.45
V
DIGITAL TIMING
POWER SUPPLIES
VDIG
Interface voltage
1.65
1.8
5.5
1.65
1.8
5.5
VANA
ADC core voltage
4.5
5
5.5
4.5
5
5.5
IDIG
Interface current
VDIG = 5 V
0.3
0.3
mA
IANA
ADC core current
VANA = 5 V
9
9
mA
Power dissipation
V
VANA = VDIG = 5 V,
fS = 200 kHz
47
REFD high with BUF on
42
42
mW
PWRD and REFD high
50
50
µW
60
47
60
mW
TEMPERATURE RANGE
θJA
(9)
Specified performance
–40
+85
–40
+85
°C
Derated performance
–55
+125
–55
+125
°C
Storage temperature
–65
+150
–65
+150
°C
Thermal impedance
TSSOP
62
62
SO
46
46
°C/W
TTL-compatible at 5V supply.
Table 1. Analog Input Range Connections (see Figure 38 and Figure 39)
4
ANALOG INPUT
RANGE
CONNECT R1IN VIA 200 Ω TO
CONNECT R2IN VIA 100 Ω TO
IMPEDANCE
±10 V
VIN
CAP
45.7 kΩ
0 V to 5 V
AGND
VIN
20.0 kΩ
0 V to 4 V
VIN
VIN
21.4 kΩ
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ADS8517
www.ti.com ................................................................................................................................................. SLAS527A – SEPTEMBER 2008 – REVISED JUNE 2009
PIN CONFIGURATION
DW, PW PACKAGES
SO-28, TSSOP-28
(TOP VIEW)
R1IN
1
28
VDIG
AGND1
2
27
VANA
R2IN
3
26
REFD
CAP
4
25
PWRD
REF
5
24
BUSY
AGND2
6
23
CS
SB/BTC
7
22
R/C
ADS8517
EXT/INT
8
21
BYTE
D7
9
20
TAG
D6
10
19
SDATA
D5
11
18
DATACLK
D4
12
17
D0
D3
13
16
D1
DGND
14
15
D2
PIN ASSIGNMENTS
PIN
DIGITAL
I/O
NAME
NO.
R1IN
1
Analog Input.
DESCRIPTION
AGND1
2
Analog sense ground. Used internally as ground reference point. Minimal current flow
R2IN
3
Analog Input.
CAP
4
Reference buffer output. 2.2-µF tantalum capacitor to ground.
REF
5
Reference input/output. Outputs internal 2.5-V reference. Can also be driven by external system
reference. In both cases, bypass to ground with a 2.2-µF tantalum capacitor.
AGND2
6
Analog ground
SB/BTC
7
I
Output mode select. Selects straight binary or binary twos complement for output data format. If
high, data are output in a straight binary format. If low, data are output in a binary twos
complement format.
EXT/INT
8
I
External/internal data select. Selects external/internal data clock for transmitting data. If high,
data is output synchronized to the clock input on DATACLK. If low, a convert command initiates
the transmission of the data from the previous conversion, along with 16-clock pulses output on
DATACLK.
D7
9
O
Data bit 7 if BYTE is high. Data bit 15 (MSB) if BYTE is low. High-Z when CS is high and/or R/C
is low. Leave unconnected when using serial output.
D6
10
O
Data bit 6 if BYTE is high. Data bit 14 if BYTE is low. High-Z when CS is high and/or R/C is low.
D5
11
O
Data bit 5 if BYTE is high. Data bit 13 if BYTE is low. High-Z when CS is high and/or R/C is low.
D4
12
O
Data bit 4 if BYTE is high. Data bit 12 if BYTE is low. High-Z when CS is high and/or R/C is low.
D3
13
O
Data bit 3 if BYTE is high. Data bit 11 if BYTE is low. High-Z when CS is high and/or R/C is low.
DGND
14
D2
15
O
Data bit 2 if BYTE is high. Data bit 10 if BYTE is low. High-Z when CS is high and/or R/C is low.
D1
16
O
Data bit 1 if BYTE is high. Data bit 9 if BYTE is low. High-Z when CS is high and/or R/C is low.
D0
17
O
Data bit 0 (LSB) if BYTE is high. Data bit 8 if BYTE is low. High-Z when CS is high and/or R/C is
low.
Digital ground
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PIN ASSIGNMENTS (continued)
DATACLK
6
18
I/O
Data clock. Either an input or an output, depending on the EXT/INT level. Output data are
synchronized to this clock. If EXT/INT is low, DATACLK transmits 16 pulses after each
conversion, and then remains low between conversions.
SDATA
19
O
Serial data output. Data are synchronized to DATACLK, with the format determined by the level
of SB/BTC. In the external clock mode, after 16 bits of data, the ADC outputs the level input on
TAG as long as CS is low and R/C is high. If EXT/INT is low, data are valid on both the rising
and falling edges of DATACLK, and between conversions SDATA stays at the level of the TAG
input when the conversion was started.
TAG
20
I
Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output
on DATA with a delay that depends on the external clock mode.
BYTE
21
I
Byte select. Selects the eight most significant bits (low) or eight least significant bits (high) on
parallel output pins.
R/C
22
I
Read/convert input. With CS low, a falling edge on R/C puts the internal sample-and-hold circuit
into the hold state and starts a conversion. With EXT/INT is low, the transmission of the data
results from the previous conversion is initiated.
CS
23
I
Chip select. Internally ORed with R/C. If R/C is low, a falling edge on CS initiates a new
conversion. If EXT/INT is low, this same falling edge will start the transmission of serial data
results from the previous conversion.
BUSY
24
O
Busy output. At the start of a conversion, BUSY goes low and stays low until the conversion is
completed and the digital outputs have been updated.
PWRD
25
I
Power-down input. If high, conversions are inhibited and power consumption is significantly
reduced. Results from the previous conversion are maintained in the output shift register.
REFD
26
I
Reference disable. REFD high shuts down the internal reference. The external reference is
required for conversions.
VANA
27
ADC core supply. Nominally +5 V. Decouple with 0.1-µF ceramic and 10-µF tantalum capacitors.
VDIG
28
I/O supply. Nominally +1.8 V.
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TYPICAL CHARACTERISTICS
At fS = 200 kHz, VDIG = VANA = 5 V, and using internal reference (see Figure 39), unless otherwise specified.
POWER-SUPPLY CURRENT
vs FREE-AIR TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs FREE-AIR TEMPERATURE
2.520
Internal Reference Voltage (V)
Power-Supply Current (mA)
10.0
9.5
9.0
8.5
8.0
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480
-50
-25
0
25
50
75
100
125
-50
0
-25
25
50
75
Temperature (°C)
Temperature (°C)
Figure 1.
Figure 2.
POWER-SUPPLY CURRENT
vs SAMPLING FREQUENCY
BIPOLAR OFFSET ERROR
vs FREE-AIR TEMPERATURE
10.0
100
125
2
9.5
1
Offset (mV)
Power-Supply Current (mA)
Bipolar ±10 V Range
9.0
8.5
0
-1
8.0
-2
50
100
150
200
-50
-25
0
Sampling Frequency (kHz)
25
50
100
Figure 3.
Figure 4.
BIPOLAR POSITIVE FULL-SCALE ERROR
vs FREE-AIR TEMPERATURE
BIPOLAR NEGATIVE FULL-SCALE ERROR
vs FREE-AIR TEMPERATURE
125
0
0.10
Bipolar 10 V Range
Negative Full-Scale Error (%)
Bipolar 10 V Range
Positive Full-Scale Error (%)
75
Temperature (°C)
0.05
0
-40
-50
0
25
50
75
100
125
-0.05
-0.10
-50
-45
0
25
50
Temperature (°C)
Temperature (°C)
Figure 5.
Figure 6.
75
100
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TYPICAL CHARACTERISTICS (continued)
At fS = 200 kHz, VDIG = VANA = 5 V, and using internal reference (see Figure 39), unless otherwise specified.
UNIPOLAR OFFSET ERROR
vs FREE-AIR TEMPERATURE
UNIPOLAR OFFSET ERROR
vs FREE-AIR TEMPERATURE
0.2
0.2
Unipolar 4 V Range
Unipolar 5 V Range
0.1
Offset (mV)
Offset (mV)
0.1
0
-0.1
0
-0.1
-0.2
-0.2
-50
0
-25
25
50
75
100
125
-50
-25
0
25
50
Figure 7.
Figure 8.
UNIPOLAR FULL-SCALE ERROR
vs FREE-AIR TEMPERATURE
UNIPOLAR FULL-SCALE ERROR
vs FREE-AIR TEMPERATURE
Unipolar 5 V Range
0.05
Offset (mV)
Offset (mV)
0.05
0
-0.05
0
-0.05
-0.10
-0.10
-50
0
-25
25
50
75
100
125
-50
-25
0
75
100
Figure 9.
Figure 10.
AC PARAMETERS
vs FREE-AIR TEMPERATURE
SIGNAL-TO-(NOISE+DISTORTION)
vs FREE-AIR TEMPERATURE
105
125
89.5
-80
fIN = 10 kHz, 0 dB
fS = 150 kHz
-85
-90
-95
THD
SNR
-100
SINAD (dB)
89.0
SFDR
THD (dB)
SFDR, SINAD, and SNR (dB)
50
Temperature (°C)
fIN = 10 kHz, 0 dB
fS = 200 kHz
88.5
fS = 50 kHz
fS = 100 kHz
88.0
SINAD
85
-105
80
-50
-25
0
25
50
75
100
-110
125
87.5
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 11.
8
25
Temperature (°C)
110
90
125
0.10
Unipolar 4 V Range
95
100
Temperature (°C)
0.10
100
75
Temperature (°C)
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
At fS = 200 kHz, VDIG = VANA = 5 V, and using internal reference (see Figure 39), unless otherwise specified.
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY AND INPUT AMPLITUDE
SIGNAL-TO-NOISE RATIO
vs INPUT FREQUENCY
100
100
0 dB
90
-20 dB
70
SNR (dB)
SINAD (dB)
80
60
50
90
40
-60 dB
30
20
10
80
0
2
4
6
8
10
12
14
16
18
20
1
10
100
Input Signal Frequency (kHz)
Input Sampling Frequency (kHz)
Figure 13.
Figure 14.
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs INPUT FREQUENCY
100
110
SFDR (dB)
SINAD (dB)
100
90
90
80
80
70
1
10
100
1
10
100
Input Sampling Frequency (kHz)
Input Sampling Frequency (kHz)
Figure 15.
Figure 16.
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
AC PARAMETERS
vs CAP PIN CAPACITOR ESR
110
-70
-80
THD (dB)
-80
-90
-100
-110
105
-85
SFDR
100
-90
95
-95
THD
90
-100
SNR
SINAD
85
-105
80
-120
1
10
100
THD (dB)
SFDR, SINAD, and SNR (dB)
fIN = 10 kHz, 0 dB
-110
0
1
Input Sampling Frequency (kHz)
2
3
4
5
6
7
8
9
10
ESR (W)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
At fS = 200 kHz, VDIG = VANA = 5 V, and using internal reference (see Figure 39), unless otherwise specified.
AC PARAMETERS
vs POWER-SUPPLY VOLTAGE
OUTPUT REJECTION
vs POWER-SUPPLY RIPPLE FREQUENCY
110
-70
105
-75
-30
100
-80
95
-85
SNR
90
-90
SINAD
85
-95
THD
80
-100
75
-105
Output Rejection (dB)
SFDR
THD (dB)
SFDR, SINAD, and SNR (dB)
-20
fIN = 10 kHz, 0 dB
-40
-50
-60
-70
70
4.00
4.25
4.50
4.75
5.00
-110
5.50
5.25
-80
10
100
Power-Supply Voltage (V)
10k
100k
Figure 19.
Figure 20.
CONVERSION TIME
vs FREE-AIR TEMPERATURE
INTEGRAL LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs POWER-SUPPLY VOLTAGE
1M
2.0
INL/DNL Max and Min (LSB)
2.40
Conversion Time (ms)
1k
Power-Supply Ripple Frequency (Hz)
2.35
2.30
2.25
1.5
1.0
INL Max
0.5
DNL Max
DNL Min
0
-0.5
INL Min
-1.0
-1.5
2.20
-50
0
-25
25
50
75
100
-2.0
4.00
125
4.75
5.00
Figure 21.
Figure 22.
3
2
2
1
1
0
5.25
5.50
DIFFERENTIAL LINEARITY ERROR
3
DNL (LSB)
INL (LSB)
4.50
Power-Supply Voltage (V)
INTEGRAL LINEARITY ERROR
0
-1
-1
-2
-2
All Codes INL
All Codes DNL
-3
-3
0
8192
16384 24576 32768 40960 49152 57344 65535
0
Code
8192
16384 24576 32768 40960 49152 57344 65535
Code
Figure 23.
10
4.25
Temperature (°C)
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
At fS = 200 kHz, VDIG = VANA = 5 V, and using internal reference (see Figure 39), unless otherwise specified.
FFT
4096 Point FFT
fIN = 1 kHz, 0 dB
Amplitude (dB)
Amplitude (dB)
FFT
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
0
25
50
75
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
4096 Point FFT
fIN = 10 kHz, 0 dB
0
100
25
50
Frequency (kHz)
Frequency (kHz)
Figure 25.
Figure 26.
75
100
Amplitude (dB)
FFT
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
4096 Point FFT
fIN = 20 kHz, 0 dB
0
25
50
75
100
Frequency (kHz)
Figure 27.
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BASIC OPERATION
PARALLEL OUTPUT
Figure 28 shows a basic circuit for operating the ADS8517 with a ±10-V input range and parallel output. Taking
R/C (pin 22) low for a minimum of 40 ns (5 µs max) initiates a conversion. BUSY (pin 24) goes low and stays low
until the conversion completes and the output register updates. If BYTE (pin 21) is low, the eight most significant
bits (MSBs) will be valid when BUSY rises; if BYTE is high, the eight least significant bits (LSBs) will be valid
when BUSY rises. Data are output in binary twos complement (BTC) format. BUSY going high can be used to
latch the data. After the first byte has been read, BYTE can be toggled, allowing the remaining byte to be read.
All convert commands are ignored while BUSY is low.
The ADS8517 begins tracking the input signal at the end of the conversion. Allowing 5 µs between convert
commands assures accurate acquisition of a new signal.
1
±10 V
2.2 mF
2.2 mF
+
2
27
3
26
4
25
5
24
6
23
7
+5 V
Pin 21
LOW
Pin 21
HIGH
B15 B14 B13 B12 B11
(MSB)
B7 B6 B5 B4 B3
28
+1.8 V
+
+5 V
+
0.1 mF
10 mF
BUSY
Convert Pulse
22
R/C
8
21
BYTE
9
20
10
19 NC(1)
11
18
12
17
13
16
14
15
ADS8517
0.1 mF
40 ns min
B10 B9 B8
B2 B1
B0
(LSB)
NOTE: (1) NC = not connected.
Figure 28. Basic ±10-V Operation, Both Parallel and Serial Output
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SERIAL OUTPUT
Figure 29 shows a basic circuit to operate the ADS8517 with a ±10-V input range and serial output. Taking R/C
(pin 22) low for 40 ns (5 µs max) initiates a conversion and outputs valid data from the previous conversion on
SDATA (pin 19) synchronized to 16 clock pulses output on DATACLK (pin 18). BUSY (pin 24) goes low and
stays low until the conversion completes and the serial data have been transmitted. Data are output in BTC
format, MSB first, and are valid on both the rising and falling edges of the data clock. BUSY going high can be
used to latch the data. All convert commands are ignored while BUSY is low.
The ADS8517 begins tracking the input signal at the end of the conversion. Allowing 5 µs between convert
commands assures accurate acquisition of a new signal.
±10 V
22 mF
+
2.2 mF
+
1
28
2
27
3
26
4
25
5
24
6
23
7
22
ADS8517
+1.8 V
+
+5 V
+
0.1 mF
10 mF
BUSY
Convert Pulse
R/C
8
21
9
20
NC(1) 10
19
SDATA
NC
(1)
11
18
DATACLK
NC
(1)
12
17 NC(1)
NC(1) 13
16 NC(1)
14
15 NC(1)
NC
(1)
0.1 mF
40 ns min
NOTE: (1) NC = not connected.
Figure 29. Basic ±10-V Operation with Serial Output
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STARTING A CONVERSION
The combination of CS (pin 23) and R/C (pin 22) held low for a minimum of 40 ns puts the sample-and-hold of
the ADS8517 in the hold state and starts conversion N. BUSY (pin 24) goes low and stays low until conversion N
completes and the internal output register has been updated. All new convert commands received while BUSY is
low are ignored.
The ADS8517 begins tracking the input signal at the end of the conversion. Allowing 5 µs between convert
commands assures accurate acquisition of a new signal. Refer to Table 2 and Table 3 for a summary of CS,
R/C, and BUSY states, and Figure 30 through Figure 36 for timing diagrams.
Table 2. Control Functions When Using Parallel Output (DATACLK Tied Low, EXT/INT Tied High)
(1)
CS
R/C
BUSY
OPERATION
1
X
X
None. Data bus is in High-Z state.
↓
0
1
Initiates conversion N. Data bus remains in High-Z state.
0
↓
1
Initiates conversion N. Data bus enters High-Z state.
0
1
↑
Conversion N completed. Valid data from conversion N on the data bus.
↓
1
1
Enables data bus with valid data from conversion N.
↓
1
0
Enables data bus with valid data from conversion N–1 (1). Conversion N in progress.
0
↑
0
Enables data bus with valid data from conversion N–1 (1). Conversion N in progress.
0
0
↑
New conversion initiated without acquisition of a new signal. Data are invalid. CS and/or R/C
must be high when BUSY goes high.
X
X
0
New convert commands ignored. Conversion N in progress.
See Figure 30 and Figure 31 for constraints on data valid from conversion N–1.
CS and R/C are internally ORed and level-triggered. It does not matter which input goes low first when initiating a
conversion. If, however, it is critical that CS or R/C initiates conversion N, be sure the less critical input is low at
least tsu2 ≥ 10 ns before the initiating input. If EXT/INT (pin 8) is low when initiating conversion N, serial data from
conversion N–1 is output on SDATA (pin 19) following the start of conversion N. See Internal Data Clock in the
Reading Data section for more information.
To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. This
configuration has no effect when using the internal data clock in the serial output mode. However, when using an
active external data clock, the parallel and serial outputs are affected whenever R/C goes high; refer to the
Reading Data section for more information. In the internal clock mode, data are clocked out every convert cycle
regardless of the states of CS and R/C. The conversion result is available as soon as BUSY returns to high.
Therefore, data always represent the previously-completed conversion, even when read during a conversion.
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READING DATA
The ADS8517 outputs serial or parallel data in straight binary (SB) or binary twos complement data output
format. If SB/BTC (pin 7) is high, the output is in SB format; if it is low, the output is in BTC format. Refer to
Table 4 for the ideal output codes. The first conversion immediately following a power-up does not produce a
valid conversion result.
The parallel output can be read without affecting the internal output registers; however, reading the data through
the serial port shifts the internal output registers one bit per data clock pulse. As a result, data can be read on the
parallel port before reading the same data on the serial port, but data cannot be read through the serial port
before reading the same data on the parallel port.
Table 3. Control Functions When Using Serial Output (1)
CS
R/C
BUSY
EXT/INT
DATACLK
↓
0
1
0
Output
Initiates conversion N. Valid data from conversion N–1 clocked out on SDATA.
0
↓
1
0
Output
Initiates conversion N. Valid data from conversion N–1 clocked out on SDATA.
↓
0
1
1
Input
0
↓
1
1
↓
1
1
1
Input
Conversion N completed. Valid data from conversion N clocked out on SDATA
synchronized to external data clock.
↓
1
0
1
Input
Valid data from conversion N–1 output on SDATA synchronized to external data clock.
Conversion N in progress.
0
↑
0
1
Input
Valid data from conversion N–1 output on SDATA synchronized to external data clock.
Conversion N in progress.
0
0
↑
X
Input
New conversion initiated without acquisition of a new signal. Data are invalid. CS and/or
R/C must be high when BUSY goes high.
X
X
0
X
X
(1)
OPERATION
Initiates conversion N. Internal clock still runs conversion process.
Initiates conversion N. Internal clock still runs conversion process.
New convert commands ignored. Conversion N in progress..
See Figure 34, Figure 35, and Figure 36 for constraints on data valid from conversion N–1.
Table 4. Output Codes and Ideal Input Voltages
DIGITAL OUTPUT
DESCRIPTION
Full-scale range
Least significant bit (LSB)
+Full-scale (FS – 1LSB)
Midscale
1 LSB below midscale
–Full-scale
BINARY TWOS COMPLEMENT
(SB/BTC LOW)
ANALOG INPUT
STRAIGHT BINARY (SB/BTC HIGH)
±10
0 V to 5 V
0 V to 4 V
305 µV
76 µV
61 µV
BINARY CODE
HEX
CODE
BINARY CODE
HEX CODE
9.999695 V
4.999924 V
3.999939 V
0111 1111 1111 1111
7FFF
1111 1111 1111 1111
FFFF
0V
2.5 V
2V
0000 0000 0000 0000
0000
1000 0000 0000 0000
8000
305 µV
2.499924 V
1.999939 V
1111 1111 1111 1111
FFFF
0111 1111 1111 1111
7FFF
-10 V
0V
0V
1000 0000 0000 0000
8000
0000 0000 0000 0000
0000
Parallel Output
To use the parallel output, tie EXT/INT (pin 8) high and DATACLK (pin 18) low. SDATA (pin 19) should be left
unconnected. The parallel output is active when R/C (pin 22) is high and CS (pin 23) is low. Any other
combination of CS and R/C 3-states the parallel output. Valid conversion data can be read in two 8-bit bytes on
D7-D0 (pins 9-13 and 15-17). When BYTE (pin 21) is low, the eight most significant bits are valid with the MSB
on D7. When BYTE is high, the eight least significant bits are valid with the LSB on D0. BYTE can be toggled to
read both bytes within one conversion cycle.
Upon initial device power-up, the parallel output contains indeterminate data.
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Parallel Output (After a Conversion)
After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. Valid
data from conversion N are available on D7-D0 (pin 9-13 and 15-17). BUSY going high can be used to latch the
data. Refer to Table 5, Figure 30, and Figure 31 for timing specifications.
t1
t1
R/C
t3
t3
t4
BUSY
t6
t5
t6
t7
MODE
Acquire
t8
Convert
Acquire
Convert
t12
Parallel
Data Bus
Previous
High Byte Valid
Previous High Previous Low
Byte Valid
Byte Valid
Hi-Z
t12
t10
t11
Not Valid
High Byte
Valid
Low Byte
Valid
t2
t9
Hi-Z
t9
t12
t12
t12
High Byte
Valid
t12
BYTE
Figure 30. Conversion Timing With Parallel Output (CS and DATACLK Tied Low, EXT/INT Tied High)
t21
t21
t1
t21
t21
R/C
t21
t21
CS
t3
t4
BUSY
t21
t21
BYTE
t21
Data Bus
Hi-Z State
High Byte
t21
t9
t21
Hi-Z State
t21
Low Byte
Hi-Z State
t9
Figure 31. CS to Control Conversion and Read Timing With Parallel Outputs
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Parallel Output (During a Conversion)
After conversion N has been initiated, valid data from conversion N–1 can be read and are valid up to 2.2 µs
after the start of conversion N. Do not attempt to read data beyond 2.2 µs after the start of conversion N until
BUSY (pin 24) goes high; doing so may result in reading invalid data. Refer to Table 5, Figure 30, and Figure 31
for timing constraints.
Table 5. Conversion and Data Timing with Parallel Interface at TA = –40°C to +85°C
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
Convert pulse width
5
µs
t2
Data valid delay after R/C low
2.3
2.5
µs
t3
BUSY delay from start of conversion
20
85
ns
t4
BUSY low
2.3
2.5
µs
t5
BUSY delay after end of conversion
90
t6
Aperture delay
40
ns
t7
Conversion time
2.2
µs
t8
Acquisition time
t9
Bus relinquish time
10
t10
BUSY delay after data valid
20
60
ns
t11
Previous data valid after start of conversion
1.8
2.2
µs
t21
R/C to CS setup time
10
t7 + t8
0.04
1.8
ns
µs
2.7
Throughput time
83
ns
ns
5
µs
Serial Output
Data can be clocked out with the internal data clock or an external data clock. When using the serial output, be
careful with the parallel outputs, D7-D0 (pins 9-13 and 15-17), because these pins come out of a High-Z state
whenever CS (pin 23) is low and R/C (pin 22) is high. The serial output cannot be 3-stated and is always active.
Refer to the Applications Information section for specific serial interfaces. If an external clock is used, the TAG
input can be used to daisy-chain multiple ADS8517 data pins together.
Internal Data Clock (During a Conversion)
To use the internal data clock, tie EXT/INT (pin 8) low. The combination of R/C (pin 22) and CS (pin 23) low
initiates conversion N and activates the internal data clock (typically, a 900-kHz clock rate). The ADS8517
outputs 16 bits of valid data, MSB first, from conversion N–1 on SDATA (pin 19), synchronized to 16 clock pulses
output on DATACLK (pin 18). The data are valid on both the rising and falling edges of the internal data clock.
The rising edge of BUSY (pin 24) can be used to latch the data. After the 16th clock pulse, DATACLK remains
low until the next conversion is initiated, while SDATA returns to the state of the TAG pin input sensed at the
start of transmission. Refer to Table 6 and Figure 33 for more information.
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External Data Clock
To use an external data clock, tie EXT/INT (pin 8) high. The external data clock is not and cannot be
synchronized with the internal conversion clock; care must be taken to avoid corrupting the data. To enable the
output mode of the ADS8517, CS (pin 23) must be low and R/C (pin 22) must be high. DATACLK must be high
for 20% to 70% of the total data clock period; the clock rate can be between dc and 10 MHz. Serial data from
conversion N can be output on SDATA (pin 19) after conversion N completes or during conversion N+1.
An obvious way to simplify control of the converter is to tie CS low and use R/C to initiate conversions.
While this configuration is perfectly acceptable, there is a possible problem when using an external data clock. At
an indeterminate point from 12 µs after the start of conversion N until BUSY rises, the internal logic shifts the
results of conversion N into the output register. If CS is low, R/C high, and the external clock is high at this point,
data are lost. Consequently, with CS low, either R/C and/or DATACLK must be low during this period to avoid
losing valid data.
External Data Clock (After a Conversion)
After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. With CS
low and R/C high, valid data from conversion N are output on SDATA (pin 19) synchronized to the external data
clock input on DATACLK (pin 18). The MSB is valid on the first falling edge and the second rising edge of the
external data clock. The LSB is valid on the 16th falling edge and 17th rising edge of the data clock. TAG (pin
20) inputs a bit of data for every external clock pulse. The first bit input on TAG is valid on SDATA on the 17th
falling edge and the 18th rising edge of DATACLK; the second input bit is valid on the 18th falling edge and the
19th rising edge, etc. With a continuous data clock, TAG data is output on SDATA until the internal output
registers are updated with the results from the next conversion. Refer to Table 6 and Figure 35 for more
information.
External Data Clock (During a Conversion)
After conversion N has been initiated, valid data from conversion N–1 can be read and are valid up to 2.2 µs
after the start of conversion N. Do not attempt to clock out data from 2.2 µs after the start of conversion N until
BUSY (pin 24) rises; doing so results in data loss.
NOTE:
For the best possible performance when using an external data clock, data should not
be clocked out during a conversion.
The switching noise of the asynchronous data clock can cause digital feedthrough, degrading converter
performance. Refer to Table 6 and Figure 36 for more information.
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Table 6. Timing Requirements (TA = –40°C to +85°C)
PARAMETER
MIN
TYP
MAX
0.04
5
UNIT
µs
tw1
Pulse duration, convert
td1
Delay time, BUSY from R/C low
20
85
ns
tw2
Pulse duration, BUSY low
2.3
2.5
µs
td2
Delay time, BUSY, after end of conversion
90
td3
Delay time, aperture
40
tconv
Conversion time
2.0
2.2
tacq
Acquisition time
2.6
2.7
tconv + tacq
ns
Cycle time
ns
2.4
µs
µs
5
171
µs
td4
Delay time, R/C low to internal DATACLK output
tc1
Cycle time, internal DATACLK
ns
td5
Delay time, data valid to internal DATACLK high
td6
Delay time, data valid after internal DATACLK low
tc2
Cycle time, external DATACLK
35
ns
tw3
Pulse duration, external DATACLK high
15
ns
92
96
98
ns
2
3.5
ns
41
43
ns
tw4
Pulse duration, external DATACLK low
15
ns
tsu1
Setup time, R/C rise/fall to external DATACLK high
15
ns
tsu2
Setup time, R/C transition to CS transition
10
ns
td8
Delay time, data valid from external DATCLK high
td9
Delay time, CS rising edge to external DATACLK rising edge
15
td10
Delay time, previous data available after CS, R/C low
1.8
tsu3
Setup time, BUSY transition to first external DATACLK
td11
Delay time, final external DATACLK to BUSY rising edge
tsu4
th1
2
25
40
ns
ns
2.2
µs
5
ns
825
ns
Setup time, TAG valid before rising edge of DATACLK
2
ns
Hold time, TAG valid after rising edge of DATACLK
2
ns
CS
R/C
R/C
CS
td9
tsu1
tsu1
tsu1
External
DATACLK
tsu1
External
DATACLK
CS Set Low, Discontinuous Ext DATACLK
R/C Set Low, Discontinuous Ext DATACLK
BUSY
CS
tsu2
tsu2
tsu3
External
DATACLK
R/C
1
2
CS Set Low, Discontinuous Ext DATACLK
Figure 32. Critical Timing Parameters
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tw1
tw1
R/C
td1
td1
tw2
tw2
(N + 1)th
BUSY
(N + 2)th
td2
td3
STATUS
Error
Correction
Nth Conversion
td2
td11
td3
td11
Error
(N+1)th Conversion Correction
(N+1)th Accquisition
tconv
tconv
tacq
tc1
td4
(N+2)th Accquisition
tacq
td4
Internal
1
DATACLK
2
16
16
td6
td5
SDATA
2
1
D15
TAG = 0
TAG = 0
D0
D15
D0
TAG = 0
Nth Conversion Data
(N−1)th Conversion Data
CS, EXT/INT, and TAG are tied low
8 starts READ
Figure 33. Basic Conversion Timing: Internal DATACLK (Read Previous Data During Conversion)
tw1
tw1
R/C
td1
td1
tw2
BUSY
tw2
(N + 1)th
(N + 2)th
td2
td3
STATUS
Error
Correction
Nth Conversion
td2
td3
td11
td11
(N+1)th Accquisition
(N+1)th Conversion
tacq
tconv
(N+2)th Accquisition
tacq
tconv
tsu3
tsu1
Error
Correction
tsu3
tsu1
External
1
DATACLK
SDATA
TAG = 0
16
No more
data to
shift out
1
TAG = 0
EXT/INT tied high, CS and TAG are tied low
2
1
16
Nth Data
TAG = 0
16
1
No more
data to
shift out
TAG = 0
2
16
(N+1)th Data
TAG = 0
tw1 + tsu1 starts READ
Figure 34. Basic Conversion Timing: External DATACLK
20
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tw1
R/C
td1
tsu1
tw2
td1
BUSY
td3
td2
td11
STATUS
Nth Conversion
Error
Correction
td3
(N+1) th Accquisition
tsu3
tconv
tacq
tc2
External
DATACLK
tsu1
tw4
tw3
1
0
2
4
3
5
10
11
12
13
14
15
16
SYNC = 0
td8
td8
Nth Conversion Data
D15
DATA
D14
D13
D12
D11
D10
D05
D04
D03
D02
D01
D00
T00
Txx
T02
T03
T04
T05
T06
T11
T12
T13
T14
T15
T16
T17
Ty y
th1
tsu4
TAG
T01
T00
EXT/INT tied high, CS tied low
tw1 + tsu1 starts READ
Figure 35. Read After Conversion (Discontinuous External DATACLK)
tw1
R/C
td1
tw2
BUSY
td10
td3
td2
Error
Correction
(N + 1)th Conversion
STATUS
tsu3
tconv
tc2
External
tsu1
tw3
1
0
DATACLK
td11
tw4
2
3
4
5
td8
11
12
13
14
Nth Conversion Data
D15
SDATA
10
EXT/INT tied high, CS and TAG tied low
D14
D13
D12
D11
D10
D05
D04
D03
15
16
td8
D02
D01
D00
Rising DATACLK change DATA, tw1 + tsu1 Starts READ
TAG is not recommended for this mode. There is not enough
time to do so without violating td11.
Figure 36. Read During Conversion (Discontinuous External DATACLK)
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ADS8517
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TAG FEATURE
The TAG feature allows data from multiple ADS8517 converters to be read on a single serial line. The converters
are cascaded together using the DATA pins as outputs and the TAG pins as inputs, as illustrated in Figure 37.
The DATA pin of the last converter drives the processor serial data input. Data are then shifted through each
converter, synchronous to the externally supplied data clock, onto the serial data line. The internal clock cannot
be used for this configuration.
The preferred timing uses the discontinuous, external data clock during the sampling period. Data must be read
during the sampling period because there is not sufficient time to read data from multiple converters during a
conversion period without violating the td11 constraint (see the External Data Clock section). The sampling period
must be sufficiently long enough to allow all data words to be read before starting a new conversion.
Note that in Figure 37, the state of the DATA pin at the end of a READ cycle reflects the state of the TAG pin at
the start of the cycle for each converter. The ADS8517 works the same way when it is running in external or
internal clock mode. That is, the state of the TAG pin is shown on the DATA pin at the 17th clock after all 16 bits
have shifted out. However, it is only practical to use the TAG feature with the external clock mode when multiple
ADS8517s are daisy-chained, so that they are running at the same clock speed. For example, when two
converters (ADS8517A and ADS8517B) are cascaded together, the 17th external clock cycle brings the MSB
data of ADS8517A onto the DATA pin of ADS8517B.
ADS8517A
Processor
TAG
DATA
CS
R/C
DATACLK
ADS8517B
TAG
DATA
A00
D
CS
R/C
DATACLK
SCLK
GPIO
GPIO
SDI
D
Q
D
B00
TAG (B)
D
DATA (A)
A15
Q
Q
B15
DATA (B)
Q
DATACLK
R/C
(both A and B)
BUSY
(both A and B)
SYNC
(both A and B)
External
DATACLK
1
2
3
4
15
16
18
17
DATA (A)
A15
A14
A13
A01
A00
DATA (B)
B15
B14
B13
B01
B00
19
20
21
32
33
34
TAG(A) = 0
Nth Conversion Data
A15
A14
A13
A12
A00
TAG(A) = 0
EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low.
Figure 37. Timing of TAG Feature With Single Conversion (Using External DATACLK)
22
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ANALOG INPUTS
The ADS8517 offers three analog input ranges, as shown in Table 1. The offset specification is factory-calibrated
with internal resistors. The gain specification is factory-calibrated with 0.1%, 0.25-W external resistors, as shown
in Figure 38 and Figure 39. The external resistors can be omitted if a larger gain error is acceptable or if using
software calibration. The hardware trim circuitry shown in Figure 38 and Figure 39 can reduce the error to zero.
±10 V
0 V to 5 V
1
VIN
2
3
1 MW
2.2 mF
5
2.2 mF
2
AGND1
3
VIN
R2IN
+5 V
+
CAP
+
50 kW
1
R1IN
4
+5 V
+
6
0 V to 4 V
1 MW
REF
4
2.2 mF
5
50 kW
2.2 mF
+
6
AGND2
1
R1IN
R1IN
2
VIN
AGND1
3
R2IN
+5 V
+
CAP
1 MW
REF
4
2.2 mF
5
50 kW
2.2 mF
+
6
AGND2
AGND1
R2IN
CAP
REF
AGND2
Figure 38. Circuit Diagrams (with Gain Adjust Trim)
±10 V
0 V to 5 V
1
VIN
2
3
1
R1IN
2
AGND1
3
R2IN
VIN
4
2.2 mF
5
2.2 mF
+
CAP
+
+
6
0 V to 4 V
1 MW
5
REF
2.2 mF
AGND2
4
2.2 mF
+
6
1
R1IN
AGND1
R1IN
2
VIN
3
R2IN
+
CAP
4
2.2 mF
5
REF
2.2 mF
AGND2
+
6
AGND1
R2IN
CAP
REF
AGND2
Figure 39. Circuit Diagrams (Without Gain Adjust Trim)
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ADS8517
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Analog input pins R1IN and R2IN have ±25-V overvoltage protection. The input signal must be referenced to
AGND1. This referencing minimizes ground-loop problems typical to analog designs. The analog input should be
driven by a low-impedance source. A typical driving circuit using the OPA627 or OPA132 is shown in Figure 40.
+15 V
2.2 mF
22 pF
ADS8517
2 kW
100 nF
R1IN
Pin 7
2 kW
VIN
AGND1
Pin 1
Pin 2
OPA627
or
OPA132
22 pF
Pin 3
Pin 6
R2IN
CAP
Pin 4
EXT/INT
2.2 mF
REF
2.2 mF
2.2 mF
100 nF
DGND
AGND2
GND
GND
-15 V
GND
GND
GND
GND
Figure 40. Typical Driving Circuit (±10 V, No Trim)
24
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REFERENCE
The ADS8517 can operate with the internal 2.5 V reference or an external reference. An external reference
connected to pin 5 (REF) bypasses the internal reference. The external reference must drive the 6-kΩ resistor
that separates pin 5 from the internal reference (see the front page diagram). The load varies with the difference
between the internal and external reference voltages. The internal reference is approximately 2.5 V (range is
from 2.48 V to 2.52 V). The external reference voltage can vary from 2.3 V to 2.7 V. The reference, whether
internal or external, is buffered internally with the output on pin 4 (CAP). Figure 41 shows characteristic
impedances at the input and output of the buffer with all combinations of power-down and reference power-down.
The reference voltage determines the size of the least significant bit (LSB). The larger reference voltages
produce a larger LSB, which can improve SNR. Smaller reference voltages can degrade SNR.
ZCAP
CAP
(Pin 4)
CDAC
Buffer
ZREF
Internal
Reference
REF
(Pin 5)
ZCAP W
ZREF W
PWRD 0
REFD 0
1
6k
PWRD 0
REFD 1
1
1M
PWRD 1
REFD 0
200
6k
PWRD 1
REFD 1
200
1M
Figure 41. Characteristic Impedances of the Internal Buffer
The ADS8517 is factory-tested with 2.2 µF capacitors connected to pin 4 (CAP) and pin 5 (REF). Each capacitor
should be placed as close as possible to the pin. The capacitor on pin 5 band-limits the internal reference noise.
A smaller capacitor can be used, but it may degrade SNR and SINAD. The capacitor on pin 4 stabilizes the
reference buffer and provides switching charge to the CDAC during conversion. Capacitors smaller than 1 µF
may cause the buffer to become unstable and not hold sufficient charge for the CDAC. The devices are tested to
specifications with 2.2 µF, making larger capacitors unnecessary (Figure 42 shows how capacitor values larger
than 2.2 µF have little effect on improving performance). The equivalent series resistance (ESR) of these
compensation capacitors is also critical; keep the total ESR under 3 Ω. See the Typical Characteristics section
concerning how ESR affects performance.
7000
Power−Up Time − ms
6000
5000
4000
3000
2000
1000
0
0.1
1
10
CAP − Pin Value − mF
100
Figure 42. Power-Down to Power-Up Time versus Capacitor Value on CAP
Neither the internal reference nor the buffer should be used to drive an external load. Such loading can degrade
performance, as shown in Figure 41. Any load on the internal reference causes a voltage drop across the 6-kΩ
resistor and affects gain. The internal buffer is capable of driving ±2-mA loads, but any load can cause
perturbations of the reference at the CDAC, thus degrading performance.
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ADS8517
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POWER-DOWN
The ADS8517 has analog power-down and reference power-down capabilities via PWRD (pin 25) and REFD (pin
26), respectively. PWRD and REFD high powers down all analog circuitry, maintaining data from the previous
conversion in the internal registers, provided that the data have not already been shifted out through the serial
port. Typical power consumption in this mode is 50 µW. Power recovery is typically 1 ms, using a 2.2-µF
capacitor connected to CAP. Figure 42 shows power-down to power-up recovery time relative to the capacitor
value on CAP. With +5 V applied to VDIG, the digital circuitry of the ADS8517 remains active at all times,
regardless of PWRD and REFD states.
PWRD
PWRD high powers down all of the analog circuitry except for the reference. Data from the previous conversion
are maintained in the internal registers and can still be read. With PWRD high, a convert command yields
meaningless data.
REFD
REFD high powers down the internal 2.5-V reference. All other analog circuitry, including the reference buffer, is
active. REFD should be high when using an external reference to minimize power consumption and the loading
effects on the external reference. See Figure 41 for the characteristic impedance of the reference buffer input for
both REFD high and low. The internal reference consumes approximately 5 mW.
26
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LAYOUT
POWER
For host processors that are able to advantage of a lower interface supply voltage, the ADS8517 offers a wide
range of voltages—from 5.5V to as low as 1.65V. The ADS8517 should be considered as an analog component
because, as noted in the Electrical Characteristics, it uses 95% of its power for the analog circuitry. If the
interface is at the same +5V as the analog supply, the two +5-V supplies should be separate. Connecting VDIG
(pin 28) directly to a digital supply can reduce converter performance because of switching noise from the digital
logic. For best performance, the +5-V supply should be produced from whichever analog supply is present for the
rest of the analog signal conditioning. If a +12-V or +15-V suppy is present in the system, a simple +5-V regulator
can be used. Although it is not suggested, if the digital supply in the system must be used to power the
converter, be sure it is properly filtered.
POWER-ON SEQUENCE
Care must be taken with power sequencing when the interface and analog supplies are different. Refer to the
Absolute Maximum Ratings for details. The analog supply should be powered on before the digital supply (used
for the interface). It is important that the voltage difference between VDIG and the digital inputs does not exceed
the limit of –0.3V to VDIG + 0.3V. All digital inputs should be kept inactive (logic low) until the digital (interface)
supply is steady.
GROUNDING
Three ground pins are present on the ADS8517. DGND is the digital supply ground. AGND2 is the analog supply
ground. AGND1 is the ground to which all analog signals internal to the A/D converter are referenced. AGND1 is
more susceptible to current induced voltage drops and must have the path of least resistance back to the power
supply.
To achieve optimum performance, all the ground pins of the A/D converter should be tied to an analog ground
plane, separated from the system digital logic ground. Both analog and digital ground planes should be tied to
the system ground as near to the power supplies as possible. This configuration helps to prevent dynamic digital
ground currents from modulating the analog ground through a common impedance to power ground.
SIGNAL CONDITIONING
The ADS8517 features high-impedance inputs as the result of the resistive input attenuation circuit. For ±10V, 0V
to 5V, and 0V to 4V inputs, the equivalent input impedances are 45.7kΩ, 20kΩ and 21.4kΩ respectively. Lower
cost op amps may be used to drive the ADC inputs because the driving requirement is not as high compared to
other converters. This input circuit not only reduces the power consumption on the signal conditioning op amp,
but it also works as a buffer to attenuate any charge injection resulting from the operation of the CDAC FET
sample switches, even though the design of those FET switches is optimized to give minimal charge injection.
Another benefit provided by the ADS8517 high-impedance front-end is assured ±25V overvoltage protection. In
most cases, this internal protection eliminates the need for external input protection circuitry.
INTERMEDIATE LATCHES
The ADS8517 does have 3-state outputs for the parallel port, but intermediate latches should be used if the bus
is active during conversion. If the bus is not active during conversion, the 3-state outputs can be used to isolate
the A/D converter from other peripherals on the same bus.
Intermediate latches are beneficial on any monolithic A/D converter. The ADS8517 has an internal LSB size of
38 µV (with a 2.5-V internal reference). Transients from fast-switching signals on the parallel port, even when the
A/D converter is 3-stated, can be coupled through the substrate to the analog circuitry, causing degradation of
converter performance.
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APPLICATION INFORMATION
TRANSITION NOISE
Apply a dc input to the ADS8517 and initiate 1000 conversions. The digital output of the converter varies in
output codes because of the internal noise of the ADS8517. This variance is true for all 16-bit SAR converters.
The transition noise specification found in the Electrical Characteristics section is a statistical figure that
represents the one sigma limit or rms value of these output codes.
Using a histogram to plot the output codes, the distribution should appear bell-shaped, with the peak of the bell
curve representing the nominal output code for the input voltage value. The ±1σ, ±2σ, and ±3σ distributions
represent 68.3%, 95.5%, and 99.7%, respectively, of all codes. Multiplying the transition noise (TN) by 6 yields
the ±3σ distribution, or 99.7%, of all codes. Statistically, up to three codes could fall outside the five-code
distribution when executing 1000 conversions. The ADS8517 has a TN of 0.8 LSBs, which yields five output
codes for a ±3σ distribution. Figure 43 shows 16,384 conversion histogram results.
7740
4230
3855
16
7FFD
288
7FFE
7FFF
8000
8001
247
8
8002
8003
Figure 43. Histogram of 16,384 Conversions with VIN = 0 V in ±10 V Bipolar Range
AVERAGING
The noise of the converter can be compensated by averaging the digital codes. By averaging conversion results,
transition noise is reduced by a factor of 1/√n where n is the number of averages. For example, averaging four
conversion results reduces the TN by 1/2 to 0.4 LSBs. Averaging should only be used for input signals with
frequencies near dc.
For ac signals, a digital filter can be used to low-pass filter and decimate the output codes. This action works in a
similar manner to averaging: for every decimation by 2, the signal-to-noise ratio improves by 3 dB.
28
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ADS8517 AS AN SPI MASTER DEVICE (INT/EXT TIED LOW)
Figure 44 shows a simple interface between the ADS8517 and an SPI-equipped microcontroller or TMS320
series digital signal processor (DSP) when using the internal serial data clock. This interface assumes that the
microcontroller or DSP is configured as an SPI slave, is capable of receiving 16-bit transfers, and that the
ADS8517 is the only serial peripheral on the SPI bus.
ADS8517
Microcontroller
TOUT
SS
R/C
BUSY
MOSI
SDATA
SCLK
DATACLK
EXT/INT
SPI Slave
CS
BYTE
SPI Master
NOTE: CPOL = 0 (inactive SCLK is LOW)
CPHA = 0 or 1 (data valid on either SCLK edge)
Figure 44. ADS8517 as SPI Master
To maintain synchronization with the ADS8517, the microcontroller slave select (SS) input should be connected
to the BUSY output of the ADS8517. When a transition from high-to-low occurs on BUSY (indicating the current
conversion is in process), the ADS8517 internal SCLK begins shifting the previous conversion data into the
MOSI pin of the microcontroller. In this scenario, the CONV input to the ADS8517 can be controlled from an
external trigger source, or a trigger generated by the microcontroller. The ADS8517 internal SCLK provides 2 ns
(min) of setup time and 41 ns (min) of hold time on the SDATA output (see td5 and td6 in Table 6), allowing the
microcontroller to sample data on either the rising or falling edge of SCLK.
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ADS8517 AS AN SPI SLAVE DEVICE (INT/EXT TIED HIGH)
Figure 45 shows another interface between the ADS8517 and an SPI-equipped microcontroller or DSP in which
the host processor acts as an SPI master device.
TOUT
INT
VS
ADS8517
Microcontroller
R/C
EXT/INT
BUSY
MOSI
SDATA
SCLK
DATACLK
CS
SPI Master
BYTE
SPI Slave
NOTE: CPOL = 0 (inactive SCLK is LOW)
CPHA = 1 (data valid on SCLK falling edge)
Figure 45. ADS8517 as SPI Slave
In this configuration, the data transfer from the ADS8517 is triggered by the rising edge of the serial data clock
provided by the SPI master. The SPI interface should be configured to read valid SDATA on the falling edge of
SCLK. When a minimum of 17 SCLKs are provided to the ADS8517, data can be strobed to the host processor
on the rising SCLK edge providing a 2ns (min) hold time (see td8 in Table 6).
When using an external interrupt to facilitate serial data transfers, as shown in Figure 45, there are two options
for the configuration of the interrupt service routine (ISR): falling-edge-triggered or rising-edge-triggered.
A falling-edge-triggered transfer would initiate an SPI transfer after the falling edge of BUSY, providing the host
controller with the previous conversion results, while the current conversion cycle is underway. The timing for this
type of interface is described in detail in Figure 36. Care must be taken to ensure the entire 16-bit conversion
result is retrieved from the ADS8517 before BUSY returns high to avoid the potential corruption of the current
conversion cycle.
A rising-edge-triggered transfer is the preferred method of obtaining the conversion results. This timing is
depicted in Figure 35. This method of obtaining data ensures that SCLK is static during the conversion cycle and
provides the host processor with current cycle conversion results.
8-BIT SPI INTERFACE
For microcontrollers that only support 8-bit SPI transfers, it is recommended to configure the ADS8517 for SPI
slave operation, as depicted in Figure 45. With the microcontroller configured as the SPI master, two 8-bit
transfers are required to obtain full 16-bit conversion results from the ADS8517. The eight MSBs of the
conversion result are considered valid on the falling SCLK edges of the first transfer, with the remaining four
LSBs being valid on the first four falling SCLK edges in the second transfer.
30
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2008) to Revision A ............................................................................................... Page
•
•
Changed data sheet to reflect TSSOP-28 package availability............................................................................................. 1
Deleted lead temperature specification from Absolute Maximum Ratings ............................................................................ 2
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS8517IBDW
ACTIVE
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8517I
B
ADS8517IBPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ADS8517I
B
ADS8517IBPWR
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ADS8517I
B
ADS8517IDW
LIFEBUY
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8517I
ADS8517IPW
LIFEBUY
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ADS8517I
ADS8517IPWR
LIFEBUY
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ADS8517I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2019
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS8517IBPWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
ADS8517IPWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS8517IBPWR
TSSOP
PW
28
2000
350.0
350.0
43.0
ADS8517IPWR
TSSOP
PW
28
2000
350.0
350.0
43.0
Pack Materials-Page 2
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Copyright © 2019, Texas Instruments Incorporated
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