Texas Instruments | Dual, 12-Bit, 275 MSPS Digital-to-Analog Converter (Rev. B) | Datasheet | Texas Instruments Dual, 12-Bit, 275 MSPS Digital-to-Analog Converter (Rev. B) Datasheet

Texas Instruments Dual, 12-Bit, 275 MSPS Digital-to-Analog Converter (Rev. B) Datasheet
DAC5662
www.ti.com ................................................................................................................................................................ SLAS425B – JULY 2004 – REVISED MAY 2007
DUAL, 12-BIT 275 MSPS DIGITAL-TO-ANALOG CONVERTER
FEATURES
APPLICATIONS
•
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•
•
•
•
•
•
•
•
•
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1
2
12-Bit Dual Transmit DAC
275 MSPS Update Rate
Single Supply: 3 V to 3.6 V
High SFDR: 85 dBc at 5 MHz
High IMD3: 78 dBc at 15.1 and 16.1 MHz
WCDMA ACLR: 70 dB at 30.72 MHz
Independent or Single Resistor Gain Control
Dual or Interleaved Data
On-Chip 1.2-V Reference
Low Power: 330 mW
Power-Down Mode: 15 mW
Package: 48-Pin TQFP
•
•
•
•
Cellular Base Transceiver Station Transmit
Channel
– CDMA: W-CDMA, CDMA2000, IS-95
– TDMA: GSM, IS-136, EDGE/UWC-136
Medical/Test Instrumentation
Arbitrary Waveform Generators (ARB)
Direct Digital Synthesis (DDS)
Cable Modem Termination System (CMTS)
WRTB
WRTA
CLKB
CLKA
DE
MUX
IOUTA1
Latch A
12−b DAC
DA[11:0]
IOUTA2
BIASJ_A
IOUTB1
Latch B
DB[11:0]
12−b DAC
MODE
IOUTB2
BIASJ_B
GSET
1.2 V Reference
EXTIO
SLEEP
DVDD
DGND
AVDD
AGND
Figure 1.
DESCRIPTION
The DAC5662 is a monolithic, dual-channel 12-bit high-speed digital-to-analog converter (DAC) with on-chip
voltage reference.
Operating with update rates of up to 275 MSPS, the DAC5662 offers exceptional dynamic performance and
tight-gain and offset matching, characteristics that make it suitable in either I/Q baseband or direct IF
communication applications.
Each DAC has a high-impedance differential current output, suitable for single-ended or differential analog-output
configurations. External resistors allow scaling the full-scale output current for each DAC separately or together,
typically between 2 mA and 20 mA. An accurate on-chip voltage reference is temperature compensated and
delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used.
The DAC5662 has two 12-bit parallel input ports with separate clocks and data latches. For flexibility, the
DAC5662 also supports multiplexed data for each DAC on one port when operating in the interleaved mode.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
DAC5662
SLAS425B – JULY 2004 – REVISED MAY 2007 ................................................................................................................................................................ www.ti.com
The DAC5662 has been specifically designed for a differential transformer coupled output with a 50-Ω doubly
terminated load. For a 20-mA full-scale output current a 4:1 impedance ratio (resulting in an output power of
4 dBm) and 1:1 impedance ratio transformer (-2 dBm output power) are supported.
The DAC5662 is available in a 48-pin thin quad FlatPack (TQFP). Pin compatibility between family members
provides 12-bit (DAC5662) and 14-bit (DAC5672) resolution. Furthermore, the DAC5662 is pin compatible to the
DAC2902 and AD9765 dual DACs. The device is characterized for operation over the industrial temperature
range of -40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
48-TQFP
TA
DAC5662IPFB
-40°C to 85°C
DAC5662IPFBR
MODE
AVDD
IOUTA1
IOUTA2
BIASJ_A
EXTIO
GSET
BIASJ_B
IOUTB2
IOUTB1
AGND
SLEEP
DEVICE INFORMATION
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
Top View
48−Pin TQFP
PFB Package
6
7
32
31
30
8
29
9
28
10
27
11
26
25
12
13 14 15 16 17 18 19 20 21 22 23 24
NC
NC
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
NC
NC
DGND
DVDD
WRTA/WRTIQ
CLKA/CLKIQ
CLKB/RESETIQ
WRTB/SELECTIQ
DGND
DVDD
DB11 (MSB)
DB10
DA11 (MSB)
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0 (LSB)
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
I
Analog ground
47
I
Analog supply voltage
44
O
Full-scale output current bias for DACA
BIASJ_B
41
O
Full-scale output current bias for DACB
CLKA/CLKIQ
18
I
Clock input for DACA, CLKIQ in interleaved mode.
CLKB/RESETI
Q
19
I
Clock input for DACB, RESETIQ in interleaved mode.
DA[11:0]
1-12
I
Data port A. DA11 is MSB and DA0 is LSB. Internal pulldown.
DB[11:0]
23-34
I
Data port B. DB11 is MSB and DB0 is LSB. Internal pulldown.
NAME
NO.
AGND
38
AVDD
BIASJ_A
2
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TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
DGND
15, 21
I
Digital ground
DVDD
16, 22
I
Digital supply voltage
EXTIO
43
I/O
GSET
42
I
Gain-setting mode: H - 1 resistor, L - 2 resistors. Internal pullup.
IOUTA1
46
O
DACA current output. Full-scale with all bits of DA high.
IOUTA2
45
O
DACA complementary current output. Full-scale with all bits of DA low.
IOUTB1
39
O
DACB current output. Full-scale with all bits of DB high.
IOUTB2
40
O
DACB complementary current output. Full-scale with all bits of DB low.
MODE
48
I
Mode Select: H – Dual Bus, L – Interleaved. Internal pullup.
13, 14, 35,
36
-
No connection
SLEEP
37
I
Sleep function control input: H – DAC in power-down mode, L – DAC in operating mode. Internal
pulldown.
WRTA/WRTIQ
17
I
Input write signal for PORT A (WRTIQ in interleaving mode).
WRTB/SELEC
TIQ
20
I
Input write signal for PORT B (SELECTIQ in interleaving mode).
NC
Internal reference output (bypass with 0.1 µF to AGND) or external reference input.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Supply voltage range
AVDD
(2)
-0.5 V to 4 V
DVDD (3)
-0.5 V to 4 V
Voltage between AGND and DGND
-0.5 V to 0.5 V
Voltage between AVDD and DVDD
Supply voltage range
-0.5 V to 0.5 V
DA[11:0] and DB[11:0] (3)
-0.5 V to DVDD + 0.5 V
MODE, SLEEP, CLKA, CLKB, WRTA, WRTB (3)
-0.5 V to DVDD + 0.5 V
IOUTA1, IOUTA2, IOUTB1, IOUTB2 (2)
EXTIO, BIASJ_A, BIASJ_B, GSET
(2)
-1 V to AVDD + 0.5 V
-0.5 V to AVDD + 0.5 V
Peak input current (any input)
+20 mA
Peak total input current (all inputs)
-30 mA
Operating free-air temperature range
-40 °C to 85 °C
Storage temperature range
-65 °C to 150 °C
(1)
(2)
(3)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Measured with respect to AGND.
Measured with respect to DGND.
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC Specifications
Resolution
12
Bits
DC Accuracy (1)
INL
Integral nonlinearity
DNL
Differential nonlinearity
1 LSB = IOUTFS/212, TA = 25°C
-2
0.3
2
LSB
-2
0.2
2
LSB
Analog Output
Offset error
Gain error
Minimum full-scale output current
0.03
%FSR
With external reference
±0.25
%FSR
With internal reference
0.5
%FSR
(2)
2
Maximum full-scale output current (2)
Gain mismatch
With internal reference
Output voltage compliance range (3)
RO
Output resistance
CO
Output capacitance
mA
20
-2
0.07
-1
mA
+2
1.25
%FSR
V
300
kΩ
5
pF
Reference Output
Reference voltage
1.14
Reference output current (4)
1.2
1.26
100
V
nA
Reference Input
VEXTIO
Input voltage
RI
Input resistance
CI
0.1
1.25
V
1
MΩ
Small signal bandwidth
300
kHz
Input capacitance
100
pF
Temperature Coefficients
0
ppm of
FSR/°C
With external reference
50
ppm of
FSR/°C
With internal reference
50
ppm of
FSR/°C
20
ppm/°C
Offset drift
Gain drift
Reference voltage drift
(1)
(2)
(3)
(4)
4
Measured differentially through 50 Ω to AGND.
Nominal full-scale current, IOUTFS, equals 32x the IBIAS current.
The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,
resulting in reduced reliability of the DAC5662 device. The upper limit of the output compliance is determined by the load resistors and
full-scale output current. Exceeding the upper limit adversely affects distortion performance and intergral nonlinearity.
Use an external buffer amplifier with high impedance input to drive any external load.
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, fDATA = 200 MSPS, fOUT = 1 MHz,
independent gain set mode (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply
AVDD
Analog supply voltage
3
3.3
3.6
V
DVDD
Digital supply voltage
3
3.3
3.6
V
Including output current through load
resistor
75
90
mA
Sleep mode with clock
2.5
6
mA
Sleep mode without clock
2.5
IAVDD
IDVDD
Supply current, analog
Supply current, digital
38
mA
Sleep mode with clock
12.5
18
mA
Sleep mode without clock
<10
330
Power dissipation
Sleep mode without clock
DPSRR
TA
Power supply rejection ratio
Operating free-air temperature
µA
390
15
fDATA = 275 MSPS, fOUT = 20 MHz
APSRR
mA
25
mW
350
-0.2
0.2
-0.2
0.2
-40
85
%FSR/V
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°C
5
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ELECTRICAL CHARACTERISTICS
AC specifications over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set
mode, differential 1:1 impedance ratio transformer coupled output, 50-Ω doubly terminated load (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Output
fclk
Maximum output update rate (1)
ts
Output settling time to 0.1%
(DAC)
tr
tf
275
MSPS
20
ns
Output rise time 10% to 90%
(OUT)
1.4
ns
Output fall time 90% to 10%
(OUT)
1.5
ns
IOUTFS = 20 mA
55
pA/√Hz
IOUTFS = 2 mA
30
pA/√Hz
1st Nyquist zone, TA = 25°C, fDATA = 50
MSPS, fOUT = 1 MHz, IOUTFS = 0 dB
81
1st Nyquist zone, TA = 25°C, fDATA = 50
MSPS, fOUT = 1 MHz, IOUTFS = -6 dB
83
1st Nyquist zone, TA = 25°C, fDATA = 50
MSPS, fOUT = 1 MHz, IOUTFS = -12 dB
81
1st Nyquist zone, TA = 25°C, fDATA = 100
MSPS, fOUT = 5 MHz
85
1st Nyquist zone, TA = 25°C, fDATA = 100
MSPS, fOUT = 20 MHz
78
Output noise
Mid-scale transition
AC Linearity
SFDR
Spurious free dynamic range
1st Nyquist zone, TMIN to TMAX, fDATA = 200
MSPS, fOUT = 20 MHz
SNR
Signal-to-noise ratio
ACLR
Adjacent channel leakage ratio
IMD3
IMD
Third-order two-tone
intermodulation
Four-tone intermodulation
Channel isolation
(1)
6
66
dBc
71
1st Nyquist zone, TA = 25°C, fDATA = 200
MSPS, fOUT = 41 MHz
68
1st Nyquist zone, TA = 25°C, fDATA = 275
MSPS, fOUT = 20 MHz
72
1st Nyquist zone, TA = 25°C, fDATA = 100
MSPS, fOUT = 5 MHz
73
1st Nyquist zone, TA = 25°C, fDATA = 200
MSPS, fOUT = 20 MHz
67
W-CDMA signal with 3.84-MHz Bandwidth,
fDATA = 61.44 MSPS, IF = 15.360 MHz
70
W-CDMA signal with 3.84-MHz Bandwidth,
fDATA = 122.88 MSPS, IF = 30.72 MHz
70
Each tone at -6 dBFS, TA = 25°C,
fDATA = 200 MSPS, fOUT = 45.4 and 46.4
MHz
62
Each tone at -6 dBFS, TA = 25°C,
fDATA = 100 MSPS, fOUT = 15.1 and 16.1
MHz
78
Each tone at -12 dBFS, TA = 25°C,
fDATA = 100 MSPS, fOUT = 15.6, 15.8, 16.2,
and 16.4 MHz
77
Each tone at -12 dBFS, TA = 25°C,
fDATA = 165 MSPS, fOUT = 68.8, 69.6, 71.2,
and 72.0 MHz
56
Each tone at -12 dBFS, TA = 25°C,
fDATA = 165 MSPS, fOUT = 19.0, 19.1, 19.3,
and 19.4 MHz
74
TA = 25°C, fDATA = 165 MSPS,
fOUT (CH1) = 20 MHz, fOUT (CH2) = 21 MHz
97
dB
dB
dBc
dBc
dBc
Specified by design and bench characterization. Not production tested.
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ELECTRICAL CHARACTERISTICS
Digital specifications over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Input
VIH
High-level input voltage
2
3.3
V
VIL
Low-level input voltage
0
0.8
V
IIH
High-level input current
50
µA
IIL
Low-level input current
10
µA
IIH(GSET)
High-level input current, GSET pin
7
µA
IIL(GSET)
Low-level input current, GSET pin
-30
µA
IIH(MODE)
High-level input current, MODE pin
-30
µA
IIL(MODE)
Low-level input current, MODE pin
-80
µA
CI
Input capacitance
5
pF
SWITCHING CHARACTERISTICS
Digital specifications over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Timing - Dual Bus Mode
tsu
Input setup time
1
th
Input hold time
1
tLPH
Input clock pulse high time
tLAT
Clock latency (WRTA/B to outputs)
tPD
Propagation delay time
ns
ns
2
4
ns
4
clk
1.5
ns
ns
Timing - Single Bus Interleaved Mode
tsu
Input setup time
0.5
th
Input hold time
0.5
tLAT
Clock latency (WRTA/B to outputs)
tPD
Propagation delay time
4
ns
4
1.5
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ns
7
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TYPICAL CHARACTERISTICS
INL - Integral Nonlinearity Error - LSB
INTEGRAL NONLINEARITY
vs
INPUT CODE
0.4
0.3
0.2
0.1
-0.0
-0.1
-0.2
-0.3
-0.4
0
512
1024
1536
2048
2560
3072
3584
Input Code
4096
G001
Figure 2.
DNL - Differential Nonlinearity Error - LSB
DIFFERENTIAL NONLINEARITY
vs
INPUT CODE
0.20
0.15
0.10
0.05
-0.00
-0.05
-0.10
-0.15
-0.20
0
512
1024
1536
2048
2560
Input Code
3072
3584
4096
G002
Figure 3.
8
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TYPICAL CHARACTERISTICS (continued)
SPURIOUS-FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY
100
95
SFDR − Spurious-Free Dynamic Range − dBc
SFDR − Spurious-Free Dynamic Range − dBc
100
0 dBfS
90
85
−6 dBfS
80
75
−12 dBfS
70
65
fdata = 52 MSPS
Dual Bus Mode
60
−6 dBfS
90
0 dBfS
85
80
75
−12 dBfS
70
65
fdata = 78 MSPS
Dual Bus Mode
60
0
4
8
12
16
20
fO − Output Frequency − MHz
24
0
5
10
15
20
25
30
fO − Output Frequency − MHz
G003
Figure 4.
Figure 5.
SPURIOUS-FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY
35
G004
100
SFDR − Spurious-Free Dynamic Range − dBc
100
SFDR − Spurious-Free Dynamic Range − dBc
95
0 dBfS
95
90
85
−6 dBfS
80
75
−12 dBfS
70
65
fdata = 100 MSPS
Dual Bus Mode
60
95
90
0 dBfS
85
80
−6 dBfS
75
−12 dBfS
70
65
fdata = 165 MSPS
Dual Bus Mode
60
0
5
10
15
20
25
30
fO − Output Frequency − MHz
35
40
0
5
G005
Figure 6.
10 15 20 25 30 35 40 45 50 55 60 65
fO − Output Frequency − MHz
G006
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
SINGLE-TONE SPECTRUM
SINGLE-TONE SPECTRUM
0
0
fdata = 165 MSPS
fOUT = 30.1 MHz
Dual Bus Mode
fdata = 78 MSPS
fOUT = 15 MHz
Dual Bus Mode
−20
Power − dBm
Power - dBm
-20
-40
-60
-80
−40
−60
−80
-100
0.0
7.8
15.6
23.4
31.2
−100
0.0
39.0
16.5
f - Frequency - MHz
33.0
49.5
66.0
82.5
f − Frequency − MHz
G007
G008
Figure 8.
Figure 9.
TWO-TONE IMD3
vs
OUTPUT FREQUENCY
TWO-TONE IMD3
vs
OUTPUT FREQUENCY
95
100
fdata = 78 MSPS
Dual Bus Mode
fdata = 165 MSPS
Dual Bus Mode
95
90
85
Two-Tone IMD3 − dBc
Two-Tone IMD3 − dBc
90
80
75
70
85
80
75
70
65
60
65
55
60
50
0
5
10
15
20
25
fO − Output Frequency − MHz
30
35
0
G009
Figure 10.
10
10
20
30
40
fO − Output Frequency − MHz
50
G010
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
TWO-TONE SPECTRUM
TWO-TONE SPECTRUM
0
0
fdata = 78 MSPS
fOUT = 20.1 MHz
and 21.1 MHz
Dual Bus Mode
−20
Power − dBm
Power − dBm
−20
−40
−60
−80
fdata = 165 MSPS
fOUT = 30.1 MHz
and 31.1 Mhz
Dual Bus Mode
−40
−60
−80
−100
19.0
19.5
20.0
20.5
21.0
21.5
−100
29.0
22.0
f − Frequency − MHz
29.5
30.0
30.5
31.0
31.5
32.0
f − Frequency − MHz
G011
G012
Figure 12.
Figure 13.
POWER
vs
FREQUENCY
POWER
vs
FREQUENCY
−20
−20
fdata = 122.88 MSPS
Baseband Signal
ACPR = 72 dB
Dual Bus Mode
−40
Power − dBm
Power − dBm
−40
−60
−80
−100
fdata = 122.88 MSPS
IF = 30.72 MHz
ACPR = 72 dB
Dual Bus Mode
−60
−80
−100
−120
0
1
2
3
4
5
6
7
8
9
10
−120
18 20 22 24 26 28 30 32 34 36 38 40 42 44
f − Frequency − MHz
f − Frequency − MHz
G013
Figure 14.
G014
Figure 15.
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Digital Inputs and Timing
Digital Inputs
The data input ports of the DAC5662 accept a standard positive coding with data bit D11 being the most
significant bit (MSB). The converter outputs support a clock rate of up to 275 MSPS. The best performance will
typically be achieved with a symmetric duty cycle for write and clock; however, the duty cycle may vary as long
as the timing specifications are met. Similarly, the setup and hold times may be chosen within their specified
limits.
All digital inputs of the DAC5662 are CMOS compatible. Figure 16 and Figure 17 show schematics of the
equivalent CMOS digital inputs of the DAC5662. The pullup and pulldown circuitry is approximately equivalent to
100kΩ. The 12-bit digital data input follows the offset positive binary coding scheme. The DAC5662 is designed
to operate with a digital supply (DVDD) of 3 V to 3.6 V.
DVDD
DA[11:0]
DB[11:0]
SLEEP
CLKA/B
WRTA/B
400W
Internal
Digital In
100kW
DGND
Figure 16. CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor
DVDD
100kW
GSET
MODE
400W
Internal
Digital In
DGND
Figure 17. CMOS/TTL Digital Equivalent Input With Internal Pullup Resistor
Input Interfaces
The DAC5662 features two operating modes selected by the MODE pin, as shown in Table 1.
• For dual-bus input mode, the device essentially consists of two separate DACs. Each DAC has its own
separate data input bus, clock input, and data write signal (data latch-in).
• In single-bus interleaved mode, the data should be presented interleaved at the I-channel input bus. The
Q-channel input bus is not used in this mode. The clock and write input are now shared by both DACs.
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Table 1. Operating Modes
MODE PIN
Mode pin connected to DGND
Mode pin connected to DVDD
Bus input
Single-bus interleaved mode, clock and write input equal for both
DACs
Dual-bus mode, DACs operate
independently
Dual-Bus Data Interface and Timing
In dual-bus mode, the MODE pin is connected to DVDD. The two converter channels within the DAC5662 consist
of two independent, 12-bit, parallel data ports. Each DAC channel is controlled by its own set of write (WRTA,
WRTB) and clock (CLKA, CLKB) lines. The WRT lines control the channel input latches and the CLK lines
control the DAC latches. The data is first loaded into the input latch by a rising edge of the WRT line
The internal data transfer requires a correct sequence of write and clock inputs, since essentially two clock
domains having equal periods (but possibly different phases) are input to the DAC5662. This is defined by a
minimum requirement of the time between the rising edge of the clock and the rising edge of the write inputs.
This essentially implies that the rising edge of CLK must occur at the same time or before the rising edge of the
WRT signal. A minimum delay of 2 ns should be maintained if the rising edge of the clock occurs after the rising
edge of the write. Note that these conditions are satisfied when the clock and write inputs are connected
externally. Note that all specifications were measured with the WRT and CLK lines connected together.
D[11:0]
Valid Data
tsu
th
t1ph
WRT1/
WRT2
CLK1/
CLK2
tsettle
tlat
tpd
IOUT
or
IOUT
Figure 18. Dual Bus Mode Operation
Single-Bus Interleaved Data Interface and Timing
In single-bus interleaved mode, the MODE pin is connected to DGND. Figure 19 shows the timing diagram. In
interleaved mode, the I- and Q-channels share the write input (WRTIQ) and update clock (CLKIQ and internal
CLKDACIQ). Multiplexing logic directs the input word at the I-channel input bus to either the I-channel input latch
(SELECTIQ is high) or to the Q-channel input latch (SELECTIQ is low). When SELECTIQ is high, the data value
in the Q-channel latch is retained by presenting the latch output data to its input again. When SELECTIQ is low,
the data value in the I-channel latch is retained by presenting the latch output data to its input.
In interleaved mode, the I-channel input data rate is twice the update rate of the DAC core. As in dual-bus mode,
it is important to maintain a correct sequence of write and clock inputs. The edge-triggered flip-flops latch the Iand Q-channel input words on the rising edge of the write input (WRTIQ). This data is presented to the I- and
Q-DAC latches on the following falling edge of the write inputs. The DAC5662 clock input is divided by a factor of
two before it is presented to the DAC latches.
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Correct pairing of the I- and Q-channel data is done by RESETIQ. In interleaved mode, the clock input CLKIQ is
divided by two, which would translate to a non-deterministic relation between the rising edges of the CLKIQ and
CLKDACIQ. RESETIQ ensures, however, that the correct position of the rising edge of CLKDACIQ with respect
to the data at the input of the DAC latch is determined. CLKDACIQ is disabled (low) when RESETIQ is high.
D[11:0]
Valid Data
tsu
th
SELECTIQ
WRTIQ
CLKIQ
RESETIQ
tsettle
tlat
tpd
IOUT
or
IOUT
Figure 19. Single-Bus Interleaved Mode Operation
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APPLICATION INFORMATION
Theory of Operation
The architecture of the DAC5662 uses a current steering technique to enable fast switching and high update
rate. The core element within the monolithic DAC is an array of segmented current sources that are designed to
deliver a full-scale output current of up to 20 mA. An internal decoder addresses the differential current switches
each time the DAC is updated and a corresponding output current is formed by steering all currents to either
output summing node, IOUT1 and IOUT2. The complementary outputs deliver a differential output signal, which
improves the dynamic performance through reduction of even-order harmonics, common-mode signals (noise),
and double the peak-to-peak output signal swing by a factor of two, compared to single-ended operation.
The segmented architecture results in a significant reduction of the glitch energy, improves the dynamic
performance (SFDR), and DNL. The current outputs maintain a high output impedance of greater
than 300 kΩ.
When GSET is high (one resistor mode), the full-scale output current for both DACs is determined by the ratio of
the internal reference voltage (1.2 V) and an external resistor RSET connected to BIASJ_A. When GSET is low
(two resistor mode), the full-scale output current for each DACs is determined by the ratio of the internal
reference voltage (1.2 V) and separate external resistors RSET connected to BIASJ_A and BIASJ_B. The
resulting IREF is internally multiplied by a factor of 32 to produce an effective DAC output current that can range
from 2 mA to 20 mA, depending on the value of RSET.
The DAC5662 is split into a digital and an analog portion, each of which is powered through its own supply pin.
The digital section includes edge-triggered input latches and the decoder logic, while the analog section
comprises the current source array with its associated switches, and the reference circuitry.
DAC Transfer Function
Each of the DACs in the DAC5662 has a set of complementary current outputs, IOUT1 and IOUT2. The full-scale
output current, IOUTFS, is the summation of the two complementary output currents:
I
+I
)I
OUTFS
OUT1
OUT2
(1)
The individual output currents depend on the DAC code and can be expressed as:
I
OUT1
+I
OUTFS
ǒCode
Ǔ
4096
(2)
æ 4095 - Code ÷ö
IOUT2 = IOUTFS x çç
÷÷
çè
ø
4096
(3)
where Code is the decimal representation of the DAC data input word. Additionally, IOUTFS is a function of the
reference current IREF, which is determined by the reference voltage and the external setting resistor (RSET).
V
REF
I
+ 32 I
+ 32
OUTFS
REF
R
SET
(4)
In most cases, the complementary outputs drive resistive loads or a terminated transformer. A signal voltage
develops at each output according to:
V
+I
R
OUT1
OUT1
LOAD
(5)
V
+I
R
OUT2
OUT2
LOAD
(6)
The value of the load resistance is limited by the output compliance specification of the DAC5662. To maintain
specified linearity performance, the voltage for IOUT1 and IOUT2 should not exceed the maximum allowable
compliance range.
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The total differential output voltage is:
V
+V
*V
OUTDIFF
OUT1
OUT2
(2 Code * 4095)
V
+
I
OUTDIFF
OUTFS
4096
(7)
R
LOAD
(8)
Analog Outputs
AVDD
S(1)
IOUT1
RLOAD
S(1)C
IOUT2
S(2)
S(2)C
S(N)
S(N)C
Current Source Array
RLOAD
Figure 20. Analog Outputs
The DAC5662 provides two complementary current outputs, IOUT1 and IOUT2. The simplified circuit of the
analog output stage representing the differential topology is shown in Figure 20. The output impedance of IOUT1
and IOUT2 results from the parallel combination of the differential switches, along with the current sources and
associated parasitic capacitances.
The signal voltage swing that may develop at the two outputs, IOUT1 and IOUT2, is limited by a negative and
positive compliance. The negative limit of –1 V is given by the breakdown voltage of the CMOS process and
exceeding it compromises the reliability of the DAC5662 or even causes permanent damage. With the full-scale
output set to 20 mA, the positive compliance equals 1.2 V. Note that the compliance range decreases to about 1
V for a selected output current of IOUTFS = 2 mA. Care should be taken that the configuration of DAC5662 does
not exceed the compliance range to avoid degradation of the distortion performance and integral linearity.
Best distortion performance is typically achieved with the maximum full-scale output signal limited to
approximately 0.5 Vpp. This is the case for a 50-Ω doubly terminated load and a 20-mA full-scale output current.
A variety of loads can be adapted to the output of the DAC5662 by selecting a suitable transformer while
maintaining optimum voltage levels at IOUT1 and IOUT2. Furthermore, using the differential output configuration
in combination with a transformer will be instrumental for achieving excellent distortion performance.
Common-mode errors, such as even-order harmonics or noise, can be substantially reduced. This is particularly
the case with high output frequencies.
For those applications requiring the optimum distortion and noise performance, it is recommended to select a
full-scale output of 20 mA. A lower full-scale range of 2 mA may be considered for applications that require low
power consumption, but can tolerate a slight reduction in performance level.
Output Configurations
The current outputs of the DAC5662 allow for a variety of configurations. As mentioned previously, utilizing the
converter’s differential outputs yield the best dynamic performance. Such a differential output circuit may consist
of an RF transformer or a differential amplifier configuration. The transformer configuration is ideal for most
applications with ac coupling, while op amps will be suitable for a dc-coupled configuration.
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The single-ended configuration may be considered for applications requiring a unipolar output voltage.
Connecting a resistor from either one of the outputs to ground converts the output current into a
ground-referenced voltage signal. To improve on the dc linearity by maintaining a virtual ground, an I-to-V or
op-amp configuration may be considered.
Differential With Transformer
Using an RF transformer provides a convenient way of converting the differential output signal into a
single-ended signal while achieving excellent dynamic performance. The appropriate transformer should be
carefully selected based on the output frequency spectrum and impedance requirements.
The differential transformer configuration has the benefit of significantly reducing common-mode signals, thus
improving the dynamic performance over a wide range of frequencies. Furthermore, by selecting a suitable
impedance ratio (winding ratio) the transformer can be used to provide optimum impedance matching while
controlling the compliance voltage for the converter outputs.
Figure 21 and Figure 22 show 50-Ω doubly terminated transformer configurations with 1:1 and 4:1 impedance
ratios, respectively. Note that the center tap of the primary input of the transformer has to be grounded to enable
a dc-current flow. Applying a 20-mA full-scale output current would lead to a 0.5-VPP output for a 1:1 transformer
and a 1-VPP output for a 4:1 transformer. In general, the 1:1 transformer configuration will have slightly better
output distortion, but the 4:1 transformer will have 6 dB higher output power.
50 Ω
1:1
IOUT1
100 Ω
RLOAD
50 Ω
AGND
IOUT2
50 Ω
Figure 21. Driving a Doubly Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer
100 Ω
4:1
IOUT1
AGND
RLOAD
50 Ω
IOUT2
100 Ω
Figure 22. Driving a Doubly Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer
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Single-Ended Configuration
Figure 23 shows the single-ended output configuration, where the output current IOUT1 flows into an equivalent
load resistance of 25 Ω. Node IOUT2 should be connected to AGND or terminated with a resistor of 25 Ω to
AGND. The nominal resistor load of 25 Ω gives a differential output swing of 1 VPP when applying a 20-mA
full-scale output current.
IOUT1
RLOAD
50 Ω
IOUT2
50 Ω
25 Ω
AGND
Figure 23. Driving a Doubly Terminated 50-Ω Cable Using a Single-Ended Output
Reference Operation
Internal Reference
The DAC5662 has an on-chip reference circuit which comprises a 1.2-V bandgap reference and two control
amplifiers, one for each DAC. The full-scale output current, IOUTFS, of the DAC5662 is determined by the
reference voltage, VREF, and the value of resistor RSET. IOUTFS can be calculated by:
V
REF
I
+ 32 I
+ 32
OUTFS
REF
R
SET
(9)
The reference control amplifier operates as a V-to-I converter producing a reference current, IREF, which is
determined by the ratio of VREF and RSET (see Equation 9). The full-scale output current, IOUTFS, results from
multiplying IREF by a fixed factor of 32.
Using the internal reference, a 2-kΩ resistor value results in a full-scale output of approximately 20 mA. Resistors
with a tolerance of 1% or better should be considered. Selecting higher values, the output current can be
adjusted from 20 mA down to 2 mA. Operating the DAC5662 at lower than 20-mA output currents may be
desirable for reasons of reducing the total power consumption, improving the distortion performance, or
observing the output compliance voltage limitations for a given load condition.
It is recommended to bypass the EXTIO pin with a ceramic chip capacitor of 0.1 µF or more. The control
amplifier is internally compensated and its small signal bandwidth is approximately 300 kHz.
External Reference
The internal reference can be disabled by simply applying an external reference voltage into the EXTIO pin,
which in this case functions as an input. The use of an external reference may be considered for applications that
require higher accuracy and drift performance or to add the ability of dynamic gain control.
While a 0.1-µF capacitor is recommended to be used with the internal reference, it is optional for the external
reference operation. The reference input, EXTIO, has a high input impedance (1 MΩ) and can easily be driven
by various sources. Note that the voltage range of the external reference should stay within the compliance
range of the reference input.
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Gain Setting Option
The full-scale output current on the DAC5662 can be set two ways: either for each of the two DAC channels
independently or for both channels simultaneously. For the independent gain set mode, the GSET pin (pin 42)
must be low (i.e. connected to AGND). In this mode, two external resistors are required — one RSET connected
to the BIASJ_A pin (pin 44) and the other to the BIASJ_B pin (pin 41). In this configuration, the user has the
flexibility to set and adjust the full-scale output current for each DAC independently, allowing for the
compensation of possible gain mismatches elsewhere within the transmit signal path.
Alternatively, bringing the GSET pin high (i.e. connected to AVDD), the DAC5662 switches into the simultaneous
gain set mode. Now the full-scale output current of both DAC channels is determined by only one external RSET
resistor connected to the BIASJ_A pin. The resistor at the BIASJ_B pin may be removed, however this is not
required since this pin is not functional in this mode and the resistor has no effect on the gain equation.
Sleep Mode
The DAC5662 features a power-down function which can be used to reduce the total supply current to less than
3.5 mA over the specified supply range if no clock is present. Applying a logic high to the SLEEP pin initiates the
power-down mode, while a logic low enables normal operation. When left unconnected, an internal active
pulldown circuit enables the normal operation of the converter.
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC5662IPFB
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAC5662I
DAC5662IPFBR
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAC5662I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Oct-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC5662 :
• Enhanced Product: DAC5662-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DAC5662IPFBR
Package Package Pins
Type Drawing
TQFP
PFB
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
16.4
Pack Materials-Page 1
9.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.6
1.5
12.0
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC5662IPFBR
TQFP
PFB
48
1000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°– 7°
1,05
0,95
Seating Plane
0,75
0,45
0,08
1,20 MAX
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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• DALLAS, TEXAS 75265
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