Texas Instruments | 16-Channel, Current-Input Analog-to-Digital Converter (Rev. A) | Datasheet | Texas Instruments 16-Channel, Current-Input Analog-to-Digital Converter (Rev. A) Datasheet

Texas Instruments 16-Channel, Current-Input Analog-to-Digital Converter (Rev. A) Datasheet
DDC316
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16-Channel, Current-Input
Analog-to-Digital Converter
FEATURES
DESCRIPTION
1
• SINGLE-CHIP SOLUTION TO MEASURE 16
LOW-LEVEL CURRENTS
• INTEGRATING I-TO-V CONVERSION
FRONT-END
• PROGRAMMABLE FULL-SCALE : 3pC to 12pC
• ADJUSTABLE SPEED:
– Data Rate Up To 100kSPS
– Integration Time Down To 10µs
• ANALOG SUPPLY: +5V
• DIGITAL SUPPLY: +3.3V
2
For each of the 16 inputs, the DDC316 provides a
dual-switched integrator front-end. This configuration
allows for continuous current integration: while one
integrator is being digitized by the on-chip ADC, the
other is integrating the input current. Adjustable
integration times range from 10µs to 1ms.
The DDC316 provides a serial interface of the output
data, either multiplexed onto a single data output pin
or parallel on four output pins. The output mode can
be selected based on the available integration time.
APPLICATIONS
•
•
•
The DDC316 is a 16-bit, 16-channel, current-input
analog-to-digital converter (ADC). It combines both
current-to-voltage
and
analog-to-digital
(A/D)
conversion so that 16 separate low-level current
output devices (such as photodiodes) can be directly
connected to its inputs and digitized.
CT SCANNER DAS
PHOTODIODE SENSORS
X-RAY DETECTION SYSTEMS
The DDC316 uses a +5V analog supply and a +3.3V
digital supply. Operating over the temperature range
of 0°C to +70°C, the DDC316 is offered in a BGA-64
package.
Protected by US Patent #5841310
AVDD
IN1
VREF
DVDD
DDC316
I to V
CLK
IN2
Control
I to V
CONV
DIN_CFG
RESET
IN3
I to V
DVALID
ADCs
DIN
IN4
DCLK
I to V
Serial
Interface
DOUT1
DOUT2
IN16
DOUT3
DOUT4
I to V
AGND
DGND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2009, Texas Instruments Incorporated
DDC316
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
AVDD to AGND
–0.3V to +6V
DVDD to DGND
–0.3V to +3.6V
AGND to DGND
±0.2V
VREF Input to AGND
2.0V to AVDD + 0.3V
Analog Input to AGND
–0.3V to +0.7V
Digital Input Voltage to DGND
–0.3V to DVDD + 0.3V
Digital Output Voltage to DGND
–0.3V to AVDD + 0.3V
Operating Temperature
0°C to +70°C
Storage Temperature
–60°C to +150°C
Junction Temperature (TJ)
(1)
2
+150°C
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
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ELECTRICAL CHARACTERISTICS
At TA = +25°C, AVDD = +5V, DVDD = +3.3V, VREF = +4.096V, tINT = 20µs, Range = 12pC, Format = 16 bits, CLK = 40MHz,
and HI_SPEED Bit = 1, unless otherwise noted.
DDC316
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Range 1
2.4
3
3.6
pC
Range 2
4.8
6
7.2
pC
Range 3
9.6
12
14.4
pC
Negative Full-Scale Range
–1.786% of Positive Full-Scale Range
ANALOG INPUT RANGE
pC
DYNAMIC CHARACTERISTICS
Data Rate
Integration Time, tINT
100
kSPS
HI_SPEED Bit = 1
20
1,000
µs
HI_SPEED Bit = 0
10
20
µs
1
40
MHz
40
MHz
20
MHz
System Clock Input
Data Clock (DCLK)
Daisy-Chain Readback
ACCURACY
Resolution
12
Noise, Low-Level Input (1)
CSENSOR (2) = 10pF
Integral Linearity Error (4)
Input Bias Current
TA = +25°C
Range Error Match (5)
Range Sensitivity to VREF
VREF = 4.096 ± 0.1V
16
Bits
3.5
6.0
LSB (3)
8
16
LSB (3)
±2
±10
pA
0.2
1
% of FSR (6)
1:1
Offset Error
±50
±200
LSB (3)
Offset Error Match (5)
±75
±400
LSB (3)
Low-Level Input (< 1% FSR)
±2
±10
mV
at DC
40
LSB (3)/V
±1
LSB/°C
Continuous Readings Over 1-Minute
Intervals After a 10-Minute Warm-Up
<1
LSB
±10
µV/°C
Range Drift (8)
25
ppm/°C
Range Drift Match (5)
±10
ppm/°C
DC Bias Voltage (7)
Power-Supply Rejection Ratio
PERFORMANCE OVER TEMPERATURE
Offset Drift
Offset Drift Stability
DC Bias Voltage Drift (7)
Input Bias Current Drift
Doubles Every +10°C
REFERENCE
Voltage
4.000
4.096
4.200
V
DIGITAL INPUT/OUTPUT
Logic Levels
VIH
0.8DVDD
DVDD + 0.1
V
VIL
–0.1
0.2DVDD
V
VOH
IOH = –100µA
VOL
IOL = 100µA
0.4
V
0 < VIN < DVDD
±10
µA
Input Current (IIN)
DVDD – 0.4
Data Format (9)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
V
Straight Binary
Input is less than 1% of full-scale.
CSENSOR is the capacitance seen at the DDC316 inputs from wiring, photodiode, etc.
LSB refers to 16-bit resolution.
A best-fit line is used in measuring nonlinearity.
Matching between side A and side B of the same input.
FSR is full-scale range.
Voltage produced by the DDC316 at its input that is applied to the sensor.
Range drift does not include external reference drift.
Data format is Straight Binary with a small offset. The number of bits in the output word is controlled by the Format bit.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = +25°C, AVDD = +5V, DVDD = +3.3V, VREF = +4.096V, tINT = 20µs, Range = 12pC, Format = 16 bits, CLK = 40MHz,
and HI_SPEED Bit = 1, unless otherwise noted.
DDC316
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Power-Supply Voltage (AVDD)
4.75
5.0
5.25
V
Digital Power-Supply Voltage (DVDD)
3
3.3
3.6
V
POWER-SUPPLY REQUIREMENTS
Supply Current
Analog Current
Internal Reference Buffer
BUFDIS Bit = 0
95
mA
External Reference Buffer
BUFDIS Bit = 1
85
mA
DVDD = +3.3V
5
mA
Internal Reference Buffer
BUFDIS Bit = 0, DVDD = +3.3V
540
External Reference Buffer
BUFDIS Bit = 1, DVDD = +3.3V
440
Internal Reference Buffer
BUFDIS Bit = 0, DVDD = +3.3V
31
External Reference Buffer
BUFDIS Bit = 1, DVDD = +3.3V
28
Digital Current
Total Power Dissipation
mW
640
mW
Per Channel Power Dissipation
4
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mW/channel
40
mW/channel
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PIN CONFIGURATION
GXG AND ZXG PACKAGES
BGA-64
(TOP VIEW)
Columns
H
G
F
E
D
C
B
A
IN1
IN3
IN9
IN12
IN5
IN7
IN13
IN15
1
IN2
IN4
IN10
IN11
IN6
IN8
IN14
IN16
2
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
3
AVDD
AVDD
AVDD
AVDD
AVDD
AGND
VREF_IN
VREF
4
AGND
AGND
AGND
AGND
AGND
AGND
AGND
5
AVDD
AVDD
AVDD
AVDD
AGND
DGND
VREF
Rows
QGND
VREF
6
DVALID
DIN_CFG
DGND
DIN
AGND
DGND
DVDD
RESET
7
DOUT1
DOUT2
DOUT3
DOUT4
DCLK
CLK
DVDD
CONV
8
PIN DESCRIPTIONS
PIN
LOCATION
FUNCTION
DESCRIPTION
IN1–16
1A-1H, 2A-2H
Analog Input
Analog Inputs for Channels 1 to 16
AGND
3A-3H, 4C, 5A-5G, 6D, 7D
Analog
VREF
4A, 6A, 6B
Analog Input
Voltage Reference for Internal Reference Buffer Mode
VREF_IN
4B
Analog Input
Voltage Reference for External Reference Buffer Mode
AVDD
4D-4H, 6E, 6F, 6G, 6H
Analog
Analog Power Supply, +5V Nominal
QGND
5H
Analog
Quiet Analog Ground
Digital Ground
Analog Ground
DGND
6C, 7C, 7F
Digital
RESET
7A
Digital Input
DVDD
7B, 8B
Digital
DIN
7E
Digital Input
Serial Data Input for Daisy-Chain
DIN_CFG
7G
Digital Input
Configuration Register Data Input
DVALID
7H
Digital Output
CONV
8A
Digital Input
Conversion Control Input; 0 = Integrate on Side B, 1 = Integrate on Side A
Digital Reset, Active Low
Digital Power Supply, +3V Nominal
Data Valid Output, Active Low
CLK
8C
Digital Input
Master Clock Input
DCLK
8D
Digital Input
Serial Data Clock Input
DOUT4-1
8E-8H
Digital Output
Serial Data Output
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DDC316
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TIMING DIAGRAMS
tCLK
tCLKPW
CLK
tCLKPW
CONV
tINTB
tINTA
tMEAS
DVALID
tDCDV
DIN
tDIDC
tDCDI
tCNDC
DCLK
tDVDO
DOUT(1)
tDOHD
tCNDC
tDCLKPW
tDOPD
MSB
tDCLK
tDCLKPW
LSB
Side B Data
Side A Data
NOTE: (1) DOUT1 in TDM data output mode; DOUT1 through DOUT4 in parallel data output mode.
Figure 1. Serial Interface Timing
TIMING REQUIREMENTS FOR Figure 1
At TA = 0°C to +70°C and DVDD = 3V to 3.6V, unless otherwise noted.
SYMBOL
tCLK
tCLKPW
tINTA,B
UNIT
1000
ns
0.4
tCLK periods
1000
tCLK periods
HI_SPEED bit = 0, CLK = 40MHz
10
25
µs
HI_SPEED bit = 1
800
40,000
tCLK periods
HI_SPEED bit = 1, CLK = 40MHz
20
1000
HI_SPEED bit = 0
tDIDC
Setup time from DIN to rising edge of DCLK
2
tDCDI
Hold time for DIN after rising edge of DCLK
0
tDCLK
MAX
400
Time required to perform
measurement
(1)
TYP
HI_SPEED bit = 0
tMEAS
tDCDV
HI_SPEED bit = 1
Falling edge of DVALID to valid DOUT
tCLK periods
544
tCLK periods
ns
ns
6
Falling edge of first DCLK to rising edge of DVALID
µs
274
10
19
ns
ns
DCLK period (1/fDCLK)
25
ns
tDCLKPW
DCLK pulse width, positive or negative
0.4
tDCLK periods
tDOPD (1)
Propagation delay from the falling edge of DCLK to valid DOUT1
tDOHD
(1)
tCNDC
6
MIN
25
CLK pulse width, positive or negative
Integration time for sides A and B
tDVDO (1)
(1)
DESCRIPTION
CLK period (1/fCLK)
21
ns
Hold time during which previous DOUT1 is valid after falling edge of
DCLK
5
ns
Time between CONV toggle and data retrieval
5
ns
Output load = 100kΩ || 10pF
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CLK
tSC
DIN_CFG
1
0
1
0
CFG
Bit 15
tHC
CFG
Bit 0
tDVC
DVALID
tDCDV
DCLK
tDVDO
tDOPD
tDOHD
CFG
Bit 15
DOUT1
CFG
Bit 0
Figure 2. Configuration Register Read/Write Timing
TIMING REQUIREMENTS FOR Figure 2
At TA = 0°C to +70°C and DVDD = 3.0V to 3.6V, unless otherwise noted.
SYMBOL
MIN
TYP
tSC
Valid DIN_CFG to CLK falling edge; setup time
1
12
ns
tHC
Valid DIN_CFG to CLK falling edge; hold time
3
12
ns
Delay of DVALID from falling edge of CLK
18
ns
tDVC (1)
tDCDV
(1)
(1)
DESCRIPTION
Falling edge of first DCLK to rising edge of DVALID
19
tDVDO (1)
Delay from DVALID falling edge to valid CFG bit 15 on DOUT1
6
tDOPD (1)
Propagation delay from the falling edge of DCLK to valid DOUT1
tDOHD (1)
Hold time during which previous DOUT1 is valid after falling edge of
DCLK
MAX
UNIT
ns
10
ns
21
ns
5
ns
Output load = 100kΩ || 10pF
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TYPICAL CHARACTERISTICS
At TA = +25°C, unless otherwise indicated.
NOISE vs CSENSOR
NOISE vs CSENSOR
25
Noise (16-Bit LSBs of FSR, rms)
HI_SPEED Bit = 1
20
Range 1
15
Range 2
10
Noise (16-Bit LSBs of FSR, rms)
CSENSOR
(pF)
Range 1
Range 2
Range 3
0
10
20
30
50
100
10.2
13.1
17.5
18.6
22.3
34.3
5.6
7.2
9.2
9.7
11.6
17.8
3.3
4.1
5.1
5.4
6.4
9.4
NOTE: HI_SPEED bit = 1.
5
Range 3
0
0
5
10
15
20
25
30
CSENSOR (pF)
Figure 3.
8
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THEORY OF OPERATION
GENERAL DESCRIPTION
The DDC316 contains 16 identical input channels that
perform the function of current-to-voltage integration,
followed by a multiplexed A/D conversion. Integration
time is directly controlled via the CONV pin. Each
input uses a dual-switched integrator so that the
current-to-voltage integration can be continuous over
AVDD
VREF
time. The 16 integrators from one side of the inputs
are digitized, while the other 16 are integrating to
achieve continuous charge collection. The results
from the conversion are stored in a serial output shift
register. The DVALID output goes low when the shift
register contains valid data. A block diagram of the
DDC316 is shown in Figure 4.
VREF_IN DVDD
CLK
IN1
Dual
Switched
Integrator
Configuration
and
Control
CONV
DIN_CFG
IN2
Dual
Switched
Integrator
RESET
ADC 1
IN3
Dual
Switched
Integrator
DVALID
IN4
DIN
Dual
Switched
Integrator
DCLK
Digital
Input/Output
IN13
DOUT1
Dual
Switched
Integrator
DOUT2
DOUT3
IN14
Dual
Switched
Integrator
DOUT4
ADC 4
IN15
Dual
Switched
Integrator
IN16
Dual
Switched
Integrator
AGND
DGND
Figure 4. DDC316 Block Diagram
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BASIC INTEGRATION CYCLE
The topology of the front-end of the DDC316 is an
analog integrator, as shown in Figure 5. In this
diagram, only input IN1 is shown. The input stage
consists of an operational amplifier, a selectable
feedback capacitor network (CF), and several
switches that implement the integration cycle.
The timing relationships of all of the switches shown
in Figure 5 are illustrated in Figure 6. Note that
Figure 6 conceptualizes the operation of the
integrator input stage of the DDC316 and should not
be used as an exact timing tool for design.
SREF
VREF
1.5pF
Range[1]
0.75pF
Range[0]
0.75pF
Input
Current
SINTA
SREF
IN1
SADC1A
SRESET
ESD
Protection
Diodes
Photodiode
To Converter
Integrator A
SINTB
Integrator B (same as A)
Figure 5. Basic Integration Configuration for Input 1
Integrate on Side B
Integrate on Side A
Integrate on Side B
CONV
CLK
SINTA
SINTB
SREF
SRESET
Integrate
Convert
Wait
Wait
Wait
Reset
Convert
Wait
Configuration of
Integrator A
Reset
SADC1A
VREF
Integrator A
Voltage Output
Figure 6. Conceptual Basic Integration Timing Diagram of Integrator A (as Illustrated in Figure 5)
10
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Figure 7 shows the block diagrams of the five states
of the front end integrator. The conversion starts with
the integrator being configured as shown in
Figure 7a. In this state, the ADC converts the
integrated value of side A of the previous phase.
Once the conversion is done, the integrator waits until
the ADC finishes converting the other three integrated
values (Figure 7b). At the completion of all four A/D
conversions, the charge on the integrator capacitor
(CF) is reset with SREF and SRESET (see Figure 7c). In
this manner, the selected capacitor is charged to the
reference voltage, VREF. Once the integration
capacitor is charged, SREF and SRESET are switched
so that VREF is no longer connected to the amplifier
circuit while it waits to begin integrating (see
Figure 7d). With the rising edge of CONV, SINTA
closes, which begins the integration of side A. This
process puts the integrator stage into Integrate mode
(see Figure 7e).
Charge from the input signal is collected on the
integration capacitor, causing the voltage output of
the amplifier to decrease. The falling edge of CONV
stops the integration by switching the input signal
from side A to side B (SINTA and SINTB). Before the
falling edge of CONV, the signal on side B was
converted by the ADC and reset during the time that
side A was integrating. With the falling edge of
CONV, side B starts integrating the input signal. At
this point, the output voltage of the side A operational
amplifier is presented to the input of the ADC, and
the entire cycle repeats.
This internal switching network is controlled externally
with the convert pin (CONV) and the system clock
(CLK). For the best noise performance, CONV must
be synchronized with the rising edge of CLK. It is
recommended that CONV toggle within ±5ns of the
rising edge of CLK. The noninverting inputs of the
integrators are connected to ground. Consequently,
the DDC316 analog ground should be as clean as
possible.
SREF
CF
CF
SREF
VREF
SINT
VREF
SINT
SREF
IN
SREF
IN
To
Converter
SRESET
SADC
SRESET
SADC
a) Convert Configuration
b) Wait to Reset Configuration
SREF
CF
CF
SREF
VREF
SINT
To
Converter
VREF
SINT
SREF
SREF
IN
IN
To
Converter
SRESET
SADC
SRESET
SADC
To
Converter
d) Wait to Integrate Configuration
c) Reset Configuration
CF
SREF
VREF
SINT
SREF
IN
SRESET
SADC
To
Converter
e) Integrate Configuration
Figure 7. Diagrams for the Five Configurations of DDC316 Front-End Integrators
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FREQUENCY RESPONSE
Ranges
The frequency response of the DDC316 is set by the
front-end integrators and is consistent with a
traditional continuous time integrator, as shown in
Figure 8. By adjusting tINT, the user can change the
3dB bandwidth and the location of the notches in the
response. The frequency response of the ADC that
follows the front-end integrator is of no consequence
because the converter samples a held signal from the
integrators. That is, the input to the ADC is always a
DC signal. Aliasing can occur because the output of
the front-end integrators are sampled. Whenever the
frequency of the input signal exceeds one-half of the
sampling rate, the signal folds back down to lower
frequencies.
There are three different capacitors available on-chip
for both sides of every channel in the DDC316. The
range control bits (Range[1:0]) change the capacitor
value for all integrators. Consequently, all inputs and
both sides of each input always have the same
full-scale (FS) range. Table 1 shows the capacitor
value selected for each range selection.
Table 1. Range Selection
RANGE
RANGE[1:0]
BITS
CF
(pF, typ)
INPUT RANGE
(pC, typ)
1
00
0.75
–0.0469 to 3
2
01
1.5
–0.0938 to 6
3
10
3
–0.1876 to 12
0
Resolution
Gain (dB)
-10
-20
-30
-40
-50
0.1
tINT
1
tINT
10
tINT
100
tINT
Frequency
Figure 8. DDC316 Frequency Response
The DDC316 provides three different resolutions for
the convenience of the user. The user can select the
resolution needed for the application and the time
available for data retrieval. The three available
resolutions are 16-bit, 14-bit, and 12-bit. The serial
output data from the DDC316 are provided in an
offset binary code, as shown in Table 2. The RES
bits in the configuration register select how many bits
are used in the output word. When 12-bits are
selected, the last four bits are truncated; when 14-bits
are chosen, the last two bits are truncated. Note that
an offset is included in the output to allow slightly
negative inputs (for example, from board leakages)
from clipping the reading. The offset is approximately
1.8% of the positive full-scale.
OPERATION SETTINGS
Data Format
The DDC316 provides different settings of operation
to provide flexibility in terms of range, resolution, etc.
The settings are programmable using an on-chip
register and are described in the following sections.
The DDC316 outputs 12 to 16 bits of data depending
on the selected resolution. The format is straight
binary with an offset to help prevent leakage currents
from the printed circuit board (PCB), or the sensors
forcing a clipping on the negative full-scale. Table 2
summarizes the ideal output codes for the different
resolutions.
Table 2. Ideal Output Code (1) vs Input Signal
(1)
12
INPUT
SIGNAL
IDEAL OUTPUT CODE
RESOLUTION = 16 BITS
IDEAL OUTPUT CODE
RESOLUTION = 14 BITS
IDEAL OUTPUT CODE
RESOLUTION = 12 BITS
≥ 100% FS
1111 1111 1111 1111
1111 1111 1111 11
1111 1111 1111
0.07019% FS
0000 0100 1100 0000
0000 0100 1100 00
0000 0100 1100
0.02136% FS
0000 0100 1010 0000
0000 0100 1010 00
0000 0100 1010
0.00305% FS
0000 0100 1001 0100
0000 0100 1001 01
0000 0100 1001
0.001525% FS
0000 0100 1001 0011
0000 0100 1001 00
0000 0100 1001
0% FS
0000 0100 1001 0010
0000 0100 1001 00
0000 0100 1001
–1.7857% FS
0000 0000 0000 0000
0000 0000 0000 00
0000 0000 0000
Excludes the effects of noise, INL, offset, and gain errors.
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Data Output Modes
The DDC316 provides two data output modes: time
division multiplexed (TDM) and parallel. In TDM
mode, data from all 16 channels are output on a
single data output line, DOUT1, as shown in Figure 9.
In this mode, DOUT2 through DOUT4 are not used
and forced to logic low.
In parallel output mode, as shown in Figure 10, four
channels of data are output on the four DOUT lines,
DOUT1 thorough DOUT4.
In either mode, the most significant bit (MSB) is
shifted out first.
CLK
CONV
256 DCLKs (16-Bit Resolution)
DVALID
DCLK
DOUT1
TDM Data for Inputs 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
DOUT2
DOUT3
DOUT4
Figure 9. TDM Data Output
CLK
CONV
64 DCLKs (16-Bit Resolution)
DVALID
DCLK
DOUT1
Data for Inputs 1, 2, 3, 4
DOUT2
Data for Inputs 5, 6, 7, 8
DOUT3
Data for Inputs 9, 10, 11, 12
DOUT4
Data for Inputs 13, 14, 15, 16
Figure 10. Parallel Data Output
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MINIMUM INTEGRATION TIME
DATA RETRIEVAL TIME
The minimum integration time of the DDC316 is set
by the master clock (CLK) and the HI_SPEED bit, as
shown in Table 3. The integration time specification
must always be met for both side A and side B
integrations (tINTA and tINTB). Failure to meet
integration
time
specifications
gives
invalid
conversion results.
The available time for retrieving the conversion data
(tRETRV) from the DDC316 is the difference between
the integration time (tINT) and the measurement time
(tMEAS), as shown in Figure 11. Retrieval begins after
DVALID goes low, and must complete before CONV
toggles, for optimal noise performance (see the tCNDC
timing specification).
Table 3. Minimum Integration Times
Sometimes, it is not possible to retrieve all of the data
in time when using the TDM data output mode; for
example, when integration times are short and DCLK
is slow. In these cases, using the parallel data output
mode will help because the required time for retrieval
decreases by a factor of four.
HI_SPEED
VALID
BIT
RESOLUTIONS
MINIMUM INTEGRATION TIME
(MINIMUM tINT)
0
12-bit only
400 tCLK
periods
10µs
(for CLK = 40MHz)
1
12-bit to 16-bit
800 tCLK
periods
20µs
(for CLK = 40MHz)
tINT
CONV
When operating with the HI_SPEED bit set to 0, the
DDC316 operates internally at a higher speed and
the performance is reduced to fundamentally 12 bits.
It is recommended, therefore, that the RES[1:0] bits
should be set to 12-bit resolution when HI_SPEED =
0. This will provide more flexibility in retrieving data,
because the time required to read back the
conversion results is shorter.
tMEAS
tRETRV
DVALID
tCNDC
DCLK
DOUT
Figure 11. Data Retrieval Time
14
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CONFIGURATION REGISTER
The DDC316 configuration shown in Table 4 is controlled by and configured with an on-chip, 16-bit configuration
register.
Table 4. Configuration Register
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
MODE
RES[1]
RES[0]
RANGE[1]
RANGE[0]
0
HI_SPEED
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TM[1]
TM[0]
0
BUFDIS
0
0
0
0
The following section gives a brief description of the programmable bits and the method to program the bits. Note
that in the event of an external reset or a power-on reset, all the configuration bits are set to default values. The
bits need to be reprogrammed as needed after a reset.
Bit Descriptions
Bit 15
Unused bit. This bit must always be set to one.
During a power-up or reset event, this bit is set to zero and must be programmed to one.
Bit 14
MODE—Data Output Mode.
This bit selects between the parallel and serial data output (time division multiplexing, or TDM)
modes, as shown in Table 5.
Table 5. Data Output Mode
Bits 13-12
MODE
DATA OUTPUT MODE
0
Parallel, using DOUT1, DOUT2, DOUT3, and DOUT4
(default)
1
Serial, time division multiplexed (TDM) on DOUT1
RES[1:0]—Output Data resolution.
These bits set the output data resolution. The value of the output resolution is the same for
RES[1:0] = '10' and RES[1:0] = '11'.
Table 6. Output Data Resolution
RES[1:0]
OUTPUT RESOLUTION
00
16 Bits (default)
01
14 Bits
10
12 Bits
11
Bits 11-10
RANGE[1:0]—Full-Scale Input Range.
These range bits set the value of the integration capacitors that are used in the dual-switched
integrators. Table 7 shows the three different capacitor values available. The value of the
maximum input charge is the same for RANGE = '10' and RANGE = '11'.
Table 7. Full-Scale Range
RANGE[1:0]
MAXIMUM INPUT CHARGE
00
3pC (default)
01
6pC
10
12pC
11
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Bit 9
Unused bit. This bit is reset to zero and must always be set to zero.
Bit 8
HI_SPEED—High-Speed Operation Selection.
This bit sets which speed (normal or high) will be used. The default is normal speed, and is the
generally recommended operating condition. However, if shorter integration times are needed
than are supported during normal operation, then high-speed mode is available. Note that
performance reduces to the 12-bit level during high-speed mode.
Table 8. High-Speed Mode Selection
HI_SPEED
Bits 7-6
SPEED
0
High speed
1
Normal speed (default)
TM[1:0]—Test Mode Selection.
Test mode (TM) bits allow for configuration of the device to operate in either normal mode or test
modes for verification purposes, as shown in Table 9. The test modes are provided as a means
of evaluating the DDC316 noise.
In test mode 1, the inputs (IN1 through IN16) are disconnected from the DDC316 integrators to
enable the user to measure a zero input signal, regardless of the current supplied to the
DDC316 by the external sensor.
In test mode 2, the inputs (IN1 through IN16) are disconnected from the DDC316 integrators and
at the same time a 10pF capacitor is added to the input to emulate the sensor capacitance.
In test mode 3, the inputs are disconnected from the DDC316 integrators. Each time a new
conversion begins (CONV toggles), a fixed amount of charge (approximately 1.5pC) is dumped
into the integrator.
Table 9. Test Mode Decoding
TM[1:0]
TEST MODE FUNCTION
00
Normal mode (default)
01
Test mode 1 (inputs opened)
10
Test mode 2 (inputs opened and 10pF internal
capacitor connected to integrators)
11
Test mode 3 (inputs opened and 1.5pC charge
dumped into the integrators during each
conversion)
Bit 5
Unused bit. This bit is reset to zero and must always be set to zero.
Bit 4
BUFDIS—Internal Reference Buffer Disable.
This bit is used to turn the internal reference buffer off, as shown in Table 10. See the Voltage
Reference section for more details.
Table 10. Internal Reference Buffer Disable
BUFDIS
Bits 3-0
16
INTERNAL REFERENCE BUFFER STATUS
0
Internal buffer enabled
1
Internal buffer disabled (default)
Unused bits. These bits are reset to zero and must always be set to zero.
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Writing and Reading of the Configuration Register
Figure 2 shows the timing diagram for writing to and
reading from the configuration register. Writing and
reading must be done before or after CONV toggles.
The data on pin DIN_CFG are latched on the falling
edge of CLK. The first four bits are used as
preamble; only when these bits equal '1010' are the
contents of the following 16 bits loaded into the
configuration register. Once the content is loaded, the
shift register immediately clears so that a new
configuration can be written, if needed. It is
recommended to leave the DIN_CFG pin to logic '0'
when not programming the register.
Once the configuration register updates, it is loaded
into the data shift register to be output on DOUT1.
When DVALID is goes low, the configuration register
is available to be read. If the data are not read back,
then the register is overwritten by the conversion data
on the following conversion. Data are shifted out on
the falling edge of DCLK.
SYSTEM AND DATA CLOCKS (CLK AND
DCLK)
The system clock is supplied to CLK and the data
clock is supplied to DCLK. Make sure the clock
signals are clean; avoid overshoot or ringing. DCLK
should be held low after the data have been shifted
out, or while CONV is transitioning; DCLK should not
be left free-running.
The integration and conversion process is
fundamentally independent of the data retrieval
process. Consequently, the CLK and DCLK
frequencies need not be the same, although for best
performance, it is highly recommended that they be
derived from the same clocking source to keep their
phase relationship constant.
When using multiple DDC316s, pay close attention to
the DCLK distribution on the printed circuit board
(PCB). In particular, make sure to minimize skew in
the DCLK signal because the skew can lead to timing
violations in the serial interface specifications.
DATA VALID (DVALID)
The DVALID signal indicates that data are ready.
Data retrieval may begin after DVALID goes low. This
signal goes low on the rising edge of the system
clock (CLK), and goes high on the first falling edge of
DCLK during the data retrieval process. Data retrieval
from the DDC316 can be done either by polling the
DVALID signal or by counting the number of clock
cycles after a transition of the CONV signal. While
using the counting method, the number of clock
cycles to wait depends on the mode of operation,
either the low power or the high speed mode. The
exact number of CLK cycles to wait for the two
different modes is given in Table 3.
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READBACK WITH MULTIPLE DDC316s
The serial interface supports daisy-chaining to
simplify connections when using multiple DDC316s
together. Figure 12 shows an example of a
64-channel system. The DIN pin is used to shift data
into the DDC316s. Additional DCLK pulses must then
be given during readback to ensure all the data have
shifted through, as shown in Figure 13.
Note that daisy-chaining is only supported in TDM
output mode, and will not work when using parallel
data output mode. When the daisy-chaining function
is not used, connect DIN to digital ground.
DCLK
DVALID
IN14
IN13
IN4
IN3
IN2
IN1
14
4
3
2
1
DIN
13
IN16
IN15
16
DOUT1 DDC316
15
IN2
18
IN1
IN3
19
17
DVALID
DCLK
IN4
IN14
IN13
30
29
DIN
20
IN16
IN15
32
DOUT1 DDC316
31
IN2
IN1
IN3
35
34
IN4
36
33
IN14
IN13
46
DIN
45
IN16
IN15
48
DOUT1 DDC316
47
IN2
IN1
50
IN3
51
49
IN4
52
DCLK
DVALID
DCLK
IN14
IN13
62
DIN
61
IN16
IN15
64
Sensor
DOUT1 DDC316
63
Data
Retrieval
Output
DVALID
Data Clock
Figure 12. Daisy-Chain Configuration of a 64-Channel System
DVALID
DCLK
tSTDIDC
tHDDIDC
DIN
DOUT
Input
64
MSB
Input
64
LSB
Input
63
MSB
Input 3
LSB
Input 2
MSB
Input 2
LSB
Input 1
MSB
Input 1
LSB
Input
64
MSB
Figure 13. Daisy-Chain Readback of Four Devices (64 Channels)
18
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VOLTAGE REFERENCE
quality capacitors with low ESR (< 1Ω) are necessary
for optimum performance. High ESR capacitors will
lead to oscillation of the internal buffer. Ceramic
capacitors with ESR < 1Ω at 100kHz are
recommended.
The reference voltage is used to reset the integration
capacitors before an integration cycle begins. It is
also used by the ADCs when they measure the
voltage stored on the integrators after an integration
cycle ends. During this sampling, the external
reference must supply the charge needed by the
ADCs. For an integration time of 20µs, this charge
translates to an average VREF current of
approximately 270µA. The amount of charge needed
by the ADC is independent of the integration time;
therefore, increasing the integration time lowers the
average current. For example, an integration time of
40µs lowers the average VREF current to 135µA.
+5V
VREF (4A, 6A, 6B)
0.47mF
+
10mF
0.1mF
DDC316
1
REF3140
2
10kW
VREF_IN (4B)
+
10mF
0.1mF
3
It is critical that VREF be stable during the different
modes of operation (see Figure 7). The ADC
measures the voltage on the integrator with respect
to VREF. Since the integrator capacitors are initially
reset to VREF, any drop in VREF, from the time the
capacitors are reset to the time when the converter
measures the integrator output, introduces an offset.
It is also important that VREF be stable over longer
periods of time because changes in VREF
correspond directly to changes in the full-scale range.
Finally, VREF should introduce as little additional
noise as possible. For these reasons, it is strongly
recommended that the external reference source be
buffered with an operational amplifier.
Figure 14. Recommended Circuit when Using the
Internal VREF Buffer
External VREF Buffer
The internal buffer can be turned off using the control
bits as explained in the Configuring the Modes
section under Bit 4 and Table 10. For this option,
configure the driving circuit as illustrated in Figure 15.
The voltage reference is generated by a +4.096V
reference. A low-pass filter to reduce noise connects
the reference to an operational amplifier configured
as a buffer. The VREF_IN pin must be left
disconnected.
The DDC316 offers two options for driving the
reference voltage: through an external buffer or
through an internal buffer. In both the cases, the
reference voltage is generated external to the chip
using an accurate reference, such as the REF3140.
This amplifier used as buffer should have low noise
and input/output common-mode ranges that support
VREF. Even though the circuit in Figure 15 might
appear to be unstable as a result of the large output
capacitors, it works well for most operational
amplifiers. It is not recommended that series
resistance be placed in the output lead to improve
stability because it can cause a drop in VREF and
produce large offsets.
Internal VREF Buffer
The DDC316 provides an internal VREF buffer to
drive the four on-chip ADCs. The reference voltage
must be provided at VREF_IN (pin 4B), as shown in
Figure 14. The external capacitors at the VREF pins
are necessary to stabilize the internal buffer. It is
recommended that these capacitors be placed as
close as possible to the device under test. Also, good
+5V
+5V
0.1mF
0.47mF
7
2
1
REF3140
2
10kW
3
+
10mF
3
0.1mF
OPA350
6
VREF (4A, 6A, 6B)
+
10mF
4
0.1mF
DDC316
VREF_IN (4B)
Figure 15. Recommended Circuit when Using an External VREF Buffer
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RESET (RESET)
LAYOUT
The DDC316 can be reset asynchronously by taking
the RESET input low. Make sure the reset pulse is at
least two CLK cycles wide. Once the RESET signal is
pulled high, the internal reset is released tRST later,
after which the configuration register can be written. It
is very important that RESET is glitch-free to avoid
unintentional resets.
Power Supplies and Grounding
tCLK
period
CLK
tRST,PUL
Both AVDD and DVDD should be as quiet as
possible. It is particularly important to eliminate noise
from AVDD that is nonsynchronous with the DDC316
operation. For this reason, switching-supplies are not
recommended. Figure 18 illustrates how to supply
power to the DDC316. Each supply of the DDC316
should be bypassed with 10µF solid ceramic
capacitors. It is recommended that both the analog
and digital grounds (AGND and DGND) be connected
to a single ground plane on the PCB.
VA
RESET
AVDD
RESETINTERNAL
AGND
10mF
tRST
DDC316
DIN_CFG
VD
DVDD
Figure 16. Reset Timing
DGND
10mF
POWER-UP SEQUENCING
Figure 18. Power-Supply Connections
Figure 17 shows the internal timing after the part
powers up. Once the digital supply is above the
threshold voltage, the internal power-on reset circuit
releases the POR signal. The internal reset signal to
the digital logic is released tPOR time after the
PORINTERNAL, after which the configuration register
can be written.
CLK
PORINTERNAL
RESETINTERNAL
tPOR
DIN_CFG
Shielding Analog Signal Paths
As with any precision circuit, careful PCB layout
ensures the best performance. It is essential to make
short, direct interconnections and avoid stray wiring
capacitance, particularly at the analog input pins and
QGND. These analog input pins are high-impedance
and extremely sensitive to extraneous noise. The
QGND pin should be treated as a sensitive analog
signal and connected directly to the supply ground
with proper shielding. Leakage currents between the
PCB traces can exceed the input bias current of the
DDC316 if shielding is not implemented. Digital
signals should be kept as far as possible from the
analog input signals on the PCB.
Figure 17. Power-Up Timing
Table 11. Timing Figure 16 and Figure 17
SYMBOL
tRST,PUL
20
DESCRIPTION
MIN
TYP
MAX
UNITS
RESET pin low width
2
tCLK periods
tRST
Wait from RESET high to beginning of configuration register write
20
tCLK periods
tPOR
Wait from power-up to power-on reset release
40,000
tCLK periods
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Revision History
NOTE: Page numbers for previous revisions may be differ from page numbers in the current version.
Changes from Original (March 2008) to Revision A ....................................................................................................... Page
•
•
•
•
•
Changed test condition for Offset Drift Stability specification ................................................................................................ 3
Changed Figure 1 ................................................................................................................................................................. 6
Changed Figure 2 ................................................................................................................................................................. 7
Added missing text................................................................................................................................................................. 9
Deleted duplicate mechanical package drawing.................................................................................................................. 20
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Feb-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DDC316CGXGR
ACTIVE
NFBGA
GXG
64
1000
TBD
SN/PB
Level-3-240C-168 HR
0 to 70
DDC316
DDC316CGXGT
ACTIVE
NFBGA
GXG
64
250
TBD
SN/PB
Level-3-240C-168 HR
0 to 70
DDC316
DDC316CZXGR
ACTIVE
NFBGA
ZXG
64
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
0 to 70
DDC316
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Feb-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
DDC316CGXGR
NFBGA
GXG
64
DDC316CGXGT
NFBGA
GXG
DDC316CZXGR
NFBGA
ZXG
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
330.0
16.4
8.3
8.3
2.25
12.0
16.0
Q1
64
250
180.0
16.4
8.3
8.3
2.25
12.0
16.0
Q1
64
1000
330.0
16.4
8.3
8.3
2.25
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DDC316CGXGR
NFBGA
GXG
64
1000
350.0
350.0
43.0
DDC316CGXGT
NFBGA
GXG
64
250
213.0
191.0
55.0
DDC316CZXGR
NFBGA
ZXG
64
1000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
GXG0064A
NFBGA - 1.45 mm max height
SCALE 1.500
PLASTIC BALL GRID ARRAY
8.1
7.9
A
B
BALL A1 CORNER
8.1
7.9
1.45
1.27
C
SEATING PLANE
0.41
TYP
0.31
BALL TYP
0.12 C
5.6 TYP
(1.2) TYP
SYMM
(1.2) TYP
H
G
F
5.6
TYP
SYMM
E
D
C
64X
B
A
0.51
0.41
0.15
0.08
C A B
C
0.8 TYP
1
BALL A1 CORNER
2
3
4
5
6
7
8
0.8 TYP
4220524/A 12/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
GXG0064A
NFBGA - 1.45 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
64X ( 0.4)
1
2
3
4
5
6
7
8
A
(0.8) TYP
B
C
D
SYMM
E
F
G
H
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.05 MAX
( 0.4)
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
METAL UNDER
SOLDER MASK
0.05 MIN
EXPOSED
METAL
( 0.4)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4220524/A 12/2018
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
GXG0064A
NFBGA - 1.45 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
( 0.4) TYP
1
2
3
4
5
6
7
8
A
(0.8) TYP
B
C
D
SYMM
E
F
G
H
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:12X
4220524/A 12/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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