Texas Instruments | 12-Bit, 3-MSPS, microPOWER, Miniature SAR Analog-to-Digital Converter | Datasheet | Texas Instruments 12-Bit, 3-MSPS, microPOWER, Miniature SAR Analog-to-Digital Converter Datasheet

Texas Instruments 12-Bit, 3-MSPS, microPOWER, Miniature SAR Analog-to-Digital Converter Datasheet
ADS7883
www.ti.com ....................................................................................................................................................................................................... SLAS594 – JULY 2008
12-BIT, 3-MSPS, MICROPOWER, MINIATURE
SAR ANALOG-TO-DIGITAL CONVERTER
FEATURES
APPLICATIONS
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1
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•
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3-MHz Sample Rate Serial Device
12-Bit Resolution
Zero Latency
48-MHz Serial Interface
Supply Range: 2.7 V to 5.5 V
Low Power Dissipation:
– 6.45 mW at 3-V VDD, 2 MSPS
– 13.5 mw at 5-V VDD, 3 MSPS
±0.6 LSB INL, ±0.5 LSB DNL
72 dB SINAD, –84 dB THD
Unipolar Input Range: 0 V to VDD
Power-Down Current: 1 µA
Wide Input Bandwidth: 30 MHz at 3 dB
6-Pin SOT23 Package
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Base Band Converters in Radio
Communication
Motor Current/Bus Voltage Sensors in Digital
Drives
Optical Networking (DWDM, MEMS Based
Switching)
Optical Sensors
Battery Powered Systems
Medical Instrumentations
High-Speed Data Acquisition Systems
High-Speed Closed-Loop Systems
DESCRIPTION
The ADS7883 is a 12-bit, 3-MSPS analog-to-digital converter (ADC). The device includes a capacitor based SAR
A/D converter with inherent sample and hold. The serial interface in the device is controlled by the CS and SCLK
signals for glueless connections with microprocessors and DSPs. The input signal is sampled with the falling
edge of CS, and SCLK is used for conversion and serial data output.
The device operates from a wide supply range from 2.7 V to 5.5 V. The low power consumption of the device
makes it suitable for battery-powered applications. The device also includes a power saving power-down feature
for when the device is operated at lower conversion speeds.
The high level of the digital input to the device is not limited to device VDD. Therefore the digital input can go as
high as 5.5 V when the device supply is 2.7 V. This feature is useful when digital signals are received from
another circuit with different supply levels. This also reduces restrictions on power-up sequencing.
The ADS7883 is available in a 6-pin SOT23 package and is specified for operation from –40°C to 125°C.
MicroPower Miniature SAR Converter Family
BIT
< 300 KSPS
300 KSPS – 1.25 MSPS
3 MSPS
3 MSPS for 4.5 VDD to 5.5 VDD
12-Bit
ADS7866 (1.2 VDD to 3.6 VDD)
ADS7886 (2.35 VDD to 5.25 VDD)
ADS7883
10-Bit
ADS7867 (1.2 VDD to 3.6 VDD)
ADS7887 (2.35 VDD to 5.25 VDD)
ADS7884 (2.7 VDD to 5.5 VDD)
8-Bit
ADS7868 (1.2 VDD to 3.6 VDD)
ADS7888 (2.35 VDD to 5.25 VDD)
ADS7885 (2.7 VDD to 5.5 VDD)
2 MSPS for 2.7 VDD to 4.5 VDD
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
ADS7883
SLAS594 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SAR
+IN
OUTPUT
LATCHES
&
3−STATE
DRIVERS
CDAC
SDO
COMPARATOR
VDD
CONVERSION
&
CONTROL
LOGIC
SCLK
CS
PACKAGE/ORDERING INFORMATION (1)
DEVICE
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
NO MISSING
CODES AT
RESOLUTION
(BIT)
ADS7883SB
±1
±1
12
PACKAGE
TYPE
6-Pin
SOT23
ADS7883S
(1)
±2
±2
PACKAGE
DESIGNAT
OR
DBV
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
INFORMATION
TRANSPORT
MEDIA
QUANTITY
7883
ADS7883SBDBVT
Small Tape and
Reel 250
7883
ADS7883SBDBVR
Large Tape and
Reel 3000
7883
ADS7883SDBVT
Small Tape and
Reel 250
7883
ADS7883SDBVR
Large Tape and
Reel 3000
–40°C to 125°C
11
For most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
UNIT
+IN to AGND
–0.3 V to +VDD +0.3 V
+VDD to AGND
–0.3 V to 7.0 V
Digital input voltage to GND
–0.3 V to (7.0 V)
Digital output to GND
–0.3 V to (+VDD + 0.3 V)
Operating temperature range
–40°C to 125°C
Storage temperature range
–65°C to 150°C
Junction temperature (TJ Max)
150°C
Power dissipation, SOT23 package
Thermal impedance, θJA
Lead temperature, soldering
(1)
2
(TJ Max–TA)/θJA
SOT23
295.2°C/W
Vapor phase (60 sec)
215°C
Infrared (15 sec)
220°C
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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ELECTRICAL SPECIFICATIONS
VDD = 2.7 V to 5.5 V, TA = –40°C to 125°C, fsample = 2 MSPS for VDD = 2.7 V to 4.5 V, fsample = 3 MSPS for VDD = 4.5 V to 5.5
V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
VDD
V
–0.2
VDD+0.2
V
ANALOG INPUT
Full-scale input voltage span (1)
Absolute input voltage range
+IN
(2)
CI
Input capacitance
IIlkg
Input leakage current
TA = 125°C
27
pF
40
nA
12
Bits
SYSTEM PERFORMANCE
Resolution
No missing codes
INL
Integral nonlinearity
DNL
Differential nonlinearity
EO
Offset error (4) (5) (6)
EG
Gain error (5)
ADS7883SB
12
ADS7883S
11
ADS7883SB
–1
±0.6
1
ADS7883S
–2
±0.75
2
ADS7883SB
–1
±0.5
1
ADS7883S
–2
±0.75
2
Bits
LSB (3)
LSB
–3
±0.2
3
LSB
–3.5
±0.3
3.5
LSB
32-MHz SCLK, VDD = 3 V
398
422
48-MHz SCLK, VDD = 5 V
265
281
32-MHz SCLK, VDD = 3 V
78
48-MHz SCLK, VDD = 5 V
52
SAMPLING DYNAMICS
Conversion time
Acquisition time
Maximum throughput rate
ns
ns
32-MHz SCLK, VDD = 2.7 V to 4.5 V
2
48-MHz SCLK, VDD = 4.5 V to 5.5 V
3
Aperture delay
MHz
10
ns
–84
dB
DYNAMIC CHARACTERISTICS
THD
Total harmonic distortion (7)
fI = 100 kHz
fI = 100 kHz, ADS7883SB
69
72
fI = 100 kHz, ADS7883S
68
70
SINAD
Signal-to-noise and distortion
dB
SFDR
Spurious free dynamic range
fI = 100 kHz
Full power bandwidth
At –3 dB
30
VDD = 2.7 V to 3.6 V
1.5
5.5
VDD = 3.6 V to 5.5 V
2.2
5.5
86
dB
MHz
DIGITAL INPUT/OUTPUT
Logic family — CMOS
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
At Isource = 200 µA
VOL
Low-level output voltage
At Isink = 200 µA
VDD = 2.7 V to 3.6 V
0.4
VDD = 3.6 V to 5.5 V
0.8
VDD–0.2
0.4
V
V
V
POWER SUPPLY REQUIREMENTS
+VDD
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Supply voltage
2.7
3.3
5.5
V
Ideal input span; does not include gain or offset error
Refer to Figure 24 for details on sampling circuit
LSB means least significant bit
Measured relative to an ideal full-scale input
Offset error and gain error ensured by characterization
First transition of 000H to 001H at (Vref/210)
Calculated on the first nine harmonics of the input frequency
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ELECTRICAL SPECIFICATIONS (continued)
VDD = 2.7 V to 5.5 V, TA = –40°C to 125°C, fsample = 2 MSPS for VDD = 2.7 V to 4.5 V, fsample = 3 MSPS for VDD = 4.5 V to 5.5
V
PARAMETER
TEST CONDITIONS
MIN
At VDD = 3 V, 2-MSPS throughput
Supply current (normal mode)
Power dissipation
Power dissipation in static state
MAX
2.15
3
At VDD = 3 V, Static state
1.8
At VDD = 5 V, 3-MSPS throughput
2.7
At VDD = 5 V, Static state
Power-down state supply current
TYP
4
UNIT
mA
2
SCLK off
1
SCLK on (48 MHz)
90
250
VDD = 5 V, 3 MSPS
13.5
20
VDD = 3 V, 2 MSPS
6.45
VDD = 5 V
10
12.5
VDD = 3 V
5.4
µA
mW
mW
Power-down time
0.1
µs
Power-up time
0.8
µs
125
°C
TEMPERATURE RANGE
Specified performance
–40
TIMING REQUIREMENTS (see Figure 21)
All specifications typical at TA = –40°C to 125°C, VDD = 2.7 V to 5.5 V, unless otherwise specified.
TEST CONDITIONS (1)
PARAMETER
tconv
Conversion time
tacq
Aquisition time
tq
Minimum quiet time needed from bus 3-state to start
of next conversion
td1
Delay time, CS low to first data (0) out
tsu1
Setup time, CS low to SCLK low
td2
Delay time, SCLK falling to SDO
th1
Hold time, SCLK falling to data valid (2)
td3
Delay time, 16th SCLK falling edge to SDO 3-state
tw1
Pulse duration, CS
td4
Delay time, CS high to SDO 3-state,
twH
Pulse duration, SCLK high
twL
Pulse duration, SCLK low
(1)
(2)
4
MIN
TYP
MAX
VDD = 3 V
13.5 × tSCLK
VDD = 5 V
13.5 × tSCLK
VDD = 3 V
78
VDD = 5 V
52
VDD = 3 V
10
VDD = 5 V
10
ns
9
15
VDD = 5 V
8
11
7
VDD = 5 V
5
11
20
VDD = 5 V
9
12
5.5
VDD > 5 V
4
9
15
VDD = 5 V
8
11
10
VDD = 5 V
10
9
15
VDD = 5 V
8
11
0.45 × tSCLK
VDD = 5 V
0.45 × tSCLK
VDD = 3 V
0.45 × tSCLK
VDD = 5 V
0.45 × tSCLK
ns
ns
VDD = 3 V
VDD = 3 V
ns
ns
VDD = 3 V
VDD = 3 V
ns
ns
VDD = 3 V
VDD < 3 V
ns
ns
VDD = 3 V
VDD = 3 V
UNIT
ns
ns
ns
3-V Specifications apply from 2.7 V to 3.6 V, and 5-V specifications apply from 4.5 V to 5.5 V.
With 10-pf load.
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TIMING REQUIREMENTS (see Figure 21) (continued)
All specifications typical at TA = –40°C to 125°C, VDD = 2.7 V to 5.5 V, unless otherwise specified.
TEST CONDITIONS (1)
PARAMETER
Frequency, SCLK
td5
Delay time, second falling edge of clock and CS to
enter in powerdown (use min spec not to accidently
enter in powerdown) see Figure 22
td6
MIN
TYP
MAX
VDD = 2.7 V to 4.5 V
32
VDD = 4.5 V to 5.5 V
48
VDD = 3 V
–2
4
VDD = 5 V
–2
3
Delay time, CS and 10th falling edge of clock to enter VDD = 3 V
in powerdown (use max spec not to accidently enter
VDD = 5 V
in powerdown) see Figure 22
–2
4
–2
3
UNIT
MHz
ns
ns
DEVICE INFORMATION
SOT23 PACKAGE
(TOP VIEW)
VDD
1
6
CS
GND
2
5
SDO
VIN
3
4
SCLK
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
VDD
1
–
Power supply input, also acts like a reference voltage to ADC.
GND
2
–
Ground for power supply, all analog and digital signals are referred with respect to this pin.
VIN
3
I
Analog signal input
SCLK
4
I
Serial clock
SDO
5
O
Serial data out
CS
6
I
Chip select signal, active low
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
SCLK FREQUENCY
2.9
3
3
5V
2.5
3 MSPS
ICC - Supply Current - mA
2.7
2.6
2.5
2.4
TA = 25ºC,
SCLK = 48 MHz for VDD = 5 V,
SCLK = 32 MHz for VDD = 3 V,
SCLK = free running
Powerdown
TA = 25ºC
2 MSPS
2.3
2.2
2.5
ICC -Supply Current - mA
TA = 25ºC,
fs = 3 MSPS
2.8
ICC -Supply Current - mA
SUPPLY CURRENT
vs
SAMPLE RATE
2
3V
1.5
1
2
1.5
1
0.5
0.5
2.1
2
2.7
3.4
4.1
4.8
VDD - Supply Voltage - V
0
0
5.5
700
SIGNAL-TO-NOISE + DISTORTION
vs
INPUT FREQUENCY
73
5V
0
-10
0V
-20
-30
15
70
TA - Free Air Temperature - ºC
VDD = 5 V,
fS = 3 MSPS
72.5
72
71.5
71
70.5
70
69.5
0
125
SINAD - Signal-to-Noise + Distortion - dB
SNR - Signal-to-Noise Ratio - dB
200
400
600
800
fi - Input Frequency - KHz
VDD = 5 V,
fS = 3 MSPS
72.5
72
71.5
71
70.5
70
69.5
69
68.5
68
0
1000
200
400
600
800
fi - Input Frequency - KHz
1000
Figure 4.
Figure 5.
Figure 6.
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
SIGNAL-TO-NOISE + DISTORTION
vs
SUPPLY VOLTAGE
SIGNAL-TO-NOISE + DISTORTION
vs
FREE-AIR TEMPERATURE
-75
SINAD - Signal-to-Noise + Distortion - dB
72.2
VDD = 5 V,
fS = 3 MSPS
-77
-78
-79
-80
-81
-82
-83
-84
-85
200
400
600
800
fi - Input Frequency - KHz
1000
Figure 7.
SINAD - Signal-to-Noise + Distortion - dB
Input Leakage Current - nA
600
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
10
0
200 300 400 500
fS - Sample rate - KSPS
INPUT LEAKAGE CURRENT
vs
FREE-AIR TEMPERATURE
73
-40
-40
100
Figure 3.
20
-76
0
50
Figure 2.
VDD = 5 V
THD - Total Harmonic Distortion - dB
20
30
40
fSCLK - Frequency - MHz
Figure 1.
30
6
0
10
72
71.8
71.6
71.4
71.2
71
2.7
TA = 25ºC,
fS = 3 MSPS for VDD = 4.5 V to 5.5 V,
fS = 2 MSPS for VDD = 2.7 V to 4.5 V
3.4
4.1
4.8
VDD - Supply Voltage - V
Figure 8.
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5.5
72.2
5 V, 3 MSPS
72.1
72
71.9
71.8
71.7
2.7 V, 2 MSPS
71.6
71.5
-40
15
70
TA - Free Air Temperature - ºC
125
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
1
0.8
max DNL, 3 V, 2 MSPS
0.6
0.4
max DNL, 5 V, 3 MSPS
0
-0.2
min DNL, 5 V, 3 MSPS
-0.4
-0.6
-0.8
-1
-40
0.6
0.4
0
-0.2
-0.6
125
0
-0.2
-0.4
min DNL
-0.6
-0.8
-1
2.7
125
3.4
4.1
4.8
VDD - Supply Voltage - V
INTEGRAL NONLINEARITY
vs
SUPPLY VOLTAGE
OFFSET ERROR
vs
SUPPLY VOLTAGE
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
0.4
0.3
EO - Offset Error - LSBs
INL - Integral Nonlinearity - LSBs
max DNL
0.2
Figure 12.
max INL
0
-0.2
-1
2.7
0.4
Figure 11.
0.2
-0.8
15
70
TA - Free Air Temperature - ºC
0.6
TA = 25ºC,
fS = 3 MSPS for VDD = 4.5 V to 5.5 V,
fS = 2 MSPS for VDD = 2.7 V to 4.5 V
0.8
Figure 10.
0.6
-0.6
min INL, 5 V, 3 MSPS
-1
-40
1
-0.4
min INL, 3 V, 2 MSPS
-0.4
0.8
0.4
max INL, 5 V, 3 MSPS
0.2
-0.8
min DNL, 3 V, 2 MSPS
15
70
TA - Free Air Temperature - ºC
1
max INL, 3 V, 2 MSPS
min INL
TA = 25ºC,
fS = 3 MSPS for VDD = 4.5 V to 5.5 V,
fS = 2 MSPS for VDD = 2.7 V to 4.5 V
3.4
4.1
4.8
VDD - Supply Voltage - V
0.2
0.3
0.1
0
-0.1
-0.2
-0.3
5.5
5.5
0.4
TA = 25ºC,
fS = 3 MSPS for VDD = 4.5 V to 5.5 V,
fS = 2 MSPS for VDD = 2.7 V to 4.5 V
EO - Offset Error - LSBs
0.2
DIFFERENTIAL NONLINEARITY
vs
SUPPLY VOLTAGE
DNL - Differential Nonlinearity - LSBs
1
0.8
INL - Integral Nonlinearity - LSBs
DNL - Differential Nonlinearity - LSBs
DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
-0.4
2.7
0.2
0.1
5 V, 3 MSPS
0
-0.1
2.7 V, 2 MSPS
-0.2
-0.3
3.4
4.1
4.8
VDD - Supply Voltage - V
Figure 13.
-0.4
-40
5.5
15
70
TA - Free Air Temperature - ºC
Figure 14.
GAIN ERROR
vs
SUPPLY VOLTAGE
125
Figure 15.
GAIN ERROR
vs
FREE-AIR TEMPERATURE
1
0.4
0.8
0.3
EG - Gain Error - LSBs
EG - Gain Error - LSBs
0.6
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
2.7
TA = 25ºC,
fS = 3 MSPS for VDD = 4.5 V to 5.5 V,
fS = 2 MSPS for VDD = 2.7 V to 5.5 V
3.4
4.1
4.8
VDD - Supply Voltage - V
0.4
3 V, 2 MSPS
0.2
0
-0.2
5 V, 3 MSPS
-0.4
-0.6
-0.8
5.5
-1
-40
15
70
TA - Free Air Temperature - ºC
Figure 16.
125
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
DNL
1
0.8
0.6
DNL
0.4
VDD = 5 V,
fS = 3 MSPS,
TA = 25ºC
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
1024
3072
2048
Output Code
4096
Figure 18.
INL
1
VDD = 5 V,
fS = 3 MSPS,
TA = 25ºC
INL - LSBs
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
1024
2048
Output Code
4096
3072
Figure 19.
FFT
0
VDD = 5 V,
fS = 3 MSPS,
fi = 250 kHz,
N points = 16384
Power - dB
-20
-40
-60
-80
-100
-120
-140
0
8
250000
500000
750000
f - Frequency - Hz
Figure 20.
1000000
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1250000
1500000
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NORMAL OPERATION
The cycle begins with the falling edge of CS. This point is indicated as a in Figure 21. With the falling edge of
CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the
conversion is in progress. The data word contains two leading zeros, followed by 12-bit data in MSB first format
and padded by two lagging zeros.
The falling edge of CS clocks out the first zero, and a second zero is clocked out on the first falling edge of the
clock. Data is in MSB first format with the MSB being clocked out on the 2nd falling edge. Data is padded with
two lagging zeros as shown in Figure 21. The conversion ends on the first rising edge of SCLK after the 13th
falling edge. At this point the device enters the acquisition phase. This point is indicated by b in Figure 21.
Figure 21 shows the device data is read in a sixteen clock frame. However, CS can be asserted (pulled high) any
time after point b. SDO goes to 3-state with the CS high level. The next conversion should not be started (by
pulling CS low) until the end of the quiet sampling time (tq) after SDO goes to 3-state or until the minimum
acquisition time (tacq) has elapsed. To continue normal operation, it is necessary that CS is not pulled high until
point b. Without this, the device does not enter the acquisition phase and no valid data is available in the next
cycle. (Also refer to the Power-Down Mode section for more details.) CS going high any time during the
conversion aborts the ongoing conversion and SDO goes to 3-state.
The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as
high as 5.5 V when the device supply is 2.7 V. This feature is useful when digital signals are received from
another circuit with different supply levels. Also, this relaxes the restriction on power-up sequencing. However,
the digital output levels (VOH and VOL) are governed by VDD as listed in the Electrical Specifications table.
a
b
a
t acq
t conv
CS
tw1
t su1
1
SCLK
0
11
13
12
t h1
t d2
t d1
SDO
3
2
0
D11
16
15
14
t d4
D10
D2
D1
t d3
D0
0
0
tq
Figure 21. Interface Timing Diagram
POWER-DOWN MODE
The device enters power-down mode if CS goes high anytime after the 2nd SCLK falling edge to before the 10th
SCLK falling edge. An ongoing conversion stops and SDO goes to 3-state under this power-down condition as
shown in Figure 22.
td6
td5
CS
1
2
3
4
5
9
10
16
SCLK
SDO
Figure 22. Entering Power-Down Mode
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9
ADS7883
SLAS594 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com
A dummy cycle with CS low for more than 10 SCLK falling edges brings the device out of power-down mode. For
the device to reach the fully powered up condition requires 0.8 µs. CS can be pulled high any time after the 10th
falling edge as shown in Figure 23. Note that the power-up time of 0.8 µs is more than a single conversion cycle
at 3-MSPS speed. This means the device requires three dummy conversion frames at 3-MSPS speed or one
elongated dummy conversion frame. The data during the dummy conversion frames is invalid.
Device Starts
Powering Up
Device Fully
Powered-Up
CS
SCLK
1
SDO
2
3
4
5
6
7
8
9 10 11 12 13 14 15
16
1
2
3
4
5
6
Invalid Data
7
8
9
10 11 12 13 14 15 16
Valid Data
Figure 23. Exiting Power-Down Mode
10
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ADS7883
www.ti.com ....................................................................................................................................................................................................... SLAS594 – JULY 2008
APPLICATION INFORMATION
VDD
20 W
50 W
IN
20 pF
50 W
7 pF
GND
Figure 24. Typical Equivalent Sampling Circuit
Driving the VIN and VDD Pins
The VIN input to the ADS7883 should be driven with a low impedance source. In most cases additional buffers
are not required. In cases where the source impedance exceeds 200 Ω, using a buffer would help achieve the
rated performance of the converter. The THS4031 is a good choice for the driver amplifier buffer.
The reference voltage for the ADS7883 A/D converter is derived from the supply voltage internally. The device
offers limited low-pass filtering functionality on-chip. The supply to these converters should be driven with a low
impedance source and should be decoupled to the ground. A 1-µF storage capacitor and a 10-nF decoupling
capacitor should be placed close to the device. Wide, low impedance traces should be used to connect the
capacitor to the pins of the device. The ADS7883 draws very little current from the supply lines. The supply line
can be driven by either:
• Directly from the system supply.
• A reference output from a low drift and low drop out reference voltage generator like the REF5030 or
REF5050. The ADS7883 can operate with a wide range of supply voltages. The actual choice of the
reference voltage generator depends upon the system. Figure 26 shows one possible application circuit.
• A low-pass filtered version of the system supply followed by a buffer like the zero-drift OPA735 can also be
used in cases where the system power supply is noisy. Care should be taken to ensure that the voltage at the
VDD input does not exceed 7 V (especially during power up) to avoid damage to the converter. This can be
done easily using single supply CMOS amplifiers like the OPA735. Figure 27 shows one possible application
circuit.
VDD
1 mF
VDD
CS
VIN
SDO
GND
SCLK
10 nF
Figure 25. Supply/Reference Decoupling Capacitors
5V/7V
REF5030/REF5050
IN
3V/5V
1mF
OUT
VDD
CS
VIN
SDO
GND
1 mF
10 nF
GND
SCLK
Figure 26. Using the REF5030/REF5050 Reference
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ADS7883
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5V
C1
R1
10 W
7V
_
R2
VDD
CS
VIN
SDO
GND
SCLK
+
1 mF
1 mF
10 nF
Figure 27. Buffering with the OPA735
12
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PACKAGE OPTION ADDENDUM
www.ti.com
8-May-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS7883SBDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7883
ADS7883SBDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7883
ADS7883SDBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7883
ADS7883SDBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7883
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-May-2018
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-May-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
ADS7883SBDBVR
SOT-23
DBV
6
3000
180.0
8.4
ADS7883SBDBVT
SOT-23
DBV
6
250
180.0
ADS7883SDBVR
SOT-23
DBV
6
3000
180.0
ADS7883SDBVT
SOT-23
DBV
6
250
180.0
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
11-May-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS7883SBDBVR
SOT-23
DBV
6
3000
195.0
200.0
45.0
ADS7883SBDBVT
SOT-23
DBV
6
250
195.0
200.0
45.0
ADS7883SDBVR
SOT-23
DBV
6
3000
195.0
200.0
45.0
ADS7883SDBVT
SOT-23
DBV
6
250
195.0
200.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
6
2X 0.95
1.9
1.45 MAX
3.05
2.75
5
2
4
0.50
6X
0.25
0.2
C A B
3
(1.1)
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X (0.95)
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2
5
3
4
2X(0.95)
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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