Texas Instruments | 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS and CMOS OUTPUTS (Rev. A) | Datasheet | Texas Instruments 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS and CMOS OUTPUTS (Rev. A) Datasheet

Texas Instruments 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS and CMOS OUTPUTS (Rev. A) Datasheet
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
Maximum Sample Rate: 125 MSPS
12-Bit Resolution with No Missing Codes
3.5 dB Coarse Gain and up to 6 dB
Programmable Fine Gain for SNR/SFDR
Trade-Off
Parallel CMOS and Double Data Rate (DDR)
LVDS Output Options
Supports Sine, LVCMOS, LVPECL, LVDS Clock
Inputs and Clock Amplitude Down to 400 mVPP
Clock Duty Cycle Stabilizer
Internal Reference with Support for External
Reference
No External Decoupling Required for
References
Programmable Output Clock Position and
Drive Strength to Ease Data Capture
3.3 V Analog and 1.8 V to 3.3 V Digital Supply
32-QFN Package (5 mm × 5 mm)
Pin Compatible 12-Bit Family (ADS612X)
APPLICATIONS
•
•
•
•
•
•
•
•
Wireless Communications Infrastructure
Software Defined Radio
Power Amplifier Linearization
802.16d/e
Test and Measurement Instrumentation
High Definition Video
Medical Imaging
Radar Systems
DESCRIPTION
ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X)
is a family of 12-bit A/D converters with sampling
frequencies up to 125 MSPS. It combines high
performance and low power consumption in a
compact 32 QFN package. Using an internal high
bandwidth sample and hold and a low jitter clock
buffer helps to achieve high SNR and high SFDR
even at high input frequencies.
It features coarse and fine gain options that are used
to improve SFDR performance at lower full-scale
analog input ranges.
The digital data outputs are either parallel CMOS or
DDR LVDS (Double Data Rate). Several features
exist to ease data capture such as — controls for
output clock position and output buffer drive strength,
and LVDS current and internal termination
programmability.
The output interface type, gain, and other functions
are programmed using a 3-wire serial interface.
Alternatively, some of these functions are configured
using dedicated parallel pins so that the device
comes up in the desired state after power-up.
ADS612X includes internal references, while
eliminating the traditional reference pins and
associated external decoupling. External reference
mode is also supported.
The devices are specified over
temperature range (–40°C to 85°C).
the
industrial
ADS612X Performance Summary
SFDR, dBc
SINAD, dBFS
ADS6125
ADS6124
ADS6123
ADS6122
Fin = 10 MHz (0 dB gain)
90
91
93
95
Fin = 170 MHz (3.5 dB gain)
78
82
83
84
Fin = 10 MHz (0 dB gain)
71.1
71.3
71.5
71.6
Fin = 170 MHz (3.5 dB gain)
67.6
69.1
69.2
69.8
417
374
318
285
Power, mW
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
CLKP
DRGND
DRVDD
AGND
AVDD
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
CLKOUTP
CLOCK
GEN
CLKM
CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
Digital
Encoder
and
Serializer
INP
12-Bit
ADC
SHA
INM
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
VCM
Control
Interface
Reference
ADS612X
PDN
SEN
SDATA
SCLK
RESET
LVDS MODE
ADS61XX FAMILY
2
125 MSPS
105 MSPS
80 MSPS
65 MSPS
ADS614X
14 Bits
ADS6145
ADS6144
ADS6143
ADS6142
ADS612X
12 Bits
ADS6125
ADS6124
ADS6123
ADS6122
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Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS6125
QFN-32 (2)
RHB
–40°C to 85°C
AZ6125
ADS6124
QFN-32 (2)
RHB
–40°C to 85°C
AZ6124
ADS6123
ADS6122
(1)
(2)
QFN-32 (2)
RHB
QFN-32 (2)
RHB
–40°C to 85°C
–40°C to 85°C
AZ6123
AZ6122
ORDERING
NUMBER
TRANSPORT MEDIA
ADS6125IRHBT
Tape and Reel, small
ADS6125IRHBR
Tape and Reel, large
ADS6124IRHBT
Tape and Reel, small
ADS6124IRHBR
Tape and Reel, large
ADS6123IRHBT
Tape and Reel, small
ADS6123IRHBR
Tape and Reel, large
ADS6122IRHBT
Tape and Reel, small
ADS6122IRHBR
Tape and Reel, large
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 34 °C/W (0 LFM air flow),
θJC = 30 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in × 3 in (7.62 cm ×
7.62 cm) PCB.
ABSOLUTE MAXIMUM RATINGS (1)
VI
VALUE
UNIT
Supply voltage range, AVDD
–0.3 to 3.9
V
Supply voltage range, DRVDD
–0.3 to 3.9
V
Voltage between AGND and DRGND
–0.3 to 0.3
V
Voltage between AVDD to DRVDD
–0.3 to 3.3
V
–0.3 to 2
V
–0.3 to minimum ( 3.6, AVDD + 0.3)
V
Voltage applied to VCM pin (in external reference mode)
Voltage applied to analog input pins, INP and INM
Voltage applied to analog input pins, CLKP and CLKM
TA
Operating free-air temperature range
TJ
Operating junction temperature range
Tstg
Storage temperature range
(1)
–0.3 to (AVDD + 0.3)
V
–40 to 85
°C
125
°C
–65 to 150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Copyright © 2007–2008, Texas Instruments Incorporated
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
3
3.3
3.6
V
1.65
1.8 to 3.3
3.6
V
3
3.3
3.6
V
SUPPLIES
AVDD
Analog supply voltage
(1)
DRVDD Output buffer supply voltage
CMOS Interface
LVDS Interface
ANALOG INPUTS
Differential input voltage range
VIC
2
Input common-mode voltage
Vpp
1.5 ± 0.1
Voltage applied on VCM in external reference mode
1.45
1.5
V
1.55
V
CLOCK INPUT
FS
Input clock sample rate
ADS6125
1
125
ADS6124
1
105
ADS6123
1
80
ADS6122
1
Sine wave, ac-Coupled
Input clock amplitude differential
(VCLKP – VCLKM)
65
0.4
LVPECL, ac-Coupled
1.5
± 0.8
LVDS, ac-Coupled
MSPS
Vpp
± 0.35
LVCMOS, ac-Coupled
3.3
Input Clock duty cycle
35%
50%
65%
DIGITAL OUTPUTS
Output buffer drive strength
(2)
For CLOAD ≤ 5 pF and DRVDD ≥ 2.2
V
DEFAULT
strength
For CLOAD > 5 pF and DRVDD ≥ 2.2
V
MAXIMUM
strength
For DRVDD < 2.2 V
MAXIMUM
strength
CMOS Interface, maximum buffer
strength
CLOAD
Maximum external load capacitance from each
output pin to DRGND
10
LVDS Interface, without internal
termination
5
LVDS Interface, with internal
termination
RLOAD
Differential load resistance (external) between the LVDS output pairs
TA
Operating free-air temperature
(1)
(2)
4
pF
10
Ω
100
-40
85
°C
For easy migration to next generation, higher sampling speed devices (> 125 MSPS), use 1.8V DRVDD supply.
See Output Buffer Strength Programmability in application section
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Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122
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ADS6123, ADS6122
www.ti.com
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
DRVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal
reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted.
ADS6125
FS = 125 MSPS
PARAMETER
MIN
RESOLUTION
TYP
ADS6124
FS = 105 MSPS
MAX
MIN
TYP
ADS6123
FS = 80 MSPS
MAX
MIN
TYP
ADS6122
FS = 65 MSPS
MAX
MIN
TYP
UNIT
MAX
12
12
12
12
Bits
2
2
2
2
VPP
>1
>1
>1
>1
MΩ
7
7
7
7
pF
Analog input bandwidth
450
450
450
450
MHz
Analog input common mode current
(per input pin of each ADC)
180
151
114
92
µA
ANALOG INPUT
Differential input voltage range
Differential input resistance (at dc)
see Figure 91
Differential input capacitance
see Figure 92
REFERENCE VOLTAGES
VREFB
Internal reference bottom voltage
1
1
1
1
V
VREFT
Internal reference top voltage
2
2
2
2
V
ΔVREF
Internal reference error
(VREFT–VREFB)
VCM
Common mode output voltage
-20
±5
20
-20
1.5
±5
20
-20
1.5
±5
20
-20
1.5
±5
20
mV
1.5
V
DC ACCURACY
No missing codes
EO
Specified
Offset error
-10
Offset error temperature coefficient
±2
Specified
10
-10
0.05
±2
Specified
10
-10
0.05
±2
Specified
10
-10
0.05
±2
10
0.05
mV
mV/°C
There are two sources of gain error – internal reference inaccuracy and channel gain error
EGREF
EGCHAN
Gain error due to internal reference
inaccuracy alone, (ΔVREF /2) %
Gain error of channel alone
(1)
-1
0.25
1
-1
0.25
1
-1
0.25
1
-1
0.25
1
% FS
-1
±0.3
1
-1
±0.3
1
-1
±0.3
1
-1
±0.3
1
% FS
Channel gain error temperature
coefficient
DNL
Differential nonlinearity
INL
Integral nonlinearity
0.005
0.005
0.005
Δ%/°C
0.005
-0.75
± 0.6
2
-0.75
± 0.6
2
-0.75
± 0.5
2
-0.75
± 0.5
2
LSB
-2
±1
2
-2
±1
2
-2
±1
2
-2
±1
2
LSB
POWER SUPPLY
IAVDD
Analog supply current
IDRVDD
Digital supply current, CMOS
interface
DRVDD = 1.8 V
No load capacitance, FIN= 2 MHZ
IDRVDD
(1)
(2)
123
110
94
84
mA
6.1
5.4
4.5
4.0
mA
42
42
42
42
mA
(2)
Digital supply current, LVDS interface
DRVDD = 3.3 V
With 100 Ω external termination
Total power, CMOS
417
625
374
525
318
440
285
400
mW
Global power down
30
60
30
60
30
60
30
60
mW
This is specified by design and characterization; it is not tested in production.
In CMOS mode, the DRVDD current scales with the sampling frequency and the load capacitance on output pins (see Figure 84).
Copyright © 2007–2008, Texas Instruments Incorporated
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ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
DRVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal
reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted.
PARAMETER
TEST CONDITIONS
ADS6125
FS = 125 MSPS
MIN
TYP
MAX
ADS6124
FS = 105 MSPS
MIN
TYP
MAX
ADS6123
FS = 80 MSPS
MIN
TYP
MAX
ADS6122
FS = 65 MSPS
MIN
TYP
UNIT
MAX
DYNAMIC AC CHARACTERISTICS
Fin = 10 MHz
Fin = 50 MHz
68.5
Fin = 70 MHz
SNR
Signal to noise
ratio, CMOS
Fin = 170
MHz
Fin = 230
MHz
71.5
70.6
68.7
69.4
69.7
69.9
0 dB Gain
68.6
69.2
69.6
69.9
3.5 dB Coarse
gain
67.9
68.6
69.1
69.4
71.5
71.5
71.8
71.8
71.4
71.3
dBFS
68.5
71.3
68.5
69
71.5
71.3
71.5
71.6
69
71.6
0 dB Gain
70.3
70.3
70.6
70.7
3.5 dB Coarse
gain
69.8
69.8
70.1
70.1
0 dB Gain
69.6
69.6
70
70.1
69
69
69.5
69.6
71.1
71.3
71.5
71.6
70.3
70.7
dBFS
3.5 dB Coarse
gain
68
70.4
68
68.5
71.3
70.9
70.9
71.4
68.5
71.4
67.7
69.5
69.6
70.2
3.5 dB Coarse
gain
67.6
69.1
69.2
69.8
0 dB Gain
66.6
68
68.9
69.1
3.5 dB Coarse
gain
66.3
68
68.6
69
Fin = 10 MHz
71.5
71.5
71.7
71.7
Fin = 50 MHz
70.6
70.7
71.4
71.5
Fin = 70 MHz
71
71
71.1
71.5
0 dB Gain
69.1
69.7
70.1
70.3
3.5 dB Coarse
gain
69.3
69.5
69.9
70
0 dB Gain
68.2
68.1
69.4
69.1
3.5 dB Coarse
gain
68.3
68.3
69.2
69.1
Fin = 170
MHz
Fin = 170
MHz
Fin = 50 MHz
dBFS
dBFS
11
11.4
Fin = 70 MHz
Fin = 50 MHz
76
Fin = 70 MHz
Fin = 170
MHz
Fin = 230
MHz
11
11
Fin = 10 MHz
6
71.5
69
0 dB Gain
Fin = 230
MHz
SFDR
Spurious free
dynamic range
71.3
3.5 dB Coarse
gain
Fin = 70 MHz
Fin = 230
MHz
ENOB
Effective
number of bits
71
70.3
Fin = 50 MHz
SINAD
Signal to noise
and distortion
ratio
LVDS
71.7
71.4
70
Fin = 10 MHz
SINAD
Signal to noise
and distortion
ratio
CMOS
68.5
71.6
69
69.5
Fin = 70 MHz
Fin = 230
MHz
71.1
0 dB Gain
Fin = 50 MHz
Fin = 170
MHz
71.4
71.1
70.9
Fin = 10 MHz
SNR
Signal to noise
ratio, LVDS
71.3
90
91
80
83
84
76
11.55
11.5
11
93
79
84
89
79
86
0 dB Gain
76
80
81
82
3.5 dB Coarse
gain
78
82
83
84
0 dB Gain
75
77
79
79
3.5 dB Coarse
gain
76
79
81
82
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Bits
95
89
84
11.56
dBc
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
DRVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal
reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted.
PARAMETER
TEST CONDITIONS
ADS6125
FS = 125 MSPS
MIN
Fin = 10 MHz
Fin = 50 MHz
73
Fin = 70 MHz
THD
Total harmonic
distortion
Fin = 170
MHz
Fin = 230
MHz
90
79.5
82.5
73
MAX
MIN
76
TYP
MAX
MIN
TYP
91.5
93
88
88
83
79
78
80
75
81
79
82
76
0 dB Gain
71.5
75.5
76
76
3.5 dB Coarse
gain
72.5
77.5
78
78.5
96
96
97
98
95
96
76
91
85
76
79
96
92
93
96
79
93
0 dB Gain
81
83
83
86
3.5 dB Coarse
gain
82
84
84
87
0 dB Gain
75
79
80
79
3.5 dB Coarse
gain
76
81
81
81
90
91
93
95
80
83
Fin = 50 MHz
dBc
76
Fin = 70 MHz
UNIT
MAX
dBc
3.5 dB Coarse
gain
Fin = 10 MHz
HD3
Third harmonic
distortion
TYP
ADS6122
FS = 65 MSPS
83
Fin = 70 MHz
Fin = 230
MHz
MIN
88.5
82
Fin = 50 MHz
Fin = 170
MHz
MAX
ADS6123
FS = 80 MSPS
73.5
0 dB Gain
Fin = 10 MHz
HD2
Second
harmonic
distortion
TYP
ADS6124
FS = 105 MSPS
84
76
79
89
84
84
89
79
86
0 dB Gain
76
80
81
82
3.5 dB Coarse
gain
78
82
83
84
0 dB Gain
75
77
79
79
3.5 dB Coarse
gain
76
79
81
82
Fin = 10 MHz
93
94
96
97
Fin = 50 MHz
92
90
93
96
Fin = 70 MHz
91
90
92
95
Fin = 170
MHz
90
89
89
91
Fin = 230
MHz
90
88
89
90
IMD
2-Tone
intermodulation
distortion
F1 = 185 MHz, F2 = 190 MHz
Each tone at -7 dBFS
83
82
84
88
dBFS
Input overload
recovery
Recovery to within 1% (of final
value) for 6-dB overload with sine
wave input
1
1
1
1
clock
cycles
PSRR
AC Power
supply rejection
ratio
For 100 mVpp signal on AVDD
supply
35
35
35
35
dBc
Fin = 170
MHz
Fin = 230
MHz
Worst spur
(Other than
HD2, HD3)
dBc
dBc
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
DIGITAL CHARACTERISTICS (1)
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 AVDD = 3.3 V
PARAMETER
ADS6125/ADS6124
ADS6123/ADS6122
TEST CONDITIONS
MIN
DIGITAL INPUTS
PDN, SCLK, SEN & SDATA
TYP
MAX
UNIT
(2)
High-level input voltage
2.4
V
Low-level input voltage
0.8
V
High-level input current
33
µA
Low-level input current
–33
µA
4
pF
High-level output voltage
DRVDD
V
Low-level output voltage
0
V
2
pF
High-level output voltage
1375
mV
Low-level output voltage
1025
mV
350
mV
1200
mV
2
pF
Input capacitance
DIGITAL OUTPUTS
CMOS INTERFACE, DRVDD = 1.8 to 3.3 V
Output capacitance inside the device, from
each output to ground
Output capacitance
DIGITAL OUTPUTS
LVDS INTERFACE, DRVDD = 3.3 V, IO = 3.5 mA, RL = 100 Ω
(3)
Output differential voltage, |VOD|
225
VOS Output offset voltage, single-ended
Common-mode voltage of OUTP, OUTM
Output capacitance
Output capacitance inside the device, from
either output to ground
(1)
(2)
(3)
8
All LVDS and CMOS specifications are characterized, but not tested at production.
SCLK & SEN function as digital input pins when they are used for serial interface programming. When used as parallel control pins,
analog voltage needs to be applied as per Table 1 & Table 2.
IO Refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair.
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1)
Typical values are at 25°C, min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5
mA, RL = 100 Ω (3), no internal termination, unless otherwise noted.
For timings at lower sampling frequencies, see section Output Timings in the APPLICATION INFORMATION of this data
sheet.
PARAMETER
ta
Aperture
delay
tj
Aperture
jitter
Wake-up
time
(to valid
data)
TEST CONDITIONS
ADS6125
FS = 125 MSPS
ADS6124
FS = 105 MSPS
ADS6122
FS = 65 MSPS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
0.7
1.5
2.5
0.7
1.5
2.5
0.7
1.5
2.5
0.7
1.5
2.5
150
From global power
down
15
150
50
150
15
50
15
150
50
15
ns
fs rms
50
µs
15
50
15
50
15
50
15
50
µs
CMOS
100
200
100
200
100
200
100
200
ns
LVDS
200
500
200
500
200
500
200
500
ns
From standby
From output
buffer
disable
ADS6123
FS = 80 MSPS
Latency
9
9
9
clock
cycles
9
DDR LVDS MODE (4), DRVDD = 3.3 V
tsu
Data setup
time (5)
Data valid (6) to
zero-cross of
CLKOUTP
1.7
2.3
2.5
3.1
3.9
4.5
5.4
6.0
ns
th
Data hold
time (5)
Zero-cross of
CLKOUTP to data
becoming invalid (6)
0.7
1.7
0.7
1.7
0.7
1.7
0.7
1.7
ns
tPDI
Clock
propagation
delay
Input clock rising edge
zero-cross to output
clock rising edge
zero-cross
4.3
5.8
7.3
4.3
5.8
7.3
4.3
5.8
7.3
4.3
5.8
7.3
LVDS bit
clock duty
cycle
Duty cycle of
differential clock,
(CLKOUTPCLKOUTM)
10 ≤ Fs ≤ 125 MSPS
40%
47%
55%
40%
47%
55%
40%
47%
55%
40%
47%
55%
Data rise
time,
Data fall
time
Rise time measured
from –50 mV to 50 mV
Fall time measured
from 50 mV to –50 mV
1 ≤ Fs ≤ 125 MSPS
70
100
170
70
100
170
70
100
170
70
100
170
ps
Output clock
rise time,
Output clock
fall time
Rise time measured
from –50 mV to 50 mV
Fall time measured
from 50 mV to –50 mV
1 ≤ Fs ≤ 125 MSPS
70
100
170
70
100
170
70
100
170
70
100
170
ps
tr
tf
tCLKRI
SE
tCLKFA
LL
PARALLEL CMOS MODE, DRVDD = 2.5 V to 3.3 V, default output buffer drive strength
ns
(7)
(8)
tsu
Data setup
time (5)
Data valid to 50% of
CLKOUT rising edge
2.9
4.4
3.6
5.1
5.1
6.6
6.5
8.0
ns
th
Data hold
time (5)
50% of CLKOUT
Rising edge to data
becoming invalid (8)
1.3
2.7
2.1
3.5
3.6
5.0
5.1
6.5
ns
tPDI
Clock
propagation
delay
Input clock rising edge
zero-cross to 50% of
CLKOUT rising edge
5
6.5
5
6.5
5
6.5
5
6.5
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
7.9
7.9
7.9
7.9
ns
Timing parameters are specified by design and characterization and not tested in production.
CL is the Effective external single-ended load capacitance between each output pin and ground.
IO Refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair.
Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load.
Setup and hold time specifications take into account the effect of jitter on the output data and clock.
Data valid refers to logic high of +100 mV and logic low of –100 mV.
For DRVDD < 2.2V, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). See
Parallel CMOS interface in application section.
Data valid refers to logic high of 2V (1.7V) and logic low of 0.8 V (0.7V) for DRVDD = 3.3V (2.5V).
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TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)
For timings at lower sampling frequencies, see section Output Timings in the APPLICATION INFORMATION of this data
sheet.
PARAMETER
tr
tf
tCLKRI
SE
tCLKFA
LL
10
TEST CONDITIONS
ADS6125
FS = 125 MSPS
ADS6124
FS = 105 MSPS
ADS6123
FS = 80 MSPS
ADS6122
FS = 65 MSPS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
45%
50%
55%
45%
50%
55%
45%
50%
55%
45%
50%
55%
Output clock
duty cycle
Duty cycle of output
clock (CLKOUT)
10 ≤ Fs ≤ 125 MSPS
Data rise
time,
Data fall
time
Rise time measured
from 20% to 80% of
DRVDD
Fall time measured
from 80% to 20% of
DRVDD
1 ≤ Fs ≤ 125 MSPS
0.8
1.5
2.4
0.8
1.5
2.4
0.8
1.5
2.4
0.8
1.5
2.4
ns
Output clock
rise time,
Output clock
fall time
Rise time measured
from 20% to 80% of
DRVDD
Fall time measured
from 80% to 20% of
DRVDD
1 ≤ Fs ≤ 125 MSPS
0.8
1.5
2.4
0.8
1.5
2.4
0.8
1.5
2.4
0.8
1.5
2.4
ns
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N+4
N+3
N+2
N+12
N+11
N+10
N+1
Sample
N
N+9
Input
Signal
ta
CLKP
Input
Clock
CLKM
CLKOUTM
CLKOUTP
tsu
DDR
LVDS
Output Data
DXP, DXM
O
O
E
E – Even Bits D0,D2,D4,D6,D8,D10
O – Odd Bits D1,D3,D5,D7,D9,D11
E
N–9
O
O
E
N–8
E
O
N–7
tPDI
th
9 Clock Cycles
E
O
N–6
E
N–5
O
E
O
O
E
N
N–1
O
E
E
N+2
N+1
tPDI
CLKOUT
tsu
Parallel
CMOS
9 Clock Cycles
Output Data
D0–D11
N–8
N–9
N–7
th
N–6
N–5
N–1
N
N+1
N+2
Figure 1. Latency
Input
Clock
CLKM
CLKM
Input
Clock
CLKP
CLKP
tPDI
Output
Clock
tPDI
CLKOUTM
Output
Clock
CLKOUTP
CLKOUT
tsu
th
tsu
th
th
tsu
Output
Data Pair
(1)
(2)
Dn
Dn_Dn+1_P,
Dn_Dn+1_M
Dn
(1)
Dn+1
(2)
Output
Data
Dn
Dn
(1)
– Bits D0, D2, D4, D6, D8, D10
(1)
Dn – Bits D0–D11
Dn+1 – Bits D1, D3, D5, D7, D9, D11
Figure 2. LVDS Mode Timing
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Figure 3. CMOS Mode Timing
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DEVICE PROGRAMMING MODES
ADS612X has several features that can be easily configured using either parallel interface control or serial
interface programming.
USING SERIAL INTERFACE PROGRAMMING ONLY
To program using the serial interface, the internal registers must first be reset to their default values, and the
RESET pin must be kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are
used to access the internal registers of ADC. The registers are reset either by applying a pulse on the RESET
pin, or by a high setting on the <RST> bit (D4 in register 0x00). The Serial Interface section describes register
programming and register reset in more detail.
USING PARALLEL INTERFACE CONTROL ONLY
To control the device using parallel interface, keep RESET tied to high (AVDD). Now, SEN, SCLK, SDATA and
PDN function as parallel interface control pins. These pins can be used to directly control certain modes of the
ADC by connecting them to the correct voltage levels (as described in Table 1 to Table 3). There is no need to
apply a reset pulse.
Frequently used functions are controlled in this mode — standby, selection between LVDS/CMOS output format,
internal/external reference and 2s complement/straight binary output format. Table 1,Table 2, and Table 3
describe the modes controlled by the parallel pins.
AVDD
(5/8) AVDD
3R
(5/8) AVDD
GND
2R
AVDD
(3/8) AVDD
(3/8) AVDD
3R
To Parallel Pin
(SCLK, SDATA, SEN)
GND
Figure 4. Simple Scheme to Configure Parallel Pins
DESCRIPTION OF PARALLEL PINS
Table 1. SCLK Control Pin
SCLK
DESCRIPTION
0
Internal reference and 0 dB gain (Full-scale = 2 VPP)
(3/8) AVDD
External reference and 0 dB gain (Full-scale = 2 VPP)
(5/8) AVDD
External reference and 3.5 dB coarse gain (Full-scale = 1.34 VPP)
AVDD
Internal reference and 3.5 dB coarse gain (Full-scale = 1.34 VPP)
Table 2. SEN Control Pin
SEN
2s Complement format and DDR LVDS interface
(3/8) AVDD
Straight binary format and DDR LVDS interface
(5/8) AVDD
Straight binary and parallel CMOS interface
AVDD
12
DESCRIPTION
0
2s Complement format and parallel CMOS interface
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Table 3. SDATA, PDN Control Pins
SDATA
PDN
DESCRIPTION
Low
Low
Low
High (AVDD)
Normal operation
High (AVDD)
Low
High (AVDD)
High (AVDD)
Standby - only the ADC is powered down
Output buffers are powered down, fast wake-up time
Global power down. ADC, internal reference and output buffers are powered down, slow wake-up time
SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device
power-up, the internal registers must be reset to their default values by applying a high-going pulse on RESET
(of width greater than 10 ns).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded in
multiples of 16-bit words within a single active SEN pulse.
The first 5 bits form the register address and the remaining 11 bits form the register data.
The interface can work with SCLK frequency from 20 MHz down to very low speeds (few Hertz) and also with
non-50% SCLK duty cycle.
REGISTER ADDRESS
SDATA
A4
A3
A2
A1
REGISTER DATA
A0
D10
D9
D8
D7
D6
D5
D4
tDSU
tSCLK
D3
D2
D1
D0
tDH
SCLK
tSLOADH
SEN
tSLOADS
RESET
Figure 5. Serial Interface Timing Diagram
REGISTER INITIALIZATION
After power-up, the internal registers must be reset to their default values. This is done in one of two ways:
1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns) as
shown in Figure 5.
OR
2. By applying software reset. Using the serial interface, set the <RST> bit (D4 in register 0x00) to high. This
initializes the internal registers to their default values and then self-resets the <RST> bit to low. In this case
the RESET pin is kept low.
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SERIAL INTERFACE TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V (unless otherwise noted)
MIN
TYP MAX
UNIT
> DC
20
MHz
fSCLK
SCLK Frequency = 1/tSCLK
tSLOADS
SEN to SCLK Setup time
25
ns
tSLOADH
SCLK to SEN Hold time
25
ns
tDSU
SDATA Setup time
25
ns
tDH
SDATA Hold time
25
ns
RESET TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
t1
Power-on delay
Delay from power-up of AVDD and DRVDD to RESET pulse active
t2
Reset pulse width
t3
tPO
TYP
MAX
UNIT
5
ms
Pulse width of active RESET signal
10
ns
Register write delay
Delay from RESET disable to SEN active
25
Power-up time
Delay from power-up of AVDD and DRVDD to output stable
ns
6.5
ms
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.
For parallel interface operation, RESET has to be tied permanently HIGH.
Figure 6. Reset Timing Diagram
14
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SERIAL REGISTER MAP
Table 4 provides a summary of all the modes that can be programmed through the serial interface.
Table 4. Summary of Functions Supported by Serial Interface (1) (2)
REGISTER
ADDRESS
IN HEX
REGISTER FUNCTIONS
A4 - A0
D10
00
<PDN
OBUF>
Output
buffers
powered
down
D9
D8
D6
D5
D4
D3
D2
D1
D0
0
<STBY>
ADC Power
down
<LVDS
<COARSE
CMOS>
GAIN>
LVDS or
Coarse gain CMOS output
interface
0
0
<REF>
Internal or
external
Reference
<RST>
Software
Reset
0
<PDN
CLKOUT>
Output
clock buffer
powered
down
04
<DATAOUT
POSN>
Output data
position
control
<CLKOUT
EDGE>
Output
Clock edge
control
<CLKOUT
POSN>
Output Clock
position
control
0
0
0
0
0
0
0
0
09
Bit-wise or
Byte-wise
control
0
0
0
0
0
0
0
0
0
0
0A
<DATA
FORMAT>
2s
complement
or straight
binary
0
0
0
0
0
0
0
0
0
0
0
<TEST PATTERNS>
<CUSTOM LOW>
Custom Pattern lower 7bits
0B
<FINE GAIN>
Fine Gain 0 to 6dB
0C
(1)
(2)
D7
0E
0
0F
0
0
0
0
LVDS Termination
LVDS Internal Termination control for output data and clock
0
0
<DRIVE STRENGTH>
CMOS output buffer drive strength control
<CUSTOM HIGH>
Custom Pattern upper 5 bits
<LVDS CURRENT>
LVDS Current control
0
0
<CURRENT
DOUBLE>
LVDS current double
0
0
The unused bits in each register (shown by blank cells in above table) must be programmed as ‘0’.
Multiple functions in a register can be programmed in a single write operation.
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DESCRIPTION OF SERIAL REGISTERS
Each register function is explained in detail below.
Table 5.
A4–A0
(hex)
00
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
<PDN OBUF>
Output buffers
powered down
<COARSE
GAIN>
Coarse gain
<LVDS CMOS>
LVDS or CMOS
output interface
0
0
<REF>
Internal or
external
reference
<RST>
Software
Reset
0
<PDN CLKOUT>
Output clock
buffer powered
down
0
<STBY>
ADC Power
down
D0
0
Normal operation
1
Device enters standby mode where only ADC is powered down.
D2
<PDN CLKOUT> Power down modes
0
Output clock is active (on CLKOUT) pin
1
Output clock buffer is powered down and becomes tri-stated. Data outputs are unaffected.
D4
1
<RST>
Software reset applied - resets all internal registers and the bit self-clears to 0.
D5
<REF> Reference selection
0
Internal reference enabled
1
External reference enabled
D8
<LVDS CMOS> Output Interface selection
0
Parallel CMOS interface
1
DDR LVDS interface
D9
<COARSE GAIN> Gain programming
0
0 dB Coarse gain
1
3.5 dB Coarse gain
D10
16
<STBY> Power down modes
<PDN OBUF> Power down modes
0
Output data and clock buffers enabled
1
Output data and clock buffers disabled
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Table 6.
A4–A0
(hex)
04
D8
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
<DATAOUT POSN>
Output data position
control
<CLKOUT EDGE>
Output Clock edge
control
<CLKOUT POSN>
Output Clock
position control
0
0
0
0
0
0
0
0
<CLKOUT POSN> Output clock position control
0
Default output clock position after reset. The setup/hold timings for this clock position are specified
in the timing specifications table.
1
Output clock shifted (delayed) by 400 ps
D9
<CLKOUT EDGE>
0
Use rising edge to capture data
1
Use falling edge to capture data
D10
<DATAOUT_POSN>
0
Default position (after reset)
1
Data transition delayed by half clock cycle with respect to default position
Table 7.
A4–A0
(hex)
09
D10
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Bit-wise or
Byte-wise control
0
0
0
0
0
0
0
0
0
0
Bit-wise or byte-wise selection (DDR LVDS mode only)
0
Bit-wise sequence - Even data bits (D0, D2, D4..D12) are output at rising edge of CLKOUTP and
odd data bits (D1, D3, D5..D13) at falling edge of CLKOUTP
1
Byte-wise sequence - Lower 7 data bits (D0-D7) are output at rising edge of CLKOUTP and upper
7 data bits (D8-D13) at falling edge of CLKOUTP
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Table 8.
A4–A0
(hex)
0A
D7-D5
D10
D9
D8
<DF>
2s complement or straight binary
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
<TEST PATTERNS>
Test Patterns
000
Normal operation - <D13:D0> = ADC output
001
All zeros - <D13:D0> = 0x0000
010
All ones - <D13:D0> = 0x3FFF
011
Toggle pattern - <D13:D0> toggles between 0x2AAA and 0x1555
100
Digital ramp - <D13:D0> increments from 0x0000 to 0x3FFF by one code every cycle
101
Custom pattern - <D13:D0> = contents of CUSTOM PATTERN registers
110
Unused
111
Unused
D10
<DATA FORMAT>
0
2s Complement
1
Straight binary
Table 9.
A4–A0
(hex)
D10
D9
0B
D8
D7
D6
D5
D4
<CUSTOM LOW>
Lower 7bits of custom pattern
D3
D2
D1
D0
0
0
0
0
D3
D2
D1
D0
Table 10.
A4–A0
(hex)
D10
0C
18
D9
D8
<FINE GAIN>
Fine Gain 0 to 6dB
D7
D6
D5
0
0
0
D4
<CUSTOM HIGH>
Upper 5 bits of custom pattern
Reg 0B
D10-D4
<CUSTOM LOW> - Specifies lower 7 bits of custom pattern
Reg 0C
D4-D0
<CUSTOM HIGH> - Specifies upper 5 bits of custom pattern
D10-D8
<FINE GAIN> Gain programming
000
0 dB Gain
001
1 dB Gain
010
2 dB Gain
011
3 dB Gain
100
4 dB Gain
101
5 dB Gain
110
6 dB Gain
111
Unused
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Table 11.
A4–A0
(hex)
D10
0E
0
D1-D0
D0
D9
D8
D7
D4
D2
<LVDS
CURRENT>
LVDS Current
control
D1
D0
<CURRENT
DOUBLE>
LVDS current
double
LVDS Data buffer current control
1
2x LVDS Current set by <LVDS_CURR>
LVDS Clock buffer current control
0
Default current, set by <LVDS_CURR>
1
2x LVDS Current set by <LVDS_CURR>
<LVDS CURRENT> LVDS current programming
00
3.5 mA
01
2.5 mA
10
4.5 mA
11
1.75 mA
D9-D4
LVDS internal termination
D9-D7
<DATA TERM> Internal termination for LVDS output data bits
000
No internal termination
001
300 Ω
010
185 Ω
011
115 Ω
100
150 Ω
101
100 Ω
110
80 Ω
111
65 Ω
D6-D4
D3
<CURRENT DOUBLE> LVDS current programming
Default current, set by <LVDS_CURR>
D3-D2
D5
<LVDS TERMINATION>
LVDS Internal Termination control for output data and clock
0
D1
D6
<CLKOUT TERM> Internal termination for LVDS output clock
000
No internal termination
001
300 Ω
010
185 Ω
011
115 Ω
100
150 Ω
101
100 Ω
110
80 Ω
111
65 Ω
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Table 12.
A4–A0
(hex)
D10
D9
D8
0F
0
0
0
D7-D4
D7
D6
D5
D4
<DRIVE STRENGTH>
CMOS output buffer drive strength control
D3
D2
D1
D0
0
0
0
0
<DRIVE STRENGTH> Output buffer drive strength controls
0101
WEAKER than default drive
0000
DEFAULT drive strength
1111
STRONGER than default drive strength (recommended for load capacitances > 5 pF)
1010
MAXIMUM drive strength (recommended for load capacitances > 5 pF)
Other
Do not use
combinations
20
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
PIN CONFIGURATION (CMOS MODE)
DRVDD 1
25 OVR
26 CLKOUT
27 D6
28 D7
29 D8
30 D9
31 D10
32
D11
RHB PACKAGE
(TOP VIEW)
24 D5
Bottom Pad Connected
To DRGND
RESET 2
23 D4
CLKP 7
18 NC
CLKM 8
17 NC
PDN 16
19 D0
AVDD 15
AGND 6
VCM 14
20 D1
AVDD 13
SEN 5
AGND 12
21 D2
INM 11
SDATA 4
INP 10
22 D3
AGND 9
SCLK 3
Figure 7. CMOS Mode Pinout
Table 13. Pin Assignments – CMOS Mode
PIN NAME
PIN
TYPE
DESCRIPTION
PIN
NUMBER
NUMBER
OF PINS
AVDD
Analog power supply
I
13, 15
2
AGND
Analog ground
I
6, 9, 12
3
CLKP, CLKM
Differential clock input
I
7, 8
2
INP, INM
Differential analog input
I
10, 11
2
VCM
Internal reference mode – common-mode voltage output.
External reference mode – reference input. The voltage forced on this pin sets the
internal references.
I/O
14
1
RESET
Serial interface RESET input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin, or by using
the software reset option. See the SERIAL INTERFACE section.
In parallel interface mode, the user has to tie the RESET pin permanently HIGH.
(SCLK, SDATA and SEN are used as parallel pin controls in this mode)
The pin has an internal 100-kΩ pull-down resistor.
I
2
1
SCLK
This pin functions as serial interface clock input when RESET is low.
When RESET is tied high, it controls the coarse gain and internal/external reference
selection. Tie SCLK to low for internal reference and 0 dB gain and high for
internal reference and 3.5 dB gain. See Table 1.
The pin has an internal 100-kΩ pull-down resistor.
I
3
1
I
4
1
This pin functions as serial interface data input when RESET is low. It controls
various power down modes along with PDN pin when RESET is tied high.
SDATA
See Table 3 for detailed information.
The pin has an internal 100 kΩ pull-down resistor.
SEN
This pin functions as serial interface enable input when RESET is low. When
RESET is high, it controls output interface type and data formats. See Table 2 for
detailed information.
The pin has an internal 100-kΩ pull-up resistor to DRVDD.
I
5
1
PDN
Global power down control pin
I
16
1
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
Table 13. Pin Assignments – CMOS Mode (continued)
PIN NAME
DESCRIPTION
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
CLKOUT
CMOS Output clock
O
26
1
D0
CMOS Output data D0
O
19
1
D1
CMOS Output data D1
O
20
1
D2
CMOS Output data D2
O
21
1
D3
CMOS Output data D3
O
22
1
D4
CMOS Output data D4
O
23
1
D5
CMOS Output data D5
O
24
1
D6
CMOS Output data D6
O
27
1
D7
CMOS Output data D7
O
28
1
D8
CMOS Output data D8
O
29
1
D9
CMOS Output data D9
O
30
1
D10
CMOS Output data D10
O
31
1
D11
CMOS Output data D11
O
32
1
OVR
Indicates over-voltage on analog inputs (for differential input greater than full-scale),
CMOS level
O
25
1
DRVDD
Digital supply
I
1
1
Digital ground.
Connect the pad to the ground plane. See Board Design Considerations in
application information section.
I
PAD
1
DRGND
NC
Do not connect
17,18
2
22
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
PIN CONFIGURATION (LVDS MODE)
DRVDD 1
25 CLKOUTM
26 CLKOUTP
27 D6_D7_M
28 D6_D7_P
29 D8_D9_M
30 D8_D9_P
31 D10_D11_M
32 D10_D11_P
RHB PACKAGE
(TOP VIEW)
24 D4_D5_P
Bottom Pad Connected
To DRGND
RESET 2
23 D4_D5_M
CLKP 7
18 NC
CLKM 8
17 NC
PDN 16
19 D0_D1_M
AVDD 15
AGND 6
VCM 14
20 D0_D1_P
AVDD 13
SEN 5
AGND 12
21 D2_D3_M
INM 11
SDATA 4
INP 10
22 D2_D3_P
AGND 9
SCLK 3
Figure 8. LVDS Mode Pinout
Table 14. Pin Assignments – LVDS Mode
PIN NAME
PIN
TYPE
DESCRIPTION
PIN
NUMBER
NUMBER
OF PINS
AVDD
Analog power supply
I
13, 15
2
AGND
Analog ground
I
6, 9, 12
3
CLKP, CLKM
Differential clock input
I
7, 8
2
INP, INM
Differential analog input
I
10, 11
2
VCM
Internal reference mode – common-mode voltage output.
External reference mode – reference input. The voltage forced on this pin sets the
internal references.
I/O
14
1
RESET
Serial interface RESET input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin, or by using the
software reset option. See the SERIAL INTERFACE section.
In parallel interface mode, the user has to tie the RESET pin permanently HIGH.
(SCLK, SDATA and SEN are used as parallel pin controls in this mode)
The pin has an internal 100-kΩ pull-down resistor.
I
2
1
SCLK
This pin functions as serial interface clock input when RESET is low.
When RESET is tied high, it controls the coarse gain and internal/external reference
selection. Tie SCLK to low for internal reference and 0 dB gain and high for internal
reference and 3.5 dB gain. See Table 1.
The pin has an internal 100-kΩ pull-down resistor.
I
3
1
I
4
1
This pin functions as serial interface data input when RESET is low. It controls
various power down modes along with PDN pin when RESET is tied high.
SDATA
See Table 3 for detailed information.
The pin has an internal 100 kΩ pull-down resistor.
SEN
This pin functions as serial interface enable input when RESET is low. When RESET
is high, it controls output interface type and data formats. See Table 2 for detailed
information. The pin has an internal 100-kΩ pull-up resistor to DRVDD.
I
5
1
PDN
Global power down control pin
I
16
1
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
Table 14. Pin Assignments – LVDS Mode (continued)
PIN NAME
DESCRIPTION
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
CLKOUTP
Differential output clock, true
O
26
1
CLKOUTM
Differential output clock, complement
O
25
1
D0_D1_P
Differential output data D0 and D1 multiplexed, true
O
20
1
D0_D1_M
Differential output data D0 and D1 multiplexed, complement.
O
19
1
D2_D3_P
Differential output data D2 and D3 multiplexed, true
O
22
1
D2_D3_M
Differential output data D2 and D3 multiplexed, complement
O
21
1
D4_D5_P
Differential output data D4 and D5 multiplexed, true
O
24
1
D4_D5_M
Differential output data D4 and D5 multiplexed, complement
O
23
1
D6_D7_P
Differential output data D6 and D7 multiplexed, true
O
28
1
D6_D7_M
Differential output data D6 and D7 multiplexed, complement
O
27
1
D8_D9_P
Differential output data D8 and D9 multiplexed, true
O
30
1
D8_D9_M
Differential output data D8 and D9 multiplexed, complement
O
29
1
D10_D11_P
Differential output data D10 and D11 multiplexed, true
O
32
1
D10_D11_M
Differential output data D10 and D11 multiplexed, complement
O
31
1
DRVDD
Digital supply
I
1
1
Digital ground.
Connect the pad to the ground plane. See Board Design Considerations in application
information section.
I
PAD
1
DRGND
NC
Do not connect
17,18
2
24
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6125 (FS= 125 MSPS)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL
FFT for 70 MHz INPUT SIGNAL
0
0
SFDR = 92 dBc
SINAD = 71.3 dBFS
SNR = 71.5 dBFS
THD = 87.9 dBc
−20
−40
Amplitude − dB
Amplitude − dB
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
50
60
f − Frequency − MHz
0
10
20
40
50
60
G001
G002
Figure 9.
Figure 10.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
SFDR = 74.1 dBc
SINAD = 66.5 dBFS
SNR = 68.6 dBFS
THD = 71.4 dBc
−20
fIN1 = 190.1 MHz, –7 dBFS
fIN2 = 185.3 MHz, –7 dBFS
2-Tone IMD = –83.6 dBFS
SFDR = –81.3 dBFS
−20
−40
Amplitude − dB
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
50
f − Frequency − MHz
60
0
10
20
G003
40
50
60
G004
Figure 12.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
76
88
74
84
72
SNR − dBFS
92
80
Gain = 3.5 dB
76
Gain = 0 dB
72
30
f − Frequency − MHz
Figure 11.
SFDR − dBc
30
f − Frequency − MHz
0
Amplitude − dB
SFDR = 84.2 dBc
SINAD = 70.6 dBFS
SNR = 71 dBFS
THD = 82.7 dBc
−20
70
Gain = 0 dB
68
Gain = 3.5 dB
66
68
64
64
62
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
G005
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
Figure 13.
Copyright © 2007–2008, Texas Instruments Incorporated
G006
Figure 14.
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6125 (FS= 125 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface)
SNR vs INPUT FREQUENCY (LVDS interface)
92
76
88
74
72
SNR − dBFS
84
80
76
Gain = 0 dB
Gain = 0 dB
70
68
72
66
68
64
64
Gain = 3.5 dB
62
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
G007
Figure 15.
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
95
76
Input adjusted to get −1dBFS input
Input adjusted to get −1dBFS input
74
90
SINAD − dBFS
SFDR − dBc
5 dB
6 dB
80
4 dB
75
0 dB
70
1 dB
2 dB
70
68
66
3 dB
1 dB
64
2 dB
65
0 dB
72
3 dB
85
4 dB
62
60
100
200
300
400
fIN − Input Frequency − MHz
500
0
100
200
G009
PERFORMANCE vs AVDD
77
94
76
82
75
80
74
78
73
72
SNR
73
fIN = 10.1 MHz
AVDD = 3.3 V
72
SNR
SFDR − dBc
84
SNR − dBFS
SFDR − dBc
PERFORMANCE vs DRVDD
SFDR
74
92
71
90
70
SFDR
88
69
71
3.1
3.2
3.3
3.4
AVDD − Supply Voltage − V
3.5
86
1.8
70
3.6
G011
2.0
2.2
2.4
2.6
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2.8
3.0
DRVDD − Supply Voltage − V
Figure 19.
26
500
G010
96
78
76
400
Figure 18.
88
fIN = 70.1 MHz
DRVDD = 3.3 V
300
fIN − Input Frequency − MHz
Figure 17.
72
3.0
6 dB
5 dB
60
0
86
G008
Figure 16.
SNR − dBFS
SFDR − dBc
Gain = 3.5 dB
3.2
3.4
68
3.6
G012
Figure 20.
Copyright © 2007–2008, Texas Instruments Incorporated
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ADS6123, ADS6122
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6125 (FS= 125 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
PERFORMANCE vs TEMPERATURE
PERFORMANCE vs INPUT AMPLITUDE
94
74
110
90
SFDR (dBFS)
100
SFDR
72
SNR
88
71
86
70
80
SNR (dBFS)
80
69
70
70
60
65
SFDR (dBc)
50
60
40
60
30
−60
80
−50
−40
−30
PERFORMANCE vs CLOCK AMPLITUDE
SFDR − dBc
88
86
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
92
71.5
91
71.0
90
71.0
89
70.5
70.5
SFDR
70.0
82
69.5
80
78
2.0
2.5
SFDR − dBc
SNR
1.5
72.0
71.5
SFDR
88
70.0
SNR
87
69.5
69.0
86
69.0
68.5
85
68.0
3.0
84
Input Clock Amplitude − VPP
68.5
fIN = 10.1 MHz
68.0
30
35
40
45
50
55
60
65
70
Input Clock Duty Cycle − %
G015
Figure 23.
G016
Figure 24.
OUTPUT NOISE HISTOGRAM
(INPUTS TIED TO COMMON-MODE)
PERFORMANCE IN EXTERNAL REFERENCE MODE
60
93
76
fIN = 20.1 MHz
External Reference Mode
RMS (LSB) = 0.497
50
91
40
SFDR − dBc
Occurence − %
G014
72.0
SNR − dBFS
fIN = 20.1 MHz
1.0
50
0
Figure 22.
92
76
0.5
−10
Input Amplitude − dBFS
G013
Figure 21.
84
−20
SNR − dBFS
20
55
fIN = 10.1 MHz
30
20
74
89
72
SNR
87
70
SNR − dBFS
0
T − Temperature − °C
90
75
40
fIN = 10.1 MHz
−20
90
SNR − dBFS
SNR − dBFS
90
84
−40
85
73
SFDR − dBc, dBFS
SFDR − dBc
92
SFDR
85
10
0
83
1.30
2048 2049 2050 2051 2052 2053 2054 2055 2056 2057
Output Code
G017
68
1.35
1.40
1.45
1.55
1.60
1.65
66
1.70
VVCM − VCM Voltage − V
Figure 25.
Copyright © 2007–2008, Texas Instruments Incorporated
1.50
G018
Figure 26.
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6124 (FS= 105 MSPS)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL
FFT for 80 MHz INPUT SIGNAL
0
0
SFDR = 88.2 dBc
SINAD = 71.3 dBFS
SNR = 71.5 dBFS
THD = 87.1 dBc
−20
−40
Amplitude − dB
Amplitude − dB
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
50
f − Frequency − MHz
0
10
20
30
40
50
f − Frequency − MHz
G019
G020
Figure 27.
Figure 28.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
0
SFDR = 74.9 dBc
SINAD = 65.8 dBFS
SNR = 67.1 dBFS
THD = 73.3 dBc
−20
fIN1 = 190.1 MHz, –7 dBFS
fIN2 = 185.3 MHz, –7 dBFS
2-Tone IMD = –82.4 dBFS
SFDR = –87.8 dBFS
−20
−40
Amplitude − dB
−40
Amplitude − dB
SFDR = 84.8 dBc
SINAD = 70.8 dBFS
SNR = 71.1 dBFS
THD = 82.9 dBc
−20
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
f − Frequency − MHz
50
0
10
20
30
40
f − Frequency − MHz
G021
Figure 29.
50
G022
Figure 30.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
96
76
92
74
72
84
Gain = 3.5 dB
SNR − dBFS
SFDR − dBc
88
80
76
Gain = 0 dB
72
Gain = 0 dB
70
68
Gain = 3.5 dB
66
68
64
64
60
62
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
G023
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
Figure 31.
28
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G024
Figure 32.
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ADS6123, ADS6122
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6124 (FS= 105 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface)
SNR vs INPUT FREQUENCY (LVDS interface)
96
76
92
74
88
SFDR − dBc
SNR − dBFS
72
84
Gain = 3.5 dB
80
76
Gain = 0 dB
72
Gain = 0 dB
70
Gain = 3.5 dB
68
66
68
64
64
60
62
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
G025
Figure 33.
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
95
76
Input adjusted to get −1dBFS input
Input adjusted to get −1dBFS input
74
90
80
0 dB
75
0 dB
72
4 dB
1 dB
1 dB
2 dB
70
68
66
70
64
2 dB
4 dB
3 dB
5 dB
65
62
3 dB
60
60
0
100
200
300
400
500
fIN − Input Frequency − MHz
0
100
200
G027
PERFORMANCE vs AVDD
77
76
86
75
SFDR
84
74
82
73
96
94
72
SNR
78
71
3.4
AVDD − Supply Voltage − V
3.5
SFDR − dBc
88
3.3
G029
76
75
SFDR
92
74
90
73
SNR
88
72
86
71
84
1.8
70
3.6
77
fIN = 10.1 MHz
AVDD = 3.3 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
70
3.6
DRVDD − Supply Voltage − V
Figure 37.
Copyright © 2007–2008, Texas Instruments Incorporated
G028
PERFORMANCE vs DRVDD
SNR − dBFS
SFDR − dBc
fIN = 70.1 MHz
DRVDD = 3.3 V
3.2
500
98
78
3.1
400
Figure 36.
92
80
300
fIN − Input Frequency − MHz
Figure 35.
76
3.0
6 dB
SNR − dBFS
SFDR − dBc
5 dB
SINAD − dBFS
6 dB
85
90
G026
Figure 34.
G030
Figure 38.
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6124 (FS= 105 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
PERFORMANCE vs TEMPERATURE
PERFORMANCE vs INPUT AMPLITUDE
110
75
SFDR (dBFS)
100
SFDR
92
73
90
72
SNR
88
SNR − dBFS
74
SFDR − dBc, dBFS
94
90
80
SNR (dBFS)
80
75
70
70
60
65
SFDR (dBc)
50
60
71
40
fIN = 10.1 MHz
86
−40
0
20
40
60
55
fIN = 20.1 MHz
30
−60
70
−20
80
T − Temperature − °C
−50
−40
−30
−10
50
0
G032
Figure 40.
PERFORMANCE vs CLOCK AMPLITUDE
92
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
72.0
96
72.0
SNR
SFDR
94
71.0
92
70.5
84
70.0
82
69.5
80
78
SFDR − dBc
88
71.5
SNR − dBFS
90
86
−20
Input Amplitude − dBFS
G031
Figure 39.
SFDR − dBc
85
fIN = 10.1 MHz
71.5
SFDR
71.0
90
70.5
SNR
88
70.0
86
69.5
69.0
84
69.0
68.5
82
68.5
68.0
3.0
80
SNR − dBFS
SFDR − dBc
90
SNR − dBFS
96
fIN = 20.1 MHz
76
0.5
1.0
1.5
2.0
2.5
Input Clock Amplitude − VPP
68.0
30
35
40
45
50
55
60
Input Clock Duty Cycle − %
G033
Figure 41.
65
70
G034
Figure 42.
PERFORMANCE IN EXTERNAL REFERENCE MODE
96
76
fIN = 20.1 MHz
External Reference Mode
74
SNR
92
72
90
70
SNR − dBFS
SFDR − dBc
94
SFDR
88
86
1.30
68
1.35
1.40
1.45
1.50
1.55
VVCM − VCM Voltage − V
1.60
1.65
66
1.70
G036
Figure 43.
30
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6123 (FS= 80 MSPS)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL
FFT for 70 MHz INPUT SIGNAL
0
0
SFDR = 89.34 dBc
SINAD = 71.57 dBFS
SNR = 71.74 dBFS
THD = 86.63 dBc
−20
−40
Amplitude − dB
Amplitude − dB
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
f − Frequency − MHz
40
0
10
20
30
f − Frequency − MHz
G037
40
G038
Figure 44.
Figure 45.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
0
SFDR = 81.4 dBc
SINAD = 69 dBFS
SNR = 69.7 dBFS
THD = 78 dBc
−20
fIN1 = 190.1 MHz, –7 dBFS
fIN2 = 185.3 MHz, –7 dBFS
2-Tone IMD = –84.1 dBFS
SFDR = –89.5 dBFS
−20
−40
Amplitude − dB
−40
Amplitude − dB
SFDR = 83.43 dBc
SINAD = 71.03 dBFS
SNR = 71.49 dBFS
THD = 82.65 dBc
−20
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
f − Frequency − MHz
40
0
10
20
30
f − Frequency − MHz
G039
Figure 46.
40
G040
Figure 47.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
100
76
96
74
72
88
Gain = 3.5 dB
SNR − dBFS
SFDR − dBc
92
84
80
Gain = 0 dB
76
72
Gain = 0 dB
70
68
Gain = 3.5 dB
66
68
64
64
60
62
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
G041
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
Figure 48.
Copyright © 2007–2008, Texas Instruments Incorporated
G042
Figure 49.
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6123 (FS= 80 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface)
SNR vs INPUT FREQUENCY (LVDS interface)
100
76
96
74
92
72
Gain = 3.5 dB
SNR − dBFS
SFDR − dBc
88
84
80
76
Gain = 0 dB
Gain = 0 dB
70
Gain = 3.5 dB
68
72
66
68
64
64
60
62
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
G043
Figure 50.
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
95
74
Input adjusted to get −1dBFS input
Input adjusted to get −1dBFS input
1 dB
3 dB
70
2 dB
6 dB
80
SINAD − dBFS
85
5 dB
0 dB
4 dB
1 dB
75
66
64
4 dB
5 dB
6 dB
62
65
60
60
58
0
100
200
300
400
fIN − Input Frequency − MHz
500
0
100
200
G045
PERFORMANCE vs AVDD
77
76
82
75
80
74
78
73
SNR
100
72
74
71
3.2
3.3
3.4
AVDD − Supply Voltage − V
3.5
74
fIN = 10.1 MHz
AVDD = 3.3 V
73
SNR
SFDR − dBc
SFDR
SNR − dBFS
SFDR − dBc
PERFORMANCE vs DRVDD
84
3.1
98
72
96
71
94
92
69
90
68
88
1.8
70
3.6
G047
70
SFDR
2.0
2.2
2.4
2.6
2.8
3.0
DRVDD − Supply Voltage − V
Figure 54.
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500
G046
102
78
76
400
Figure 53.
88
fIN = 70.1 MHz
DRVDD = 3.3 V
300
fIN − Input Frequency − MHz
Figure 52.
32
3 dB
68
70
72
3.0
2 dB
3.2
3.4
SNR − dBFS
SFDR − dBc
0 dB
72
90
86
G044
Figure 51.
67
3.6
G048
Figure 55.
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122
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ADS6123, ADS6122
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6123 (FS= 80 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
PERFORMANCE vs TEMPERATURE
PERFORMANCE vs INPUT AMPLITUDE
74
110
90
100
SFDR
72
SNR
93
71
91
70
SNR − dBFS
95
69
−20
SFDR (dBFS)
90
80
80
75
70
70
SNR (dBFS)
60
65
50
60
SFDR (dBc)
40
fIN = 10.1 MHz
89
−40
85
73
SFDR − dBc, dBFS
SFDR − dBc
97
0
20
40
60
T − Temperature − °C
55
fIN = 20 MHz
30
−60
80
SNR − dBFS
99
−50
−40
−30
−20
−10
50
0
Input Amplitude − dBFS
G049
Figure 56.
G050
Figure 57.
PERFORMANCE vs CLOCK AMPLITUDE
94
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
98
72.0
72.0
fIN = 10.1 MHz
88
96
71.0
94
70.5
SFDR
69.5
69.0
86
69.0
68.5
84
68.5
68.0
3.0
82
82
1.0
1.5
2.0
2.5
70.5
SNR
70.0
69.5
78
0.5
92
88
70.0
84
fIN = 20.1 MHz
71.0
90
86
80
71.5
SFDR
Input Clock Amplitude − VPP
SNR − dBFS
SFDR − dBc
90
71.5
SFDR − dBc
SNR
SNR − dBFS
92
68.0
30
35
40
45
50
55
60
65
70
Input Clock Duty Cycle − %
G051
Figure 58.
G052
Figure 59.
PERFORMANCE IN EXTERNAL REFERENCE MODE
92
78
fIN = 20.1 MHz
External Reference Mode
90
76
88
74
SNR
86
72
84
82
1.30
SNR − dBFS
SFDR − dBc
SFDR
70
1.35
1.40
1.45
1.50
1.55
VVCM − VCM Voltage − V
1.60
1.65
68
1.70
G054
Figure 60.
Copyright © 2007–2008, Texas Instruments Incorporated
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6122 (FS= 65 MSPS)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
FFT for 20 MHz INPUT SIGNAL
FFT for 90 MHz INPUT SIGNAL
0
0
SFDR = 91.8 dBc
SINAD = 71.1 dBFS
SNR = 71.8 dBFS
THD = 89.8 dBc
−20
−40
Amplitude − dB
Amplitude − dB
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
f − Frequency − MHz
0
10
20
30
f − Frequency − MHz
G055
G056
Figure 61.
Figure 62.
FFT for 230 MHz INPUT SIGNAL
INTERMODULATION DISTORTION (IMD) vs FREQUENCY
0
0
SFDR = 82.8 dBc
SINAD = 69.5 dBFS
SNR = 70.1 dBFS
THD = 79.6 dBc
−20
fIN1 = 190.1 MHz, –7 dBFS
fIN2 = 185.3 MHz, –7 dBFS
2-Tone IMD = –88.5 dBFS
SFDR = –91.9 dBFS
−20
−40
Amplitude − dB
−40
Amplitude − dB
SFDR = 83 dBc
SINAD = 71.1 dBFS
SNR = 71.6 dBFS
THD = 82.3 dBc
−20
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
f − Frequency − MHz
30
0
10
20
f − Frequency − MHz
G057
Figure 63.
30
G058
Figure 64.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
100
76
96
74
88
72
Gain = 3.5 dB
SNR − dBFS
SFDR − dBc
92
84
80
76
Gain = 0 dB
72
Gain = 0 dB
70
68
Gain = 3.5 dB
66
68
64
64
60
62
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
G059
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
Figure 65.
34
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G060
Figure 66.
Copyright © 2007–2008, Texas Instruments Incorporated
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ADS6123, ADS6122
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6122 (FS= 65 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
SFDR vs INPUT FREQUENCY (LVDS interface)
SNR vs INPUT FREQUENCY (LVDS interface)
100
76
96
74
88
72
Gain = 3.5 dB
SNR − dBFS
SFDR − dBc
92
84
80
76
Gain = 0 dB
Gain = 0 dB
70
Gain = 3.5 dB
68
72
66
68
64
64
60
62
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
G061
Figure 67.
SFDR vs INPUT FREQUENCY ACROSS GAINS
SINAD vs INPUT FREQUENCY ACROSS GAINS
95
76
Input adjusted to get −1dBFS input
Input adjusted to get −1dBFS input
74
90
3 dB
6 dB
80
0 dB
72
1 dB
0 dB
5 dB
75
2 dB
70
68
66
70
3 dB
64
5 dB
4 dB
4 dB
65
60
100
200
300
400
fIN − Input Frequency − MHz
500
0
100
200
G063
Figure 69.
PERFORMANCE vs AVDD
fIN = 70.1 MHz
DRVDD = 3.3 V
73
SNR
72
84
71
82
70
3.4
AVDD − Supply Voltage − V
3.5
SFDR − dBc
88
75
fIN = 10.1 MHz
AVDD = 3.3 V
74
102
SNR − dBFS
74
3.3
104
75
90
3.2
100
G065
72
98
71
SFDR
96
70
94
69
92
1.8
69
3.6
73
SNR
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
68
3.6
DRVDD − Supply Voltage − V
Figure 71.
Copyright © 2007–2008, Texas Instruments Incorporated
G064
PERFORMANCE vs DRVDD
76
SFDR
3.1
500
106
77
86
400
Figure 70.
96
92
300
fIN − Input Frequency − MHz
SNR − dBFS
0
SFDR − dBc
6 dB
62
60
80
3.0
2 dB
1 dB
SINAD − dBFS
SFDR − dBc
85
94
G062
Figure 68.
G066
Figure 72.
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS - ADS6122 (FS= 65 MSPS) (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output
interface (unless otherwise noted)
PERFORMANCE vs TEMPERATURE
PERFORMANCE vs INPUT AMPLITUDE
76
110
fIN = 10.1 MHz
100
SFDR
74
92
73
SNR
90
72
88
71
86
−40
0
20
40
60
80
SNR (dBFS)
80
75
70
70
60
65
SFDR (dBc)
50
60
55
fIN = 20.1 MHz
30
−60
80
T − Temperature − °C
90
40
70
−20
85
−50
−40
−30
PERFORMANCE vs CLOCK AMPLITUDE
71.5
94
71.0
92
88
70.0
86
69.5
84
82
fIN = 20.1 MHz
1.5
2.0
2.5
SFDR − dBc
SFDR − dBc
96
70.5
SFDR
1.0
G068
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
72.0
SNR − dBFS
SNR
92
80
0.5
50
0
Figure 74.
96
90
−10
Input Amplitude − dBFS
G067
Figure 73.
94
−20
72.0
71.5
SFDR
71.0
90
70.5
SNR
88
70.0
86
69.5
69.0
84
69.0
68.5
82
68.0
3.0
80
Input Clock Amplitude − VPP
SNR − dBFS
94
SNR − dBFS
75
SFDR − dBc, dBFS
SFDR − dBc
96
90
SFDR (dBFS)
SNR − dBFS
98
68.5
fIN = 10.1 MHz
68.0
30
35
40
45
50
55
60
Input Clock Duty Cycle − %
G069
Figure 75.
65
70
G070
Figure 76.
PERFORMANCE IN EXTERNAL REFERENCE MODE
95
78
fIN = 20.1 MHz
External Reference Mode
76
SFDR
91
74
SNR
89
72
87
85
1.30
SNR − dBFS
SFDR − dBc
93
70
1.35
1.40
1.45
1.50
1.55
VVCM − VCM Voltage − V
1.60
1.65
68
1.70
G072
Figure 77.
36
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS - LOW SAMPLING FREQUENCIES
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
FS = 40 MSPS
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
100
76
96
74
72
88
SNR − dBFS
SFDR − dBc
92
84
Gain = 3.5 dB
80
76
72
Gain = 0 dB
70
Gain = 3.5 dB
68
66
Gain = 0 dB
68
64
64
60
62
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
G073
Figure 78.
G074
Figure 79.
FS = 25 MSPS
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
76
100
74
90
SNR − dBFS
SFDR − dBc
72
Gain = 3.5 dB
80
70
Gain = 0 dB
68
66
Gain = 0 dB
60
70
Gain = 3.5 dB
64
50
62
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
G075
0
50
100 150 200 250 300 350 400 450 500
fIN − Input Frequency − MHz
Figure 80.
Copyright © 2007–2008, Texas Instruments Incorporated
G076
Figure 81.
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
COMMON PLOTS
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
POWER DISSIPATION vs
SAMPLING FREQUENCY (DDR LVDS and CMOS)
COMMON-MODE REJECTION RATIO vs FREQUENCY
0.8
0.7
PD − Power Dissipation − W
0
−10
−20
CMRR − dBc
−30
−40
−50
−60
−70
−80
fIN = 2.5 MHz
CL = 5 pF
0.6
0.5
LVDS
0.4
0.3
CMOS
0.2
0.1
−90
0.0
−100
0
50
100
150
200
250
0
300
f − Frequency − MHz
25
50
75
100
fS − Sampling Frequency − MSPS
G077
Figure 82.
125
G078
Figure 83.
DRVDD current vs
SAMPLING FREQUENCY across load capacitance (CMOS)
30
1.8 V, No Load
DRVDD Current − mA
25
1.8 V, 5 pF
20
3.3 V, No Load
3.3 V, 5 pF
15
3.3 V, 10 pF
10
5
0
0
25
50
75
100
fS − Sampling Frequency − MSPS
125
G079
Figure 84.
38
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
Contour Plots Across Input and Sampling Frequencies
125
120
90
fS - Sampling Frequency - MSPS
110
75
84
84
87
72
78
81
66
69
84
84
63
100
75
81
87
90
84
90
87
70
72
78
90
87
80
66
60
69
81
63
78
60
75
84
50
90
69
72
66
40
93
30
25
10
81
84
50
78
150
100
75
60
63
200
250
300
400
350
450
500
fIN - Input Frequency - MHz
60
65
75
70
80
85
90
95
SFDR - dBc
M0049-15
Figure 85. SFDR Contour (No gain, FS = 2 VPP)
125
120
84
87
87
87
84
75
78
81
fS - Sampling Frequency - MSPS
110
69
87
100
72
66
90
75
90
90
80
90
87
70
60
78
81
87
93
84
69
90
75
81
93
66
72
78
50
90
90
40
30
25
10
87
84
93
93
50
100
150
81
78
75
200
250
300
72
63
69
400
350
450
500
fIN - Input Frequency - MHz
60
65
70
75
80
85
90
SFDR - dBc
95
M0049-16
Figure 86. SFDR Contour (with 3.5 dB Coarse gain, FS = 1.34 VPP)
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Contour Plots Across Input and Sampling Frequencies (continued)
Figure 87. SNR Contour (No gain, FS = 2 VPP)
Figure 88. SNR Contour (with 3.5 dB Coarse gain, FS = 1.34 VPP)
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APPLICATION INFORMATION
THEORY OF OPERATION
ADS612X is a family of low power 12-bit pipeline ADC in a CMOS process up to 125 MSPS sampling frequency.
It is based on switched capacitor technology and runs off a single 3.3-V supply. The conversion process is
initiated by a rising edge of the external input clock. Once the signal is captured by the input sample and hold,
the input sample is sequentially converted by a series of lower resolution stages, with the outputs combined in a
digital correction logic block. At every clock edge, the sample propagates through the pipeline resulting in a data
latency of 9 clock cycles. The output is available as 12-bit data, in DDR LVDS or CMOS and coded in either
straight offset binary or binary 2s complement format.
ANALOG INPUT
The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in
Figure 89.
This differential topology results in good ac-performance even for high input frequencies at high sampling rates.
The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V available on VCM
pin. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5 V
and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The maximum swing is determined by the internal
reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal).
Sampling
Switch
Lpkg
»1 nH
Sampling
Capacitor
RCR Filter
INP
Cbond
»1 pF
25 W
Resr
200 W
Cpar2
1 pF
50 W
3.2 pF
Csamp
4.0 pF
Ron
10 W
Cpar1
0.8 pF
50 W
Lpkg
»1 nH
Ron
15 W
Ron
15 W
25 W
Csamp
4.0 pF
INM
Cbond
»1 pF
Resr
200 W
Sampling
Capacitor
Cpar2
1 pF
Sampling
Switch
Figure 89. Input Stage
The input sampling circuit has a high 3-dB bandwidth that extends up to 450 MHz (measured from the input pins
to the voltage across the sampling capacitors).
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1
0
Magnitude − dB
−1
−2
−3
−4
−5
−6
−7
0
100
200
300
400
500
600
fIN − Input Frequency − MHz
G080
Figure 90. ADC Analog Input Bandwidth
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection.
A 5-Ω resistor in series with each input pin is recommended to damp out ringing caused by the package
parasitics. It is also necessary to present low impedance (< 50 Ω) for the common mode switching currents. For
example, this is achieved by using two resistors from each input terminated to the common mode voltage (VCM).
In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the
desired frequency range and matched impedance to the source. While doing this, the ADC input impedance
must be considered. Over a wide frequency range, the input impedance can be approximated by a parallel
combination of Rin and Cin (Zin = Rin || Cin).
R − Resistance − kΩ
100
10
1
0.1
0.01
0
100
200
300
400
500
f − Frequency − MHz
600
G083
Figure 91. ADC Input Resistance, Rin
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9
C − Capacitance − pF
8
7
6
5
4
3
2
1
0
0
100
200
300
400
500
f − Frequency − MHz
600
G084
Figure 92. ADC Input Capacitance, Cin
Using RF-Transformer Based Drive Circuits
Figure 93 shows a configuration using a single 1:1 turns ratio transformer (for example, Coilcraft WBC1-1) that
can be used for low input frequencies (about 100 MHz).
The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated on the
secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by the
sampling circuit from the RF transformer’s leakage inductances. The termination is accomplished by two resistors
connected in series, with the center point connected to the 1.5 V common mode (VCM pin). The value of the
termination resistors (connected to common mode) has to be low (< 100 Ω) to provide a low-impedance path for
the ADC common-mode switching current.
TF_ADC
0.1 mF
5W
INP
0.1 mF
25 W
25 W
5W
INM
1 :1
VCM
Figure 93. Single Transformer Drive Circuit
At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results
in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps
minimize this mismatch, and good performance is obtained for high frequency input signals. Figure 94 shows an
example using two transformers (Coilcraft WBC1-1). An additional termination resistor pair (enclosed within the
shaded box in Figure 94) may be required between the two transformers to improve the balance between the P
and M sides. The center point of this termination must be connected to ground.
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5W
0 .1mF
INP
50 W
50 W
0 .1mF
50 W
50 W
5W
INM
1:1
1:1
VCM
Figure 94. Two Transformer Drive Circuit
Using Differential Amplifier Drive Circuits
Figure 95 shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input to
differential output that can be interface to the ADC analog input pins. In addition to the single-ended to differential
conversion, the amplifier also provides gain (10 dB in Figure 95). RFIL helps to isolate the amplifier outputs from
the switching input of the ADC. Together with CFIL it also forms a low-pass filter that band-limits the noise (and
signal) at the ADC input. As the amplifier output is ac-coupled, the common-mode voltage of the ADC input pins
is set using two 200 Ω resistors connected to VCM.
The amplifier output can also be dc-coupled. Using the output common-mode control of the THS4509, the ADC
input pins can be biased to 1.5 V. In this case, use +4 V and -1 V supplies for the THS4509 so that its output
common-mode voltage (1.5 V) is at mid-supply.
RF
+VS
500 W
0.1 mF
RS
0.1 mF 10 mF
RFIL
0.1 mF
5W
INP
RG
0.1 mF
RT
CFIL
200 W
CFIL
200 W
CM THS4509
RG
RFIL
INM
5W
0.1 mF
500 W
RS || RT
VCM
0.1 mF
–VS
ADS612x
0.1 mF 10 mF
0.1 mF
RF
Figure 95. Drive Circuit Using the THS4509
See the EVM User Guide (SLWU028) for more information.
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Input Common-Mode
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-µF low-inductance capacitor
connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC
sinks a common-mode current in the order of 180 µA (at 125 MSPS). Equation 1 describes the dependency of
the common-mode current and the sampling frequency.
Fs
180 mA x
125 MSPS
(1)
Equation 1 helps to design the output capability and impedance of the CM driving circuit.
REFERENCE
ADS612X has built-in internal references REFP and REFM, requiring no external components. Design schemes
are used to linearize the converter load seen by the references; this and the integration of the requisite reference
capacitors on-chip eliminates the need for external decoupling. The full-scale input range of the converter is
controlled in the external reference mode as explained below. The internal or external reference modes can be
selected by programming the serial interface register bit <REF> (seeTable 5).
INTREF
INTERNAL
REFERENCE
VCM
1 kW
4 kW
INTREF
EXTREF
REFM
REFP
Figure 96. Reference Section
Internal Reference
When the device is in internal reference mode, the REFP and REFM voltages are generated internally.
Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog
input pins.
External Reference
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the
VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential
input voltage corresponding to full-scale is given by Equation 2.
Full−scale differential input pp + (Voltage forced on VCM) 1.33
(2)
In this mode, the 1.5 V common-mode voltage to bias the input pins has to be generated externally. There is no
change in performance compared to internal reference mode.
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COARSE GAIN and PROGRAMMABLE FINE GAIN
ADS612X includes gain settings that can be used to get improved SFDR performance (compared to 0 dB gain
mode). The gain settings are 3.5 dB coarse gain and programmable fine gain from 0 dB to 6 dB. For each gain
setting, the analog input full-scale range scales proportionally, as shown in Table 15.
The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR (as
seen in Figure 13 and Figure 14). The fine gain is programmable in 1 dB steps from 0 to 6 dB. With fine gain
also, SFDR improvement is achieved, but at the expense of SNR (there is about 1 dB SNR degradation for every
1 dB of fine gain).
So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get
best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the
SFDR improvement is significant with marginal degradation in SINAD. The gains can be programmed using the
register bits <COARSE GAIN> (see Table 5) and <FINE GAIN> (see Table 10). Note that the default gain after
reset is 0 dB.
Table 15. Full-Scale Range Across Gains
GAIN, dB
TYPE
FULL-SCALE RANGE, VPP
0
Default after reset
2.00
3.5
Coarse setting (fixed)
1.34
1
1.78
2
1.59
3
Fine gain (programmable)
4
46
1.42
1.26
5
1.12
6
1.00
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CLOCK INPUT
The clock inputs of the ADS612X can be driven differentially (SINE, LVPECL or LVDS) or single-ended
(LVCMOS), with little or no difference in performance between configurations. The common-mode voltage of the
clock inputs is set to VCM using internal 5-kΩ resistors as shown in Figure 97. This allows the use of
transformer-coupled drive circuits for sine wave clock, or ac-coupling for LVPECL, LVDS clock sources
(Figure 99 and Figure 100).
For best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to
common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with
0.1-µF capacitors, as shown in Figure 99. A single-ended CMOS clock can be ac-coupled to the CLKP input,
with CLKM connected to ground with a 0.1-µF capacitor, as shown in Figure 100.
For high input frequency sampling, the use a clock source with very low jitter is recommended. Bandpass filtering
of the clock source can help reduce the effect of jitter. There is no change in performance with a non-50% duty
cycle clock input. Figure 24 shows the performance of the ADC versus clock duty cycle.
Clock Buffer
Lpkg
» 1 nH
10 W
CLKP
Cbond
» 1 pF
Ceq
Ceq
5 kW
Resr
» 100 W
VCM
6 pF
5 kW
Lpkg
» 1 nH
10 W
CLKM
Cbond
» 1 pF
Resr
» 100 W
Ceq » 1 to 3 pF, equivalent input capacitance of clock buffer
Figure 97. Internal Clock Buffer
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1000
Impedance (Magnitude) − Ω
900
800
700
600
500
400
300
200
100
0
0
25
50
75
100
125
Clock Frequency − MHz
G082
Figure 98. Clock Buffer Input Impedance
0.1 mF
CLKP
Differential Sine-Wave
or PECL or LVDS
Clock Input
0.1 mF
CLKM
ADS612x
Figure 99. Differential Clock Driving Circuit
0.1 mF
CMOS Clock Input
CLKP
0.1 mF
CLKM
ADS612x
Figure 100. Single-Ended Clock Driving Circuit
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POWER DOWN MODES
ADS612X has four power-down modes – global power down, standby, output buffer disable and input clock
stopped. These modes can be set using the serial interface or using the parallel interface (pins SDATA and
PDN).
Table 16. Power Down Modes
POWER DOWN
MODES
PARALLEL INTERFACE
SERIAL INTERFACE
REGISTER BIT
(Table 5)
TOTAL POWER,
mW
WAKE-UP TIME
(to valid data)
<PDN OBUF>=0 and
<STBY>=0
417
-
High
<PDN OBUF>=0 and
<STBY>=1
72
Slow (50 µs)
High
Low
<PDN OBUF>=1 and
<STBY>=0
408
Fast (200 ns)
High
High
<PDN OBUF>=1 and
<STBY>=1
30
Slow (50 µs)
SDATA
PDN
Normal operation
Low
Low
Standby
Low
Output buffer disable
Global power down
Global Powerdown
In this mode, the A/D converter, internal references and the output buffers are powered down and the total power
dissipation reduces to about 30 mW. The output buffers are in high impedance state. The wake-up time from the
global power down to output data becoming valid in the normal mode is maximum 50 µs. Note that after coming
out of global power down, optimum performance will be achieved after the internal reference voltages have
stabilized (about 1 ms).
Standby
Here, only the A/D converter is powered down and the total power dissipation is about 72 mW. The wake-up time
from standby to output data becoming valid is maximum 50 µs.
Output Buffer Disable
The data output buffers can be disabled, reducing the total power to about 408 mW. With the buffers disabled,
the outputs are in high impedance state. The wake-up time from this mode to data becoming valid in normal
mode is maximum 500 ns in LVDS mode and 200 ns in CMOS mode.
Input Clock Stop
The converter enters this mode when the input clock frequency falls below 1 MSPS. The power dissipation is
about 120 mW, and the wake-up time from this mode to data becoming valid in normal mode is maximum 50 µs.
Power Supply Sequence
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated inside the device. Externally, they can be driven from separate supplies or from a single supply.
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DIGITAL OUTPUT INTERFACE
ADS612X outputs 12 data bits together with an output clock. The output interface are either parallel CMOS or
DDR LVDS voltage levels and can be selected using serial register bit <LVDS CMOS> or parallel pin SEN.
Parallel CMOS Interface
In the CMOS mode, the output buffer supply (DRVDD) can be operated over a wide range from 1.8 V to 3.3 V
(typical). Each data bit is output on separate pin as CMOS voltage level, every clock cycle.
For DRVDD ≥ 2.2 V, it is recommended to use the CMOS output clock (CLKOUT) to latch data in the receiving
chip. The rising edge of CLKOUT can be used to latch data in the receiver, even at the highest sampling speed
(125 MSPS). It is recommended to minimize the load capacitance seen by data and clock output pins by using
short traces to the receiver. Also, match the output data and clock traces to minimize the skew between them.
For DRVDD < 2.2 V, it is recommended to use external clock (for example, input clock delayed to get desired
setup/hold times).
Output Clock Position Programmability
There exists an option to shift (delay) the output clock position so that the setup time increases by 400 ps
(typical, with respect to the default timings specified). This may be useful if the receiver needs more setup time,
especially at high sampling frequencies. This can be programmed using the serial interface register bit
<CLKOUT_POSN> (see Table 6).
Output Buffer Strength Programmability
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of
sampling and degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is made
stronger. To minimize this, the ADS612X CMOS output buffers are designed with controlled drive strength to get
best SNR. The default drive strength also ensures wide data stable window for load capacitances upto 5 pF and
DRVDD supply voltage ≥ 2.2 V.
To ensure wide data stable window for load capacitance > 5 pF, there is an option to increase the drive strength
using the serial interface (<DRIVE STRENGTH>, see Table 12). Note that for DRVDD supply voltage < 2.2 V, it
is recommended to use maximum drive strength (for any value of load capacitance).
CMOS Mode Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal.
Digital current due to CMOS output switching = CL × DRVDD x (N x FAVG)
where CL = load capacitance, N × FAVG = average number of output bits switching
Figure 84 shows the current with various load capacitances across sampling frequencies at 2 MHz analog input
frequency.
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Pins
OVR
CLKOUT
D0
D1
CMOS
Output Buffers
D2
D3
D4
D5
D6
12 bit ADC data
D7
D8
D9
D10
D11
ADS612X
Figure 101. CMOS Output buffers
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DDR LVDS Interface
The LVDS interface works only with 3.3 V DRVDD supply. In this mode, the 12 data bits and the output clock are
available as LVDS (Low Voltage Differential Signal) levels. Two successive data bits are multiplexed and output
on each LVDS differential pair every clock cycle (DDR - Double Data Rate, see Figure 102 ). So, there are 7
LVDS output pairs for the 12 data bits and 1 LVDS output pair for the output clock.
LVDS Buffer Current Programmability
The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in a 350-mV
single-ended voltage swing (700-mVPP differential swing). The LVDS buffer currents can also be programmed to
2.5 mA, 4.5 mA, and 1.75 mA (register bits <LVDS CURRENT>, see Table 11). In addition, there is a current
double mode, where this current is doubled for the data and output clock buffers (register bits <CURRENT
DOUBLE>, see Table 11).
Pins
CLKOUTP
Output Clock
CLKOUTM
D0_D1_P
Data bits D0, D1
D0_D1_M
LVDS Buffers
D2_D3_P
Data bits D2, D3
D2_D3_M
D4_D5_P
Data bits D4, D5
D4_D5_M
12-Bit ADC Data
D6_D7_P
Data bits D6, D7
D6_D7_M
D8_D9_P
Data bits D8, D9
D8_D9_M
D10_D11_P
Data bits D10, D11
D10_D11_M
ADS612x
Figure 102. DDR LVDS Outputs
Even data bits D0, D2, D4, D6, D8, D10, and D12 are output at the rising edge of CLKOUTP and the odd data
bits D1, D3, D5, D7, D9, D11, and D13 are output at the falling edge of CLKOUTP. Both the rising and falling
edges of CLKOUTP must be used to capture all the 12 data bits (see Figure 103).
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CLKOUTM
CLKOUTP
D0_D1_P,
D0_D1_M
D0
D1
D0
D1
D2_D3_P,
D2_D3_M
D2
D3
D2
D3
D4_D5_P,
D4_D5_M
D4
D5
D4
D5
D6_D7_P,
D6_D7_M
D6
D7
D6
D7
D8_D9_P,
D8_D9_M
D8
D9
D8
D9
D10_D11_P,
D10_D11_M
D10
D11
D10
D11
Sample N
Sample N+1
Figure 103. DDR LVDS Interface
LVDS Buffer Internal Termination
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. The termination resistances available are – 300 Ω, 185 Ω, and 150 Ω (nominal with
±20% variation). Any combination of these three terminations can be programmed; the effective termination is
the parallel combination of the selected resistances. This results in eight effective terminations from open (no
termination) to 65 Ω.
The internal termination helps to absorb any reflections coming from the receiver end, improving the signal
integrity. With 100 Ω internal and 100 Ω external termination, the voltage swing at the receiver end is halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode. Figure 104 and Figure 105 compare the LVDS eye diagrams without and with internal termination (100 Ω).
With internal termination, the eye looks clean even with 10 pF load capacitance (from each outpin to ground).
The terminations is programmed using register bits <DATA TERM> and <CLKOUT TERM> (see Table 11).
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Figure 104. LVDS Eye Diagram - No Internal Termination
5-pF Load Capacitance
Blue Trace - Output Clock (CLKOUT)
Pink Trace - Output Data
Figure 105. LVDS Eye Diagram with 100-Ω Internal
Termination
10-pF Load Capacitance
Blue Trace - Output Clock (CLKOUT)
Pink Trace - Output Data
Output Data Format
Two output data formats are supported – 2s complement and offset binary. They can be selected using the
parallel control pin SEN or the serial interface register bit <DATA FORMAT> (see Table 8).
Output Timings
The following table lists the timings at lower sampling frequencies.
Table 17. Timing Characteristics at Lower Sampling Frequencies
Fs, MSPS
tsu DATA SETUP TIME, ns
MIN
TYP
MAX
th DATA HOLD TIME, ns
MIN
TYP
(1) (2)
tPDI CLOCK PROPAGATION DELAY, ns
MAX
MIN
TYP
MAX
5
6.5
7.9
CMOS INTERFACE, DRVDD = 2.5 V to 3.3 V
40
11.3
12.8
10
11.2
20
23
25
21
23
10
48
50
46
48
DDR LVDS INTERFACE, DRVDD = 3.3 V
(1)
(2)
54
40
10.2
10.8
0.7
1.7
4.3
5.8
7.3
20
22
23
0.7
1.7
4.5
6.5
8.5
10
47
48
0.7
1.7
4.5
6.5
8.5
Timing parameters are specified by design and characterization and not tested in production.
Timings are specified with default output buffer drive strength and CL= 5 pF
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BOARD DESIGN CONSIDERATIONS
Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital and clock sections of
the board are cleanly partitioned. See the EVM User Guide (SLWU028) for details on layout and grounding.
Supply Decoupling
As ADS612X already includes internal decoupling, minimal external decoupling can be used without loss in
performance. Note that decoupling capacitors can help to filter external power supply noise, so the optimum
number of capacitors would depend on the actual application. The decoupling capacitors should be placed very
close to the converter supply pins.
It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching
noise from sensitive analog circuitry. In case only a single 3.3-V supply is available, it should be routed first to
AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being
routed to DRVDD.
Exposed Thermal Pad
It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal
performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON
PCB Attachment (SLUA271).
Copyright © 2007–2008, Texas Instruments Incorporated
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55
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ADS6123, ADS6122
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low
frequency value.
Aperture Delay
The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling
occurs.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width)
to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential
sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate
The maximum sampling rate at which certified operation is given. All parametric testing is performed at this
sampling rate unless otherwise noted.
Minimum Conversion Rate
The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the
deviation of any single step from this ideal value, measured in units of LSBs
Integral Nonlinearity (INL)
The INL is the deviation of the ADC’s transfer function from a best fit line determined by a least squares curve fit
of that transfer function, measured in units of LSBs.
Gain Error
The gain error is the deviation of the ADC’s actual input full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
Offset Error
The offset error is the difference, given in number of LSBs, between the ADC’s actual average idle channel
output code and the ideal average idle channel output code. This quantity is often mapped into mV.
Temperature Drift
The temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree
Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter
across the TMIN to TMAX range by the difference TMAX–TMIN.
56
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ADS6125, ADS6124
ADS6123, ADS6122
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
Signal-to-Noise Ratio
SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc
and the first nine harmonics.
P
SNR + 10Log 10 s
PN
(4)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding dc.
Ps
SINAD + 10Log 10
PN ) PD
(5)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Effective Number of Bits (ENOB)
The ENOB is a measure of a converter’s performance as compared to the theoretical limit based on quantization
noise.
ENOB + SINAD * 1.76
6.02
(6)
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD).
P
THD + 10Log 10 s
PN
(7)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic).
SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion
IMD3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral
component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in units of dBc (dB to carrier) when the
absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the
fundamental is extrapolated to the converter’s full-scale range.
DC Power Supply Rejection Ratio (DC PSRR)
The DC PSSR is the ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is
typically given in units of mV/V.
Copyright © 2007–2008, Texas Instruments Incorporated
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SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR is the measure of rejection of variations in the supply voltage of the ADC. If ΔVSUP is the change in the
supply voltage and ΔVOUT is the resultant change in the ADC output code (referred to the input), then
DVOUT
(Expressed in dBc)
PSRR = 20Log 10
DVSUP
(8)
Common Mode Rejection Ratio (CMRR)
CMRR is the measure of rejection of variations in the input common-mode voltage of the ADC. If ΔVcm is the
change in the input common-mode voltage and ΔVOUT is the resultant change in the ADC output code (referred
to the input), then
DVOUT
(Expressed in dBc)
CMRR = 20Log10
DVCM
(9)
Voltage Overload Recovery
The number of clock cycles taken to recover to less than 1% error for a 6-dB overload on the analog inputs. A
6-dBFS sine wave at Nyquist frequency is used as the test stimulus.
58
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Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
REVISION HISTORY
Changes from Original (October 2007) to Revision A .................................................................................................... Page
•
•
•
Changed DDR LVDS output data sequence in Figure 1 ..................................................................................................... 11
Changed pin configuration (CMOS mode) information........................................................................................................ 21
Changed pin configuration (LVDS mode) information ......................................................................................................... 23
Copyright © 2007–2008, Texas Instruments Incorporated
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59
PACKAGE OPTION ADDENDUM
www.ti.com
26-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS6122IRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ6122
ADS6123IRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ6123
ADS6124IRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ6124
ADS6124IRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ6124
ADS6125IRHBR
ACTIVE
VQFN
RHB
32
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ6125
ADS6125IRHBT
ACTIVE
VQFN
RHB
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
AZ6125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Oct-2016
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADS6122IRHBT
VQFN
RHB
32
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
ADS6123IRHBT
VQFN
RHB
32
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
ADS6124IRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
ADS6124IRHBT
VQFN
RHB
32
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
ADS6125IRHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
ADS6125IRHBT
VQFN
RHB
32
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS6122IRHBT
VQFN
RHB
32
250
210.0
185.0
35.0
ADS6123IRHBT
VQFN
RHB
32
250
210.0
185.0
35.0
ADS6124IRHBR
VQFN
RHB
32
3000
350.0
350.0
43.0
ADS6124IRHBT
VQFN
RHB
32
250
210.0
185.0
35.0
ADS6125IRHBR
VQFN
RHB
32
3000
350.0
350.0
43.0
ADS6125IRHBT
VQFN
RHB
32
250
210.0
185.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
5 x 5, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
20.000
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
2X
3.5
SEE SIDE WALL
DETAIL
SYMM
33
32X
24
1
PIN 1 ID
(OPTIONAL)
32
0.3
0.2
0.1
0.05
C A B
C
25
SYMM
32X
0.5
0.3
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
( 0.2) TYP
VIA
8
17
(R0.05)
TYP
9
(1.475)
16
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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