Texas Instruments | 8-Bit Multiplying Digital-to-Analog Converters (Rev. D) | Datasheet | Texas Instruments 8-Bit Multiplying Digital-to-Analog Converters (Rev. D) Datasheet

Texas Instruments 8-Bit Multiplying Digital-to-Analog Converters (Rev. D) Datasheet
 SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
D Easily Interfaced to Microprocessors
D On-Chip Data Latches
D Monotonic Over the Entire A/D Conversion
D
D
D
OUT1
OUT2
GND
DB7
DB6
DB5
DB4
DB3
Range
Segmented High-Order Bits Ensure
Low-Glitch Output
Interchangeable With Analog Devices
AD7524, PMI PM-7524, and Micro Power
Systems MP7524
Fast Control Signaling for Digital
Signal-Processor Applications Including
Interface With TMS320
CMOS Technology
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
RFB
REF
VDD
WR
CS
DB0
DB1
DB2
FN PACKAGE
(TOP VIEW)
KEY PERFORMANCE SPECIFICATIONS
Resolution
Linearity error
Power dissipation at VDD = 5V
Setting time
Propagation delay time
1
OUT2
OUT1
NC
RFB
REF
D
D, N, OR PW PACKAGE
(TOP VIEW)
8 Bits
1/2LSB Max
5mW Max
100ns Max
80ns Max
GND
DB7
NC
DB6
DB5
description
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
VDD
WR
NC
CS
DB0
DB4
DB3
NC
DB2
DB1
The TLC7524C, TLC7524E, and TLC7524I are
CMOS, 8-bit, digital-to-analog converters (DACs)
designed for easy interface to most popular
microprocessors.
4
NC−No internal connection
The devices are 8-bit, multiplying DACs with input latches and load cycles similar to the write cycles of a random
access memory. Segmenting the high-order bits minimizes glitches during changes in the most significant bits,
which produce the highest glitch impulse. The devices provide accuracy to 1/2LSB without the need for thin-film
resistors or laser trimming, while dissipating less than 5mW typically.
Featuring operation from a 5V to 15V single supply, these devices interface easily to most microprocessor buses
or output ports. The 2- or 4-quadrant multiplying makes these devices an ideal choice for many
microprocessor-controlled gain-setting and signal-control applications.
The TLC7524C is characterized for operation from 0°C to 70°C. The TLC7524I is characterized for operation
from −25°C to +85°C. The TLC7524E is characterized for operation from − 40°C to +85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright  1998−2007, Texas Instruments Incorporated
!" # $%&" !# '%()$!" *!"&+
*%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"#
#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
"&#"0 !)) '!!&"&#+
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
functional block diagram
REF
R
15
2R
R
2R
R
2R
2R
2R
16
S-1
S-2
S-3
S-8
R
1
2
CS
WR
12
3
Data Latches
13
4
DB7
(MSB)
5
DB6
6
DB5
RFB
OUT1
OUT2
GND
11
DB0
(LSB)
Data Inputs
Terminal numbers shown are for the D or N package.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to 16.5V
Digital input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to VDD + 0.3V
Reference voltage, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25V
Peak digital input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA
Operating free-air temperature range, TA: TLC7524C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
TLC7524I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to +85°C
TLC7524E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Case temperature for 10 seconds, TC: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C
Lead temperature 1,6mm (1/16 inch) from case for 10 seconds: D, N, or PW package . . . . . . . . . . . +260°C
package/ordering information
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI website at www.ti.com.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
recommended operating conditions
Supply voltage, VDD
VDD = 5V
MIN NOM
MAX
VDD = 15V
MIN NOM
MAX
4.75
14.5
5
5.25
± 10
Reference voltage, Vref
High-level input voltage, VIH
15
2.4
V
0.8
40
CS hold time, th(CS)
V
V
13.5
Low-level input voltage, VIL
CS setup time, tsu(CS)
15.5
± 10
UNIT
1.5
V
40
ns
0
0
ns
Data bus input setup time, tsu(D)
25
25
ns
Data bus input hold time, th(D)
10
10
ns
Pulse duration, WR low, tw(WR)
40
40
TLC7524C
Operating free-air temperature, TA
ns
0
+70
0
+70
TLC7524I
−25
+85
−25
+85
TLC7524E
−40
+85
−40
+85
°C
C
electrical characteristics over recommended operating free-air temperature range, Vref = ±10V,
OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER
IIH
IIL
IIkg
TEST CONDITIONS
High-level input current
Low-level input current
Output leakage
current
MIN
VDD = 5V
TYP MAX
VI = VDD
VI = 0
10
10
µA
µA
−10
−10
OUT1
WR, CS at 0V,
± 400
± 200
OUT2
DB0−DB7 at VDD,
Vref = ± 10V
WR, CS at 0V,
± 400
± 200
Quiescent
DB0−DB7 at VIHmin or VILmax
1
2
mA
Standby
DB0−DB7 at 0V or VDD
500
500
µA
0.04
%FSR/%
Supply current
kSVS
Supply voltage sensitivity,
∆gain/∆VDD
∆VDD = ± 10%
Ci
Input capacitance,
DB0−DB7, WR, CS
VI = 0
nA
0.01
OUT2
DB0−DB7 at 0V,
WR, CS at 0V
OUT1
OUT2
DB0−DB7 at VDD,
0.16
0.005
5
OUT1
Output capacitance
UNIT
DB0−DB7 at 0V,
Vref = ± 10V
IDD
Co
VDD = 15V
TYP MAX
MIN
WR, CS at 0V
Reference input impedance
(REF to GND)
5
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
30
30
120
120
120
120
30
30
20
5
20
pF
pF
kΩ
3
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
operating characteristics over recommended operating free-air temperature range, Vref = ±10V,
OUT1 and OUT2 at GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 5V
MIN
TYP
MAX
VDD = 15V
TYP
MIN
MAX
UNIT
± 0.5
± 0.5
LSB
Linearity error
Gain error
See Note 1
± 2.5
± 2.5
LSB
Settling time (to 1/2 LSB)
See Note 2
100
100
ns
Propagation delay from digital input
to 90% of final analog output current
See Note 2
80
80
ns
Feedthrough at OUT1 or OUT2
Vref = ±10V (100kHz sinewave)
WR and CS at 0V, DB0−DB7 at 0V
0.5
0.5
%FSR
Temperature coefficient of gain
TA = +25°C to MAX
± 0.004
± 0.001
NOTES: 1. Gain error is measured using the internal feedback resistor. Nominal full-scale range (FSR) = Vref − 1LSB.
2. OUT1 load = 100Ω, Cext = 13pF, WR at 0V, CS at 0V, DB0 − DB7 at 0V to VDD or VDD to 0V.
operating sequence
tsu(CS)
th(CS)
CS
tw(WR)
WR
ÎÎÎ
ÎÎÎ
tsu(D)
DB0−DB7
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
th(D)
%FSR/°C
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
PRINCIPLES OF OPERATION
voltage-mode operation
It is possible to operate the current-multiplying DAC in these devices in a voltage mode. In the voltage mode,
a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the
reference voltage terminal. Figure 1 is an example of a current-multiplying DAC, which is operated in voltage
mode.
R
R
R
REF (Analog Output Voltage)
2R
2R
2R
0
2R
1
R
OUT1 (Fixed Input Voltage)
OUT2
Figure 1. Voltage Mode Operation
The relationship between the fixed-input voltage and the analog-output voltage is given by the following
equation:
VO = VI (D/256)
where
VO = analog output voltage
VI = fixed input voltage
D = digital input code converted to decimal
In voltage-mode operation, these devices meet the following specification:
PARAMETER
Linearity error at REF
TEST CONDITIONS
VDD = 5V,
OUT1 = 2.5V,
POST OFFICE BOX 655303
OUT2 at GND,
• DALLAS, TEXAS 75265
MIN
TA = +25°C
MAX
UNIT
1
LSB
5
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
PRINCIPLES OF OPERATION
The TLC7524C, TLC7524E, and TLC7524I are 8-bit multiplying DACs consisting of an inverted R-2R ladder,
analog switches, and data input latches. Binary-weighted currents are switched between the OUT1 and OUT2
bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. The high-order
bits are decoded. These decoded bits, through a modification in the R-2R ladder, control three equally-weighted
current sources. Most applications only require the addition of an external operational amplifier and a voltage
reference.
The equivalent circuit for all digital inputs low is seen in Figure 2. With all digital inputs low, the entire reference
current, Iref, is switched to OUT2. The current source I/256 represents the constant current flowing through the
termination resistor of the R-2R ladder, while the current source IIkg represents leakage currents to the
substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all
digital inputs high, the off-state switch capacitance (30pF maximum) appears at OUT2 and the on-state switch
capacitance (120pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown
in Figure 2. Analysis of the circuit for all digital inputs high is similar to Figure 2; however, in this case, Iref would
be switched to OUT1.
The DAC on these devices interfaces to a microprocessor through the data bus and the CS and WR control
signals. When CS and WR are both low, analog output on these devices responds to the data activity on the
DB0−DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects the
analog output. When either the CS signal or WR signal goes high, the data on the DB0−DB7 inputs are latched
until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless of the state
of the WR signal.
These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant or 4-quadrant multiplication are shown in Figure 3 and Figure 4. Table 1 and Table 2 summarize input
coding for unipolar and bipolar operation respectively.
RFB
R
OUT1
30 pF
IIkg
Iref
REF
OUT2
I/256
120 pF
IIkg
Figure 2. TLC7524 Equivalent Circuit With All Digital Inputs Low
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
PRINCIPLES OF OPERATION
VDD
Vref
RA = 2 kΩ
(see Note A)
RB
C (see Note B)
RFB
DB0−DB7
OUT1
−
OUT2
+
Output
CS
WR
GND
NOTES: A. RA and RB used only if gain adjustment is required.
B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent
ringing or oscillation.
Figure 3. Unipolar Operation (2-Quadrant Multiplication)
Vref
VDD
20 kΩ
RA = 2 kΩ
(see Note A)
RB
CS
WR
−
C (see Note B)
RFB
DB0−DB7
20 kΩ
Output
OUT1
−
OUT2
+
+
10 kΩ
5 kΩ
GND
NOTES: A. RA and RB used only if gain adjustment is required.
B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.
Figure 4. Bipolar Operation (4-Quadrant Operation)
Table 1. Unipolar Binary Code
DIGITAL INPUT
(see Note 3)
MSB
ANALOG OUTPUT
LSB
11111111
10000001
10000000
01111111
00000001
00000000
Table 2. Bipolar (Offset Binary) Code
DIGITAL INPUT
(see Note 4)
MSB
ANALOG OUTPUT
LSB
−Vref (255/256)
−Vref (129/256)
11111111
10000001
Vref (127/128)
Vref (1/128)
−Vref (128/256) = − Vref/2
−Vref (127/256)
10000000
0
01111111
−Vref (1/256)
0
00000001
−Vref (1/128)
−Vref (127/128)
00000000
−Vref
NOTE 3: LSB = 1/256 (Vref)
NOTE 4: LSB = 1/128 (Vref)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
PRINCIPLES OF OPERATION
microprocessor interfaces
D0−D7
Data Bus
Z−80A
DB0−DB7
WR
TLC7524
WR
OUT1
OUT2
CS
IORQ
Decode
Logic
Address Bus
A0−A15
Figure 5. TLC7524: Z-80A Interface
Data Bus
D0−D7
6800
DB0−DB7
φ2
WR
TLC7524
OUT1
OUT2
CS
VMA
A0−A15
Decode
Logic
Address Bus
Figure 6. TLC7524: 6800 Interface
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
PRINCIPLES OF OPERATION
microprocessor interfaces (continued)
A8−A15
Address Bus
8051
Decode
Logic
8-Bit
Latch
CS
WR
ALE
TLC7524
DB0−DB7
OUT1
OUT2
WR
AD0−AD7
Adress/Data Bus
Figure 7. TLC7524: 8051 Interface
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
Revision History
DATE
REV
6/07
D
PAGE
SECTION
DESCRIPTION
Front Page
—
Deleted Available Options table.
2
—
Inserted Package/Ordering information.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLC7524CD
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC7524C
TLC7524CDG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC7524C
TLC7524CDR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC7524C
TLC7524CFNR
ACTIVE
PLCC
FN
20
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 70
TLC7524C
TLC7524CN
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC7524CN
TLC7524CNE4
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC7524CN
TLC7524CNS
ACTIVE
SO
NS
16
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC7524
TLC7524CNSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC7524
TLC7524CPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P7524
TLC7524CPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P7524
TLC7524ED
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC7524E
TLC7524EDR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC7524E
TLC7524EDRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TLC7524E
TLC7524EN
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC7524EN
TLC7524ENE4
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC7524EN
TLC7524ID
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-25 to 85
TLC7524I
TLC7524IDG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-25 to 85
TLC7524I
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2018
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLC7524IDR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-25 to 85
TLC7524I
TLC7524IFN
ACTIVE
PLCC
FN
20
46
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-25 to 85
TLC7524I
TLC7524IN
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-25 to 85
TLC7524IN
TLC7524IPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-25 to 85
Y7524
TLC7524IPWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-25 to 85
Y7524
TLC7524IPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-25 to 85
Y7524
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2018
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLC7524CDR
Package Package Pins
Type Drawing
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
TLC7524CNSR
SO
NS
16
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
TLC7524CPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLC7524EDR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
TLC7524IDR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
TLC7524IPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC7524CDR
SOIC
D
16
2500
350.0
350.0
43.0
TLC7524CNSR
SO
NS
16
2000
367.0
367.0
38.0
TLC7524CPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
TLC7524EDR
SOIC
D
16
2500
350.0
350.0
43.0
TLC7524IDR
SOIC
D
16
2500
350.0
350.0
43.0
TLC7524IPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
FN0020A
PLCC - 4.57 mm max height
SCALE 1.300
PLASTIC CHIP CARRIER
B
.180 MAX
[4.57]
.350-.356
[8.89-9.04]
NOTE 3
A
3
1
(.008)
[0.2]
20
4
.020 MIN
[0.51]
18
PIN 1 ID
(OPTIONAL)
.350-.356
[8.89-9.04]
NOTE 3
.283-.339
[7.19-8.61]
14
8
9
13
.090-.120 TYP
[2.29-3.04]
20X .026-.032
[0.66-0.81]
C
SEATING PLANE
20X .013-.021
[0.33-0.53]
.007 [0.18]
C A B
.004 [0.1] C
16X .050
[1.27]
.385-.395
[9.78-10.03]
TYP
4215152/B 04/2017
NOTES:
1. All linear dimensions are in inches. Any dimensions in brackets are in millimeters. Any dimensions in parenthesis are for reference only.
Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension does not include mold protrusion. Maximum allowable mold protrusion .01 in [0.25 mm] per side.
4. Reference JEDEC registration MS-018.
www.ti.com
EXAMPLE BOARD LAYOUT
FN0020A
PLCC - 4.57 mm max height
PLASTIC CHIP CARRIER
SYMM
3
20X (.096 )
[2.45]
20X (.025 )
[0.64]
1
(R.002 ) TYP
[0.05]
20
4
18
SYMM
(.327)
[8.3]
16X (.050 )
[1.27]
14
8
9
13
(.327)
[8.3]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
EXPOSED METAL
.002 MAX
[0.05]
ALL AROUND
METAL
.002 MIN
[0.05]
ALL AROUND
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4215152/B 04/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
FN0020A
PLCC - 4.57 mm max height
PLASTIC CHIP CARRIER
SYMM
20X (.096 )
[2.45]
20X (.025 )
[0.64]
3
1
(R.002 ) TYP
[0.05]
20
4
18
SYMM
(.327)
[8.3]
16X (.050 )
[1.27]
14
8
9
13
(.327)
[8.3]
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4215152/B 04/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising