Texas Instruments | 18-Bit, 1.25MSPS Analog-to-Digital Converter (Rev. E) | Datasheet | Texas Instruments 18-Bit, 1.25MSPS Analog-to-Digital Converter (Rev. E) Datasheet

Texas Instruments 18-Bit, 1.25MSPS Analog-to-Digital Converter (Rev. E) Datasheet
 SBAS280E − JUNE 2003 − REVISED MAY 2007
FEATURES
D Data Rate: 1.25MSPS
D Signal-to-Noise Ratio: 93dB
D Total Harmonic Distortion: −101dB
D Spurious-Free Dynamic Range: 103dB
D Linear Phase with 615kHz Bandwidth
D Passband Ripple: ±0.0025dB
D Adjustable FIFO Output Buffer (ADS1626 only)
D Selectable On-Chip Reference
D Directly Connects to TMS320C6000 DSPs
D Adjustable Power Dissipation: 150 to 515mW
D Power Down Mode
D Supplies: Analog +5V
DESCRIPTION
The ADS1625 and ADS1626 are high-speed, high-precision,
delta-sigma analog-to-digital converters (ADCs) with 18-bit
resolution. The data rate is 1.25 mega samples per second
(MSPS), the bandwidth (−3dB) is 615kHz, and passband
ripple is less than ±0.0025dB (to 550kHz). Both devices offer
the same outstanding performance at these speeds with a
signal-to-noise ratio up to 93dB, total harmonic distortion
down to −101dB, and a spurious-free dynamic range up to
103dB. The ADS1626 includes an adjustable first-in, first-out
buffer (FIFO) for the output data.
The input signal is measured against a voltage reference that
can be generated on-chip or supplied externally. The digital
output data are provided over a simple parallel interface that
easily connects to digital signal processors (DSPs). An
out-of-range monitor reports when the input range has been
exceeded. The ADS1625/6 operate from a +5V analog
supply (AVDD) and +3V digital supply (DVDD). The digital
I/O supply (IOVDD) operates from +2.7 to +5.25V, enabling
the digital interface to support a range of logic families. The
analog power dissipation is set by an external resistor and
can be reduced when operating at slower speeds. A
power-down mode, activated by a digital I/O pin, shuts down
all circuitry. The ADS1625/6 are offered in a TQFP-64
package using TI PowerPAD technology.
Digital
+3V
Digital I/O +2.7V to +5.25V
APPLICATIONS
D Scientific Instruments
D Automated Test Equipment
D Data Acquisition
D Medical Imaging
D Vibration Analysis
VREFP VREFN VMID
The ADS1625 and ADS1626, along with their 16-bit,
5MSPS counterparts, the ADS1605 and ADS1606, are
well-suited for the demanding measurement requirements
of scientific instrumentation, automated test equipment,
data acquisition, and medical imaging.
RBIAS VCAP
AVDD DVDD IOVDD
PD
REFEN
RESET
CLK
CS
RD
DRDY
OTR
Reference and Bias Circuits
AINP
AINN
∆Σ
Modulator
I/O
Interface
Digital
Filter
ADS1626 Only
FIFO
ADS1625
ADS1626
DOUT[17:0]
FIFO_LEV[2:0]
AGND
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
Copyright  2003−2007, Texas Instruments Incorporated
! "# $ %& $ " '&(% ) )&%$
%"# $'%"%$ ' * #$ " +$ $&#$ $)) ,-
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SBAS280E − JUNE 2003 − REVISED MAY 2007
ORDERING INFORMATION
PRODUCT
PACKAGE−LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS1625
HTQFP−64
PAP
−40°C to +85°C
ADS1625I
ADS1626
HTQFP−64
PAP
−40°C to +85°C
ADS1626I
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS1625IPAPT
Tape and Reel, 250
ADS1625IPAPR
Tape and Reel, 1000
ADS1626IPAPT
Tape and Reel, 250
ADS1626IPAPR
Tape and Reel, 1000
(1) For the most current specifications and package information, refer to our web site at www.ti.com.
PRODUCT FAMILY
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
ADS1625/26
UNIT
AVDD to AGND
−0.3 to +6
V
DVDD to DGND
−0.3 to +3.6
V
IOVDD to DGND
−0.3 to +6
V
AGND to DGND
−0.3 to +0.3
V
Input Current
100, Momentary
mA
Input Current
10, Continuous
mA
Analog I/O to AGND
−0.3 to AVDD + 0.3
V
Digital I/O to DGND
−0.3 to IOVDD + 0.3
V
+150
°C
Operating Temperature Range
−40 to +105
°C
Storage Temperature Range
−60 to +150
°C
Maximum Junction Temperature
Lead Temperature (soldering, 10s)
+260
°C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
2
PRODUCT
RESOLUTION
DATA RATE
FIFO?
ADS1605
16 Bits
5.0MSPS
No
ADS1606
16 Bits
5.0MSPS
Yes
ADS1625
18 Bits
1.25MSPS
No
ADS1626
18 Bits
1.25MSPS
Yes
This integrated circuit can be damaged by ESD.
Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions.
Failure to observe proper handling and installation procedures can
cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.
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SBAS280E − JUNE 2003 − REVISED MAY 2007
ELECTRICAL CHARACTERISTICS
All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = 2.0V, FIFO disabled, and
RBIAS = 37kΩ, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Input
0dBFS
Differential input voltage (VIN)
(AINP − AINN)
−2dBFS
−6dBFS
−20dBFS
±1.467VREF
±1.165VREF
V
±0.735VREF
±0.147VREF
V
2.0
V
Common-mode input voltage (VCM)
(AINP + AINN) / 2
Absolute input voltage
(AINP or AINN with respect to AGND)
V
V
0dBFS
−0.1
4.7
V
−2dBFS input and smaller
0.1
4.2
V
Dynamic Specifications
Data rate
Signal-to-noise ratio (SNR)
Total harmonic distortion (THD)
1.25
fCLK
40MHz
Ǔ
MSPS
fIN = 10kHz, −2dBFS
fIN = 10kHz, −6dBFS
93
dB
90
dB
fIN = 10kHz, −20dBFS
fIN = 100kHz, −2dBFS
76
dB
93
dB
fIN = 100kHz, −6dBFS
fIN = 100kHz, −20dBFS
90
dB
76
dB
fIN = 500kHz, −2dBFS
fIN = 500kHz, −6dBFS
93
dB
90
dB
fIN = 500kHz, −20dBFS
fIN = 10kHz, −2dBFS
76
dB
70
−101
dB
fIN = 10kHz, −6dBFS
fIN = 10kHz, −20dBFS
−103
dB
−96
dB
fIN = 100kHz, −2dBFS
fIN = 100kHz, −6dBFS
−95
dB
−101
dB
fIN = 100kHz, −20dBFS
fIN = 500kHz, −2dBFS
−114
dB
−110
dB
−98
fIN = 500kHz, −6dBFS
fIN = 500kHz, −20dBFS
Signal-to-noise and distortion (SINAD)
ǒ
−90
dB
−96
dB
fIN = 10kHz, −2dBFS
fIN = 10kHz, −6dBFS
92
dB
89
dB
fIN = 10kHz, −20dBFS
fIN = 100kHz, −2dBFS
76
dB
91
dB
89
dB
76
dB
fIN = 500kHz, −2dBFS
fIN = 500kHz, −6dBFS
93
dB
90
dB
fIN = 500kHz, −20dBFS
76
dB
fIN = 100kHz, −6dBFS
fIN = 100kHz, −20dBFS
69
3
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SBAS280E − JUNE 2003 − REVISED MAY 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = 2.0V, FIFO disabled, and
RBIAS = 37kΩ, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Spurious-free dynamic range (SFDR)
Intermodulation distortion (IMD)
fIN = 10kHz, −2dBFS
fIN = 10kHz, −6dBFS
104
dB
106
dB
fIN = 10kHz, −20dBFS
fIN = 100kHz, −2dBFS
99
dB
97
dB
103
dB
102
dB
fIN = 500kHz, −2dBFS
fIN = 500kHz, −6dBFS
120
dB
113
dB
fIN = 500kHz, −20dBFS
99
dB
−98
dB
4
ns
fIN = 100kHz, −6dBFS
fIN = 100kHz, −20dBFS
92
f1 = 495kHz, −2dBFS
f2 = 505kHz, −2dBFS
Aperture delay
Digital Filter Characteristics
Passband
0
550
Passband ripple
575
−3.0dB attenuation
615
Passband transition
Stop band
0.7
Stop band attenuation
ǒ
fCLK
40MHz
fCLK
Ǔ
Ǔ
fCLK
40MHz
Ǔ
± 0.0025
kHz
dB
kHz
kHz
ǒ
Ǔ
39.3
f CLK
40MHz
Ǔ
MHz
dB
20.8
To ±0.001%
fCLK
40MHz
40MHz
72
Group delay
Settling time
ǒ
ǒ
−0.1dB attenuation
ǒ
ǒ
ǒ
36.8
40MHz
fCLK
Ǔ
Ǔ
40MHz
fCLK
µs
µs
Static Specifications
Resolution
No missing codes
Bits
1.5
LSB, rms
3.5
LSB
18
Input referred noise
Integral nonlinearity
18
−2.0dBFS signal
Bits
Differential nonlinearity
±0.5
LSB
Offset error
0.05
%FSR
1
ppmFSR/°C
Offset error drift
Gain error
0.25
%
Gain error drift
Excluding reference drift
10
ppm/°C
Common-mode rejection
at DC
75
dB
Power-supply rejection
at DC
65
dB
4
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SBAS280E − JUNE 2003 − REVISED MAY 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = 2.0V, FIFO disabled, and
RBIAS = 37kΩ, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage Reference(1)
VREF = (VREFP − VREFN)
VREFP
2.5
3.0
3.2
V
3.75
4.0
4.25
V
VREFN
0.75
1.0
1.25
V
VMID
2.3
2.5
2.8
VREF drift
Startup time
V
Internal reference (REFEN = low)
50
ppm/°C
Internal reference (REFEN = low)
15
ms
Clock Input
Frequency (fCLK)
1
Duty Cycle
fCLK = 40MHz
40
50
MHz
55
%
0.7 IOVDD
IOVDD
V
DGND
0.3 IOVDD
V
45
Digital Input/Output
VIH
VIL
VOH
VOL
IOH = 50µA
IOL = 50µA
Input leakage
DGND < VDIGIN < IOVDD
0.8 IOVDD
V
0.2 IOVDD
V
±10
µA
Power-Supply Requirements
AVDD
4.75
5.25
V
DVDD
2.7
3.3
V
IOVDD
2.7
AVDD current (IAVDD)
5.25
V
REFEN = low
110
135
mA
REFEN = high
85
105
mA
27
35
mA
3
5
mA
515
645
mW
DVDD current (IDVDD)
IOVDD current (IIOVDD)
IOVDD = 3V
Power dissipation
AVDD = 5V, DVDD = 3V, IOVDD = 3V,
REFEN = high
PD = low, CLK disabled
5
mW
Temperature Range
Specified
−40
+85
°C
Operating
−40
+105
°C
Storage
−60
+150
°C
Thermal Resistance, qJA
qJC
PowerPAD soldered to PCB with 2oz.
trace and copper pad.
25
°C/W
0.5
°C/W
(1) The specification limits for VREF, VREFP, VREFN, and VMID apply when using the internal or an external reference. The internal reference
voltages are bounded by the limits shown. When using an external reference, the limits indicate the allowable voltages that can be applied to the
reference pins.
5
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SBAS280E − JUNE 2003 − REVISED MAY 2007
DEFINITIONS
Absolute Input Voltage
Offset Error
Absolute input voltage, given in volts, is the voltage of each
analog input (AINN or AINP) with respect to AGND.
Offset Error, given in % of FSR, is the output reading when
the differential input is zero.
Aperture Delay
Offset Error Drift
Aperture delay is the delay between the rising edge of CLK
and the sampling of the input signal.
Common-Mode Input Voltage
Offset error drift, given in ppm of FSR/_C, is the drift over
temperature of the offset error. The offset error is specified
as the larger of the drift from ambient (TA = 25_C) to the
minimum or maximum operating temperatures.
Common-mode input voltage (VCM) is the average voltage
of the analog inputs:
Signal-to-Noise Ratio (SNR)
(AINP ) AINN)
2
Differential Input Voltage
Differential input voltage (VIN) is the voltage difference
between the analog inputs: (AINP−AINN).
Differential Nonlinearity (DNL)
DNL, given in least-significant bits (LSB) of the output
code, is the maximum deviation of the output code step
sizes from the ideal value of 1LSB.
Full-Scale Range (FSR)
FSR is the difference between the maximum and minimum
measurable input signals. For the ADS1625,
FSR = 2 × 1.467VREF.
Gain Error
Gain error, given in %, is the error of the full-scale input
signal with respect to the ideal value.
Gain Error Drift
Gain error drift, given in ppm/_C, is the drift over
temperature of the gain error. The gain error is specified as
the larger of the drift from ambient (TA = 25_C) to the
minimum or maximum operating temperatures.
Integral Nonlinearity (INL)
INL, given in least significant bits (LSB) of the output code,
is the maximum deviation of the output codes from a bestfit line.
Intermodulation Distortion (IMD)
IMD, given in dB, is measured while applying two input
signals of the same magnitude, but with slightly different
frequencies. It is calculated as the difference between the
rms amplitude of the input signal to the rms amplitude of
the peak spurious signal.
6
SNR, given in dB, is the ratio of the rms value of the input
signal to the sum of all the frequency components below
fCLK/2 (the Nyquist frequency) excluding the first six
harmonics of the input signal and the dc component.
Signal-to-Noise and Distortion (SINAD)
SINAD, given in dB, is the ratio of the rms value of the input
signal to the sum of all the frequency components below
fCLK/2 (the Nyquist frequency) including the harmonics of
the input signal but excluding the dc component.
Spurious Free Dynamic Range (SFDR)
SFDR, given in dB, is the difference between the rms
amplitude of the input signal to the rms amplitude of the
peak spurious signal.
Total Harmonic Distortion (THD)
THD, given in dB, is the ratio of the sum of the rms value
of the first six harmonics of the input signal to the rms value
of the input signal.
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SBAS280E − JUNE 2003 − REVISED MAY 2007
VREFP
VREFP
VMID
VREFN
VREFN
VCAP
AVDD
AGND
CLK
AGND
DGND
IOVDD
DVDD
DGND
NC
NC
PIN ASSIGNMENTS
64
63
62
61
60
59 58
57
56
55
54
53
52
51
50
49
AGND 1
48 FIFO_LEV[2] (ADS1626 Only)
ADS1625
ADS1626
AVDD 2
47 FIFO_LEV[1] (ADS1626 Only)
AGND 3
TQFP PACKAGE
(TOP VIEW)
46 FIFO_LEV[0] (ADS1626 Only)
AINN 4
45 NC
AINP 5
44 DOUT[17]
AGND 6
43 DOUT[16]
AVDD 7
42 DOUT[15]
RBIAS 8
41 DOUT[14]
PowerPAD
AGND 9
TM
40 DOUT[13]
AVDD 10
39 DOUT[12]
AGND 11
38 DOUT[11]
AVDD 12
37 DOUT[10]
REFEN 13
36 DOUT[9]
IOVDD 14
35 DOUT[8]
DGND 15
34 DOUT[7]
RESET
CS
RD
DRDY
DGND
27
28
29
30
31
32
DOUT[5]
DGND
26
DOUT[4]
25
DOUT[3]
24
DOUT[2]
22 23
DOUT[1]
21
DOUT[0]
20
DVDD
19
OTR
18
PD
33 DOUT[6]
17
DVDD
NC 16
Terminal Functions
TERMINAL
NAME
NO.
TYPE
AGND
1, 3, 6, 9, 11, 55, 57
Analog
Analog ground
AVDD
2, 7, 10, 12, 58
Analog
Analog supply
AINN
4
Analog input
Negative analog input
AINP
5
Analog input
Positive analog input
RBIAS
8
Analog
REFEN
13
Digital input: active low
DESCRIPTION
Terminal for external analog bias setting resistor
Internal reference enable. Internal pull-down resistor of 170kΩ to DGND.
NC
16, 45, 49, 50
PD
17
Digital input: active low
DVDD
18, 26, 52
Digital
Digital supply
DGND
15, 19, 25, 51, 54
Digital
Digital ground
RESET
20
Digital input: active low
Reset digital filter
CS
21
Digital input: active low
Chip select
RD
22
Digital input: active low
Read enable
OTR
23
Digital output
DRDY
Must be left unconnected
Power down all circuitry. Internal pull-up resistor of 170kΩ to DGND.
Active when analog inputs are out of range
24
Digital output: active low
DOUT [17:0]
27−44
Digital output
Data ready on falling edge
Data output. DOUT[17] is the MSB and DOUT[0] is the LSB.
FIFO_LEV[2:0]
46−48
Digital input
FIFO level (for the ADS1626 only). FIFO_LEV[2] is MSB.
NOTE: These terminals must be left unconnected on the ADS1625.
IOVDD
14, 53
Digital
CLK
56
Digital input
VCAP
59
Analog
Terminal for external bypass capacitor connection to internal bias voltage
60, 61
Analog
Negative reference voltage
62
Analog
Midpoint voltage
63, 64
Analog
Positive reference voltage
VREFN
VMID
VREFP
Digital I/O supply
Clock input
7
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SBAS280E − JUNE 2003 − REVISED MAY 2007
PARAMETER MEASUREMENT INFORMATION
t2
t1
CLK
t2
t3
t4
DRDY
t4
t6
t5
DOUT[17:0]
Data N
Data N + 2
Data N + 1
NOTE: CS and RD tied low.
Figure 1. Data Retrieval Timing (ADS1625, ADS1626 with FIFO Disabled)
RD, CS
t7
t8
DOUT[17:0]
Figure 2. DOUT Inactive/Active Timing (ADS1625, ADS1626 with FIFO Disabled)
TIMING REQUIREMENTS FOR FIGURE 1 AND FIGURE 2
SYMBOL
t1
1/t1
DESCRIPTION
CLK period (1/fCLK)
fCLK
TYP
MAX
UNIT
20
25
1000
ns
1
40
50
10
MHz
t2
CLK pulse width, high or low
t3
Rising edge of CLK to DRDY low
t4
DRDY pulse width high or low
t5
Falling edge of DRDY to data invalid
10
ns
t6
Falling edge of DRDY to data valid
15
ns
t7
Rising edge of RD and/or CS inactive (high) to DOUT high impedance
15
ns
t8
Falling edge of RD and/or CS active (low) to DOUT active.
15
ns
NOTE: DOUT[17:0] and DRDY load = 10pF.
8
MIN
ns
10
ns
16 t1
ns
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SBAS280E − JUNE 2003 − REVISED MAY 2007
CLK
t11
t9
RESET
t12
t 10
DRDY
t3
Settled
Data
DOUT[17:0]
NOTE: CS and RD tied low.
Figure 3. Reset Timing (ADS1625, ADS1626 with FIFO Disabled)
TIMING REQUIREMENTS FOR FIGURE 3
SYMBOL
DESCRIPTION
t3
Rising edge of CLK to DRDY low
t9
RESET pulse width
t10
Delay from RESET active (low) to DRDY forced high and DOUT forced low
t11
RESET rising edge to falling edge of CLK
t12
Delay from DOUT active to valid DOUT (settling to 0.001%)
MIN
TYP
MAX
10
UNIT
ns
50
ns
9
−5
ns
10
46
ns
DRDY
Cycles
NOTE: DOUT[17:0] and DRDY load = 10pF.
9
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SBAS280E − JUNE 2003 − REVISED MAY 2007
t1
t2
CLK
t2
t 13
t14
DRDY
t15
t16
CS(1)
t21
t 17
RD
t20
t18
DOUT[17:0]
t19
D1
DL(2)
D2
(1) CS may be tied low.
(2) The number of data readings (DL) is set by the FIFO level.
Figure 4. Data Retrieval Timing (ADS1626 with FIFO Enabled)
RD, CS
t7
t8
DOUT[17:0]
Figure 5. DOUT Inactive/Active Timing (ADS1626 with FIFO Enabled)
TIMING REQUIREMENTS FOR FIGURE 4 AND FIGURE 5
SYMBOL
DESCRIPTION
TYP
MAX
UNIT
25
1000
ns
t1
CLK period (1/fCLK)
20
t2
CLK pulse width, high or low
10
t7
Rising edge of RD and/or CS inactive (high) to DOUT high impedance
7
15
ns
t8
Falling edge of RD and/or CS active (low) to DOUT active.
7
15
ns
t13
Rising edge of CLK to DRDY high
t14
DRDY period
t15
DRDY positive pulse width
t16
RD high hold time after DRDY goes low
t17
CS low before RD goes low
ns
12
32 × FIFO Level(1)
1
ns
CLK
Cycles
CLK
Cycles
0
ns
0
ns
RD negative pulse width
10
ns
t19
RD positive pulse width
10
ns
t20
RD high before DRDY toggles
2
CLK
Cycles
t21
RD high before CS goes high
0
ns
t18
NOTE: DOUT[17:0] and DRDY load = 10pF.
(1) See FIFO section for more details.
10
MIN
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SBAS280E − JUNE 2003 − REVISED MAY 2007
CLK
t11
RESET
t9
t26
t25
DRDY
t23
RD
t24
Figure 6. Reset Timing (ADS1626 with FIFO Enabled)
TIMING REQUIREMENTS FOR FIGURE 6
SYMBOL
DESCRIPTION
MIN
t9
RESET pulse width
50
t11
RESET rising edge to falling edge of CLK
−5
TYP
MAX
UNIT
ns
10
ns
t23
RD pulse low after RESET goes high
32
CLK
Cycles
t24
RD pulse high before first DRDY pulse after RESET goes high
32
CLK
Cycles
t25
DRDY low after RESET goes low
t26
Delay from RESET high to valid DOUT (settling to 0.001%)
32 × (FIFO level + 1)
CLK
Cycles
See Table 4
DRDY
Cycles
11
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SBAS280E − JUNE 2003 − REVISED MAY 2007
TYPICAL CHARACTERISTICS
All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = 2.0V, and RBIAS = 37kΩ,
unless otherwise noted.
SPECTRAL RESPONSE
SPECTRAL RESPONSE
0
0
Amplitude (dB)
−40
−60
−80
−100
f IN = 10kHz, −6dBFS
SNR = 90dB
THD = −103dB
SFDR = 106dB
−20
−40
Amplitude (dB)
fIN = 10kHz, −2dBFS
SNR = 93dB
THD = −101dB
SFDR = 104dB
−20
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
125
250
375
500
625
0
125
Frequency (kHz)
SPECTRAL RESPONSE
625
−60
−80
−100
f IN = 100kHz, −6dBFS
SNR = 90dB
THD = −101dB
SFDR = 103dB
−20
−40
Amplitude (dB)
f IN = 100kHz, −2dBFS
SNR = 93dB
THD = −95dB
SFDR = 97dB
−40
Amplitude (dB)
500
0
−20
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
125
250
375
500
625
0
125
Frequency (kHz)
250
375
500
625
500
625
Frequency (kHz)
SPECTRAL RESPONSE
SPECTRAL RESPONSE
0
0
f IN = 500kHz, −2dBFS
SNR = 93dB
THD = −114dB
SFDR = 120dB
−40
f IN = 500kHz, −6dBFS
SNR = 90dB
THD = −110dB
SFDR = 113dB
−20
−40
Amplitude (dB)
−20
Amplitude (dB)
375
SPECTRAL RESPONSE
0
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
125
250
375
Frequency (kHz)
12
250
Frequency (kHz)
500
625
0
125
250
375
Frequency (kHz)
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = 2.0V, and RBIAS = 37kΩ,
unless otherwise noted.
NOISE HISTOGRAM
INTERMODULATION RESPONSE
0
9k
VIN = 0V
8k
7k
−40
Amplitude (dB)
Occurrences
f IN1 = 495kHz
f IN2 = 505kHz
IMD = −98dB
−20
6k
5k
4k
3k
−60
−80
−100
−120
1k
−140
0
−160
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
1
2
3
4
5
6
7
8
9
10
2k
400
450
SIGNAL−TO−NOISE RATIO, TOTAL HARMONIC DISTORTION,
AND SPURIOUS−FREE DYNAMIC RANGE
vs INPUT SIGNALAMPLITUDE
90
THD
VIN = −6dBFS
SNR (dB)
SNR, THD, and SFDR (dB)
VIN = −2dBFS
80
70
SNR
60
50
85
80
VIN = −20dBFS
40
30
75
fIN = 100kHz
20
10
−70
70
−60
−50
−40
−30
−20
−10
0
1k
10k
Input Signal Amplitude, VIN (dB)
130
−85
125
120
VIN = −20dBFS
SFDR (dB)
THD (dB)
−105
1M
SPURIOUS−FREE DYNAMIC RANGE
vs INPUT FREQUENCY
−80
VIN = −2dBFS
−100
100k
Input Frequency, f IN (Hz)
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
−95
600
95
SFDR
90
−90
550
SIGNAL−TO−NOISE RATIO
vs INPUT FREQUENCY
110
100
500
Frequency (MHz)
Output Code (LSB)
VIN = −6dBFS
115
105
−110
100
−115
95
−120
VIN = −6dBFS
110
VIN = −2dBFS
VIN = −20dBFS
90
1k
10k
100k
Input Frequency, fIN (Hz)
1M
1k
10k
100k
1M
Input Frequency, fIN (Hz)
13
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = 2.0V, and RBIAS = 37kΩ,
unless otherwise noted.
SIGNAL−TO−NOISE RATIO
vs INPUT COMMON−MODE VOLTAGE
TOTAL HARMONIC DISTORTION
vs INPUT COMMON−MODE VOLTAGE
−80
95
94
VIN = −2dBFS
93
−85
91
VIN = −6dBFS
90
−90
THD (dB)
SNR (dB)
92
89
VIN = −2dBFS
−95
−100
88
VIN = −6dBFS
87
−105
f IN = 100kHz
86
f IN = 100kHz
−110
85
1.5
1.7
110
1.9
2.1
2.3
2.5
2.7
2.9
1.5
1.9
2.1
2.3
2.5
2.7
Input Common−Mode Voltage, VCM (V)
SPURIOUS−FREE DYNAMIC RANGE
vs INPUT COMMON−MODE VOLTAGE
SIGNAL−TO−NOISE RATIO
vs CLK FREQUENCY
2.9
92
VIN = −6dBFS
105
1.7
Input Common−Mode Voltage, VCM (V)
RBIAS = 30kΩ
90
95
90
RBIAS = 37kΩ
88
VIN = −2dBFS
SNR (dB)
SFDR (dB)
100
85
RBIAS = 45kΩ
83
RBIAS = 50kΩ
84
80
RBIAS = 60kΩ
75
fIN = 100kHz
70
82
fIN = 100kHz, −6dBFS
80
65
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
10
15
20
Input Common−Mode Voltage, VCM (V)
TOTAL HARMONIC DISTORTION
vs CLK FREQUENCY
35
40
45
50
55
60
110
fIN = 100kHz, −6dBFS
RBIAS = 60kΩ
−80
105
RBIAS = 30kΩ
RBIAS = 50kΩ
100
−85
SFDR (dB)
THD (dB)
30
SPURIOUS−FREE DYNAMIC RANGE
vs CLK FREQUENCY
−75
R BIAS = 45kΩ
−90
RBIAS = 37kΩ
−95
95
RBIAS = 45kΩ
90
RBIAS = 37kΩ
85
RBIAS = 50kΩ
RBIAS = 30kΩ
−100
80
−105
fIN = 100kHz, −6dBFS
RBIAS = 60kΩ
75
10
15
20
25
30
35
40
45
CLK Frequency, fCLK (MHz)
14
25
CLK Frequency, fCLK (MHz)
50
55
60
10
15
20
25
30
35
40
45
CLK Frequency, fCLK (MHz)
50
55
60
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = 2.0V, and RBIAS = 37kΩ,
unless otherwise noted.
SIGNAL−TO−NOISE RATIO
vs TEMPERATURE
TOTAL HARMONIC DISTORTION
vs TEMPERATURE
−91
100
−93
VIN = −2dBFS
95
THD (dB)
90
SNR (dB)
VIN = −2dBFS
−95
VIN = −6dBFS
85
80
−97
VIN = −20dBFS
−99
−101
VIN = −20dBFS
75
VIN = −6dBFS
−103
fIN = 100kHz
70
−40
fIN = 100kHz
−15
10
35
60
−105
−40
85
−15
10
35
60
Temperature (_ C)
Temperature (_C)
SPURIOUS−FREE DYNAMIC RANGE
vs TEMPERATURE
POWER−SUPPLY CURRENT
vs TEMPERATURE
106
85
120
VIN = −6dBFS
IAVDD (REFEN = Low)
104
100
IAVDD (REFEN = High)
VIN = −20dBFS
Current (mA)
SFDR (dB)
102
100
98
VIN = −2dBFS
96
80
60
20
94
fIN = 100kHz
92
−40
−15
10
35
60
IDVDD + I IOVDD
40
RBIAS = 37kΩ
fCLK = 40MHz
0
−40
85
−15
Temperature (_C)
10
35
60
85
Temperature (_ C)
SUPPLY CURRENT vs CLK FREQUENCY
ANALOG SUPPLY CURRENT vs RBIAS
125
140
AVDD = 5V, DVDD = IOVDD = 3V, REFEN = High
130
Analog Current, IAVDD (mA)
105
Supply Current (mA)
DVDD = IOVDD = 3V
IAVDD (RBIAS = 37kΩ)
85
65
I AVDD (RBIAS = 60kΩ)
45
I DVDD + IIOVDD
25
120
110
100
REFEN = Low
90
80
70
REFEN = High
60
5
fCLK = 40MHz
50
5
15
25
35
45
CLK Frequency, fCLK (MHz)
55
65
30
35
40
45
50
55
60
RBIAS (kΩ)
15
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = 2.0V, and RBIAS = 37kΩ,
unless otherwise noted.
INTEGRAL NONLINEARITY
DIFFERENTIAL NONLINEARITY
4
3
0.5
fIN = 100Hz, −2dBFS
0.4
fIN = 100Hz, −2dBFS
0.3
0.2
DNL (LSB)
INL (LSB)
2
1
0
−1
0
−0.1
−0.2
−2
−0.3
−3
−0.4
−4
−100k −80k −60k −40k −20k
0
20k
40k 60k
Output Code (LSB)
16
0.1
80k 100k
−0.5
−100k −80k −60k −40k −20k
0
20k
40k 60k
Output Code (LSB)
80k 100k
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
OVERVIEW
The ADS1625 and ADS1626 are high-performance
delta-sigma ADCs with a default oversampling ratio of 32.
The modulator uses an inherently stable 2-1-1 pipelined
delta-sigma
modulator architecture incorporating
proprietary circuitry that allows for very linear high-speed
operation. The modulator samples the input signal at
40MSPS (when fCLK = 40MHz). A low-ripple, linear-phase
digital filter decimates the modulator output to provide data
output word rates of 1.25MSPS with a signal passband out
to 615kHz.
Conceptually, the modulator and digital filter measure the
differential input signal, VIN = (AINP – AINN), against the
scaled differential reference, VREF = (VREFP – VREFN),
as shown in Figure 7. The voltage reference can either be
generated internally or supplied externally. An 18-bit parallel data bus, designed for direct connection to DSPs, outputs the data. A separate power supply for the I/O allows
flexibility for interfacing to different logic families. Out-ofrange conditions are indicated with a dedicated digital output pin. Analog power dissipation is controlled using an external resistor. This allows reduced dissipation when
operating at slower speeds. When not in use, power consumption can be dramatically reduced using the PD pin.
The ADS1626 incorporates an adjustable FIFO for the output data. The level of the FIFO is set by the FIFO_LEV[2:0]
pins. Other than the FIFO, the ADS1625 and ADS1626 are
identical, and together are referred to as the ADS1625/6.
ANALOG INPUTS (AINP, AINN)
The ADS1625/6 measures the differential signal,
VIN = (AINP − AINN), against the differential reference,
VREF = (VREFP – VREFN). The reference is scaled
internally so that the full-scale differential input voltage is
1.467VREF. That is, the most positive measurable
differential input is 1.467VREF, which produces the most
VREFP VREFN
positive digital output code of 7FFFh. Likewise, the most
negative measurable differential input is –1.467VREF, which
produces the most negative digital output code of 8000h.
The ADS1625/6 supports a very wide range of input
signals. For VREF = 3V, the full scale input voltages are
±4.4V. Having such a wide input range makes out-of-range
signals unlikely. However, should an out-of-range signal
occur, digital output OTR will go high.
To achieve the highest analog performance, it is
recommended that the inputs be limited to ±1.165VREF
(−2dBFS). For VREF = 3V, the corresponding
recommended input range is ±3.78V.
The analog inputs must be driven with a differential signal
to achieve optimum performance. The recommended
common-mode
voltage
of
the
input
signal,
V CM + AINP ) AINN, is 2.0V. For signals larger than
2
−2dBFS, the input common-mode voltage needs to be
raised in order to meet the absolute input voltage
specifications. The Typical Characteristics show how
performance varies with input common-mode voltage.
In addition to the differential and common-mode input
voltages, the absolute input voltage is also important. This
is the voltage on either input (AINP or AINN) with respect
to AGND. The range for this voltage is:
−0.1V < (AINN or AINP) < 4.6V.
If either input is taken below –0.1V, ESD protection diodes
on the inputs will turn on. Exceeding 4.6V on either input
will result in degradation in the linearity performance. ESD
protection diodes will also turn on if the inputs are taken
above AVDD (+5V).
For signals below –2dBFS, the recommended absolute
input voltage is:
0.1V < (AINN or AINP) < 4.2V
Keeping the inputs within this range provides for optimum
performance.
IOVDD
Σ
VREF
1.467
1.467VREF
OTR
AINP
AINN
Σ
VIN
Σ∆
Modulator
Digital
Filter
Parallel
Interface
ADS1626 Only
FIFO
DOUT[17:0]
FIFO_LEV[2:0]
Figure 7. Conceptual Block Diagram
17
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
INPUT CIRCUITRY
The ADS1625/6 uses switched-capacitor circuitry to
measure the input voltage. Internal capacitors are charged
by the inputs and then discharged internally with this cycle
repeating at the frequency of CLK. Figure 8 shows a
conceptual diagram of these circuits. Switches S2 represent
the net effect of the modulator circuitry in discharging the
sampling capacitors, the actual implementation is different.
The timing for switches S1 and S2 is shown in Figure 9.
S1
ADS1625
ADS1626
AINP
input to AGND, improve linearity and should be placed as
close to the pins as possible. Place the drivers close to the
inputs and use good capacitor bypass techniques on their
supplies; usually a smaller high-quality ceramic capacitor
in parallel with a larger capacitor. Keep the resistances
used in the driver circuits low—thermal noise in the driver
circuits degrades the overall noise performance. When the
signal can be ac-coupled to the ADS1625/6 inputs, a
simple RC filter can set the input common-mode voltage.
The ADS1625/6 is a high-speed, high-performance ADC.
Special care must be taken when selecting the test
equipment and setup used with this device. Pay particular
attention to the signal sources to ensure they do not limit
performance when measuring the ADS1625/6.
S2
10pF
8pF
392Ω
VMID
−
S1
V IN
392Ω
40pF
392Ω
OPA2822
2
0.01µ F
AINN
S2
10pF
8pF
VCM (1)
AINP
100pF
392Ω
1µ F
1kΩ
(2 )
392Ω
VMID
V CM (1 )
AGND
VIN
Figure 8. Conceptual Diagram of Internal
Circuitry Connected to the Analog Inputs
49.9Ω
(2)
392Ω
40pF
392Ω
OPA2822
100pF(3)
AD S162 5
AD S162 6
(2 )
1kΩ
2
0.01µ F
49.9Ω
AINN
(2)
V CM (1 )
100pF
392Ω
1µ F
AGND
t SAMPLE = 1/f CLK
(1) Recommended VC M = 2.0V.
(2) Optional ac−coupling circuit provides common−mode input voltage.
(3) Increase to 390pF when f IN ≤ 100kHz for improved SNR and THD.
On
S1
Off
On
S2
Off
Figure 10. Recommended Driver Circuit Using the
OPA2822
Figure 9. Timing for the Switches in Figure 2
22pF
24.9Ω
AINP
DRIVING THE INPUTS
392Ω
392Ω
The external circuits driving the ADS1625/6 inputs must
be able to handle the load presented by the switching
capacitors within the ADS1625/6. Input switches S1 in
Figure 9 are closed approximately of the
sampling period, tsample, allowing only ≈12ns for the
internal capacitors to be charged by the inputs, when
fCLK = 40MHz.
Figure 10 and Figure 11 show the recommended circuits
when using single-ended or differential op amps,
respectively. The analog inputs must be driven
differentially to achieve optimum performance. The
external capacitors, between the inputs and from each
18
100pF
−VIN
VCM
ADS1625
THS4503
100pF
+VIN
392Ω
392Ω
ADS1626
24.9Ω
AINN
100pF
22pF
Figure 11. Recommended Driver Circuits Using
the THS4503 Differential Amplifier
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
REFERENCE INPUTS (VREFN, VREFP, VMID)
The ADS1625 can operate from an internal or external
voltage reference. In either case, reference voltage VREF is
set by the differential voltage between VREFN and VREFP:
VREF = (VREFP – VREFN). VREFP and VREFN each use
two pins, which should be shorted together. VMID equals
approximately 2.5V and is used by the modulator. VCAP
connects to an internal node, and must also be bypassed
with an external capacitor. For the best analog performance,
it is recommended that an external reference voltage (VREF)
of 3.0V be used.
and VREFN = 1V. The external circuitry must be capable
of providing both a dc and a transient current. Figure 13
shows a simplified diagram of the internal circuitry of the
reference when the internal reference is disabled. As with
the input circuitry, switches S1 and S2 open and close as
shown in Figure 9.
ADS1625
ADS1626
S1
VREFP
VREFP
To use the internal reference, set the REFEN pin low. This
activates the internal circuitry that generates the reference
voltages. The internal reference voltages are applied to
the pins. Good bypassing of the reference pins is critical
to achieve optimum performance and is done by placing
the bypass capacitors as close to the pins as possible.
Figure 12 shows the recommended bypass capacitor
values. Use high quality ceramic capacitors for the smaller
values. Avoid loading the internal reference with external
circuitry. If the ADS1625/6 internal reference is to be used
by other circuitry, buffer the reference voltages to prevent
directly loading the reference pins.
ADS1625
ADS1626
10µF
0.1µF
VREFN
VREFN
50pF
S1
Figure 13. Conceptual Internal Circuitry for the
Reference When REFEN = High
Figure 14 shows the recommended circuitry for driving
these reference inputs. Keep the resistances used in the
buffer circuits low to prevent excessive thermal noise from
degrading performance. Layout of these circuits is critical;
make sure to follow good high-speed layout practices.
Place the buffers, and especially the bypass capacitors, as
close to the pins as possible. VCAP is unaffected by the
setting on REFEN and must be bypassed when using the
internal or an external reference.
VREFP
VREFP
392Ω
22µF
22µF
S2
300Ω
INTERNAL REFERENCE (REFEN = LOW)
0.001µ F
ADS1625
ADS1626
VMID
0.1µF
10µF
0.1µF
VREFP
VREFP
OPA2822
10µ F
4V
22µF
0.1µ F
392Ω
VREFN
VREFN
10µF
0.001µ F
22 µ F
22 µ F
0.1 µ F
0.1µF
VCAP
0.1µF
VMID
OPA2822
10 µ F
2.5V
0.1µ F
392Ω
AGND
22 µ F
0.001 µ F
Figure 12. Reference Bypassing When Using the
Internal Reference
VREFN
VREFN
OPA2822
1V
10 µ F
0.1µ F
EXTERNAL REFERENCE (REFEN = HIGH)
To use an external reference, set the REFEN pin high. This
deactivates the internal generators for VREFP, VREFN
and VMID, and saves approximately 25mA of current on
the analog supply (AVDD). The voltages applied to these
pins must be within the values specified in the Electrical
Characteristics table. Typically VREFP = 4V, VMID = 2.5V
VCAP
0.1µ F
AGND
Figure 14. Recommended Buffer Circuit When
Using an External Reference
19
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SBAS280E − JUNE 2003 − REVISED MAY 2007
CLOCK INPUT (CLK)
Table 2. Output Code Versus Input Signal
The ADS1625/6 requires an external clock signal to be
applied to the CLK input pin. The sampling of the
modulator is controlled by this clock signal. As with any
high-speed data converter, a high quality clock is essential
for optimum performance. Crystal clock oscillators are the
recommended CLK source; other sources, such as
frequency synthesizers, are usually not adequate. Make
sure to avoid excess ringing on the CLK input; keeping the
trace as short as possible will help.
Measuring high-frequency, large-amplitude signals
requires tight control of clock jitter. The uncertainty during
sampling of the input from clock jitter limits the maximum
achievable SNR. This effect becomes more pronounced
with higher frequency and larger magnitude inputs.
Fortunately, the ADS1625/6 oversampling topology
reduces clock jitter sensitivity over that of Nyquist rate
converters like pipeline and successive approximation
converters by a factor of √32.
In order to not limit the ADS1625/6 SNR performance,
keep the jitter on the clock source below the values shown
in Table 1. When measuring lower frequency and lower
amplitude inputs, more CLK jitter can be tolerated. In
determining the allowable clock source jitter, select the
worst-case input (highest frequency, largest amplitude)
that will be seen in the application.
INPUT SIGNAL
(INP – INN)
IDEAL OUTPUT
CODE(1)
OTR
≥ +1.467VREF (> 0dB)(2)
1FFFFh
1
≥ +1.467VREF (0dB)
1FF57h
0
+1.467V REF
00001h
0
2 17 * 1
0
00000h
0
−1.467V REF
3FFFFh
0
ǒ2 2 * 1 Ǔ
200A8h
0
ǒ2 2 * 1Ǔ (2)
20000h
1
2 17
*1
v −1.467V REF
v −1.467V REF
17
17
17
17
(1) Excludes effects of noise, INL, offset and gain errors.
(2) Large step inputs.
OUT-OF-RANGE INDICATION (OTR)
If the output code on DOUT[17:0] exceeds the positive or
negative full-scale, the out-of-range digital output OTR will
go high on the falling edge of DRDY. When the output code
returns within the full-scale range, OTR returns low on the
falling edge of DRDY.
DATA RETRIEVAL
Table 1. Maximum Allowable Clock Source Jitter
for Different Input Signal Frequencies and
Amplitude
MAXIMUM
FREQUENCY
MAXIMUM
AMPLITUDE
MAXIMUM
ALLOWABLE
CLOCK SOURCE
JITTER (RMS)
500kHz
−2dB
7ps
500kHz
−20dB
50ps
100kHz
−2dB
35ps
100kHz
−20dB
285ps
INPUT SIGNAL
Data retrieval is controlled through a simple parallel
interface. The falling edge of the DRDY output indicates
new data are available. To activate the output bus, both CS
and RD must be low, as shown in Table 3. On the
ADS1625, both of these signals can be tied low. On the
ADS1626 with FIFO enabled, only CS can be tied low
because RD must toggle to operate the FIFO. See the
FIFO section for more details. Make sure the DOUT bus
does not drive heavy loads (> 20pF), as this will degrade
performance. Use an external buffer when driving an edge
connector or cables.
Table 3. Truth Table for CS and RD
DATA FORMAT
The 18-bit output data is in binary two’s complement format,
as shown in Table 2. Under normal operation, the output
codes range between 200A8h to 1FF57h. Signals less than
−1.467VREF will clip at 200A8h and likewise, signals greater
than 1.467VREF will clip at 1FF57h. For large step changes
on the inputs, the output clips at the positive full-scale value
of 1FFFFh (positive transients) or the negative full-scale
value of 20000h (negative transients).
20
CS
RD
DOUT[17:0]
0
0
Active
0
1
High impedance
1
0
High impedance
1
1
High impedance
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SBAS280E − JUNE 2003 − REVISED MAY 2007
RESETTING THE ADS1625
RESETTING THE ADS1626
The ADS1625 and ADS1626 with FIFO disabled are
asynchronously reset when the RESET pin is taken low.
During reset, all of the digital circuits are cleared,
DOUT[17:0] are forced low, and DRDY forced high. It is
recommended that the RESET pin be released on the
falling edge of CLK. Afterwards, DRDY goes low on the
second rising edge of CLK. Allow 46 DRDY cycles for the
digital filter to settle before retrieving data. See Figure 3 for
the timing specifications.
The ADS1626 with the FIFO enabled requires a different
reset sequence than the ADS1625, as shown in Figure 16.
Ignore any DRDY toggles that occur while RESET is low.
Release RESET on the rising edge of CLK, then
afterwards toggle RD to complete the reset sequence.
Reset can be used to synchronize multiple ADS1625s. All
devices to be synchronized must use a common CLK
input. With the CLK inputs running, pulse RESET on the
falling edge of CLK, as shown in Figure 15. Afterwards, the
converters will be converting synchronously with the
DRDY
outputs
updating
simultaneously.
After
synchronization, allow 46 DRDY cycles (t12) for output
data to fully settle.
Clock
RESET
CLK
DRDY
DOUT[17:0]
DRDY1
DOUT[17:0]1
ADS16252
RESET
CLK
DRDY
DOUT[17:0]
Ignore
t26
DRDY
RD
Toggle RD to complete reset sequence
After resetting, the settling time for the ADS1626 is 46 CLK
cycles, regardless of the FIFO level. Therefore, for higher
FIFO levels, it takes fewer DRDY cycles to settle because
the DRDY period is longer. Table 4 shows the number of
DRDY cycles required to settle for each FIFO level.
DRDY2
DOUT[17:0]2
CLK
RESET
RESET
Figure 16. Resetting the ADS1626 with the FIFO
Enabled
ADS16251
RESET
CLK
t12
DRDY1
Settled
Data
DOUT[17:0]1
Table 4. ADS1626 Reset Settling
FIFO LEVEL
FILTER SETTLING TIME AFTER RESET
(t26 in units of DRDY cycles )
2
23
4
12
6
8
8
6
10
5
12
4
14
4
DRDY2
Settled
Data
DOUT[17:0]2
Synchronized
Figure 15. Synchronizing Multiple Converters
21
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
SETTLING TIME
IMPULSE RESPONSE
The settling time is an important consideration when
measuring signals with large steps or when using a
multiplexer in front of the analog inputs. The ADS1625/6
digital filter requires time for an instantaneous change in
signal level to propagate to the output.
Figure 18 plots the normalized response for an input applied
at t = 0. The X-axis units of time are DRDY cycles. As shown
in Figure 18, the peak of the impulse takes 26 DRDY cycles
to propagate to the output. For fCLK = 40MHz, a DRDY cycle
is 0.8µs in duration and the propagation time (or group delay)
is 26 × 0.8µs = 20.8µs.
Figure 17 shows the settling error as a function of time for a
full-scale signal step applied at t = 0. This figure uses DRDY
cycles for the time scale (X-axis). After 46 DRDY cycles, the
settling error drops below 0.001%. For fCLK = 40MHz, this
corresponds to a settling time of 36.8µs.
101
Settling Error (%)
0.8
0.6
0.4
0.2
0
−0.2
−0.4
100
0
10
20
30
40
Time (DRDY cycles)
10−1
Figure 18. Impulse Response
10−2
10−3
10−4
25
30
35
40
Settling Time (DRDY cycles)
Figure 17. Settling Time
22
1.0
Normalized Response
Be sure to allow the filter time to settle after applying a large
step in the input signal, switching the channel on a
multiplexer placed in front of the inputs, resetting the
ADS1625/6, or exiting the power-down mode.
45
50
50
60
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
FREQUENCY RESPONSE
0.0025
0.0015
0.0010
0.0005
0
−0.0005
−0.0010
Figure 20 shows the passband ripple from dc to 550kHz
(fCLK = 40MHz). Figure 21 shows a closer view of the
passband transition by plotting the response from 500kHz
to 640kHz (fCLK = 40MHz).
20
−0.0015
−0.0020
−0.0025
0
300
400
500
600
1
0
−1
−2
−3
−4
fC LK = 40MHz
−5
−20
Magnitude (dB)
200
Figure 20. Passband Ripple
f CLK = 40MHz
0
100
Frequency (kHz)
Magnitude (dB)
The overall frequency response repeats at multiples of the
CLK frequency. To help illustrate this, Figure 22 shows the
response out to 120MHz (fCLK = 40MHz). Notice how the
passband response repeats at 40MHz, 80MHz and
120MHz; it is important to consider this when there is
high-frequency noise present with the signal. The
modulator bandwidth extends to 100MHz. High-frequency
noise around 40MHz and 80MHz will not be attenuated by
either the modulator or the digital filter. This noise will alias
back in-band and reduce the overall SNR performance
unless it is filtered out prior to the ADS1625/6. To prevent
this, place an anti-alias filter in front of the ADS1625/6 that
rolls off before 39MHz.
fCLK = 40MHz
0.0020
Magnitude (dB)
The linear phase FIR digital filter sets the overall frequency
response. Figure 19 shows the frequency response from dc
to 20MHz for fCLK = 40MHz. The frequency response of the
ADS1625/6 filter scales directly with CLK frequency. For
example, if the CLK frequency is decreased by half (to
20MHz), the values on the X-axis in Figure 19 would need to
be scaled by half, with the span becoming dc to 10MHz.
−6
−40
500
520
540
560
580
600
620
640
Frequency (kHz)
−60
−80
Figure 21. Passband Transition
−100
−120
−140
2
4
6
8
10
12
14
16
18
20
20
Frequency (MHz)
Figure 19. Frequency Response.
fCL K = 40MHz
0
−20
Magnitude (dB)
0
−40
−60
−80
−100
−120
−140
0
20
40
60
80
100
120
Frequency (MHz)
Figure 22. Frequency Response Out to 120MHz
23
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
FIFO (ADS1626 ONLY)
The ADS1626 includes an adjustable level first-in first-out
buffer (FIFO) for the output data. The FIFO allows data to
be temporarily stored within the ADS1626 to provide more
flexibility for the host controller when retrieving data. Pins
FIFO_LEV[2:0] set the level or depth of the FIFO. Note that
these pins must be left unconnected on the ADS1625. The
FIFO is enabled by setting at least one of the FIFO_LEV
inputs high. Table 5 shows the corresponding FIFO level
and DRDY period for the different combinations of
FIFO_LEV[2:0] settings. For the best performance when
using the FIFO, it is recommended to:
1.
2.
3.
4.
Set IOVDD = 3V.
Synchronize data retrieval with CLK.
Minimize loading on outputs DOUT[17:0].
Ensure rise and fall times on CLK and RD are 1ns or
longer.
Table 5. FIFO Buffer Level Settings for the
ADS1626
FIFO_LEV[2:0]
FIFO BUFFER LEVEL
DRDY PERIOD
000
0: disabled,
operates like ADS1625
32/fCLK
001
2
010
4
64/fCLK
128/fCLK
011
6
192/fCLK
256/fCLK
100
8
101
10
110
12
320/fCLK
384/fCLK
111
14
448/fCLK
FIFO Operation
The ADS1626 FIFO collects the number of output
readings set by the level corresponding to the
FIFO_LEV[2:0] setting. When the specified level is
reached, DRDY is pulsed high, indicating the data in the
FIFO are ready to be read. The DRDY period is a function
of the FIFO level, as shown in Table 5. To read the data,
make sure CS is low (it is acceptable to tie it low) and then
take RD low. The first, or oldest, data will be presented on
the data output pins. After reading this data, advance to the
next data reading by toggling RD. On the next falling edge
24
of RD, the second data are present on the data output pins.
Continue this way until all the data have been read from the
FIFO, making sure to take RD high when complete.
Afterwards, wait until DRDY toggles and repeat the
readback cycle. Figure 23 shows an example readback
when FIFO_LEV[2:0] = 010 (level = 4).
Readback considerations
The exact number of data readings set by the FIFO level
must be read back each time DRDY toggles. The one
exception is that readback can be skipped entirely. In this
case, the DRDY period increases to 512 CLK period.
Figure 24 illustrates an example when readback is
skipped with the FIFO level = 4. Do not read back more or
less readings from the FIFO than set by the level. This
interrupts the FIFO operation and can cause DRDY to stay
low indefinitely. If this occurs, the RESET pin must be
toggled followed by a RD pulse. This resets the ADS1626
FIFO and also the digital filter, which must settle
afterwards before valid data is ready. See the section,
Resetting the ADS1626, for more details. Also note that
the RD signal is independent of the CS signal. Therefore,
when multiple devices are used, the RD signal should not
be shared. Alternatively, individual RD signals can be
generated by performing an OR operation with the CS
signal.
Setting the FIFO Level
The FIFO level setting is usually a static selection that is
set when power is first applied to the ADS1626. If the FIFO
level needs to be changed after powerup, there are two
options. One is to asynchronously set the new value on pin
FIFO_LEV[2:0] then toggle RESET. Remember that the
ADS1626 will need to settle after resetting. See the
section, Resetting the ADS1626, for more details. The
other option avoids requiring a reset, but needs
synchronization of the FIFO level change with the
readback. The FIFO_LEV[2:0] pins have to be changed
after RD goes high after reading the first data, but before
RD goes low to read the last data from the FIFO. The new
FIFO level becomes active immediately and the DRDY
period adjusts accordingly. When decreasing the FIFO
level this way, make sure to give adequate time for
readback of the data before setting the new, smaller level.
Figure 25 illustrates an example of a synchronized FIFO
level change from 4 to 8.
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
DRDY
CS(1)
RD
Data1(2)
DOUT[17:0]
Data2
Data3
Data4
(1) CS can be tied low.
(2) Data1 are the oldest data and Data4 are the most recent.
Figure 23. Example of FIFO Readback when FIFO Level = 4
128/fCLK
512/fCLK
DRDY
RD
Figure 24. Example of Skipping Readback when FIFO Level = 4
128/fCLK
256/fCLK
DRDY
RD
FIFO_LEV[2:0]
010 (Level = 4)
100 (Level = 8)
Change FIFO_LEV[2:0] here
Figure 25. Example of Synchronized Change of FIFO Level from 4 to 8
25
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
ANALOG POWER DISSIPATION
POWER DOWN (PD)
An external resistor connected between the RBIAS pin
and the analog ground sets the analog current level, as
shown in Figure 26. The current is inversely proportional
to the resistor value. Table 6 shows the recommended
values of RBIAS for different CLK frequencies. Notice that
the analog current can be reduced when using a slower
frequency CLK input, because the modulator has more
time to settle. Avoid adding any capacitance in parallel to
RBIAS, since this will interfere with the internal circuitry
used to set the biasing.
When not in use, the ADS1625/6 can be powered down by
taking the PD pin low. All circuitry will be shutdown, including
the voltage reference. To minimize the digital current during
power down, stop the clock signal supplied to the CLK input.
There is an internal pull-up resistor of 170kΩ on the PD pin,
but it is recommended that this pin be connected to IOVDD
if not used. If using the ADS1626 with the FIFO enabled,
issue a reset after exiting the power-down mode. Make sure
to allow time for the reference to start up after exiting
power-down mode. The internal reference typically requires
15ms. After the reference has stabilized, allow at least 100
DRDY cycles for the modulator and digital filter to settle
before retrieving data.
ADS1625
ADS1626
POWER SUPPLIES
RBIAS
RBIAS
AGND
Figure 26. External Resistor Used to Set Analog
Power Dissipation
Table 6. Recommended RBIAS Resistor Values for
Different CLK Frequencies
fCLK
DATA
RATE
RBIAS
TYPICAL POWER
DISSIPATION WITH REFEN
HIGH
10MHz
312.5kHz
65kΩ
150mW
20MHz
625kHz
60kΩ
305mW
30MHz
937.5kHz
50kΩ
390mW
40MHz
1.25MHz
37kΩ
515mW
26
Three supplies are used on the ADS1625/6: analog
(AVDD), digital (DVDD) and digital I/O (IOVDD). Each
supply must be suitably bypassed to achieve the best
performance. It is recommended that a 1µF and 0.1µF
ceramic capacitor be placed as close to each supply pin as
possible. Connect each supply-pin bypass capacitor to the
associated ground, see Figure 27. Each main supply bus
should also be bypassed with a bank of capacitors from
47µF to 0.1µF, as shown.
The IO and digital supplies (IOVDD and DVDD) can be
connected together when using the same voltage. In this
case, only one bank of 47µF to 0.1µF capacitors is needed
on the main supply bus, though each supply pin must still
be bypassed with a 1µF and 0.1µF ceramic capacitor.
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
DVDD
47µF
4.7µF
1µF
0.1µF
47µF
4.7µF
1µF
0.1µF
47µF
4.7µF
1µF
0.1µF
IOVDD
53
52
51
DGND
CP
DVDD
54
DGND
AVDD
55
AGND
2
57
AGND
AGND
58
AVDD
1
CP
IOVDD
CP
AVDD
CP
If using separate analog and
digital ground planes, connect
together on the ADS1625/6 PCB.
3
6
AGND
7
AVDD
9
AGND
CP
AGND
NOTE: CP = 1µF | | 0.1µF
ADS1625
ADS1626
CP
10 AVDD
11 AGND
CP
12 AVDD
18
CP
19
25
DVDD
DGND
15 DGND
DGND
14 IOVDD
CP
DVDD
DGND
26
CP
Figure 27. Recommended Power-Supply Bypassing
27
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
LAYOUT ISSUES
APPLICATIONS
The ADS1625/6 is a very high-speed, high-resolution data
converter. In order to achieve the maximum performance,
careful attention must be given to the printed circuit board
(PCB) layout. Use good high-speed techniques for all
circuitry. Critical capacitors should be placed close to pins
as possible. These include capacitors directly connected
to the analog and reference inputs and the power supplies.
Make sure to also properly bypass all circuitry driving the
inputs and references.
INTERFACING THE ADS1625 TO THE
TMS320C6000
There are two possible approaches for the ground plane on
the PCB: a single common plane or two separate planes, one
for the analog grounds and one for the digital grounds. When
using only one common plane, isolate the flow of current on
pin 58 from pin 1; use breaks on the ground plane to
accomplish this. Pin 58 carries the switching current from the
analog clocking for the modulator and can corrupt the quiet
analog ground on pin 1. When using two planes, it is
recommended that they be tied together right at the PCB. Do
not try to connect the ground planes together after running
separately through edge connectors or cables as this
reduces performance and increases the likelihood of latchup.
In general, keep the resistances used in the driving circuits
for the inputs and reference low to prevent excess thermal
noise from degrading overall performance. Avoid having
the ADS1625/6 digital outputs drive heavy loads. Buffers
on the outputs are recommended unless the ADS1625/6
is connected directly to a DSP or controller situated
nearby. Additionally, make sure the digital inputs are
driven with clean signals as ringing on the inputs can
introduce noise.
The ADS1625/6 uses TI PowerPAD technology. The
PowerPAD is physically connected to the substrate of the
silicon inside the package and must be soldered to the
analog ground plane on the PCB using the exposed metal
pad underneath the package for proper heat dissipation.
Please refer to application report SLMA002, located at
www.ti.com, for more details on the PowerPAD package.
Figure 28 illustrates how to directly connect the ADS1625
to the TMS320C6000 DSP. The processor controls
reading using output ARE. The ADS1625 is selected using
the DSP control output, CE2. The ADS1625 18-bit data
output bus is directly connected to the TMS320C6000 data
bus. The data ready output from the ADS1625, DRDY,
drives interrupt EXT_INT7 on the TMS320C6000.
ADS1625
TMS320C6000
18
DOUT[17:0]
XD[17:0]
DRDY
EXT_INT7
CS
CE2
RD
ARE
Figure 28. ADS1625—TMS320C6000 Interface
Connection
INTERFACING THE ADS1626 TO THE
TMS320C6000
Figure 29 illustrates how to directly connect the ADS1626
to the TMS320C6000 DSP. The processor controls
reading using output ARE. The ADS1626 is permanently
selected by grounding the CS pin. The ADS1626 18-bit
data output bus is directly connected to the TMS320C6000
data bus. The data ready output from the ADS1626,
DRDY, drives interrupt EXT_INT7 on the TMS320C6000.
ADS1626
TMS320C6000
18
DOUT[17:0]
DRDY
XD[17:0]
EXT_INT7
CS
RD
ARE
Figure 29. ADS1626—TMS320C6000 Interface
Connection
28
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
INTERFACING THE ADS1625 TO THE
TMS320VC5510
INTERFACING THE ADS1626 TO THE
TMS320VC5510
Figure 30 illustrates how to connect the ADS1625 to the
TMS320VC5510 DSP. The DSP controls reading using
output ARE. The ADS1625 is selected using the DSP
control output CE2. The ADS1625 18-bit data output bus
is directly connected to the TMS320VC5510 data bus. The
data ready output from the ADS1625, DRDY, drives the
INT3 interrupt line on the TMS320VC5510.
Figure 31 illustrates how to directly connect the ADS1626
to the TMS320VC5510 Digital Signal Processor. The
processor controls reading the ADC using the ARE output.
The ADS1626 is permanently selected by grounding the
CS pin. If there are any additional devices connected to the
TMS320VC5510 I/O space, address decode logic will be
required between the ADC and the DSP to prevent data
bus contention and ensure that only one device at a time
is selected. The ADS1626 18-bit data output bus is directly
connected to the TMS320VC5510. The data ready output
from the ADS1626, DRDY, drives interrupt INT3 on the
TMS320VC5510.
ADS1625
TMS320VC5510
18
DOUT[17:0]
D[17:0]
DRDY
INT3
CS
CE2
RD
ARE
ADS1626
TMS320VC5510
18
DOUT[17:0]
DRDY
D[17:0]
INT3
CS
Figure 30. ADS1625—TMS320VC5510 Interface
Connection
RD
ARE
Figure 31. ADS1626—TMS320VC5510 Interface
Connection
Code Composer Studio, available from TI, provides
support for interfacing TI DSPs through a collection of data
converter plugins. Check the TI web site, located at
www.ti.com/sc/dcplug-in, for the latest information on
ADS1625/6 support.
29
www.ti.com
SBAS280E − JUNE 2003 − REVISED MAY 2007
Revision History
DATE
REV
PAGE
SECTION
5/16/07
E
24
Readback Considerations
DESCRIPTION
Added last three sentences.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
30
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS1625IPAPT
ACTIVE
HTQFP
PAP
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS1625I
ADS1626IPAPT
ACTIVE
HTQFP
PAP
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
ADS1626I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS1625IPAPT
HTQFP
PAP
64
250
180.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
ADS1626IPAPT
HTQFP
PAP
64
250
180.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS1625IPAPT
HTQFP
PAP
64
250
213.0
191.0
55.0
ADS1626IPAPT
HTQFP
PAP
64
250
213.0
191.0
55.0
Pack Materials-Page 2
www.ti.com
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harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated
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