Texas Instruments | 16-Bit, 5MSPS Analog-to-Digital Converter (Rev. H) | Datasheet | Texas Instruments 16-Bit, 5MSPS Analog-to-Digital Converter (Rev. H) Datasheet

Texas Instruments 16-Bit, 5MSPS Analog-to-Digital Converter (Rev. H) Datasheet
ADS1605
ADS1606
SBAS274H − MARCH 2003 − REVISED MAY 2007
16-Bit, 5MSPS
Analog-to-Digital Converter
FEATURES
DESCRIPTION
D
D
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D
D
D
D
D
D
The ADS1605 and ADS1606 are high-speed, high-precision, delta-sigma analog-to-digital converters (ADCs)
with 16-bit resolution. The data rate is 5 mega-samples
per second (MSPS), the bandwidth (−3dB) is 2.45MHz,
and passband ripple is less than ±0.0025dB (to
2.2MHz). Both devices offer the same outstanding performance at these speeds with a signal-to-noise ratio up
to 88dB, total harmonic distortion down to −99dB, and
a spurious-free dynamic range up to 101dB. For even
higher-speed operation, the data rate can be doubled to
10MSPS in 2X mode. The ADS1606 includes an adjustable first-in first-out buffer (FIFO) for the output data.
The input signal is measured against a voltage reference that can be generated on-chip or supplied externally. The digital output data are provided over a simple
parallel interface that easily connects to digital signal
processors (DSPs). An out-of-range monitor reports
when the input range has been exceeded. The
ADS1605/6 operate from a +5V analog supply (AVDD)
and +3V digital supply (DVDD). The digital I/O supply
(IOVDD) operates from +2.7 to +5.25V, enabling the
digital interface to support a range of logic families. The
analog power dissipation is set by an external resistor
and can be reduced when operating at slower speeds.
A power down mode, activated by a digital I/O pin, shuts
down all circuitry. The ADS1605/6 are offered in a
TQFP-64 package using TI PowerPAD technology.
The ADS1605 and ADS1606, along with their 18-bit
counterparts, the ADS1625 and ADS1626, are well
suited for the demanding measurement requirements
of scientific instrumentation, automated test equipment, data acquisition, and medical imaging.
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Data Rate: 5MSPS (10MSPS in 2X Mode)
Signal-to-Noise Ratio: 88dB
Total Harmonic Distortion: −99dB
Spurious-Free Dynamic Range: 101dB
Linear Phase with 2.45MHz Bandwidth
Passband Ripple: ±0.0025dB
Selectable On-Chip Reference
Directly Connects to TMS320C6000 DSPs
Easily Upgradable to 18 Bits with the
ADS1625 and ADS1626
Adjustable Power Dissipation: 315 to 570mW
Power Down Mode
Supplies: Analog
+5V
Digital
+3V
Digital I/O +2.7V to +5.25V
APPLICATIONS
D
D
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Scientific Instruments
Automated Test Equipment
Data Acquisition
Medical Imaging
Vibration Analysis
VREFP VREFN
VMID RBIAS VCAP
AVDD
DVDD
IOVDD
PD
REFEN
RESET
CLK
CS
2XMODE
Reference and Bias Circuits
AINP
DS
Modulator
I/O
Interface
Digital
Filter
RD
DRDY
OTR
AINN
ADS1606 Only
FIFO
ADS1605
ADS1606
DOUT[15:0]
FIFO_LEV[2:0]
AGND
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
Copyright  2003−2007, Texas Instruments Incorporated
! ! www.ti.com
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SBAS274H − MARCH 2003 − REVISED MAY 2007
ORDERING INFORMATION(1)
PRODUCT
PACKAGE−LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS1605
HTQFP−64
PAP
−40°C to +85°C
ADS1605I
ADS1606
HTQFP−64
PAP
−40°C to +85°C
ADS1606I
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS1605IPAPT
Tape and Reel, 250
ADS1605IPAPR
Tape and Reel, 1000
ADS1606IPAPT
Tape and Reel, 250
ADS1606IPAPR
Tape and Reel, 1000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web
site at www.ti.com.
PRODUCT FAMILY
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
ADS1605, ADS1606
UNIT
AVDD to AGND
−0.3 to +6
V
DVDD to DGND
−0.3 to +3.6
V
IOVDD to DGND
−0.3 to +6
V
−0.3 to +0.3
V
AGND to DGND
Input Current
100mA, Momentary
Input Current
10mA, Continuous
Analog I/O to AGND
−0.3 to AVDD + 0.3
Digital I/O to DGND
−0.3 to IOVDD + 0.3
V
+150
°C
Operating Temperature Range
−40 to +105
°C
Storage Temperature Range
−60 to +150
°C
Maximum Junction Temperature
V
Lead Temperature (soldering, 10s)
+260
°C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
2
PRODUCT
RESOLUTION
DATA RATE
FIFO?
ADS1605
16 Bits
5.0MSPS
No
ADS1606
16 Bits
5.0MSPS
Yes
ADS1625
18 Bits
1.25MSPS
No
ADS1626
18 Bits
1.25MSPS
Yes
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
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SBAS274H − MARCH 2003 − REVISED MAY 2007
ELECTRICAL CHARACTERISTICS
All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V,
FIFO disabled, and RBIAS = 37kΩ, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Input
0dBFS
Differential input voltage (VIN)
(AINP − AINN)
−2dBFS
−6dBFS
−20dBFS
±1.467VREF
±1.165VREF
V
±0.735VREF
±0.147VREF
V
2.0
V
Common-mode input voltage (VCM)
(AINP + AINN) / 2
Absolute input voltage
(AINP or AINN with respect to AGND)
V
V
0dBFS
−0.1
4.7
V
−2dBFS input and smaller
0.1
4.2
V
Dynamic Specifications
Data rate
5.0
fIN = 100kHz, −2dBFS
fIN = 100kHz, −6dBFS
Total harmonic distortion (THD)
Ǔ
MSPS
dB
84
dB
70
dB
86
dB
fIN = 500kHz, −6dBFS
fIN = 500kHz, −20dBFS
83
dB
69
dB
fIN = 2MHz, −2dBFS
fIN = 2MHz, −6dBFS
84
dB
82
dB
fIN = 2MHz, −20dBFS
fIN = 100kHz, −2dBFS
69
dB
−93
dB
62
fIN = 100kHz, −6dBFS
fIN = 100kHz, −20dBFS
−99
fIN = 500kHz, −2dBFS
fIN = 500kHz, −6dBFS
−94
dB
−97
dB
fIN = 500kHz, −20dBFS
fIN = 2MHz, −2dBFS
−93
dB
−98
dB
fIN = 2MHz, −6dBFS
fIN = 2MHz, −20dBFS
−101
dB
−92
dB
fIN = 100kHz, −2dBFS
fIN = 100kHz, −6dBFS
86
dB
84
dB
70
dB
86
dB
fIN = 500kHz, −6dBFS
fIN = 500kHz, −20dBFS
83
dB
69
dB
fIN = 2MHz, −2dBFS
fIN = 2MHz, −6dBFS
84
dB
82
dB
fIN = 2MHz, −20dBFS
69
dB
fIN = 100kHz, −20dBFS
fIN = 500kHz, −2dBFS
Signal-to-noise and distortion (SINAD)
fCLK
40MHz
88
fIN = 100kHz, −20dBFS
fIN = 500kHz, −2dBFS
Signal-to-noise ratio (SNR)
ǒ
−94
62
dB
−85
dB
3
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SBAS274H − MARCH 2003 − REVISED MAY 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V,
FIFO disabled, and RBIAS = 37kΩ, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
fIN = 100kHz, −2dBFS
fIN = 100kHz, −6dBFS
Intermodulation distortion (IMD)
UNIT
dB
101
dB
96
dB
95
dB
fIN = 500kHz, −6dBFS
fIN = 500kHz, −20dBFS
100
dB
95
dB
fIN = 2MHz, −2dBFS
fIN = 2MHz, −6dBFS
102
dB
105
dB
fIN = 2MHz, −20dBFS
96
dB
f1 = 1.99MHz, −6dBFS
f2 = 2.00MHz, −6dBFS
−94
dB
4
ns
fIN = 100kHz, −20dBFS
fIN = 500kHz, −2dBFS
Spurious free dynamic range (SFDR)
MAX
96
85
Aperture delay
Digital Filter Characteristics
Passband
0
2.2
Passband ripple
2.3
−3.0dB attenuation
2.45
Passband transition
Stop band
2.8
Stop band attenuation
ǒ
fCLK
40MHz
fCLK
40MHz
fCLK
Ǔ
Ǔ
Ǔ
±0.0025
MHz
dB
MHz
MHz
ǒ
Ǔ
37.2
f CLK
40MHz
Ǔ
MHz
dB
5.2
To ±0.001%
fCLK
40MHz
40MHz
72
Group delay
Settling time
ǒ
ǒ
−0.1dB attenuation
ǒ
ǒ
ǒ
9.4
40MHz
fCLK
Ǔ
Ǔ
40MHz
fCLK
µs
µs
Static Specifications
Resolution
No missing codes
Bits
1.0
LSB, rms
±0.75
LSB
16
Input-referred noise
Integral nonlinearity
16
−1.5dBFS signal
Bits
Differential nonlinearity
±0.25
LSB
Offset error
0.05
%FSR
1
ppmFSR/°C
Offset error drift
Gain error
0.25
%
Gain error drift
Excluding reference drift
10
ppm/°C
Common-mode rejection
At dc
75
dB
Power-supply rejection
At dc
65
dB
4
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SBAS274H − MARCH 2003 − REVISED MAY 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V,
FIFO disabled, and RBIAS = 37kΩ, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage Reference(1)
VREF = (VREFP − VREFN)
VREFP
2.5
3.0
3.2
V
3.75
4.0
4.25
V
VREFN
0.75
1.0
1.25
V
VMID
2.3
2.5
2.8
VREF drift
Startup time
V
Internal reference (REFEN = low)
50
ppm/°C
Internal reference (REFEN = low)
15
ms
Clock Input
Frequency (fCLK)
40
Duty Cycle
fCLK = 40MHz
50
MHz
55
%
0.7 IOVDD
IOVDD
V
DGND
0.3 IOVDD
V
45
Digital Input/Output
VIH
VIL
VOH
VOL
IOH = 50µA
IOL = 50µA
Input leakage
DGND < VDIGIN < IOVDD
IOVDD − 0.5
V
DGND +0.5
V
±10
µA
Power-Supply Requirements
AVDD
4.75
5.25
V
DVDD
2.7
3.3
V
IOVDD
2.7
AVDD current (IAVDD)
5.25
V
REFEN = low
110
135
mA
REFEN = high
85
105
mA
45
55
mA
4
6
mA
570
710
mW
DVDD current (IDVDD)
IOVDD current (IIOVDD)
IOVDD = 3V
Power dissipation
AVDD = 5V, DVDD = 3V, IOVDD = 3V,
REFEN = high
PD = low, CLK disabled
5
mW
Temperature Range
Specified
−40
+85
°C
Operating
−40
+105
°C
Storage
−60
+150
°C
Thermal Resistance, θJA
θJC
PowerPAD soldered to PCB with 2oz.
PowerPAD
trace and copper pad.
25
°C/W
0.5
°C/W
(1) The specification limits for VREF, VREFP, VREFN, and VMID apply when using the internal or an external reference. The internal reference
voltages are bounded by the limits shown. When using an external reference, the limits indicate the allowable voltages that can be applied to
the reference pins.
5
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SBAS274H − MARCH 2003 − REVISED MAY 2007
DEFINITIONS
Absolute Input Voltage
Absolute input voltage, given in volts, is the voltage of
each analog input (AINN or AINP) with respect to
AGND.
Aperture Delay
Aperture delay is the delay between the rising edge of
CLK and the sampling of the input signal.
Common-Mode Input Voltage
Common-mode input voltage (VCM) is the average voltage of the analog inputs:
(AINP ) AINN)
2
Differential Input Voltage
Differential input voltage (VIN) is the voltage difference
between the analog inputs: (AINP−AINN).
Differential Nonlinearity (DNL)
DNL, given in least-significant bits of the output code
(LSB), is the maximum deviation of the output code step
sizes from the ideal value of 1LSB.
Full-Scale Range (FSR)
FSR is the difference between the maximum and minimum measurable input signals. FSR = 2 × 1.467VREF.
Gain Error
Gain error, given in %, is the error of the full-scale input
signal with respect to the ideal value.
Gain Error Drift
Gain error drift, given in ppm/_C, is the drift over temperature of the gain error. The gain error is specified as
the larger of the drift from ambient (T = 25_C) to the
minimum or maximum operating temperatures.
Integral Nonlinearity (INL)
INL, given in least-significant bits of the output code
(LSB), is the maximum deviation of the output codes
from a best fit line.
6
Intermodulation Distortion (IMD)
IMD, given in dB, is measured while applying two input
signals of the same magnitude, but with slightly different
frequencies. It is calculated as the difference between
the rms amplitude of the input signal to the rms amplitude of the peak spurious signal.
Offset Error
Offset Error, given in % of FSR, is the output reading
when the differential input is zero.
Offset Error Drift
Offset error drift, given in ppm of FSR/_C, is the drift
over temperature of the offset error. The offset error is
specified as the larger of the drift from ambient (T =
25_C) to the minimum or maximum operating temperatures.
Signal-to-Noise Ratio (SNR)
SNR, given in dB, is the ratio of the rms value of the input signal to the sum of all the frequency components
below fCLK/2 (the Nyquist frequency) excluding the first
six harmonics of the input signal and the dc component.
Signal-to-Noise and Distortion (SINAD)
SINAD, given in dB, is the ratio of the rms value of the
input signal to the sum of all the frequency components
below fCLK/2 (the Nyquist frequency) including the harmonics of the input signal but excluding the dc component.
Spurious-Free Dynamic Range (SFDR)
SFDR, given in dB, is the difference between the rms
amplitude of the input signal to the rms amplitude of the
peak spurious signal.
Total Harmonic Distortion (THD)
THD, given in dB, is the ratio of the sum of the rms value
of the first six harmonics of the input signal to the rms
value of the input signal.
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SBAS274H − MARCH 2003 − REVISED MAY 2007
VREFP
VREFP
VMID
VREFN
VREFN
VCAP
AVDD
AGND
CLK
AGND
DGND
IOVDD
DVDD
DGND
NC
NC
PIN ASSIGNMENTS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AGND
1
AVDD
2
AGND
3
46 FIFO_LEV[0] (ADS1606 Only)
AINN
4
45 NC
AINP
5
44 DOUT[15]
AGND
6
43 DOUT[14]
AVDD
7
RBIAS
8
AGND
9
40 DOUT[11]
AVDD 10
39 DOUT[10]
AGND 11
38 DOUT[9]
AVDD 12
37 DOUT[8]
REFEN 13
36 DOUT[7]
NC 14
35 DOUT[6]
2XMODE 15
34 DOUT[5]
TQFP PACKAGE
(TOP VIEW)
48 FIFO_LEV[2] (ADS1606 Only)
AD S1605
AD S1606
47 FIFO_LEV[1] (ADS1606 Only)
42 DOUT[13]
Pow erPA D
41 DOUT[12]
TM
23
24
25
26
27
28
29
30
31
32
DGND
DVDD
NC
NC
DOUT[0]
DOUT[1]
DOUT[2]
DOUT[3]
RESET
22
DRDY
DGND
21
OTR
20
RD
19
CS
18
PD
33 DOUT[4]
17
DVDD
NC 16
Terminal Functions
TERMINAL
NAME
NO.
TYPE
AGND
1, 3, 6, 9, 11, 55, 57
Analog
Analog ground
AVDD
2, 7, 10, 12, 58
Analog
Analog supply
AINN
4
Analog input
Negative analog input
AINP
5
Analog input
Positive analog input
RBIAS
8
Analog
REFEN
NC
2XMODE
PD
DESCRIPTION
Terminal for external analog bias setting resistor
13
Digital input: active low
Internal reference enable. Internal pull-down resistor of 170kΩ to DGND.
14,16, 27, 28, 45, 50
Not connected
These terminals are not connected within the ADS1605/6 and must be left
unconnected.
15
Digital input
Digital filter decimation rate. Internal pull-down resistor of 170kΩ to DGND.
17
Digital input: active low
DVDD
18, 26, 52
Digital
Digital supply
DGND
19, 25, 51, 54
Digital
Digital ground
RESET
20
Digital input: active low
Reset digital filter
CS
21
Digital input: active low
Chip select
RD
22
Digital input: active low
Read enable
OTR
23
Digital output
Analog inputs out of range
DRDY
24
Digital output: active low
Data ready on falling edge
DOUT [15:0]
29−44
Digital output
FIFO_LEV[2:0]
46−48
Digital input
IOVDD
53
Digital
CLK
56
Digital input
VCAP
VREFN
VMID
VREFP
Power down all circuitry. Internal pull-up resistor of 170kΩ to DGND.
Data output. DOUT[15] is the MSB and DOUT[0] is the LSB.
FIFO level (for the ADS1606 only). FIFO_LEV[2] is MSB.
NOTE: These terminals must be left disconnected on the ADS1605.
Digital I/O supply
Clock input
59
Analog
Terminal for external bypass capacitor connection to internal bias voltage
60, 61
Analog
Negative reference voltage
62
Analog
Midpoint voltage
63, 64
Analog
Positive reference voltage
7
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SBAS274H − MARCH 2003 − REVISED MAY 2007
PARAMETER MEASUREMENT INFORMATION
t2
t1
CLK
t2
t3
t4
DRDY
t4
t6
t5
DOUT[15:0]
Data N + 1
Data N
Data N + 2
NOTE: CS and RD tied low.
Figure 1. Data Retrieval Timing (ADS1605, ADS1606 with FIFO Disabled)
RD, CS
t7
t8
DOUT[15:0]
Figure 2. DOUT Inactive/Active Timing (ADS1605, ADS1606 with FIFO Disabled)
TIMING REQUIREMENTS FOR FIGURE 1 AND FIGURE 2
SYMBOL
t1
1/t1
DESCRIPTION
CLK period (1/fCLK)
fCLK
TYP
MAX
UNIT
20
25
1000
ns
1
40
50
10
MHz
t2
CLK pulse width, high or low
t3
Rising edge of CLK to DRDY low
t4
DRDY pulse width high or low
t5
Falling edge of DRDY to data invalid
10
ns
t6
Falling edge of DRDY to data valid
15
ns
t7
Rising edge of RD and/or CS inactive (high) to DOUT high impedance
15
ns
t8
Falling edge of RD and/or CS active (low) to DOUT active.
15
ns
NOTE: DOUT[15:0] and DRDY load = 10pF.
8
MIN
ns
10
ns
4 t1
ns
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SBAS274H − MARCH 2003 − REVISED MAY 2007
CLK
t11
RESET
t9
t12
t 10
DRDY
t3
Settled
Data
DOUT[15:0]
NOTE: CS and RD tied low.
Figure 3. Reset TIming (ADS1605, ADS1606 with FIFO Disabled)
TIMING REQUIREMENTS FOR FIGURE 3
SYMBOL
DESCRIPTION
t3
Rising edge of CLK to DRDY low
t9
RESET pulse width
t10
Delay from RESET active (low) to DRDY forced high and DOUT forced low
t11
RESET rising edge to falling edge of CLK
t12
Delay from DOUT active to valid DOUT (settling to 0.001%)
MIN
TYP
MAX
10
UNIT
ns
50
ns
9
−5
ns
10
47
ns
DRDY
Cycles
NOTE: DOUT[15:0] and DRDY load = 10pF.
9
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SBAS274H − MARCH 2003 − REVISED MAY 2007
t1
t2
CLK
t2
t 13
t14
DRDY
t15
t16
CS(1)
t21
t 17
RD
t20
t18
DOUT[15:0]
t19
D1
DL(2)
D2
(1) CS may be tied low.
(2) The number of data readings (DL) is set by the FIFO level.
Figure 4. Data Retrieval Timing (ADS1606 with FIFO Enabled)
RD, CS
t7
t8
DOUT[15:0]
Figure 5. DOUT Inactive/Active Timing (ADS1606 with FIFO Enabled)
TIMING REQUIREMENTS FOR FIGURE 4 AND FIGURE 5
SYMBOL
DESCRIPTION
TYP
MAX
UNIT
25
1000
ns
t1
CLK period (1/fCLK)
20
t2
CLK pulse width, high or low
10
t7
Rising edge of RD and/or CS inactive (high) to DOUT high impedance
7
15
ns
t8
Falling edge of RD and/or CS active (low) to DOUT active.
7
15
ns
t13
Rising edge of CLK to DRDY high
t14
DRDY period
t15
DRDY positive pulse width
t16
RD high hold time after DRDY goes low
t17
CS low before RD goes low
ns
12
8 × FIFO Level(1)
1
ns
CLK
Cycles
CLK
Cycles
0
ns
0
ns
RD negative pulse width
10
ns
t19
RD positive pulse width
10
ns
t20
RD high before DRDY toggles
2
CLK
Cycles
t21
RD high before CS goes high
0
ns
t18
NOTE: DOUT[15:0] and DRDY load = 10pF.
(1) See FIFO section for more details.
10
MIN
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SBAS274H − MARCH 2003 − REVISED MAY 2007
CLK
t11
RESET
t9
t26
t25
DRDY
t23
RD
t24
Figure 6. Reset Timing (ADS1606 with FIFO Enabled)
TIMING REQUIREMENTS FOR FIGURE 6
SYMBOL
DESCRIPTION
MIN
t9
RESET pulse width
50
t11
RESET rising edge to falling edge of CLK
−5
TYP
MAX
UNIT
ns
10
ns
t23
RD pulse low after RESET goes high
8
CLK
Cycles
t24
RD pulse high before first DRDY pulse after RESET goes high
8
CLK
Cycles
t25
DRDY low after RESET goes low
t26
Delay from RESET high to valid DOUT (settling to 0.001%)
8 × (FIFO level + 1)
CLK
Cycles
See Table 4
DRDY
Cycles
11
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TYPICAL CHARACTERISTICS
All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V, and
RBIAS = 37kΩ, unless otherwise noted.
SPECTRAL RESPONSE
SPECTRAL RESPONSE
0
0
Amplitude (dB)
−40
−60
−80
−100
fIN = 100kHz, −6dBFS
SNR = 84dB
THD = −99dB
SFDR = 101dB
−20
−40
Amplitude (dB)
fIN = 100kHz, −2dBFS
SNR = 88dB
THD = −93dB
SFDR = 96dB
−20
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
0.5
1.0
1.5
2.0
2.5
0
0.5
Frequency (MHz)
SPECTRAL RESPONSE
0
Amplitude (dB)
−40
−60
−80
−100
−40
2.5
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
0.5
1.0
1.5
2.0
2.5
0
0.5
Frequency (MHz)
2.0
2.5
2.0
2.5
f IN = 2MHz, −6dBFS
SNR = 82dB
THD = −101dB
SFDR = 105dB
−20
−40
Amplitude (dB)
−40
1.5
SPECTRAL RESPONSE
0
fIN = 2MHz, −2dBFS
SNR = 84dB
THD = −98dB
SFDR = 102dB
−20
1.0
Frequency (MHz)
SPECTRAL RESPONSE
0
Amplitude (dB)
2.0
fIN = 500kHz, −6dBFS
SNR = 83dB
THD = −103dB
SFDR = 106dB
−20
Amplitude (dB)
fIN = 500kHz, −2dBFS
SNR = 86dB
THD = −97dB
SFDR = 97dB
−20
1.5
SPECTRAL RESPONSE
0
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
0.5
1.0
1.5
Frequency (MHz)
12
1.0
Frequency (MHz)
2.0
2.5
0
0.5
1.0
1.5
Frequency (MHz)
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TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V, and
RBIAS = 37kΩ, unless otherwise noted.
INTERMODULATION RESPONSE
NOISE HISTOGRAM
0
18k
VIN = 0V
Power Spectral Density (dB)
16k
Occurrences
14k
12k
10k
8k
6k
4k
2k
−4
−3
−2
−1
0
1
2
3
4
−40
−60
−80
−100
−120
−140
−160
1.95 1.96 1.97 1.98 1.99 2.00 2.01 2.02 2.03 2.04 2.05
0
−5
fIN1 = 1.99MHz
fIN2 = 2.00MHz
IMD = −94dB
−20
5
Output Code (LSB)
Frequency (MHz)
SIGNAL−TO−NOISE RATIO,
TOTAL HARMONIC DISTORTION,
AND SPURIOUS−FREE DYNAMIC RANGE
vs INPUT SIGNAL AMPLITUDE
SIGNAL−TO−NOISE RATIO
vs INPUT FREQUENCY
110
90
VIN = −2dBFS
85
90
80
70
60
50
THD
40
VIN = −6dBFS
80
SFDR
SNR (dB)
SNR, THD, and SFDR (dB)
100
75
VIN = −20dBFS
70
SNR
30
65
fIN = 100kHz
20
10
−70
−60
−50
−40
−30
−20
−10
60
0.001
0
0.01
0.1
1
Input Signal Amplitude, VIN (dB)
Input Frequency, fIN (MHz)
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
SPURIOUS−FREE DYNAMIC RANGE
vs INPUT FREQUENCY
−85
10
110
108
106
VIN = −20dBFS
VIN = −6dBFS
104
SFDR (dB)
THD (dB)
−90
−95
VIN = −2dBFS
−100
100
98
96
VIN = −6dBFS
−105
102
VIN = −2dBFS
VIN = −20dBFS
94
92
−110
0.001
0.01
0.1
Input Frequency, fIN (MHz)
1
10
90
0.001
0.01
0.1
1
10
Input Frequency, fIN (MHz)
13
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SBAS274H − MARCH 2003 − REVISED MAY 2007
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V, and
RBIAS = 37kΩ, unless otherwise noted.
SIGNAL−TO−NOISE RATIO
vs INPUT COMMON−MODE VOLTAGE
TOTAL HARMONIC DISTORTION
vs INPUT COMMON−MODE VOLTAGE
−65
89
87
−75
VIN = −2dBFS
−85
83
THD (dB)
SNR (dB)
85
VIN = −6dBFS
81
VIN = −2dBFS
−95
VIN = −6dBFS
−105
−115
79
−125
77
fIN = 100kHz
fIN = 100kHz
−135
75
1.5
1.7
1.9
2.1
2.3
2.5
1.5
2.3
SIGNAL−TO−NOISE RATIO
vs CLK FREQUENCY
90
VIN = −6dBFS
2.5
RBIAS = 30kΩ
85
80
95
VIN = −2dBFS
75
SNR (dB)
90
85
80
RBIAS = 37kΩ
70
R BIAS = 45kΩ
65
RBIAS = 50kΩ
60
55
75
RBIAS = 60kΩ
50
70
f IN = 100kHz, − 6dBFS
45
fIN = 100kHz
40
65
1.5
1.7
1.9
2.1
2.3
2.5
10
20
Input Common−Mode Voltage, VCM (V)
−65
fIN = 100kHz, −6dBFS
RBIAS = 30kΩ
100
SFDR (dB)
RBIAS = 45kΩ
−85
60
105
RBIAS = 50kΩ
−80
50
110
RBIAS = 60kΩ
−75
40
SPURIOUS−FREE DYNAMIC RANGE
vs CLK FREQUENCY
fIN = 100kHz, −6dBFS
−70
30
CLK Frequency, fCLK (MHz)
TOTAL HARMONIC DISTORTION
vs CLK FREQUENCY
THD (dB)
2.1
SPURIOUS−FREE DYNAMIC RANGE
vs INPUT COMMON−MODE VOLTAGE
100
−90
RBIAS = 37kΩ
95
RBIAS = 45kΩ
90
RBIAS = 50kΩ
85
−95
RBIAS = 60kΩ
RBIAS = 37kΩ
80
−100
RBIAS = 30kΩ
−105
75
10
20
30
40
CLK Frequency, fCLK (MHz)
14
1.9
Input Common−Mode Voltage, VCM (V)
105
SFDR (dB)
1.7
Input Common−Mode Voltage, VCM (V)
50
60
10
20
30
40
CLK Frequency, fCLK (MHz)
50
60
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SBAS274H − MARCH 2003 − REVISED MAY 2007
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V, and
RBIAS = 37kΩ, unless otherwise noted.
SIGNAL−TO−NOISE RATIO
vs TEMPERATURE
TOTAL HARMONIC DISTORTION
vs TEMPERATURE
−85
100
VIN = −2dBFS
90
−90
VIN = −6dBFS
80
THD (dB)
SNR (dB)
VIN = −20dBFS
70
−95
VIN = −2dBFS
−100
VIN = −6dBFS
VIN = −20dBFS
−105
60
fIN = 100kHz
50
−40
fIN = 100kHz
−15
10
35
60
85
−110
−40
−15
10
SPURIOUS−FREE DYNAMIC RANGE
vs TEMPERATURE
POWER−SUPPLY CURRENT
vs TEMPERATURE
85
130
I AVDD (REFEN = low)
120
105
110
Current (mA)
VIN = −6dBFS
SFDR (dB)
60
Temperature (_C)
110
100
VIN = −20dBFS
95
100
IAVDD (REFEN = high)
90
80
70
60
VIN = −2dBFS
90
IDVDD + IIOVDD
50
40
fIN = 100kHz
85
−40
−15
10
35
60
30
−40
85
DVDD = IOVDD = 3V
RBIAS = 37kΩ, fCLK = 40MHz
−15
10
Temperature (_ C)
35
60
85
Temperature (_ C)
ANALOG SUPPLY CURRENT vs RBIAS
SUPPLY CURRENT vs CLK FREQUENCY
140
100
130
Analog Current, IAVDD (mA)
IAVDD (RBIAS = 37kΩ)
80
Supply Current (mA)
35
Temperature (_C)
IAVDD (RBIAS = 60kΩ)
60
40
IDVDD + IIOVDD
20
AVDD = 5V, DVDD = IOVDD = 3V, REFEN = High
120
110
100
REFEN = low
90
80
70
REFEN = high
60
50
0
10
20
30
CLK Frequency, fCLK (MHz)
40
50
30
35
40
45
50
55
60
RBIAS (kΩ)
15
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SBAS274H − MARCH 2003 − REVISED MAY 2007
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V, and
RBIAS = 37kΩ, unless otherwise noted.
INTEGRAL NONLINEARITY
1.0
f IN = 100Hz, −1.5dBFS
0.4
0.6
0.3
0.4
0.2
DNL (LSB)
INL (LSB)
0.8
DIFFERENTIAL NONLINEARITY
0.5
0.2
0
−0.2
0.1
0
−0.1
−0.4
−0.2
−0.6
−0.3
−0.8
−0.4
−0.5
−1.0
−25k −20k −15k −10k −5k
0
5k
Output Code (LSB)
16
f IN = 100Hz, −1.5dBFS
10k 15k
20k 25k
−25k −20k −15k −10k −5k
0
5k
Output Code (LSB)
10k 15k
20k 25k
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SBAS274H − MARCH 2003 − REVISED MAY 2007
OVERVIEW
The ADS1605 and ADS1606 are high-performance deltasigma ADCs with a default oversampling ratio of 8. The
modulator uses an inherently stable 2-1-1 pipelined deltasigma modulator architecture incorporating proprietary
circuitry that allows for very linear high-speed operation.
The modulator samples the input signal at 40MSPS
(when fCLK = 40MHz). A low-ripple linear phase digital filter decimates the modulator output to provide data output
word rates of 5MSPS with a signal passband out to
2.45MHz. The 2X mode, enabled by a digital I/O pin,
doubles the data rate to 10MSPS by reducing the oversampling ratio to 4. See the 2X Mode section for more details.
Conceptually, the modulator and digital filter measure the
differential input signal, VIN = (AINP – AINN), against the
scaled differential reference, VREF = (VREFP – VREFN),
as shown in Figure 7. The voltage reference can either be
generated internally or supplied externally. An 16-bit parallel data bus, designed for direct connection to DSPs, outputs the data. A separate power supply for the I/O allows
flexibility for interfacing to different logic families. Out-ofrange conditions are indicated with a dedicated digital output pin. Analog power dissipation is controlled using an
external resistor. This allows reduced dissipation when
operating at slower speeds. When not in use, power consumption can be dramatically reduced using the PD pin.
The ADS1606 incorporates an adjustable FIFO buffer for
the output data. The level of the FIFO is set by the
FIFO_LEV[2:0] pins. Other than the FIFO buffer, the
ADS1605 and ADS1606 are identical, and are referred to
together in this data sheet as the ADS1605/6.
ANALOG INPUTS (AINP, AINN)
The ADS1605/6 measures the differential signal,
VIN = (AINP − AINN), against the differential reference,
VREF = (VREFP – VREFN). The reference is scaled internally so that the full-scale differential input voltage is
1.467VREF. That is, the most positive measurable differential input is 1.467VREF, which produces the most posiVREFP VREFN
tive digital output code of 7FFFh. Likewise, the most negative measurable differential input is –1.467VREF, which
produces the most negative digital output code of 8000h.
The ADS1605/6 supports a very wide range of input signals. For VREF = 3V, the full-scale input voltages are
±4.4V. Having such a wide input range makes out-ofrange signals unlikely. However, should an out-of-range
signal occur, the digital output OTR will go high.
To achieve the highest analog performance, it is recommended that the inputs be limited to ±1.165VREF
(−2dBFS). For VREF = 3V, the corresponding recommended input range is ±3.78V.
The analog inputs must be driven with a differential signal
to achieve optimum performance. The recommended
common-mode voltage of the input signal,
V CM + AINP ) AINN, is 2.0V. For signals larger than
2
−2dBFS, the input common-mode voltage needs to be
raised in order to meet the absolute input voltage specifications. The Typical Characteristics show how performance varies with input common-mode voltage.
In addition to the differential and common-mode input voltages, the absolute input voltage is also important. This is
the voltage on either input (AINP or AINN) with respect to
AGND. The range for this voltage is:
* 0.1V t (AINN or AINP) t 4.6V
If either input is taken below –0.1V, ESD protection diodes
on the inputs will turn on. Exceeding 4.6V on either input
will result in degradation in the linearity performance. ESD
protection diodes will also turn on if the inputs are taken
above AVDD (+5V).
For signals below –2dBFS, the recommended absolute
input voltage is:
* 0.1V t (AINN or AINP) t 4.2V
Keeping the inputs within this range provides for optimum
performance.
IOVDD
Σ
VREF
1.467
OTR
1.467VREF
AINP
AINN
Σ
VIN
Σ∆
Modulator
Digital
Filter
Parallel
Interface
ADS1606 Only
FIFO
DOUT[15:0]
FIFO_LEV[2:0]
2XMODE
Figure 7. Conceptual Block Diagram
17
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SBAS274H − MARCH 2003 − REVISED MAY 2007
INPUT CIRCUITRY
The ADS1605/6 uses switched-capacitor circuitry to
measure the input voltage. Internal capacitors are
charged by the inputs and then discharged internally
with this cycle repeating at the frequency of CLK.
Figure 8 shows a conceptual diagram of these circuits.
Switches S2 represent the net effect of the modulator
circuitry in discharging the sampling capacitors; the actual implementation is different. The timing for switches
S1 and S2 is shown in Figure 9.
S1
ADS1605
ADS1606
AINP
AGND, improve linearity and should be placed as close
to the pins as possible. Place the drivers close to the inputs and use good capacitor bypass techniques on their
supplies; usually a smaller high-quality ceramic capacitor in parallel with a larger capacitor. Keep the resistances used in the driver circuits low—thermal noise in the
driver circuits degrades the overall noise performance.
When the signal can be ac-coupled to the ADS1605/6
inputs, a simple RC filter can set the input common
mode voltage. The ADS1605/6 is a high-speed, highperformance ADC. Special care must be taken when
selecting the test equipment and setup used with this
device. Pay particular attention to the signal sources to
ensure they do not limit performance when measuring
the ADS1605/6.
S2
10pF
8pF
392 Ω
VMID
−
S1
AINN
V IN
392Ω
40pF
392 Ω
O P A 2 8 22
2
0.01 µ F
S2
10pF
8pF
V CM(1)
AINP
(2)
100pF
392 Ω
VMID
49.9Ω
1µ F
AGND
1kΩ
(2)
392Ω
100pF (3)
V CM(1)
Figure 8. Conceptual Diagram of Internal
Circuitry Connected to the Analog Inputs
V IN
392 Ω
40pF
392Ω
O P A 2 8 22
A D S 1 6 06
(2)
1kΩ
2
0.01 µ F
49.9Ω
AINN
(2)
V CM(1)
t SAMPLE = 1/f CLK
A D S 1 6 05
100pF
392Ω
1µ F
AGND
On
S1
Off
On
S2
Off
(1) Recommended VCM = 2.0V.
(2) Optional ac−coupling circuit provides common−mode input voltage.
(3) Increase to 390pF when fIN ≤ 100kHz for improved SNR and THD.
Figure 10. Recommended Driver Circuit Using the
OPA2822
Figure 9. Timing for the Switches in Figure 2
22pF
24.9Ω
DRIVING THE INPUTS
The external circuits driving the ADS1605/6 inputs must
be able to handle the load presented by the switching
capacitors within the ADS1605/6. The input switches
S1 in Figure 8 are closed approximately one half of the
sampling period, tsample, allowing only ≈12ns for the internal capacitors to be charged by the inputs, when fCLK
= 40MHz.
Figure 10 and Figure 11 show the recommended circuits when using single-ended or differential op amps,
respectively. The analog inputs must be driven differentially to achieve optimum performance. The external capacitors, between the inputs and from each input to
18
AINP
392Ω
392Ω
100pF
−VIN
VCM
ADS1605
THS4503
100pF
+VIN
392Ω
392Ω
ADS1606
24.9Ω
AINN
100pF
22pF
Figure 11. Recommended Driver Circuits Using
the THS4503 Differential Amplifier
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SBAS274H − MARCH 2003 − REVISED MAY 2007
REFERENCE INPUTS (VREFN, VREFP, VMID)
The ADS1605/6 can operate from an internal or external voltage reference. In either case, the reference voltage VREF is set by the differential voltage between
VREFN and VREFP: VREF = (VREFP – VREFN).
VREFP and VREFN each use two pins, which should
be shorted together. VMID equals approximately 2.5V
and is used by the modulator. VCAP connects to an internal node and must also be bypassed with an external
capacitor. For the best analog performance, it is recommended that an external reference voltage (VREF) of
3.0V be used.
INTERNAL REFERENCE (REFEN = LOW)
To use the internal reference, set the REFEN pin low.
This activates the internal circuitry that generates the
reference voltages. The internal reference voltages are
applied to the pins. Good bypassing of the reference
pins is critical to achieve optimum performance and is
done by placing the bypass capacitors as close to the
pins as possible. Figure 12 shows the recommended
bypass capacitor values. Use high quality ceramic capacitors for the smaller values. Avoid loading the internal reference with external circuitry. If the ADS1605/6
internal reference is to be used by other circuitry, buffer
the reference voltages to prevent directly loading the
reference pins.
ADS1605
ADS1606
10µF
0.1µF
VREFP
VREFP
in the Electrical Characteristics table. Typically VREFP
= 4V, VMID = 2.5V and VREFN = 1V. The external circuitry must be capable of providing both a dc and a transient current. Figure 13 shows a simplified diagram of
the internal circuitry of the reference when the internal
reference is disabled. As with the input circuitry,
switches S1 and S2 open and close as shown in
Figure 9.
ADS1605
ADS1606
S1
VREFP
VREFP
S2
300Ω
VREFN
VREFN
50pF
S1
Figure 13. Conceptual Internal Circuitry for the
Reference When REFEN = High
Figure 14 shows the recommended circuitry for driving
these reference inputs. Keep the resistances used in
the buffer circuits low to prevent excessive thermal
noise from degrading performance. Layout of these circuits is critical, make sure to follow good high-speed
layout practices. Place the buffers and especially the
bypass capacitors as close to the pins as possible.
VCAP is unaffected by the setting on REFEN and must
be bypassed when using the internal or an external reference.
392Ω
0.001µF
22µF
22µF
ADS1605
ADS1606
VMID
0.1µF
10µF
0.1µF
VREFP
VREFP
OPA2822
10µF
4V
0.1µF
392Ω
22µF
0.1µF
VREFN
VREFN
10µF
0.001µF
22µF
22µF
0.1µF
VMID
OPA2822
VCAP
10µF
2.5V
0.1µF
0.1µF
392Ω
0.001µF
AGND
Figure 12. Reference Bypassing When Using the
Internal Reference
EXTERNAL REFERENCE (REFEN = HIGH)
To use an external reference, set the REFEN pin high.
This deactivates the internal generators for VREFP,
VREFN and VMID, and saves approximately 25mA of
current on the analog supply (AVDD). The voltages applied to these pins must be within the values specified
22µF
VREFN
VREFN
OPA2822
1V
10µF
0.1µF
VCAP
0.1µF
AGND
Figure 14. Recommended Buffer Circuit When
Using an External Reference
19
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SBAS274H − MARCH 2003 − REVISED MAY 2007
CLOCK INPUT (CLK)
The ADS1605/6 requires an external clock signal to be
applied to the CLK input pin. The sampling of the modulator is controlled by this clock signal. As with any highspeed data converter, a high quality clock is essential
for optimum performance. Crystal clock oscillators are
the recommended CLK source; other sources such as
frequency synthesizers are usually not adequate. Make
sure to avoid excess ringing on the CLK input; keeping
the trace as short as possible will help.
Measuring high frequency, large amplitude signals requires tight control of clock jitter. The uncertainty during
sampling of the input from clock jitter limits the maximum achievable SNR. This effect becomes more pronounced with higher frequency and larger magnitude inputs. Fortunately, the ADS1605/6 oversampling
topology reduces clock jitter sensitivity over that of Nyquist rate converters like pipeline and successive
approximation converters by a factor of Ǹ8.
In order to not limit the ADS1605/6 SNR performance,
keep the jitter on the clock source below the values
shown in Table 1. When measuring lower frequency
and lower amplitude inputs, more CLK jitter can be tolerated. In determining the allowable clock source jitter,
select the worst-case input (highest frequency, largest
amplitude) that will be seen in the application.
Table 1. Maximum Allowable Clock Source Jitter
for Different Input Signal Frequencies and
Amplitude
MAXIMUM
AMPLITUDE
MAXIMUM
ALLOWABLE
CLOCK SOURCE
JITTER
2MHz
−2dB
1.9ps
2MHz
−20dB
14ps
1MHz
−2dB
3.8ps
1MHz
−20dB
28ps
500kHz
−2dB
7.6ps
500kHz
−20dB
57ps
100kHz
−2dB
38ps
100kHz
−20dB
285ps
INPUT SIGNAL
MAXIMUM
FREQUENCY
Likewise, when the input is negative out-of-range by going below the negative full-scale value of –1.467VREF,
the output clips to 8000h and the OTR output goes high.
The OTR remains high while the input signal is out-ofrange.
Table 2. Output Code Versus Input Signal
INPUT SIGNAL
(INP – INN)
IDEAL OUTPUT
CODE(1)
OTR
≥+1.467VREF (> 0dB)
7FFFH
1
1.467VREF (0dB)
7FFFH
0
+1.467V REF
0001H
0
2 15 * 1
0
0000H
0
−1.467V REF
FFFFH
0
8000H
0
8000H
1
2 15
*1
ǒ2 2 * 1 Ǔ
15
−1.467V REF
15
ǒ2 2 * 1 Ǔ
v −1.467V REF
15
15
(1) Excludes effects of noise, INL, offset and gain errors.
OUT-OF-RANGE INDICATION (OTR)
If the output code on DOUT[15:0] exceeds the positive
or negative full-scale, the out-of-range digital output
OTR will go high on the falling edge of DRDY. When the
output code returns within the full-scale range, OTR returns low on the falling edge of DRDY.
DATA RETRIEVAL
Data retrieval is controlled through a simple parallel interface. The falling edge of the DRDY output indicates
new data are available. To activate the output bus, both
CS and RD must be low, as shown in Table 3. Make
sure the DOUT bus does not drive heavy loads (>
20pF), as this will degrade performance. Use an external buffer when driving an edge connector or cables.
Table 3. Truth Table for CS and RD
CS
RD
0
0
Active
0
1
High impedance
DATA FORMAT
1
0
High impedance
The 16-bit output data are in binary two’s complement
format as shown in Table 2. When the input is positive
out-of-range, exceeding the positive full-scale value of
1.467VREF, the output clips to all 7FFFh and the OTR
output goes high.
1
1
High impedance
20
DOUT[15:0]
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SBAS274H − MARCH 2003 − REVISED MAY 2007
RESETTING THE ADS1605
RESETTING THE ADS1606
The ADS1605 and ADS1606 (with FIFO disabled) are
asynchronously reset when the RESET pin is taken low.
During reset, all of the digital circuits are cleared,
DOUT[15:0] are forced low, and DRDY forced high. It
is recommended that the RESET pin be released on the
falling edge of CLK. Afterwards, DRDY goes low on the
second rising edge of CLK. Allow 47 DRDY cycles for
the digital filter to settle before retrieving data. See
Figure 3 for the timing specifications.
The ADS1606 with the FIFO enabled requires a different reset sequence than the ADS1605, as shown in
Figure 16. Ignore any DRDY toggles that occur while
RESET is low. Release RESET on the rising edge of
CLK, then afterwards toggle RD to complete the reset
sequence.
Reset can be used to synchronize multiple ADS1605s.
All devices to be synchronized must use a common
CLK input. With the CLK inputs running, pulse RESET
on the falling edge of CLK, as shown in Figure 15. Afterwards, the converters will be converting synchronously
with the DRDY outputs updating simultaneously. After
synchronization, allow 47 DRDY cycles (t12) for output
data to fully settle.
CLK
RESET
Ignore
t26
DRDY
RD
Toggle RD to complete reset sequence
ADS16051
RESET
Clock
RESET
CLK
DRDY
DOUT[15:0]
DRDY1
DOUT[15:0]1
ADS16052
RESET
CLK
DRDY
DOUT[15:0]
DRDY2
DOUT[15:0]2
Figure 16. Resetting the ADS1606 with the FIFO
Enabled
After resetting, the settling time for the ADS1606 is 47
CLK cycles, regardless of the FIFO level. Therefore, for
higher FIFO levels, it takes fewer DRDY cycles to settle
because the DRDY period is longer. Table 4 shows the
number of DRDY cycles required to settle for each FIFO
level.
CLK
Table 4. ADS1606 Reset Settling
RESET
t12
DRDY1
Settled
Data
DOUT[15:0]1
DRDY2
FIFO LEVEL
FILTER SETTLING TIME AFTER RESET
(t26 in units of DRDY cycles )
2
24
4
12
6
8
8
6
10
5
12
4
14
4
Settled
Data
DOUT[15:0]2
Synchronized
Figure 15. Synchronizing Multiple Converters
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SETTLING TIME
IMPULSE RESPONSE
The settling time is an important consideration when
measuring signals with large steps or when using a multiplexer in front of the analog inputs. The ADS1605/6
digital filter requires time for an instantaneous change
in signal level to propagate to the output.
Figure 18 plots the normalized response for an input
applied at t = 0 with 2XMODE = low. The X-axis units of
time are DRDY cycles (for the ADS1605 or the ADS1606
with FIFO disabled). As shown in Figure 18, the peak of
the impulse takes 26 DRDY cycles to propagate to the
output. For fCLK = 40MHz, a DRDY cycle is 0.2µs in
duration and the propagation time (or group delay) is 26
× 0.2µs = 5.2µs.
Figure 17 shows the settling error as a function of time
for a full-scale signal step applied at t = 0 with
2XMODE = low. This figure uses DRDY cycles (for the
ADS1605 or the ADS1606 with FIFO disabled) for the
time scale (X-axis). After 47 DRDY cycles, the settling
error drops below 0.001%. For fCLK = 40MHz, this corresponds to a settling time of 9.4µs.
101
Settling Error (%)
0.8
0.6
0.4
0.2
0
−0.2
−0.4
100
0
5
10
15
20
25
30
35
40
Time (DRDY cycles)
10−1
10−2
Figure 18. Impulse Response
10−3
10−4
25
30
35
40
Settling Time (DRDY cycles)
Figure 17. Settling Time
22
1.0
Normalized Responce
Be sure to allow the filter time to settle after applying a
large step in the input signal, switching the channel on
a multiplexer placed in front of the inputs, resetting the
ADS1605/6, or exiting the power-down mode,
45
50
45
50
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FREQUENCY RESPONSE
0.0025
0.0015
0.0010
0.0005
0
−0.0005
−0.0010
−0.0015
−0.0020
Figure 20 shows the passband ripple from dc to 2.2MHz
(fCLK = 40MHz). Figure 21 shows a closer view of the
passband transition by plotting the response from
2.0MHz to 2.5MHz (fCLK = 40MHz).
0
0.5
1.0
1.5
2.0
2.5
Frequency (MHz)
Figure 20. Passband Ripple
1
0
−1
Magnitude (dB)
The overall frequency response repeats at multiples of
the CLK frequency. To help illustrate this, Figure 22
shows the response out to 120MHz (fCLK = 40MHz).
Notice how the passband response repeats at 40MHz,
80MHz and 120MHz; it is important to consider this
when there is high-frequency noise present with the signal. The modulator bandwidth extends to 100MHz.
High-frequency noise around 40MHz and 80MHz will
not be attenuated by either the modulator or the digital
filter. This noise will alias back in-band and reduce the
overall SNR performance unless it is filtered out prior to
the ADS1605/6. To prevent this, place an anti-alias filter
in front of the ADS1605/6 that rolls off before 37MHz.
fC LK = 40MHz
0.0020
Magnitude (dB)
The linear phase FIR digital filter sets the overall frequency response. The decimation rate is set to 8
(2XMODE = low) for all the figures shown in this section.
Figure 19 shows the frequency response from dc to
20MHz for fCLK = 40MHz. The frequency response of
the ADS1605/6 filter scales directly with CLK frequency.
For example, if the CLK frequency is decreased by half
(to 20MHz), the values on the X-axis in Figure 19 would
need to be scaled by half, with the span becoming dc to
10MHz.
−2
−3
−4
−5
fCL K = 40MHz
−6
20
−7
fCL K = 40MHz
2.0 2.05
0
2.1 2.15
2.2 2.25
2.3 2.35
2.4 2.45 2.5
Magnitude (dB)
Frequency (MHz)
−20
Figure 21. Passband Transition
−40
−60
−80
20
−100
fCL K = 40MHz
0
0
2
4
6
8
10
12
14
16
Frequency (MHz)
Figure 19. Frequency Response
18
20
Magnitude (dB)
−120
−20
−40
−60
−80
−100
0
20
40
60
80
100
120
Frequency (MHz)
Figure 22. Frequency Response Out to 120MHz
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SBAS274H − MARCH 2003 − REVISED MAY 2007
FIFO (ADS1606 ONLY)
The ADS1606 includes an adjustable level first-in firstout buffer (FIFO) for the output data. The FIFO allows
data to be temporarily stored within the ADS1606 to
provide more flexibility for the host controller when retrieving data. Pins FIFO_LEV[2:0] set the level or depth
of the FIFO. Note that these pins must be left unconnected on the ADS1605. The FIFO is enabled by setting
at least one of the FIFO_LEV inputs high. Table 5
shows the corresponding FIFO level and DRDY period
for the different combinations of FIFO_LEV[2:0] settings. For the best performance when using the FIFO,
it is recommended to:
1. Set IOVDD = 3V.
2. Synchronize data retrieval with CLK.
3. Minimize loading on outputs DOUT[15:0].
4. Ensure rise and fall times on CLK and RD are 1ns
or longer.
Table 5. FIFO Buffer Level Settings for the
ADS1606
FIFO_LEV[2:0]
FIFO BUFFER LEVEL
DRDY PERIOD
000
0: disabled,
operates like ADS1605
8/fCLK
001
2
010
4
16/fCLK
32/fCLK
011
6
48/fCLK
64/fCLK
100
8
101
10
110
12
80/fCLK
96/fCLK
111
14
112/fCLK
FIFO Operation
The ADS1606 FIFO collects the number of output readings set by the level corresponding to the
FIFO_LEV[2:0] setting. When the specified level is
reached, DRDY is pulsed high, indicating the data in the
FIFO are ready to be read. The DRDY period is a function of the FIFO level, as shown in Table 5. To read the
data, make sure CS is low (it is acceptable to tie it low)
and then take RD low. The first, or oldest, data will be
presented on the data output pins. After reading this
data, advance to the next data reading by toggling RD.
On the next falling edge of RD, the second data are
present on the data output pins. Continue this way until
all the data have been read from the FIFO, making sure
to take RD high when complete. Afterwards, wait until
DRDY toggles and repeat the readback cycle.
Figure 23 shows an example readback when
FIFO_LEV[2:0] = 010 (level = 4).
Readback considerations
The exact number of data readings set by the FIFO level must be read back each time DRDY toggles. The one
exception is that readback can be skipped entirely. In
this case, the DRDY period increases to 128 CLK period. Figure 24 shows an example when readback is
skipped with the FIFO level = 4. Do not read back more
or less readings from the FIFO than set by the level.
This interrupts the FIFO operation and can cause
DRDY to stay low indefinitely. If this occurs, the RESET
pin must be toggled followed by a RD pulse. This resets
the ADS1606 FIFO and also the digital filter, which then
must settle afterwards before valid data is ready. See
the section, Resetting the ADS1606, for more details.
Also note that the RD signal is independent of the CS
signal. Therefore, when multiple devices are used, the
RD signal should not be shared. Alternatively, individual
RD signals can be generated by performing an OR operation with the CS signal.
Setting the FIFO Level
The FIFO level setting is usually a static selection that
is set when power is first applied to the ADS1606. If the
FIFO level needs to be changed after powerup, there
are two options. One is to asynchronously set the new
value on pin FIFO_LEV[2:0] then toggle RESET. Remember that the ADS1606 will need to settle after resetting. See the section, Resetting the ADS1606, for
more details. The other option avoids requiring a reset,
but needs synchronization of the FIFO level change
with the readback. The FIFO_LEV[2:0] pins have to be
changed after RD goes high after reading the first data,
but before RD goes low to read the last data from the
FIFO. The new FIFO level becomes active immediately
and the DRDY period adjusts accordingly. When decreasing the FIFO level this way, make sure to give adequate time for readback of the data before setting the
new, smaller level. Figure 25 shows an example of a
synchronized FIFO level change from 4 to 8.
DRDY
CS(1)
RD
DOUT[15:0]
Data1(2)
Data2
Data3
Data4
(1) CS can be tied low.
(2) Data1 is the oldest data and Data4 is the most recent.
Figure 23. Example of FIFO Readback when FIFO Level = 4
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SBAS274H − MARCH 2003 − REVISED MAY 2007
32/fCLK
128/fCLK
DRDY
RD
Figure 24. Example of Skipping Readback when FIFO Level = 4
32/fCLK
64/fCLK
DRDY
RD
FIFO_LEV[2:0]
010 (Level = 4)
100 (Level = 8)
Change FIFO_LEV[2:0] here
Figure 25. Example of Synchronized Change of FIFO Level from 4 to 8
ANALOG POWER DISSIPATION
An external resistor connected between the RBIAS pin
and the analog ground sets the analog current level, as
shown in Figure 26. The current is inversely proportional to the resistor value. Table 6 shows the recommended values of RBIAS for different CLK frequencies.
Notice that the analog current can be reduced when using a slower frequency CLK input because the modulator has more time to settle. Avoid adding any capacitance in parallel to RBIAS , since this will interfere with
the internal circuitry used to set the biasing.
Table 6. Recommended RBIAS Resistor Values for
Different CLK Frequencies
fCLK
DATA
RATE
RBIAS
TYPICAL POWER
DISSIPATION WITH REFEN
HIGH
16MHz
2MHz
60kΩ
315mW
24MHz
3MHz
50kΩ
400mW
32MHz
4MHz
45kΩ
475mW
40MHz
5MHz
37kΩ
570mW
POWER DOWN (PD)
ADS1605
ADS1606
RBIAS
RBIAS
AGND
Figure 26. External Resistor Used to Set Analog
Power Dissipation
When not in use, the ADS1605/6 can be powered down
by taking the PD pin low. All circuitry will be shutdown,
including the voltage reference. To minimize the digital
current during power down, stop the clock signal supplied to the CLK input. There is an internal pull-up resistor of 170kΩ on the PD pin, but it is recommended that
this pin be connected to IOVDD if not used. If using the
ADS1606 with the FIFO enabled, issue a reset after exiting power-down mode. Make sure to allow time for the
reference to start up after exiting power-down mode.
The internal reference typically requires 15ms. After the
reference has stabilized, allow at least 100 DRDY
cycles for the modulator and digital filter to settle before
retrieving data.
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POWER SUPPLIES
main supply bus should also be bypassed with a bank
of capacitors from 47µF to 0.1µF, as shown.
Three supplies are used on the ADS1605/6: analog
(AVDD), digital (DVDD) and digital I/O (IOVDD). Each
supply must be suitably bypassed to achieve the best
performance. It is recommended that a 1µF and 0.1µF
ceramic capacitor be placed as close to each supply pin
as possible. Connect each supply-pin bypass capacitor
to the associated ground, as shown in Figure 27. Each
The IO and digital supplies (IOVDD and DVDD) can be
connected together when using the same voltage. In
this case, only one bank of 47µF to 0.1µF capacitors is
needed on the main supply bus, though each supply pin
must still be bypassed with a 1µF and 0.1µF ceramic capacitor.
DVDD
47µF
4.7µF
1µF
0.1µF
47µF
4.7µF
1µF
0.1µF
IOVDD
CP
AVDD
CP
AVDD
54
53
52
51
DGND
2
55
DVDD
AGND
57
DGND
1
58
IOVDD
0.1µF
AGND
1µF
AGND
4.7µF
AVDD
47µF
CP
CP
If using separate analog and
digital ground planes, connect
together on the ADS1605/6 PCB.
3
6
AGND
7
AVDD
9
AGND
CP
DGND
AGND
NOTE: CP = 1µF  0.1µF
ADS1605
ADS1606
CP
10 AVDD
11 AGND
19
25
CP
Figure 27. Recommended Power-Supply Bypassing
26
DVDD
DGND
18
DGND
12 AVDD
DVDD
CP
26
CP
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SBAS274H − MARCH 2003 − REVISED MAY 2007
2X MODE
The 2XMODE digital input determines the performance
(16-bit or 14-bit) by setting the oversampling ratio.
When 2XMODE = low, the oversampling ratio = 8 for
16-bit performance. When 2XMODE = high, the oversampling ratio = 4 for 14-bit performance. Note that
when 2XMODE is high, all 16 bits of DOUT remain active. Decreasing the oversampling ratio from 8 to 4
doubles the data rate in 2X mode. For fCLK = 40MHz,
the data rate then becomes 10MSPS. In addition, the
group delay decreases to 0.9µs and the settling time becomes 1.3µs or 13 DRDY cycles. With the reduced
oversampling in 2X mode, the noise increases. Typical
SNR performance degrades by 14dB. THD remains
approximately the same. There is an internal pull-down
resistor of 170kΩ on the 2XMODE; however, it is recommended this pin be forced either high or low. For
more information on the performance of the 2X mode,
see application note Operating the ADS1605 and
ADS1606 in 2X Mode: 10MSPS (SLAA180), available
for download at www.ti.com.
LAYOUT ISSUES
The ADS1605/6 is a very high-speed, high-resolution
data converter. In order to achieve the maximum performance, careful attention must be given to the printed
circuit board (PCB) layout. Use good high-speed techniques for all circuitry. Critical capacitors should be
placed close to pins as possible. These include capacitors directly connected to the analog and reference inputs and the power supplies. Make sure to also properly
bypass all circuitry driving the inputs and references.
Two approaches can be used for the ground planes: either a single common plane; or two separate planes,
one for the analog grounds and one for the digital
grounds. When using only one common plane, isolate
the flow of current on pin 57 from pin 1; use breaks on
the ground plane to accomplish this. Pin 57 carries the
switching current from the analog clocking for the modulator and can corrupt the quiet analog ground on pin 1.
When using two planes, it is recommended that they be
tied together right at the PCB. Do not try to connect the
ground planes together after running separately
through edge connectors or cables as this reduces performance and increases the likelihood of latchup.
In general, keep the resistances used in the driving circuits for the inputs and reference low to prevent excess
thermal noise from degrading overall performance.
Avoid having the ADS1605/6 digital outputs drive heavy
loads. Buffers on the outputs are recommended unless
the ADS1605/6 is connected directly to a DSP or controller situated nearby. Additionally, make sure the digital inputs are driven with clean signals as ringing on the
inputs can introduce noise.
The ADS1605/6 uses TI PowerPAD technology. The
PowerPAD is physically connected to the substrate of
the silicon inside the package and must be soldered to
the analog ground plane on the PCB using the exposed
metal pad underneath the package for proper heat
dissipation. Please refer to application report
SLMA002, located at www.ti.com, for more details on
the PowerPAD package.
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SBAS274H − MARCH 2003 − REVISED MAY 2007
APPLICATIONS INFORMATION
INTERFACING THE ADS1605 TO THE
TMS320C6000
Figure 28 illustrates how to directly connect the
ADS1605 to the TMS320C6000 DSP. The processor
controls reading using output ARE. The ADS1605 is selected using the DSP control output, CE2. The
ADS1605 16-bit data output bus is directly connected
to the TMS320C6000 data bus. The data ready output
from the ADS1605, DRDY, drives interrupt EXT_INT7
on the TMS320C6000.
INTERFACING THE ADS1606 TO THE
TMS320C6000
Figure 29 illustrates how to directly connect the
ADS1606 to the TMS320C6000 DSP. The processor
controls reading using output ARE. The ADS1606 is
permanently selected by grounding the CS pin. The
ADS1606 16-bit data output bus is directly connected
to the TMS320C6000 data bus. The data ready output
from the ADS1606, DRDY, drives interrupt EXT_INT7
on the TMS320C6000.
ADS1606
ADS1605
16
DOUT[15:0]
TMS320C6000
16
DOUT[15:0]
XD[15:0]
DRDY
DRDY
TMS320C6000
XD[15:0]
EXT_INT7
EXT_INT7
CS
CS
CE2
RD
RD
ARE
Figure 28. ADS1605—TMS320C6000 Interface
Connection
28
ARE
Figure 29. ADS1606—TMS320C6000 Interface
Connection
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INTERFACING THE ADS1605 TO THE
TMS320C5400
INTERFACING THE ADS1606 TO THE
TMS320C5400
Figure 30 illustrates how to connect the ADS1605 to the
TMS320C5400 DSP. The processor controls the reading using the outputs R/W and IS. The I/O space select
signal (IS) is optional and is used to prevent the
ADS1605 RD input from being strobed when the DSP
is accessing other external memory spaces (address or
data). This can help reduce the possibility of digital
noise coupling into the ADS1605. When not using this
signal, replace NAND gate U1 with an inverter between
R/W and RD. Two signals, IOSTRB and A15, combine
using NAND gate U2 to select the ADS1605. If there are
no additional devices connected to the TMS320C5400
I/O space, U2 can be eliminated. Simply connect
IOSTRB directly to CS. The ADS1605 16-bit data output bus is directly connected to the TMS320C5400 data
bus. The data ready output from the ADS1605, DRDY,
drives interrupt INT3 on the TMS320C5400.
Figure 31 illustrates how to directly connect the
ADS1606 to the TMS320C5400 DSP. The processor
controls reading using outputs R/W and IS. The
ADS1606 is permanently selected by grounding the CS
pin. If there are any additional devices connected to
theTMS320C5400 I/O space, address decode logic will
be required between the ADC and the DSP to prevent
data bus contention and ensure only one device at a
time is selected. The ADS1606 16-bit data output bus
is directly connected to the TMS320C5400 data bus.
The data ready output from the ADS1606, DRDY,
drives interrupt INT3 on the TMS320C5400.
ADS1606
16
DOUT[15:0]
D[15:0]
DRDY
ADS1605
16
DOUT[15:0]
INT3
CS
U2
RD
U1
INT3
TMS320C5400
D[15:0]
DRDY
TMS320C5400
CS
RD
U1
R/W
IS
IOSTRB
A15
R/W
IS
Figure 30. ADS1605—TMS320C5400 Interface
Connection
Figure 31. ADS1606—TMS320C5400 Interface
Connection
Code Composer Studio, available from TI, provides
support for interfacing TI DSPs through a collection of
data converter plugins. Check the TI website, located
at www.ti.com/sc/dcplug−in, for the latest information
on ADS1605/6 support.
29
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SBAS274H − MARCH 2003 − REVISED MAY 2007
Revision History
DATE
REV
PAGE
SECTION
5/15/07
H
24
Readback Considerations
DESCRIPTION
Added last three sentences.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
30
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS1605IPAPR
ACTIVE
HTQFP
PAP
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS1605I
ADS1605IPAPT
ACTIVE
HTQFP
PAP
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS1605I
ADS1605IPAPTG4
ACTIVE
HTQFP
PAP
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS1605I
ADS1606IPAPT
ACTIVE
HTQFP
PAP
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS1606I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS1605IPAPR
HTQFP
PAP
64
1000
330.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
ADS1605IPAPT
HTQFP
PAP
64
250
180.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
ADS1606IPAPT
HTQFP
PAP
64
250
180.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS1605IPAPR
HTQFP
PAP
64
1000
350.0
350.0
43.0
ADS1605IPAPT
HTQFP
PAP
64
250
213.0
191.0
55.0
ADS1606IPAPT
HTQFP
PAP
64
250
213.0
191.0
55.0
Pack Materials-Page 2
www.ti.com
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