Texas Instruments | Dual 8-Bit Multiplying Digital-to-Analog Converter (Rev. B) | Datasheet | Texas Instruments Dual 8-Bit Multiplying Digital-to-Analog Converter (Rev. B) Datasheet

Texas Instruments Dual 8-Bit Multiplying Digital-to-Analog Converter (Rev. B) Datasheet
SLAS063B − APRIL 1989 − REVISED MARCH 2007
D Easy Microprocessor Interface
D On-Chip Data Latches
D Digital Inputs Are T TL-Compatible With
D
D
D
10.8-V to 15.75-V Power Supply
Monotonic Over the Entire A/D Conversion
Range
Fast Control Signaling for Digital Signal
Processor (DSP) Applications Including
Interface With TMS320
CMOS Technology
KEY PERFORMANCE SPECIFICATIONS
Resolution
Linearity Error
Power Dissipation
Settling Time
Propagation Delay Time
DW OR N PACKAGE
(TOP VIEW)
AGND
OUTA
RFBA
REFA
DGND
DACA/DACB
(MSB) DB7
DB6
DB5
DB4
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
OUTB
RFBB
REFB
VDD
WR
CS
DB0 (LSB)
DB1
DB2
DB3
8 bits
1/2 LSB
20 mW
100 ns
80 ns
description
The TLC7628C is a dual, 8-bit, digital-to-analog converter (DAC) designed with separate on-chip data latches
and featuring exceptionally close DAC-to-DAC matching. Data are transferred to either of the two DAC data
latches through a common, 8-bit input port. Control input DACA/DACB determines which DAC is loaded. The
load cycle of this device is similar to the write cycle of a random-access memory, allowing easy interface to most
popular microprocessor buses and output ports. Segmenting the high-order bits minimizes glitches during
changes in the most significant bits, where glitch impulse is typically the strongest.
The TLC7628C operates from a 10.8-V to 15.75-V power supply and is TTL-compatible over this range. 2- or
4-quadrant multiplying makes this device a sound choice for many microprocessor-controlled gain-setting and
signal-control applications.
The TLC7628C is characterized for operation from 0°C to +70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright  1995 − 2007, Texas Instruments Incorporated
!"# $"%&! '#(
'"! ! $#!! $# )# # #* "#
'' +,( '"! $!#- '# #!#&, !&"'#
#- && $##(
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1
SLAS063B − APRIL 1989 − REVISED MARCH 2007
functional block diagram
DB0
14
REFA
13
12
11
Data
Inputs
10
Input
Buffer
9
8
DB7
DACA/DACB
WR
CS
8
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Latch A
8
3
RFBA
4
2
OUTA
DACA
1
AGND
7
15
20
8
6
16
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
19
Logic
Control
Latch B
8
RFBB
OUTB
DACB
18
REFB
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VDD (to AGND or DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 17 V
Voltage between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD
Input voltage range, VI (to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3 V
Reference voltage range, VrefA or VrefB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
Feedback voltage range, VRFBA or VRFBB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
Output voltage range, VOA or VOB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
Peak input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 µA
Operating free-air temperature range, TA: TLC7628C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C
Case temperature for 10 seconds, TC: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . +260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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recommended operating conditions
MIN
Supply voltage, VDD
NOM
10.8
MAX
UNIT
15.75
V
± 10
Reference voltage, VrefA or VrefB
High-level input voltage, VIH
V
2.4
V
Low-level input voltage, VIL
0.8
CS setup time, tsu(CS)
CS hold time, th(CS) (see Figure 1)
V
50
ns
0
ns
DAC select setup time, tsu(DAC) (see Figure 1)
60
ns
DAC select hold time, th(DAC) (see Figure 1)
10
ns
Data bus input setup time tsu(D) (see Figure 1)
25
ns
Data bus input hold time th(D) (see Figure 1)
10
ns
Pulse duration, WR low, tw(WR) (see Figure 1)
50
ns
Operating free-air temperature, TA
TLC7628C
0
+70
°C
electrical characteristics over recommended ranges of operating free-air temperature and VDD,
VrefA = Vref B = 10 V, VOA and VOB at 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IIH
High-level input current
VI = VDD
IIL
Low-level input current
VI = 0
MIN
10
25°C
1
Full range
−10
25°C
−1
Reference input impedance REFA or REFB to
AGND
Ikg
5
DAC data latch loaded with 00000000,
VrefA = ± 10 V
Full range
± 200
25°C
± 50
DAC data latch loaded with 00000000,
VrefB = ± 10 V
Full range
OUTB
± 200
Output leakage current
25°C
Ci
Input capacitance
Co
Output capacitance (OUTA, OUTB)
UNIT
µA
A
A
µA
kΩ
nA
± 50
±1%
DC supply sensitivity ∆gain/∆VDD
Supply current
20
OUTA
Input resistance match (REFA to REFB)
IDD
MAX
Full range
∆VDD = ± 5 %
Quiescent
All digital inputs at VIHmin or VILmax
Standby
All digital inputs at 0 V or VDD
Full range
0.02
25°C
0.01
2
Full range
0.5
25°C
0.1
DB0−DB7
10
WR, CS,
DACA/DACB
15
DAC data latches loaded with 00000000
25
DAC data latches loaded with 11111111
60
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%/%
mA
pF
pF
3
SLAS063B − APRIL 1989 − REVISED MARCH 2007
operating characteristics over recommended ranges of operating free-air temperature and VDD,
VrefA = VrefB = 10 V, VOA and VOB at 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Linearity error
Settling time (to 1/2 LSB)
See Note 1
Gain error
See Note 2
REFA to OUTA
AC feedthrough
REFB to OUTB
See Note 3
UNIT
± 1/2
LSB
100
ns
Full range
±3
25°C
±2
Full range
−65
25°C
−75
LSB
dB
± 0.0035 %FSR/°C
Temperature coefficient of gain
Propagation delay (from digital input to
90% of final analog output current)
Channel-to-channel
isolation
MAX
See Note 4
80
REFA to OUTB
See Note 5
25°C
80
REFB to OUTA
See Note 6
25°C
80
ns
dB
Digital-to-analog glitch impulse area
Measured for code transition from 00000000 to 11111111,
TA = 25°C
330
nV•s
Digital crosstalk
Measured for code transition from 00000000 to 11111111,
TA = 25°C
60
nV•s
Harmonic distortion
NOTES: 1.
2.
3.
4.
5.
6.
Vi = 6 V, f = 1 kHz, TA = 25°C
−85
dB
OUTA, OUTB load = 100 Ω, Cext = 13 pF; WR and CS at 0 V; DB0−DB7 at 0 V to VDD or VDD to 0 V.
Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = Vref − 1 LSB. Both DAC latches are
loaded with 11111111.
Vref = 20 V peak-to-peak, 10-kHz sine wave
VrefA = VrefB = 10 V; OUTA/OUTB load = 100 Ω, Cext = 13 pF; WR and CS at 0 V; DB0−DB7 at 0 V to VDD or VDD to 0 V.
VrefA = 20 V peak-to-peak, 10-kHz sine wave; VrefB = 0
VrefB = 20 V peak-to-peak, 10-kHz sine wave; VrefA = 0
ÏÏÏ
th(CS)
tsu(CS)
CS
1.3 V
ÏÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏ
1.3 V
0.3 V
tsu(DAC)
DACA/DACB
1.3 V
3.5 V
th(DAC)
1.3 V
3.5 V
0.3 V
tw(WR)
WR
1.3 V
tsu(D)
DB0 −DB7
1.3 V
3.5 V
1.3 V
Data In Stable
0.3 V
th(D)
3.5 V
1.3 V
0.3 V
For all input signals, tr = tf = 5 ns (10% to 90% points).
Figure 1. Setup and Hold Times
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APPLICATION INFORMATION
This device is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant and 4-quadrant multiplication are shown in Figures 2 and 3. Input coding for unipolar and bipolar
operation are summarized in Tables 2 and 3, respectively.
VI(A)
± 10 V
R1 (see Note A)
R2 (see Note A)
RFBA
REFA
DBO
Input
Buffer
6
DACA/
DACB
15
CS
16
WR
DACA
AGND
RFBB
Control
Logic
VOA
R4 (see Note A)
C2 (see Note B)
8
Latch
8
5
OUTB
DACB
REFB
DGND
A3
AGND
R3 (see Note A)
RECOMMENDED TRIM
RESISTOR VALUES
R1, R3
R2, R4
A1
VOB
+
DB7
8
Latch
+
7
8
C1 (see Note B)
OUTA
−
17
14
−
VDD
AGND
VI(B)
± 10 V
500 Ω
150 Ω
NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment with
digital input of 255.
B. C1 and C2 phase compensation capacitors (10 pF to 15 pF) are required when using high-speed amplifiers to prevent ringing or
oscillation.
Figure 2. Unipolar Operation (2-Quadrant Multiplication)
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SLAS063B − APRIL 1989 − REVISED MARCH 2007
APPLICATION INFORMATION
VI(A)
±10 V
DGND
5
Control
Logic
CS
WR
8
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
Latch
8
5 kΩ
C2
(see Note C)
OUTB
DACB
R3 (see Note A)
VOA
R8
10 kΩ
AGND
(see Note B)
R10
20 kΩ
A4
VOB
R12
5 kΩ
20 kΩ
±10 V
VI(B)
500 Ω
150 Ω
A2
(see
Note B)
R9
A3
REFB
RECOMMENDED TRIM
RESISTOR VALUES
R1, R3
R2, R4
R4 (see Note A)
+
15
16
RFBA
10 kΩ
R11
20 kΩ
+
DACA/
DACB
AGND
A1
−
6
8
R5
−
DB7
Latch
(see
Note B)
R7
+
7
8
C1(see Note C)
RFBA
OUTA
DACA
+
Input
Buffer
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
REFA
DBO
−
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
20 kΩ
R1 (see Note A)
R2 (see Note A)
−
17
VDD
14
R6 (see Note B)
NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Adjust R1 for VOA = 0 V with
code 10000000 in DACA latch. Adjust R3 for VOB = 0 V with 10000000 in DACB latch.
B. Matching and tracking are essential for resistor pairs R6, R7, R9, and R10.
C. C1 and C2 phase compensation capacitors (10 pF to 15 pF) may be required if A1 and A3 are high-speed amplifiers.
Figure 3. Bipolar Operation (4-Quadrant Operation)
Address Bus
A8−A15
DACA/DACB
Address
Decode
Logic
A
CS
TLC7628
WR
A+1
CPU
8051
DB0
WR
DB7
ALE
AD0−AD7
Latch
Data Bus
NOTE D: A = decoded address for TLC7628 DACA
A + 1 = decoded address for TLC7628 DACB
Figure 4. TLC7628 — Intel 8051 Interface
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APPLICATION INFORMATION
A8−A15
Address Bus
DACA/DACB
Address
Decoder
Logic
VMA
A
CS
TLC7628
WR
A+1
CPU
6800
DB0
DB7
φ2
D0 −D7
Data Bus
NOTE D: A = decoded address for TLC7628 DACA
A + 1 = decoded address for TLC7628 DACB
Figure 5. TLC7628 − 6800 Interface
voltage-mode operation
The current-multiplying DAC in the TLC7628C can be operated in a voltage mode. In the voltage mode, a fixed
voltage is placed on the current output terminal. The analog output voltage is then available at the reference
voltage terminal. An example of a current-multiplying DAC operating in voltage mode is shown in Figure 6. The
relationship between the fixed input voltage and the analog output voltage is given by the following equation:
Analog output voltage = fixed input voltage (D/256)
where D = the digital input. In voltage-mode operation, these devices meet the following specification:
LINEARITY ERROR
TEST CONDITIONS
Analog output voltage for REFA, REFB
REF
(Analog output voltage)
VDD = 12 V,
R
R
2R
OUTA or OUTB at 5 V,
MIN
TA = 25°C
MAX
UNIT
1
LSB
R
2R
2R
“0”
“1”
2R
R
OUT (Fixed input voltage)
AGND
Figure 6. Current-Multiplying DAC Operating in Voltage Mode
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PRINCIPLES OF OPERATION
This device contains two, identical, 8-bit, multiplying DACs: DACA and DACB. Each DAC consists of an inverted
R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched between the DAC
output and AGND, thus maintaining a constant current in each ladder leg independent of the switch state. Most
applications require only the addition of an external operational amplifier and voltage reference. A simplified D/A
circuit for DACA or DACB with all digital inputs low is shown in Figure 7.
Figure 8 shows the DACA or DACB equivalent circuit. Both DACs share the analog ground terminal 1 (AGND).
With all digital inputs high, the reference current flows to OUTA. A small leakage current (IIkg) flows across
internal junctions, and as with most semiconductor devices, doubles every 10°C. The Co is caused by the
parallel combination of the NMOS switches and has a value that depends on the number of switches connected
to the output. The range of Co is 25 pF to 60 pF maximum. The equivalent output resistance (ro) varies with the
input code from 0.8R to 3R where R is the nominal value of the ladder resistor in the R-2R network.
The TLC7628C interfaces to a microprocessor through the data bus, CS, WR, and DACA/DACB control signals.
When CS and WR are both low, the analog output on this device, specified by the DACA/DACB control line,
responds to the activity on the DB0−DB7 data bus inputs. In this mode, the input latches are transparent and
input data directly affects the analog output. When either the CS signal or WR signal goes high, the data on the
DB0−DB7 inputs are latched until the CS and WR signals go low again. When CS is high, the data inputs are
disabled, regardless of the state of the WR signal.
The digital inputs of the TLC7628C provides TTL compatibility when operated from a supply voltage of 10.8 V
to 15.75 V.
R
R
R
REF
2R
2R
2R
2R
2R
RFB
S1
S2
S3
S8
R
OUT
AGND
DACA Data Latches and Drivers
Figure 7. Simplified Functional Circuit for DACA or DACB
RFB
R
R
REF
OUTA
1/256
COUT
Ilkg
AGND
Latch A or Latch B Loaded With 11111111
Figure 8. TLC7628 Equivalent Circuit for DACA or DACB
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PRINCIPLES OF OPERATION
Table 1. Mode Selection Table
DACA/DACB
CS
WR
DACA
DACB
L
H
X
X
L
L
H
X
L
L
X
H
Write
Hold
Hold
Hold
Hold
Write
Hold
Hold
L = low level,
H = high level,
Table 2. Unipolar Binary Code
DAC LATCH CONTENTS
(see Note 7 )
MSB
ANALOG OUTPUT
LSB
11111111
10000001
10000000
01111111
00000001
00000000
X = don’t care
Table 3. Bipolar (Offset Binary) Code
DAC LATCH CONTENTS
(see Note 8)
MSB
−VI (255/256)
−VI (129/256)
−VI (128/256) = − Vi /2
−VI (127/256)
−VI (1/256)
−VI (0/256) = 0
ANALOG OUTPUT
LSB
11111111
10000001
10000000
01111111
00000001
00000000
VI (127/128)
VI (1/128)
0V
−VI (1/128)
−VI (127/128)
−VI (128/128)
NOTES: 7. 1 LSB = (2 − 8)VI
8. 1 LSB = (2 − 7)VI
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLC7628CDW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC7628C
TLC7628CDWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
TLC7628C
TLC7628CN
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC7628CN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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24-Aug-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLC7628CDWR
Package Package Pins
Type Drawing
SOIC
DW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
10.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.3
2.7
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC7628CDWR
SOIC
DW
20
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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