Texas Instruments | DAC8801: 14-Bit, Serial Input Multiplying Digital-to-Analog Converter (Rev. B) | Datasheet | Texas Instruments DAC8801: 14-Bit, Serial Input Multiplying Digital-to-Analog Converter (Rev. B) Datasheet

Texas Instruments DAC8801: 14-Bit, Serial Input Multiplying Digital-to-Analog Converter (Rev. B) Datasheet
 DAC8801
SLAS403B – NOVEMBER 2004 – REVISED FEBRUARY 2007
14-Bit, Serial Input Multiplying Digital-to-Analog Converter
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
14-Bit Monotonic
±1 LSB INL
±0.5 LSB DNL
Low Noise: 12 nV/√Hz
Low Power: IDD = 2 µA
+2.7 V to +5.5 V Analog Power Supply
2 mA Full-Scale Current ±20%
with VREF = 10 V
0.5 µs Settling Time
4-Quadrant Multiplying Reference-Input
Reference Bandwidth: 10 MHz
±10 V Reference Input
Reference Dynamics: -105 THD
3-Wire 50-MHz Serial Interface
Tiny 8-Lead 3 x 3 mm SON and 3 x 5 mm
MSOP Packages
Industry-Standard Pin Configuration
APPLICATIONS
•
•
•
•
Automatic Test Equipment
Instrumentation
Digitally Controlled Calibration
Industrial Control PLCs
DESCRIPTION
The DAC8801 multiplying digital-to-analog converter
is designed to operate from a single 2.7-V to 5.5-V
supply.
The applied external reference input voltage VREF
determines the full-scale output current. An internal
feedback resistor (RFB) provides temperature
tracking for the full-scale output when combined with
an external I-to-V precision amplifier.
A serial-data interface offers high-speed, three-wire
microcontroller compatible inputs using data-in (SDI),
clock (CLK), and chip select (CS).
On power-up, the DAC register is filled with zeroes,
and the DAC output is at zero scale.
The DAC8801 is packaged in space-saving 8-lead
SON and MSOP packages.
14
14
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
DAC8801
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SLAS403B – NOVEMBER 2004 – REVISED FEBRUARY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
(1)
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
DAC8801
±1
±0.5
MSOP-8
DGK
-40°C to 85°C
F01
DAC8801IDGKT
Tape and Reel,
250
DAC8801
±1
±0.5
MSOP-8
DGK
-40°C to 85°C
F01
DAC8801IDGKR
Tape and Reel,
2500
DAC8801
±1
±0.5
SON-8
DRB
-40°C to 85°C
E01
DAC8801IDRBT
Tape and Reel,
250
DAC8801
±1
±0.5
SON-8
DRB
-40°C to 85°C
E01
DAC8801IDRBR
Tape and Reel,
2500
(1)
TRANSPORT
MEDIA,
QUANTITY
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or refer to our
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VDD to GND
UNITS
–0.3 to 7
V
Digital Input voltage to GND
–0.3 to +VDD + 0.3
V
VOUT to GND
–0.3 to +VDD + 0.3
V
Operating temperature range
–40 to 105
°C
VREF, RFB to GND
–25 to 25
V
Storage temperature range
–65 to 150
°C
125
°C
Junction temperature range (TJ max)
Power dissipation
Thermal impedance, RΘJA
Lead temperature, soldering
Vapor phase (60s)
Lead temperature, soldering
Infrared (15s)
(TJ max – TA) / RΘJA
W
55
°C/W
215
°C
220
°C
ESD rating, HBM
4000
V
ESD rating, CDM
1000
V
(1)
2
DAC8801
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V; IOUT = Virtual GND, GND = 0 V; VREF = 10 V; TA = Full Operating Temperature; all specifications -40°C
to 85°C unless otherwise noted.
PARAMETER
CONDITIONS
DAC8801
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
14
Bits
Relative accuracy
Differential nonlinearity
Output leakage current
Data = 0000h, TA = 25°C
Output leakage current
Data = 0000h, TA = TMAX
Full-scale gain error
All ones loaded to DAC register
±1
LSB
±0.5
LSB
10
±1
Full-scale tempco
nA
10
nA
±4
mV
±3
ppm of
FSR/°C
2
mA
50
pF
OUTPUT CHARACTERISTICS (1)
Output current
Output capacitance
REFERENCE
Code dependent
INPUT (1)
VREF Range
–15
15
V
Input resistance
5
kΩ
Input capacitance
5
pF
LOGIC INPUTS AND OUTPUT (1)
VIL
Input low voltage
VDD = 2.7V
VDD = 5V
VDD = 2.7V
2.1
VDD = 5V
2.4
0.6
V
0.8
V
V
VIH
Input high voltage
IIL
Input leakage current
10
µA
CIL
Input capacitance
10
pF
50
MHz
V
INTERFACE TIMING
fCLK
Clock input frequency
t(CH)
Clock pulse width high
10
ns
t(CL)
Clock pulse width low
10
ns
t(CSS)
CS to Clock setup time
0
ns
t(CSH)
Clock to CS hold time
10
ns
t(DS)
Data setup time
5
ns
t(DH)
Data hold time
10
ns
POWER REQUIREMENTS
VDD
2.7
IDD (normal operation)
Logic inputs = 0 V
VDD = 4.5 V to 5.5 V
VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V
VIH = VDD and VIL = GND
5.5
V
5
µA
3
5
µA
1
2.5
µA
AC CHARACTERISTICS (1) (2)
ts
(1)
(2)
To ±0.1% of full-scale, Data = 0000h to 3FFFh to 0000h
0.3
To ±0.006% of full-scale, Data = 0000h to 3FFFh to 0000h
0.5
Reference multiplying BW
VREF = 5 VPP, Data = 3FFFh
10
MHz
DAC glitch impulse
VREF = 0 V, Data = 3FFFh to 2000h
2
nV/s
Feedthrough error
VREF = 100 mVRMS, 100kHz, Data = 0000h
Digital feedthrough
CS = 1 and fCLK = 1MHz
Output voltage settling time
–70
2
µs
dB
nV/s
Specified by design and characterization, not production tested.
All ac characteristic tests are performed in a closed-loop system using the THS4011 I-to-V converter amplifier.
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ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7 V to 5.5 V; IOUT = Virtual GND, GND = 0 V; VREF = 10 V; TA = Full Operating Temperature; all specifications -40°C
to 85°C unless otherwise noted.
PARAMETER
DAC8801
CONDITIONS
Total harmonic distortion
VREF = 5 VPP, Data = 3FFFh, f = 1 kHz
Output spot noise voltage
f = 1 kHz, BW = 1 Hz
MIN
TYP
MAX
UNITS
–105
12
dB
nV/√Hz
PIN ASSIGNMENTS
DGK PACKAGE
(TOP VIEW)
DRB PACKAGE
(TOP VIEW)
CLK
1
8
CS
CLK
1
8
CS
SDI
2
7
VDD
SDI
2
7
RFB
3
6
GND
VDD
VREF
4
5
IOUT
RFB
3
6
GND
VREF
4
5
IOUT
TERMINAL FUNCTIONS
4
PIN
NAME
1
CLK
Clock input, positive edge triggered clocks data into shift register
DESCRIPTION
2
SDI
Serial register input, data loads directly into the shift register MSB first. Extra leading bits are ignored.
3
RFB
Internal matching feedback resistor. Connect to external op amp output.
4
VREF
DAC reference input pin. Establishes DAC full-scale voltage. Constant input resistance versus code.
5
IOUT
DAC current output. Connects to inverting terminal of external precision I to V op amp.
6
GND
Analog and digital ground
7
VDD
Posiitve power supply input. Specified range of operation 2.7 V to 5.5 V.
8
CS
Chip select, active low digital input. Transfers shift register data to DAC register on rising edge. See Table 1 for
operation.
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TYPICAL CHARACTERISTICS: VDD = 5 V
At TA = 25°C, +VDD = 5 V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = +25_ C
0.6
0.6
0.4
0.4
0.2
0
−0.2
0.2
0
−0.2
−0.4
−0.4
−0.6
−0.6
−0.8
−0.8
−1.0
−1.0
0
1.0
2048
4096
0
6144 8192 10240 12288 14336 16384
Digital Input Code
2048
4096
Figure 2.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
TA = −40_C
0.8
0.6
0.4
0.4
DNL (LSB)
0.6
0.2
0
−0.2
0.2
0
−0.2
−0.4
−0.4
−0.6
−0.6
−0.8
−0.8
−1.0
−1.0
0
2048
4096
6144
8192 10240 12288 14336 16384
0
2048
4096
Digital Input Code
Figure 4.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
TA = +85_ C
0.8
6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 3.
1.0
TA = +85_ C
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 1.
TA = −40_C
0.8
INL (LSB)
TA = +25_ C
0.8
DNL (LSB)
INL (LSB)
0.8
0.2
0
−0.2
0.2
0
−0.2
−0.4
−0.4
−0.6
−0.6
−0.8
−0.8
−1.0
−1.0
0
2048
4096
6144
8192 10240 12288 14336 16384
0
Digital Input Code
Figure 5.
2048
4096
6144 8192 10240 12288 14336 16384
Digital Input Code
Figure 6.
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TYPICAL CHARACTERISTICS: VDD = 5 V (continued)
At TA = 25°C, +VDD = 5 V, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
REFERENCE BANDWIDTH
1.6
VDD = +5.0V
1.2
6
0
−6
− 12
− 18
− 24
− 30
− 36
− 42
− 48
− 54
− 60
− 66
− 72
− 78
− 84
− 90
− 96
− 102
− 108
− 114
1 0
0x3FFF
0x2000
0x1000
0x0800
0x0400
0x0200
0x0100
0x0080
0x0040
0x0020
0x0010
0x0008
0x0004
0x0002
0x0001
Attenuation (dB)
Supply Current, IDD (mA)
1.4
1.0
0.8
0.6
0.4
0.2
VDD = +2.7V
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0x0000
1 00
10 0k
1M
Figure 7.
Figure 8.
DAC SETTLING TIME
DAC GLITCH
Voltage Output Settling
Trigger Pulse
Output Voltage (50mV/div)
Output Voltage (5V/div)
10k
10M
100 M
Bandwidth (H z )
Logic Input Voltage (V)
Time (0.1µs/div)
Code: 3FFFh to 2000h
Trigger Pulse
Time (0.2µs/div)
Figure 9.
6
1k
Figure 10.
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TYPICAL CHARACTERISTICS: VDD = 2.7 V
At TA = 25°C, +VDD = 2.7 V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
TA = +25_ C
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
1.0
TA = +25_ C
0.8
0.2
0
−0.2
0.2
0
−0.2
−0.4
−0.4
−0.6
−0.6
−0.8
−0.8
−1.0
−1.0
0
2048
4096
6144
8192 10240 12288 14336 16384
0
2048
4096
Digital Input Code
1.0
Figure 12.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.6
0.6
0.4
0.4
0.2
0
−0.2
0.2
0
−0.2
−0.4
−0.4
−0.6
−0.6
−0.8
−0.8
−1.0
−1.0
0
2048
4096
0
6144 8192 10240 12288 14336 16384
Digital Input Code
2048
4096
6144
8192 10240 12288 14336 16384
Digital Input Code
Figure 13.
Figure 14.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = +85_ C
0.8
TA = +85_ C
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
TA = −40_C
0.8
DNL (LSB)
INL (LSB)
Figure 11.
TA = −40_C
0.8
6144 8192 10240 12288 14336 16384
Digital Input Code
0.2
0
−0.2
0.2
0
−0.2
−0.4
−0.4
−0.6
−0.6
−0.8
−0.8
−1.0
−1.0
0
2048
4096
6144
8192 10240 12288 14336 16384
0
2048
4096
6144
8192 10240 12288 14336 16384
Digital Input Code
Digital Input Code
Figure 15.
Figure 16.
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THEORY OF OPERATION
The DAC8801 is a single channel current output, 16-bit digital-to-analog converter (DAC). The architecture,
illustrated in Figure 17, is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the
ladder is either switched to GND or the IOUT terminal. The IOUT terminal of the DAC is held at a virtual GND
potential by the use of an external I/V converter op amp. The R-2R ladder is connected to an external reference
input VREF that determines the DAC full-scale current. The R-2R ladder presents a code independent load
impedance to the external reference of 5 kΩ± 25%. The external reference voltage can vary in a range of -10 V
to 10 V, thus providing bipolar IOUT current operation. By using an external I/V converter and the DAC8801 RFB
resistor, output voltage ranges of -VREF to VREF can be generated.
When using an external I/V converter and the DAC8801 RFB resistor, the DAC output voltage is given by
Equation 1:
V OUT + −VREF CODE
16384
(1)
R
R
R
VREF
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
2R
RFB
IOUT
GND
Figure 17. Equivalent R-2R DAC Circuit
Each DAC code determines the 2R leg switch position to either GND or IOUT. Because the DAC output
impedance as seen looking into the IOUT terminal changes versus code, the external I/V converter noise gain will
also change. Because of this, the external I/V converter op amp must have a sufficiently low offset voltage such
that the amplifier offset is not modulated by the DAC IOUT terminal impedance change. External op amps with
large offset voltages can produce INL errors in the transfer function of the DAC8801 due to offset modulation
versus DAC code. For best linearity performance of the DAC8801, an op amp (OPA277) as shown in Figure 18
is recommended. This circuit allows VREF to swing from -10V to +10V.
VDD
U1
VDD
VREF
RFB
DAC8801
U2 15 V
IOUT
_
V+
OPA277
GND
+
V−
−15 V
Figure 18. Voltage Output Configuration
8
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SDI
D13
D12
D11
D10
D9
D8
D7
D6
D1
D0
CLK
t(DS)
t(CH)
t(CL)
t(DH)
t(CSS)
t(CSH)
CS
Figure 19. DAC8801 Timing Diagram
Table 1. Control Logic Truth Table (1)
(1)
CLK
CS
Serial Shift Register
DAC Register
X
H
No effect
Latched
↑+
L
Shift register data advanced one bit
Latched
X
H
No effect
Latched
X
↑+
Shift register data transferred to DAC register
New data loaded from serial register
↑+ Positive logic transition; X = Don't care
Table 1. Serial Input Register Data Format, Data Loaded MSB First
Bit
B13
(MSB)
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
(LSB)
Data (1)
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(1)
A full 16-bit data word can be loaded into the serial register, but only the last 14 bits are transferred to the DAC register when CS goes
high.
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APPLICATION INFORMATION
Stability Circuit
For a current-to-voltage design as shown in Figure 20, the DAC8801 current output (IOUT) and the connection
with the inverting node of the op amp should be as short as possible and according to correct PCB layout
design. For each code change there is a step function. If the GBP of the op amp is limited and parasitic
capacitance is excessive at the inverting node then gain peaking is possible. Therefore, for circuit stability, a
compensation capacitor C1 (4 pF to 20 pF typ) can be added to the design as shown in Figure 20.
VDD
VDD
VREF
RFB
_
IOUT
U1
VREF
C1
U2
VOUT
+
GND
Figure 20. Gain Peaking Prevention Circuit With Compensation Capacitor
Positive Voltage Output Circuit
As shown in Figure 21, in order to generate a positive voltage output, a negative reference is input to the
DAC8801. This design is suggested instead of using an inverting amp to invert the output due to tolerance
errors of the resistor. For a negative reference, VOUT and GND of the reference are level-shifted to a virtual
ground and a -2.5 V input to the DAC8801 with an op amp.
+2.5V Reference
VOUT
VIN
GND
VREF
−
+
VDD
VDD
RFB
DAC8801
−2.5 V
OPA277
C1
IOUT
OPA277
−
+
VOUT
GND
0 3 VOUT 3 +2.5 V
Figure 21. Positive Voltage Output Circuit
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APPLICATION INFORMATION (continued)
Bipolar Output Circuit
The DAC8801, as a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output IOUT is the inverse of the input reference voltage at VREF.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. As shown in Figure 22,
external op amp U4 is added as a summing amp and has a gain of 2X that widens the output span to 5 V. A
4-quadrant multiplying circuit is implemented by using a 2.5-V offset of the reference voltage to bias U4.
According to the circuit transfer equation given in Equation 2, input data (D) from code 0 to full scale produces
output voltages of VOUT = -2.5 V to VOUT = 2.5 V.
V OUT +
ǒ16,D384 * 1Ǔ
VREF
(2)
10 kW
VDD
5 kW
VREF
C2
−
RFB
VDD
+2.5 V
(+10 V)
10 kW
+
C1
DAC8801
VOUT
U4
OPA277
−
IOUT
+
GND
U2
OPA277
−2.5 V 3 VOUT 3 +2.5 V
(−10 V 3 VOUT 3 +10 V)
Figure 22. Bipolar Output Circuit
Programmable Current Source Circuit
A DAC8801 can be integrated into the circuit in Figure 23 to implement an improved Howland current pump for
precise voltage to current conversions. Bidirectional current flow and high voltage compliance are two features of
the circuit. A application of this circuit includes a 4-mA to 20-mA current transmitter with up to a 500-Ω load.
With a matched resistor network, the load current of the circuit is shown in Equation 3:
(R2 ) R3) ń R1
IL +
VREF D
R3
(3)
R24
15 kW
C1
10 pF
R14
150 kW
VDD
VDD
VREF
VREF
RFB
U1
DAC8801
U2
OPA277
R34
50 W
−
U2
OPA277
IOUT
−
VOUT
+
R1
150 kW
R2
15 kW
R3
50 W
+
IL
GND
LOAD
Figure 23. Programmable Bidirectional Current Source Circuit
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APPLICATION INFORMATION (continued)
The value of R3 in the previous equation can be reduced to increase the output current drive of U3. U3 can
drive ±20 mA in both directions with voltage compliance limited up to 15 V by the U3 voltage supply. Elimination
of the circuit compensation capacitor C1 in the circuit is not suggested because of the change in the output
impedance ZO, according to Equation 4:
R1ȀR3(R1 ) R2)
ZO +
R1(R2Ȁ ) R3Ȁ) * R1Ȁ(R2 ) R3)
(4)
As shown in Equation 4, with matched resistors, ZO is infinite and the circuit is optimum for use as a current
source. However, if unmatched resistors are used, ZO is positive or negative with negative output impedance
being a potential cause of oscillation. Therefore, by incorporating C1 into the circuit, possible oscillation
problems are eliminated. The value of C1 can be determined for critical applications; however, for most
applications a value of several pF is suggested.
Cross-Reference
The DAC8801 has an industry-standard pinout. Table 2 provides the cross-reference information.
Table 2. Cross Reference
PRODUCT
INL
(LSB)
DNL
(LSB)
SPECIFIED
TEMPERATURE
RANGE
DAC8801IDGK
±1
±1
DAC8801IDRB
±1
±1
PACKAGE
DESCIPTION
PACKAGE
OPTION
CROSS
REFERENCE
-40°C to +85°C
8-Lead MicroSOIC
MSOP-8
ADS5553CRM
-40°C to +85°C
8-Lead Small Outline
SON-8
N/A
Table 3. DAC8801 Revision History
Revision
Date
A
12/04
Description
Removed the "Product Preview" label.
Added information to the Features.
Added Output leakage current Data = 0000h, TA = TMAX in the Electrical Characteristics table.
Added Input high voltage for 2.7 V and 5 V in the Electrical Characteristics table.
Changed the values of the Power Requirements and the AC characteristics in the Electrical Characteristics table.
B
10/06
Changed the ESD rating, HBM from 1500 to 4000 in the Absolute Maximum Ratings.
Revised Figure 8.
12
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
12-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC8801IDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
F01
DAC8801IDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
F01
DAC8801IDGKTG4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
F01
DAC8801IDRBT
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
E01
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Aug-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC8801IDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8801IDGKT
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8801IDRBT
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC8801IDGKR
VSSOP
DGK
8
2500
350.0
350.0
43.0
DAC8801IDGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
DAC8801IDRBT
SON
DRB
8
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRB0008A
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
1.5 0.1
DIM A
OPT 1
OPT 2
(0.1)
(0.2)
4X (0.23)
EXPOSED
THERMAL PAD
(DIM A) TYP
4
5
2X
1.95
1.75 0.1
8
1
6X 0.65
8X
PIN 1 ID
(OPTIONAL)
(0.65)
8X
0.37
0.25
0.1
0.05
C A B
C
0.5
0.3
4218875/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.5)
(0.65)
SYMM
8X (0.6)
(0.825)
8
8X (0.31) 1
SYMM
(1.75)
(0.625)
6X (0.65)
4
5
(R0.05) TYP
( 0.2) VIA
TYP
(0.23)
(0.5)
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218875/A 01/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.65)
4X (0.23)
SYMM
METAL
TYP
8X (0.6)
8X (0.31)
4X
(0.725)
8
1
(2.674)
SYMM
(1.55)
6X (0.65)
4
5
(R0.05) TYP
(1.34)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218875/A 01/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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