Texas Instruments | 16-Bit 250-KSPS Sampling CMOS Analog-to-Digital Converter (Rev. B) | Datasheet | Texas Instruments 16-Bit 250-KSPS Sampling CMOS Analog-to-Digital Converter (Rev. B) Datasheet

Texas Instruments 16-Bit 250-KSPS Sampling CMOS Analog-to-Digital Converter (Rev. B) Datasheet
 ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
16-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
105dB SFDR at 250-kHz Sample Rate
Standard ±10-V Input Range
±1.5 LSB Max INL
±1 LSB Max DNL, 16-Bits No Missing Codes
±2 mV Max Bipolar Zero Error With ±0.4
PPM/°C Drift
±0.1% FSR Max Full-Scale Error With ±2
PPM/°C Drift
Single 5-V Supply Operation
Pin-Compatible With ADS7805 (Low Speed)
and 12-Bit ADS8504/7804
Uses Internal or External Reference
Full Parallel Data Output
70-mW Typ Power Dissipation at 250 KSPS
28-Pin SSOP and SOIC Packages
Industrial Process Control
Data Acquisition Systems
Digital Signal Processing
Medical Equipment
Instrumentation
DESCRIPTION
The ADS8505 is a complete 16-bit sampling A/D
converter using state-of-the-art CMOS structures. It
contains a complete 16-bit, capacitor-based, SAR
A/D with S/H, reference, clock, interface for
microprocessor use, and 3-state output drivers.
The ADS8505 is specified at a 250-kHz sampling
rate over the full temperature range. Precision
resistors provide an industry standard ±10-V input
range, while the innovative design allows operation
from a single +5-V supply, with power dissipation
under 100 mW.
The ADS8505 is available in 28-pin SOIC and 28-pin
SSOP packages, both fully specified for operation
over the industrial –40°C to 85°C temperature range.
Clock
Successive Approximation Register and Control Logic
R/C
CS
BYTE
BUSY
CDAC
9.8 kΩ
± 10 V Input
5 kΩ
2 kΩ
Comparator
Output
Latches
and
Three
State
Drivers
Three
State
Parallel
Data
Bus
CAP
Buffer
Internal
+2.5 V Ref
4 kΩ
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2007, Texas Instruments Incorporated
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SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
ADS8505IB
NO
MISSING
CODE
±1.5
16
MINIMUM
SINAD
(dB)
86
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
LEAD
PACKAGE
DESIGNATOR
SO-28
DW
±4
15
83
ADS8505IBDBR
ADS8505IDW
DW
ADS8505IDWR
–40°C to 85°C
SSOP-28
(1)
ADS8505IBDB
DB
SO-28
ADS8505I
ADS8505IBDW
ADS8505IBDWR
–40°C to 85°C
SSOP-28
ORDERING
NUMBER
ADS8505IDB
DB
ADS8505IDBR
TRANSPORT
MEDIA, QTY
Tube, 20
Tape and Reel, 1000
Tube, 50
Tape and Reel, 2000
Tube, 20
Tape and Reel, 1000
Tube, 50
Tape and Reel, 2000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted) (2)
UNIT
±25V
VIN
Analog inputs
REF
+VANA + 0.3 V to AGND2 – 0.3 V
CAP
Indefinite short to AGND2, momentary short to VANA
±0.3 V
DGND, AGND1, AGND2
Ground voltage differences
VANA
6V
VDIG to VANA
0.3 V
VDIG
6V
Digital inputs
–0.3 V to +VDIG + 0.3 V
Maximum junction temperature
165°C
Internal power dissipation
825 mW
Lead temperature (soldering, 10s)
(1)
(2)
300°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
ELECTRICAL CHARACTERISTICS
TA = –40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted)
ADS8505I
PARAMETER
ADS8505IB
TEST CONDITIONS
UNIT
MIN
TYP
Resolution
MAX
MIN
TYP
16
MAX
16
Bits
ANALOG INPUT
Voltage range
±10
±10
V
Impedance
11.5
11.5
kΩ
50
50
pF
Capacitance
THROUGHPUT SPEED
Conversion cycle
Throughput rate
2
Acquire and convert
4
250
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250
µs
kHz
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ELECTRICAL CHARACTERISTICS (continued)
TA = –40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted)
ADS8505I
PARAMETER
ADS8505IB
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
DC ACCURACY
INL
Integral linearity error
–4
4
–1.5
1.5
LSB (1)
DNL
Differentiall linearity error
–2
2
–1
1
LSB (1)
No missing codes
15
Transition noise (2)
0.77
Full-scale error (3) (4)
Int. ref.
Full-scale error drift
Int. ref.
Full-scale error (3) (4)
Ext. 2.5-V ref.
Full-scale error drift
Ext. 2.5-V ref.
–0.5
0.5
–0.25
–0.25
0.25
–5
–0.1
5
–8
0.25
±0.01
–2
0.1
2
–8
%FSR
ppm/°C
±0.4
8
%FSR
ppm/°C
±2
±0.4
+4.75 V < VD < +5.25 V
LSB
±7
±2
Bipolar zero error drift
Bits
0.77
±7
Bipolar zero error (3)
Power supply sensitivity
(VDIG = VANA = VD)
16
mV
ppm/°C
8
LSB
AC ACCURACY
SFDR
Spurious free dynamic range
fI = 20 kHz
THD
Total harmonic distortion
fI = 20 kHz
SINAD
Signal-to-(noise + distortion)
92
–98
fI = 20 kHz
83
–60-dB Input
SNR
Signal-to-noise ratio
98
96
–92
88
–103
86
30
fI = 20 kHz
83
Full-power bandwidth (6)
88
105
86
500
dB (5)
–96
dB
88
dB
32
dB
88
dB
500
kHz
SAMPLING DYNAMICS
Aperture delay
Transient response
5
FS Step
5
2
Overvoltage recovery (7)
ns
2
150
150
µs
ns
REFERENCE
Internal reference voltage
2.48
2.5
2.52
2.48
2.5
2.52
V
Internal reference source current (must
use external buffer)
1
1
µA
Internal reference drift
8
8
ppm/°C
External reference voltage range for
specified linearity
External reference current drain
2.3
2.5
Ext. 2.5-V ref.
2.7
2.3
100
2.5
2.7
V
100
µA
V
DIGITAL INPUTS
Logic levels
VIL
Low-level input voltage
–0.3
0.8
–0.3
0.8
VIH
High-level input voltage
2.0
VDIG +0.3 V
2.0
VDIG +0.3 V
V
IIL
Low-level input current
±10
±10
µA
IIH
High-level input current
±10
±10
µA
0.4
V
DIGITAL OUTPUTS
Data format (parallel 16-bits)
Data coding (binary 2's complement)
VOL
Low-level output voltage
ISINK = 1.6 mA
VOH
High-level output voltage
ISOURCE = 500 mA
Leakage current
Hi-Z state,
VOUT = 0 V to VDIG
±5
±5
µA
Output capacitance
Hi-Z state
15
15
pF
(1)
(2)
(3)
(4)
(5)
(6)
(7)
0.4
4
4
V
LSB means least significant bit. For the 16-bit, ±10-V input ADS8505, one LSB is 305 µV.
Typical rms noise at worst case transitions and temperatures.
As measured with fixed resistors shown in Figure 27. Adjustable to zero with external potentiometer.
Full-scale error is the worst case of –full-scale or +full-scale deviation from ideal first and last code transitions, divided by the transition
voltage (not divided by the full-scale range) and includes the effect of offset error.
All specifications in dB are referred to a full-scale ±10-V input.
Full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB, or 10 bits of
accuracy.
Recovers to specified performance after 2 x FS input overvoltage.
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ELECTRICAL CHARACTERISTICS (continued)
TA = –40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted)
ADS8505I
PARAMETER
ADS8505IB
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
DIGITAL TIMING
Bus access timing
83
83
ns
Bus relinquish timing
83
83
ns
V
POWER SUPPLIES
VDIG
Digital input voltage
4.75
5
5.25
4.75
5
5.25
VANA
Analog input voltage
4.75
5
5.25
4.75
5
5.25
IDIG
Digital input current
2
5
2
5
IANA
Analog input current
12
15
12
15
mA
70
100
70
100
mW
Power dissipation
Must be ≤ VANA
fS = 250 kHz
V
mA
TEMPERATURE RANGE
Specified performance
–40
85
–40
85
°C
Derated performance (8)
–55
125
–55
125
°C
Storage
–65
150
–65
150
°C
THERMAL RESISTANCE (ΘJA)
(8)
SSOP
62
62
°C/W
SO
46
46
°C/W
The internal reference may not be started correctly beyond the industrial temperature range (–40°C to 85°C), therefore use of an
external reference is recommended.
DEVICE INFORMATION
DB OR DW PACKAGE
(TOP VIEW)
VIN 1
AGND1 2
27 VANA
REF 3
26 BUSY
CAP 4
25 CS
AGND2 5
D15 (MSB) 6
4
28 VDIG
24 R/C
23 BYTE
D14 7
22 D0 (LSB)
D13 8
21 D1
D12 9
20 D2
D11 10
19 D3
D10 11
18 D4
D9 12
17 D5
D8 13
16 D6
DGND 14
15 D7
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SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
DEVICE INFORMATION (continued)
Terminal Functions
TERMINAL
NAME
DB/DW NO.
DIGITAL
I/O
DESCRIPTION
AGND1
2
Analog ground. Used internally as ground reference point.
AGND2
5
Analog ground.
BUSY
26
O
At the start of a conversion, BUSY goes low and stays low until the conversion is
completed and the digital outputs have been updated.
BYTE
23
I
Selects 8 most significant bits (low) or 8 least significant bits (high).
CAP
4
CS
25
Reference buffer capacitor. 2.2-µF Tantalum capacitor to ground.
DGND
14
D15 (MSB)
6
O
Data bit 15. Most significant bit (MSB) of conversion results. Hi-Z state when CS is
high, or when R/C is low.
D14
7
O
Data bit 14. Hi-Z state when CS is high, or when R/C is low.
D13
8
O
Data bit 13. Hi-Z state when CS is high, or when R/C is low.
D12
9
O
Data bit 12. Hi-Z state when CS is high, or when R/C is low.
D11
10
O
Data bit 11. Hi-Z state when CS is high, or when R/C is low.
D10
11
O
Data bit 10. Hi-Z state when CS is high, or when R/C is low.
D9
12
O
Data bit 9. Hi-Z state when CS is high, or when R/C is low.
D8
13
O
Data bit 8. Hi-Z state when CS is high, or when R/C is low.
D7
15
O
Data bit 7. Hi-Z state when CS is high, or when R/C is low.
D6
16
O
Data bit 6. Hi-Z state when CS is high, or when R/C is low.
D5
17
O
Data bit 5. Hi-Z state when CS is high, or when R/C is low.
D4
18
O
Data bit 4. Hi-Z state when CS is high, or when R/C is low.
D3
19
O
Data bit 3. Hi-Z state when CS is high, or when R/C is low.
D2
20
O
Data bit 2. Hi-Z state when CS is high, or when R/C is low.
D1
21
O
Data bit 1. Hi-Z state when CS is high, or when R/C is low.
D0 (LSB)
22
O
Data bit 0. Least significant bit (LSB) of conversion results. Hi-Z state when CS is high,
or when R/C is low.
R/C
24
I
With CS low and BUSY high, a falling edge on R/C initiates a new conversion. With CS
low, a rising edge on R/C enables the parallel output.
REF
3
Reference input/output. 2.2-µF Tantalum capacitor to ground.
VANA
27
Analog supply input. Nominally +5 V. Decouple to ground with 0.1-µF ceramic and
10-µF tantalum capacitors.
VDIG
28
Digital supply input. Nominally +5 V. Connect directly to pin 27. Must be ≤ VANA.
VIN
1
Analog input. See Figure 28.
I
Internally ORed with R/C. If R/C is low, a falling edge on CS initiates a new conversion.
Digital ground.
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TYPICAL CHARACTERISTICS
100
95
90
fs = 250 KSPS,
fi = 20 kHz
85
-20
0
20
40
60
TA - Free-Air Temperature - ºC
-95
-90
-85
fs = 250 KSPS
-80
fi = 20 kHz
-20
0
20
40
60
TA - Free-Air Temperature - º C
fs = 250 KSPS
95
fi = 20 kHz
90
85
80
75
70
-40
80
-20
0
20
40
60
Figure 2.
Figure 3.
SIGNAL-TO-NOISE
AND DISTORTION
vs
FREE-AIR TEMPERATURE
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
SIGNAL-TO-NOISE
AND DISTORTION
vs
INPUT FREQUENCY
SNR - Signal-to-Noise Ratio - dB
85
80
75
-20
0
20
40
60
TA - Free-Air Temperature - ºC
SINAD - Signal-to-Noise and Distortion - dB
100
fs = 250 KSPS
fI = 20 kHz
95
90
85
80
75
70
1
80
10
80
TA - Free-Air Temperature - º C
Figure 1.
90
70
-40
-100
-75
-40
80
100
95
100
SNR - Signal-to-Noise Ratio - dB
THD - Total Harmonic Distortion - dB
105
80
-40
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
-105
110
100 125
105
100
95
90
85
80
75
70
65
60
1
fi - Input Frequency - kHz
10
fi - Input Frequency - kHz
100 125
Figure 4.
Figure 5.
Figure 6.
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
INTERNAL REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
2.510
115
110
105
100
95
90
85
80
Internal Reference Voltage − V
120
120
110
100
90
80
10
fi - Input Frequency - kHz
Figure 7.
100 125
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
70
2.492
60
75
1
6
TOTAL HARMONIC DISTORTION
vs
FREE-AIR TEMPERATURE
THD - Total Harmonic Distortion - dB
SFDR - Spurious Free Dynamic Range - dB
SINAD - Signal-to-Noise and Distortion - dB
SFDR - Spurious Free Dynamic Range - dB
SPURIOUS FREE DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
1
10
fi - Input Frequency - kHz
100 125
Figure 8.
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2.490
−40
−20
0
20
40
60
TA − Free-Air Temperature − 5C
Figure 9.
80
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SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
TYPICAL CHARACTERISTICS (continued)
NEGATIVE FULL-SCALE ERROR
vs
FREE-AIR TEMPERATURE
0.25
4
0.2
3
2
1
0
−1
−2
−3
−4
−5
−40
−20
0
20
40
60
TA − Free-Air Temperature − 5C
External Reference
0.15
0.1
0.05
0
−0.05
−0.1
−0.15
−0.2
−20
0
20
40
60
TA − Free-Air Temperature − 5C
0.15
0.1
0.05
0
−0.05
−0.1
−0.15
−0.2
−40
80
−20
0
20
40
60
TA − Free-Air Temperature − 5C
Figure 10.
Figure 11.
Figure 12.
POSITIVE FULL-SCALE ERROR
vs
FREE-AIR TEMPERATURE
POSITIVE FULL-SCALE ERROR
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
0.25
0.2
Internal Reference
0.1
0.05
0
−0.05
−0.1
−0.15
−0.2
−20
0
20
40
60
TA − Free-Air Temperature − 5C
0.1
0.05
0
−0.05
−0.1
17
16
15
14
13
11
−0.2
−40
80
−20
0
20
40
60
TA − Free-Air Temperature − 5C
Figure 13.
10
-40
80
-20
0
20
40
60
TA - Free-Air Temperature - ºC
Figure 14.
80
Figure 15.
PERFORMANCE
vs
CAP PIN CAPACITOR ESR
HISTOGRAM
4500
4000
18
12
−0.15
110
4028
8192
Conversions
of a DC Input
| THD |
100
3500
3000
2500
Performance
−0.25
−40
19
0.15
IDD - Supply Current - mA
0.15
80
20
External Reference
Positive Full−Scale Error − %FSR
0.2
Hits
Positive Full−Scale Error − %FSR
0.2
Internal Reference
−0.25
−40
80
NEGATIVE FULL-SCALE ERROR
vs
FREE-AIR TEMPERATURE
Negative Full−Scale Error − %FSR
5
Negative Full−Scale Error − %FSR
BPZ − Bipolar Zero Scale Error − mV
BIPOLAR ZERO SCALE ERROR
vs
FREE-AIR TEMPERATURE
2221
2000
1713
1500
SINAD
90
80
70
1000
0
2.2 mF Capacitor on
CAP Pin (pin 4)
60
500
1
−3
151
−2
−1
0
1
Code
76
2
2
3
50
0
1
2
Figure 16.
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4 5 6 7
8
ESR - Resistance - W
9
10
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
INTEGRAL NONLINEARITY
1.5
INL - LSBs
1
0.5
0
-0.5
-1
-1.5
0
16384
32768
Code
Figure 18.
49152
65536
49152
65536
DIFFERENTIAL NONLINEARITY
1
DNL - LSBs
0.5
0
-0.5
-1
0
16384
32768
Code
Figure 19.
FFT (20-kHz Input)
Amplitude - dB
20
0
-20
8192 Points
fs = 250 KSPS
fi = 20 KHz, 0dB
SINAD = 87.7 dB
THD = -103.9 dB
-40
-60
-80
-100
-120
-140
-160
-180
0
25
50
75
f - Frequency - kHz
Figure 20.
100
125
BASIC OPERATION
Figure 21 shows a basic circuit to operate the ADS8505 with a full parallel data output. Taking R/C (pin 24) low
for a minimum of 40 ns (1.75 µs max) initiates a conversion. BUSY (pin 26) goes low and stays low until the
conversion is completed and the output registers are updated. Data is output in binary 2's complement format
with the MSB on pin 6. BUSY going high can be used to latch the data.
8
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BASIC OPERATION (continued)
The ADS8505 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convert
commands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors
compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the
CALIBRATION section).
STARTING A CONVERSION
The combination of CS (pin 25) and R/C (pin 24) low for a minimum of 40 ns immediately puts the sample/hold
of the ADS8505 in the hold state and starts conversion n. BUSY (pin 26) goes low and stays low until
conversion n is completed and the internal output register has been updated. All new convert commands during
BUSY low will abort the conversion in progress and reset the ADC (see Figure 26).
The ADS8505 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convert
commands assures accurate acquisition of a new signal. Refer to Table 1 for a summary of CS, R/C, and BUSY
states and Figure 23 through Figure 25 for the timing diagrams.
CS and R/C are internally ORed and level triggered. There is not a requirement which input goes low first when
initiating a conversion. If, however, it is critical that CS or R/C initiates conversion n, be sure the less critical
input is low at least 10 ns prior to the initiating input.
To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. The
parallel output becomes active whenever R/C goes high. Refer to the READING DATA section.
Table 1. Control Line Functions for Read and Convert
(1)
(2)
CS
R/C
BUSY
OPERATION
1
X
X
None. Databus is in Hi-Z state.
↓
0
1
Initiates conversion n. Databus remains in Hi-Z state.
0
↓
1
Initiates conversion n. Databus enters Hi-Z state.
0
1
↑
Conversion n completed. Valid data from conversion n on the databus.
↓
1
1
Enables databus with valid data from conversion n.
↓
1
0
Enables databus with valid data from conversion n-1 (1). Conversion n in progress.
0
↑
0
Enables databus with valid data from conversion n-1 (1). Conversion n in progress.
0
0
↑
Data is invalid. CS and/or R/C must be high when BUSY goes high.
X
↓
0
Conversion n is halted. Causes ADC to reset. (2)
See Figure 23 and Figure 24 for constraints on data valid from conversion n-1.
See Figure 26 for details on ADC reset.
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200 Ω
1
28
2
27
3
26
4
25
5
24
B15 (MSB)
6
23
B14
7
B13
33.2 kΩ
+
2.2 µF
2.2 µF
+
+
0.1 µF
+5V
+
10 µF
Convert Pulse
22
B0 (LSB)
8
21
B1
B12
9
20
B2
B11
10
19
B3
B10
11
18
B4
B9
12
17
B5
B8
13
16
B6
14
15
B7
ADS8505
40 ns Min
Figure 21. Basic Operation
READING DATA
The ADS8505 outputs full or byte-reading parallel data in binary 2's complement data output format. The parallel
output is active when R/C (pin 24) is high and CS (pin 25) is low. Any other combination of CS and R/C 3-states
the parallel output. Valid conversion data can be read in a full parallel, 16-bit word or two 8-bit bytes on pins
6-13 and pins 15-22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle. Refer to
Table 2 for ideal output codes and Figure 22 for bit locations relative to the state of BYTE.
Table 2. Ideal Input Voltages and Output Codes
DESCRIPTION
ANALOG INPUT
Full-scale range
±10 V
DIGITAL OUTPUT BINARY 2'S COMPLEMENT
BINARY CODE
HEX CODE
7FFF
Least significant bit (LSB)
305 µV
Full scale (10 V-1 LSB)
9.999695 V
0111 1111 1111 1111
Midscale
0V
0000 0000 0000 0000
0000
One LSB below midscale
-305 µV
1111 1111 1111 1111
FFFF
–Full scale
-10 V
1000 0000 0000 0000
8000
PARALLEL OUTPUT (After a Conversion)
After conversion n is completed and the output registers have been updated, BUSY (pin 26) goes high. Valid
data from conversion n is available on D15-D0 (pins 6-13 and 15-22). BUSY going high can be used to latch the
data. Refer to Table 3, Figure 23, Figure 24, and Figure 25 for timing specifications.
PARALLEL OUTPUT (During a Conversion)
After conversion n has been initiated, valid data from conversion n-1 can be read and is valid up to t2 (2.2 µs
typ) after the start of conversion n. Do not attempt to read data from t2 (2.2 µs typ) after the start of conversion n
until BUSY (pin 26) goes high; this may result in reading invalid data. Refer to Table 3, Figure 23, Figure 24, and
Figure 25 for timing specifications.
Note: For the best possible performance, data should not be read during a conversion. The switching noise of
the asynchronous data transfer can cause digital feedthrough degrading converter performance.
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The number of control lines can be reduced by tying CS low while using the falling edge of R/C to initiate
conversions and the rising edge of R/C to activate the output mode of the converter. See Figure 23.
Table 3. Conversion Timing
SYMBOL
DESCRIPTION
MIN
TYP
tw1
Pulse duration, convert
ta
Access time, data valid after R/C low
2.2
15
MAX
40
tpd
Propagation delay time, BUSY from R/C low
tw2
Pulse duration, BUSY low
td1
Delay time, BUSY after end of conversion
5
td2
Delay time, aperture
5
UNITS
1750
ns
3.2
µs
25
ns
2.2
µs
ns
ns
Conversion time
tacq
Acquisition time
1.8
tdis
Disable time, bus
10
30
td3
Delay time, BUSY after data valid
35
50
ns
tv
Valid time, previous data remains valid after R/C low
1.5
2
µs
tconv + tacq
2.2
µs
tconv
µs
83
Throughput time
4
ns
µs
tsu
Setup time, R/C to CS
10
ns
tc
Cycle time between conversions
4
µs
ten
Enable time, bus
10
30
83
ns
td4
Delay time, BYTE
5
10
30
ns
BYTE LOW
BYTE HIGH
+5 V
Bit 15 (MSB) 6
23
Bit 7 6
22 Bit 0 (LSB)
Bit 6 7
Bit 13 8
21 Bit 1
Bit 5 8
21 Bit 9
Bit 12 9
20 Bit 2
Bit 4 9
20 Bit 10
Bit 11 10
19 Bit 3
Bit 3 10
19 Bit 11
Bit 10 11
18 Bit 4
Bit 2 11
18 Bit 12
Bit 9 12
17 Bit 5
Bit 1 12
17 Bit 13
Bit 8 13
16 Bit 6
Bit 0 (LSB) 13
16 Bit 14
14
15 Bit 7
14
Bit 14 7
ADS8505
23
ADS8505
22 Bit 8
15 Bit 15 (MSB)
Figure 22. Bit Locations Relative to State of BYTE (Pin 23)
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tw1
R/C
tc
ta1
tw2
BUSY
tpd
td2
td1
Acquire
MODE
Convert
Acquire
tconv
DATA BUS
Previous
Data Valid
Previous
Data Valid
Hi−Z
Convert
tacq
Not Valid
Data Valid
Hi−Z
Data Valid
td3
tdis
tv
Figure 23. Conversion Timing with Outputs Enabled after Conversion (CS Tied Low)
tsu
tsu
tsu
tsu
R/C
tw1
CS
tpd
tw2
BUSY
td2
MODE Acquire
Convert
Acquire
tconv
Hi−Z State
DATA BUS
Data Valid
ten
Hi−Z State
tdis
Figure 24. Using CS to Control Conversion and Read Timing
tsu
tsu
R/C
CS
BYTE
Pins 6 − 13 Hi−Z
Pins 15 − 22 Hi−Z
High Byte
Low Byte
ten
td4
Low Byte
High Byte
Hi−Z
tdis
Hi−Z
Figure 25. Using CS and BYTE to Control Data Bus
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tc
tw1
tw1
R/C
tpd
tpd
BUSY
0 ns MIN
4.75V
VANA
VDIG
DATA BUS
Unknown
Hi-Z
Not Valid
Hi-Z
Not Valid
Data Valid
td3
Figure 26. ADC Reset
ADC RESET
The ADC reset function of the ADS8505 can be used to terminate the current conversion cycle. Bringing R/C low
for at least 40 ns while BUSY is low will initiate the ADC reset. To initiate a new conversion, R/C must return to
the high state and remain high long enough to acquire a new sample (see Table 3, tc) before going low to initiate
the next conversion sequence. In applications that do not monitor the BUSY signal, it is recommended that the
ADC reset function be implemented as part of a system initialization sequence.
INPUT RANGES
The ADS8505 offers a standard ±10-V input range. Figure 28 shows the necessary circuit connections for the
ADS8505 with and without hardware trim. Offset and full-scale error specifications are tested and specified with
the fixed resistors shown in Figure 28(b). Full-scale error includes offset and gain errors measured at both +FS
and –FS. Adjustments for offset and gain are described in the CALIBRATION section of this data sheet.
Offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors
compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the
CALIBRATION section).
The nominal input impedance of 11.5 kΩ results from the combination of the internal resistor network shown on
the front page of the product data sheet and the external resistors. The input resistor divider network provides
inherent overvoltage protection assured to at least ±25 V. The 1% resistors used for the external circuitry do not
compromise the accuracy or drift of the converter. They have little influence relative to the internal resistors, and
tighter tolerances are not required.
The input signal must be referenced to AGND1. This minimizes the ground loop problem typical to analog
designs. The analog signal should be driven by a low impedance source. A typical driving circuit using an
OPA627 or OPA132 is shown in Figure 27.
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+15V
2.2 mF
22 pF
ADS8505
200 W
100 nF
GND
VIN
2 kW
Pin 7
2 kW
Vin
Pin 2
22 pF
Pin3
Pin 1
−
OPA 627
or
OPA 132
+
REF
2.2 mF
33.2 kW
Pin 6
AGND1
Pin4
GND
CAP
2.2 mF
GND
100 nF
2.2 mF
DGND
GND
AGND2
−15 V
GND
Figure 27. Typical Driving Circuit (±10 V, No Trim)
14
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APPLICATION INFORMATION
CALIBRATION
The ADS8505 can be trimmed in hardware or software. The offset should be trimmed before the gain since the
offset directly affects the gain. To achieve optimum performance, several iterations may be required.
Hardware Calibration
To calibrate the offset and gain of the ADS8505, install the proper resistors and potentiometers as shown in
Figure 28(a).
Software Calibration
To calibrate the offset and gain of the ADS8505 in software, no external resistors are required. See the No
Calibration section for details on the effects of the external resistors.
No Calibration
See Figure 28(b) for circuit connections. The external resistors shown in Figure 28(b) may not be necessary in
some applications. These resistors provide compensation for an internal adjustment of the offset and gain which
allows calibration with a single supply.
200 Ω
1
±10 V
2
33.2 kΩ
+5 V
2.2 µF +
50 kΩ
Offset
50 kΩ
Gain
576 kΩ
3
4
+
2.2 µF
5
VIN
±10 V
200 Ω
1
2
AGND1
33.2 kΩ
2.2 µF +
REF
4
CAP
2.2 µF
AGND1
REF
CAP
+
AGND2
(a) ±10 V With Hardware Trim
3
VIN
5
AGND2
(b) ±10 V Without Hardware Trim
Note: Use 1% metal film resistors.
Figure 28. Circuit Diagram With and Without External Resistors
REFERENCE
The ADS8505 can operate with its internal 2.5-V reference or an external reference. By applying an external
reference to pin 5, the internal reference can be bypassed. The reference voltage at REF is buffered internally
with the output on CAP (pin 4).
The internal reference has an 8 ppm/°C drift (typical) and accounts for approximately 20% of the full-scale error
(FSE = ±0.5%).
REF
REF (pin 3) is an input for an external reference or the output for the internal 2.5-V reference. A 2.2-µF capacitor
should be connected as close to the REF pin as possible. The capacitor and the output resistance of REF create
a low-pass filter to bandlimit noise on the reference. Using a smaller value capacitor introduces more noise to
the reference degrading the SNR and SINAD. The REF pin should not be used to drive external ac or dc loads.
The range for the external reference is 2.3 V to 2.7 V and determines the actual LSB size. Increasing the
reference voltage increases the full-scale range and the LSB size of the converter which can improve the SNR.
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SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
APPLICATION INFORMATION (continued)
CAP
CAP (pin 4) is the output of the internal reference buffer. A 2.2-µF capacitor can be placed between the CAP pin
and ground. Because the internal reference buffer is internally compensated, the external capacitor is not
necessary for compensation of the reference buffer. This relaxes the performance requirements of the capacitor
and makes the performance of the ADC less sensitive to the capacitor.
The output of the buffer is capable of driving up to 2 mA of current to a dc load. A dc load requiring more than 2
mA of current from the CAP pin begins to degrade the linearity of the ADS8505. Using an external buffer allows
the internal reference to be used for larger dc loads and ac loads. Do not attempt to directly drive an ac load
with the output voltage on CAP. This causes performance degradation of the converter.
LAYOUT
POWER
For optimum performance, tie the analog and digital power pins to the same +5-V power supply and tie the
analog and digital grounds together. As noted in the electrical specifications, the ADS8505 uses 90% of its
power for the analog circuitry. The ADS8505 should be considered as an analog component.
The +5-V power for the A/D should be separate from the +5 V used for the system's digital logic. Connecting
VDIG (pin 28) directly to a digital supply can reduce converter performance due to switching noise from the digital
logic. For best performance, the +5-V supply can be produced from whatever analog supply is used for the rest
of the analog signal conditioning. If +12-V or +15-V supplies are present, a simple +5-V regulator can be used.
Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter
the supply. Either using a filtered digital supply or a regulated analog supply, both VDIG and VANA should be tied
to the same +5-V source.
GROUNDING
Three ground pins are present on the ADS8505. DGND is the digital supply ground. AGND2 is the analog
supply ground. AGND1 is the ground which all analog signals internal to the A/D are referenced. AGND1 is more
susceptible to current induced voltage drops and must have the path of least resistance back to the power
supply.
All the ground pins of the A/D should be tied to the analog ground plane, separated from the system's digital
logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the
system ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents
from modulating the analog ground through a common impedance to power ground.
SIGNAL CONDITIONING
The FET switches used for the sample/hold on many CMOS A/D converters release a significant amount of
charge injection which can cause the driving op-amp to oscillate. The FET switch on the ADS8505, compared to
the FET switches on other CMOS A/D converters, releases 5% to 10% of the charge. There is also a resistive
front end which attenuates any charge which is released. The end result is a minimal requirement for the
anti-alias filter on the front end. Any op-amp sufficient for the signal in an application is sufficient to drive the
ADS8505.
The resistive front end of the ADS8505 also provides an assured ±25-V overvoltage protection. In most cases,
this eliminates the need for external input protection circuitry.
INTERMEDIATE LATCHES
The ADS8505 does have 3-state outputs for the parallel port, but intermediate latches should be used if the bus
is to be active during conversions. If the bus is not active during conversion, the 3-state outputs can be used to
isolate the A/D from other peripherals on the same bus. The 3-state outputs can also be used when the A/D is
the only peripheral on the data bus.
16
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Intermediate latches are beneficial on any monolithic A/D converter. The ADS8505 has an internal LSB size of
38 µV. Transients from fast switching signals on the parallel port, even when the A/D is 3-stated, can be coupled
through the substrate to the analog circuitry causing degradation of converter performance.
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ADS8505
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SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September, 2005) to A Revision ............................................................................................. Page
•
•
•
•
•
•
•
Added SFDR value ............................................................................................................................................................... 1
Changed 3.0 to 1.5 Max INL................................................................................................................................................. 1
Changed 3.0 to 1.5 Minimum Relative Accuracy.................................................................................................................. 2
Changed REF and CAP - reversed ...................................................................................................................................... 2
Changed INL, SFDR, THD, SNR values .............................................................................................................................. 2
Changed SFDR-TA, THD-TA, SINAD-TA, SNR-fi, SINAD-fi SFDR-fi, THD-fi, IDD-TA, CAP ESR, INL, DNL, and
FFT curves............................................................................................................................................................................ 6
Changed CAP description................................................................................................................................................... 16
Changes from A Revision (October, 2006) to B Revision ............................................................................................. Page
•
•
•
•
•
18
Deleted text from basic operation description ...................................................................................................................... 8
Changed text in starting a conversion description................................................................................................................ 9
Changed operation descriptions and R/C in table ................................................................................................................ 9
Added SAR Reset timing .................................................................................................................................................... 13
Added ADC RESET section ............................................................................................................................................... 13
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS8505IBDB
ACTIVE
SSOP
DB
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8505I
B
ADS8505IBDBG4
ACTIVE
SSOP
DB
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8505I
B
ADS8505IBDBR
ACTIVE
SSOP
DB
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8505I
B
ADS8505IBDBRG4
ACTIVE
SSOP
DB
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8505I
B
ADS8505IBDW
ACTIVE
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8505I
B
ADS8505IBDWR
ACTIVE
SOIC
DW
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8505I
B
ADS8505IDB
LIFEBUY
SSOP
DB
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8505I
ADS8505IDW
ACTIVE
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8505I
ADS8505IDWG4
ACTIVE
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8505I
ADS8505IDWR
ACTIVE
SOIC
DW
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS8505I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
18-Feb-2019
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS8505IBDBR
SSOP
DB
28
2000
330.0
16.4
8.1
10.4
2.5
12.0
16.0
Q1
ADS8505IBDWR
SOIC
DW
28
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
ADS8505IDWR
SOIC
DW
28
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS8505IBDBR
SSOP
DB
28
2000
350.0
350.0
43.0
ADS8505IBDWR
SOIC
DW
28
1000
350.0
350.0
66.0
ADS8505IDWR
SOIC
DW
28
1000
350.0
350.0
66.0
Pack Materials-Page 2
PACKAGE OUTLINE
DB0028A
SSOP - 2 mm max height
SCALE 1.500
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
26X 0.65
28
1
2X
10.5
9.9
NOTE 3
8.45
14
15
28X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.15
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214853/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
28X (1.85)
(R0.05) TYP
1
28X (0.45)
28
26X (0.65)
SYMM
15
14
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214853/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
28X (1.85)
SYMM
(R0.05) TYP
1
28X (0.45)
28
26X (0.65)
SYMM
14
15
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214853/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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