Texas Instruments | 16-Bit 4MSPS Fully Differential Pseudo Bipolar Input Micro Power Sampling ADC (Rev. B) | Datasheet | Texas Instruments 16-Bit 4MSPS Fully Differential Pseudo Bipolar Input Micro Power Sampling ADC (Rev. B) Datasheet

Texas Instruments 16-Bit 4MSPS Fully Differential Pseudo Bipolar Input Micro Power Sampling ADC (Rev. B) Datasheet
 ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
16-BIT, 4-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER
SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE,
REFERENCE
FEATURES
APPLICATIONS
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•
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Fully Differential Input with Pseudo-Bipolar
Input Range -4 V to +4 V
16-Bit NMC at 4 MSPS
1 LSB INL Typ
92dB SNR, -102dB THD Typ with 100-kHz
Input
Internal 4.096-V Reference and Reference
Buffer
REFIN/2 Available for Setting Analog Input
Common-Mode Voltage
Zero Latency
High-Speed Parallel Interface
Single Supply Operation Capability
Low Power: 155 mW at 4 MHz Typ, Flexible
Power-Down Scheme
Pin-Out Similar to ADS8412/8402
48-Pin 9×9 TQFP Package
DWDM
Instrumentation
High-Speed, High-Resolution, Zero Latency
Data Acquisition Systems
Transducer Interface
Medical Instruments
Spectrum Analysis
ATE
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DESCRIPTION
The ADS8422 is a 16-bit, 4-MHz A/D converter with
an internal 4.096-V reference. The device includes a
16-bit capacitor-based multi-bit SAR A/D converter
with inherent sample and hold. This converter
includes a full 16-bit interface and an 8-bit option
where data is read using two 8-bit read cycles if
necessary.
The ADS8422 has a fully differential, pseudo-bipolar
input. It is available in a 48-lead TQFP package and
is characterized over the industrial -40°C to +85°C
temperature range.
HIGH-SPEED SAR CONVERTER FAMILY (1)
TYPE/SPEED
500 kHz
~600 kHz
ADS8383
ADS8381
750 kHz
1 MHz
1.25 MHz
2 MHz
3 MHz
4MHz
ADS8481
18-Bit Pseudo-Diff
ADS8380 (s)
18-Bit Pseudo-Bipolar, Fully Diff
ADS8382 (s)
ADS8370 (s)
ADS8482
ADS8371
ADS8471
ADS8401
ADS8411
ADS8329/30 (s)
ADS8405
ADS8410 (s)
ADS8472
ADS8402
ADS8412
ADS8406
ADS8413 (s)
16-Bit Pseudo-Diff
ADS8327/28 (s)
ADS8372 (s)
ADS8422
16-Bit Pseudo-Bipolar, Fully Diff
14-Bit Pseudo-Diff
ADS7890 (s)
12-Bit Pseudo-Diff
(1)
ADS7886
ADS7891
ADS7883
ADS7881
S: Serial
+IN
CDAC
−IN
COMMOUT
Output
Latches
and
3-State
Drivers
SAR
Temp Sensor
TEMPOUT
Comparator
½
REFIN
REFOUT
Clock
4.096-V
Internal Reference
Conversion
and
Control Logic
BYTE
16-/8-Bit
Parallel Data
Output Bus
PD2
RESET/PD1
CONVST
BUSY
CS
RD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
ADS8422
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SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
MODEL
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY (LSB)
NO MISSING CODES
RESOLUTION (BIT)
PACKAGE
TYPE
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
ADS8422I
±6
±2
15
9×9 48-Pin
TQFP
PFB
–40°C to 85°C
ADS8422IB
(1)
±2
+1.5/-1
16
9×9 48-Pin
TQFP
PFB
ORDERING
INFORMATION
TRANSPORT
MEDIA QTY.
ADS8422IPFBT
Small tape and
reel 250
ADS8422IPFBR
Tape and reel
1000
ADS8422IBPFBT
Small tape and
reel 250
ADS8422IBPFBR
Tape and reel
1000
–40°C to 85°C
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
+IN to AGND
–0.4 to +VA + 0.1
V
–IN to AGND
–0.4 to +VA + 0.1
V
+VA to AGND
–0.3 to 7
V
+VBD to BDGND
–0.3 to 7
V
Digital input voltage to BDGND
–0.3 to +VBD + 0.3
V
Digital output voltage to BDGND
Voltage
–0.3 to +VBD + 0.3
V
TA
Operating free-air temperature range
–40 to 85
°C
Tstg
Storage temperature range
–65 to 150
°C
150
°C
Junction temperature (TJ max)
TQFP 48-pin package
Lead temperature, soldering
(1)
2
Power dissipation
(TJMax – TA)/θJA
θJA thermal impedance
86
°C/W
Vapor phase (60 sec)
215
°C
Infrared (15 sec)
220
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
SPECIFICATIONS
TA = –40°C to 85°C, +VA = 5 V, +VAREG = 5 V to 3 V, +VBD = 5 V to 2.7 V, fSAMPLE = 4 MSPS, Vref = 4.096 V (measured
with internal reference buffer) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input voltage (1)
Absolute input voltage
+IN – (–IN)
–Vref
Vref
+IN
–0.2
Vref + 0.2
–IN
–0.2
Vref + 0.2
Common-mode input range
(Vref)/2 – 0.2
Input capacitance
(Vref)/2
(Vref)/2 + 0.2
30
Input leakage current
V
V
V
pF
1
nA
SYSTEM PERFORMANCE
Resolution
16
No missing codes
Integral linearity
(2) (3)
Differential linearity
Bits
ADS8422I
15
ADS8422IB
16
ADS8422I
–6
±2
6
ADS8422IB
–2
±1
2
ADS8422I
–2
±0.7
2
ADS8422IB
–1
±0.7
1.5
–0.5
±0.25
0.5
Offset error
Bits
±0.2
Offset error drift
±0.05
Gain error (4) (5)
Vref = 4.096 V
Gain error drift
Vref = 4.096 V
±2
–0.1
LSB
(16 bit) (2)
LSB
(16 bit)
mV
ppm/°C
0.1
%FS
ppm/°C
At dc
81
Common-mode rejection ratio
At code 0000h with [+IN + (–IN)]/2 =
512 mVpp at 500 kHz,
78
Noise
At 0000h output code
40
µV RMS
Power supply rejection ratio
At 8000h output code
78
dB
dB
SAMPLING DYNAMICS
Conversion time
0.180
Acquisition time
µs
µs
0.070
Throughput rate
4
MHz
Aperture delay
3
ns
Aperture jitter
7
ps RMS
70
ns
140
ns
Step response
Overvoltage recovery
(1)
(2)
(3)
(4)
(5)
Ideal input span, does not include gain or offset error.
LSB means least significant bit and is equal to 2VREF/65536.
This is endpoint INL, not best fit.
Measured relative to an ideal full-scale input [+IN – (–IN)] of 8.192 V.
This specification does not include the internal reference voltage error and drift.
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SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
SPECIFICATIONS (Continued)
TA = –40°C to 85°C, +VA = 5 V, +VAREG = 5.25 V to 3 V, +VBD = 5 V to 2.7 V, fSAMPLE = 4 MSPS, Vref = 4.096 V (measured
with internal reference buffer) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
Total harmonic distortion (THD) (1)
Signal to noise ratio (SNR)
Signal to noise + distortion (SINAD)
Spurious free dynamic range (SFDR)
VIN = 8 Vpp
VIN = 8 Vpp
VIN = 8 Vpp
VIN = 8 Vpp
10 kHz
–114
100 kHz
–102
500 kHz
–100
10 kHz
93
100 kHz
92
500 kHz
90
10 kHz
92.5
100 kHz
91.5
500 kHz
89.5
10 kHz
116
100 kHz
109
500 kHz
106
–3dB Small signal bandwidth
Maximum input frequency, fi(max) (2)
dB
dB
dB
dB
30
VIN = 8 Vpp
MHz
2
MHz
VOLTAGE REFERENCE INPUT
Reference voltage at REFIN, Vref
3.9
Reference resistance
4.096
4.15
1000
V
MΩ
INTERNAL REFERENCE OUTPUT
Internal reference start-up time
From 95% (+VA), with 1-µF capacitor on REFOUT
Reference voltage range, Vref
IO = 0, TA = 25°C
25
Source current
Static load
Line regulation
+VA = 4.75 V to 5.25 V
±1
mV
Drift
IO = 0
±6
PPM/°C
4.088
4.096
ms
4.104
V
10
µA
ANALOG COMMON-MODE, PIN 3
Output voltage range
IO = 0
Source current
Static load
(1)
(2)
4
VREF/2 - 0.016
VREF/2
200
VREF/2 + 0.016
V
µA
Calculated on the first nine harmonics of the input frequency.
ADC Sampling circuit is optimized to accept inputs until Nyquist frequency. Dynamic performance may degrade rapidly above fi(max).
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SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
SPECIFICATIONS (Continued)
TA = –40°C to 85°C, +VA = 5 V, +VAREG = 5 V to 3 V, +VBD = 5 V to 2.7 V, fSAMPLE = 4 MSPS, Vref = 4.096 V (measured
with internal reference buffer) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT/OUTPUT
Logic family – CMOS
Logic level
VIH
IIH = 5 µA
VIL
IIL = 5 µA
VOH
IOH = 2 TTL loads
VOL
IOL = 2 TTL loads
0.75×(+VBD)
+VBD + 0.3
–0.3
0.8
+VBD – 0.6
V
0.4
Data format – Twos complement
POWER SUPPLY REQUIREMENTS
Power supply voltage
+VA
4.75
5
5.25
+VAREG
2.85
3.0
5.25
2.7
3.0
5.25
+VA = 5 V, PD1 = 1, PD2 = 1
24
27
+VAREG = 5 V, PD1 = 1, PD2 = 1
12
14
+VAREG = 3 V, PD1 = 1, PD2 = 1
12
14
+VBD
+VA
Supply current
+VAREG
+VBD (1)
+VBD = 3 V, 10 pF/pin
0.55
+VBD = 5 V, 20 pF/pin
1.8
V
mA
mA
mA
POWER DOWN (2)
Supply current
+VA
+VAREG
2.5
PD1 = 0, PD2 = 1, +VA = 5 V
Power
(PD1, PD2) : (0,1) → (1,1)
Power-up time
Supply current
+VA
+VAREG
mA
17
mW
5
µs
µA
5
PD1 = 0, PD2 = 0
µA
5
Power
Power-up time
3.4
5
µW
40
(PD1, PD2) : (0,0) → (1,1) , 1-µF Storage
capacitor from REFOUT to AGND
25
ms
TEMPERATURE RANGE
Operating free-air
(1)
(2)
–40
85
°C
This includes the current required for charging the external load capacitance on the digital outputs and is measured with four digital
outputs toggling at the same time.
(PD1 , PD2 ) = (1,0) is reserved. Do not use this power-down pins combination.
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SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
TIMING CHARACTERISTICS FROM DIGITAL INPUTS
All specifications typical at –40°C to 85°C, +VBD = 2.7 V to 5.25 V
(1) (2)
PARAMETER
MIN
TYP
MAX
UNIT
CONVERSION AND ACQUISITION
t(ACQ)
Acquisition time, internal to device, not externally visible
70
ns
tw1
tw2
Pulse duration, CONVST low
20
ns
Pulse duration, CONVST high
100
tp1
ns
Period, CONVST
250
ns
30
ns
10
ns
tq1
Quiet time, last toggle of interface input signals during acquisition before CONVST falling
tq2
Quiet time, CONVST falling to first toggle of interface input signals
(3)
(3)
POWER DOWN
PD1 low for only ADC reset (no powerdown)
tw3
Pulse duration
20
PD1 low for ADC reset and also ADC powerdown
1500
PD2 low pulse duration for REFOUT and COMMOUT buffers powerdown
1500
Pulse duration, all others unspecified
(1)
(2)
(3)
500
ns
10
ns
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from after 90% of transition.
All digital output signals loaded with 10-pF capacitors at +VBD = 2.7 V and 20-pF capacitor at +VBD = 5.25 V and timed to reaching
90% of transition.
Quiet time zones are for meeting performance and not functionality.
TIMING CHARACTERISTICS OF DIGITAL OUTPUTS
All specifications typical at –40°C to 85°C, +VBD = 2.7 V to 5.25 V
(1) (2)
PARAMETER
MIN
TYP
MAX
UNIT
180
ns
CONVERSION AND ACQUISITION
t(CONV)
Conversion time, internal to device, not externally visible
td1
Delay time, CONVST fall to conversion start (aperture delay)
3
ns
DATA READ OPERATION
td2
Delay time, CONVST low to data valid if CS = RD = 0
td3
Delay time, data valid to BUSY low if CS = RD = 0
225
td4
Delay time, RD (or CS) low to data valid
17
ns
td5
Delay time, BYTE toggle to data valid
20
ns
td6
Delay time, data three-state after RD (or CS) high
12
ns
5
ns
ns
POWER DOWN
td7
td8
td9
(1)
(2)
6
Delay time, PD1 low to BUSY rising
20
ns
5
µs
25
ms
Delay time, power up (after AVDD = 4.75 V)
25
ms
Delay time, data three-state after PD1 low
1.5
µs
Delay time, PD1 high to device operational (with PD2 held high)
Delay time, PD2 high to REFOUT/COMMOUT valid
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from after 90% of transition.
All digital output signals loaded with 10-pF capacitors at +VBD = 2.7 V and 20-pF capacitor at +VBD = 5.25 V and timed to reaching
90% of transition.
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SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
PIN ASSIGNMENTS
REFM
REFM
+VA
AGND
AGND
+VA
CS
RD
CONVST
BYTE
RESET/PD1
PD2
PFB Package
(Top View)
48 47 46 45 44 43 42 41 40 39 38 37
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
BUSY
BDGND
+VBD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
BDGND
DB8
+VBD
1
CAP2
AGND
AGND
DB15
DB14
DB13
DB12
DB11
DB10
DB9
REFIN
REFOUT
COMMOUT
+VA
AGND
+IN
−IN
AGND
CAP1
+VAREG
NC
AGND
A.
NC - No connection
B.
Pins 9 and 13 are internally regulated 3-V outputs and are externally to be connected to decoupling capacitors only.
C.
+VAREG can be connected to a 3-V to 5-V supply.
D.
Pin 3 outputs REFIN/2
E.
Pin 38 can be used for ADC powerdown and pin 37 for analog output powerdown.
TERMINAL FUNCTIONS
NAME
NO
I/O
AGND
5, 8, 12, 14,
15, 44, 45
–
Analog ground
BDGND
DESCRIPTION
25, 35
–
Digital ground for bus interface digital supply
BUSY
36
O
Status output. High when a conversion is in progress.
BYTE
39
I
Byte select input. Used for 8-bit bus reading.
0: No fold back
1: Low byte D[7:0] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[15:8].
COMMOUT
3
O
This pin outputs REFIN/2 and can be used to set the common-mode voltage of the differential analog input, (+IN +
–IN)/2.
CONVST
40
I
Convert start. This input is low true and can act independent of the CS input.
CS
42
I
Chip select.
9, 13
O
Decoupling of internally generated 3-V supply. Add 1-µF capacitor from these pins to AGND.
CAP1, CAP2
8-BIT BUS
Data Bus
BYTE = 0
16-BIT BUS
BYTE = 1
BYTE = 0
DB15
16
O
D15 (MSB)
D7
D15 (MSB)
DB14
17
O
D14
D6
D14
DB13
18
O
D13
D5
D13
DB12
19
O
D12
D4
D12
DB11
20
O
D11
D3
D11
DB10
21
O
D10
D2
D10
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SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
TERMINAL FUNCTIONS (continued)
NAME
NO
I/O
DB9
22
O
D9
D1
D9
DESCRIPTION
DB8
23
O
D8
D0 (LSB)
D8
DB7
26
O
D7
All ones
D7
DB6
27
O
D6
All ones
D6
DB5
28
O
D5
All ones
D5
DB4
29
O
D4
All ones
D4
DB3
30
O
D3
All ones
D3
DB2
31
O
D2
All ones
D2
DB1
32
O
D1
All ones
D1
DB0
33
O
D0 (LSB)
All ones
D0 (LSB)
–IN
7
I
Inverting input channel
+IN
6
I
Noninverting input channel
NC
11
–
No connection
PD2
37
I
Low true signal. A logic low longer than 1.5 µs applied to this pin powers down only the analog outputs that include
REFOUT and COMMOUT. (NOTE: The combination PD1 = 1, PD2 = 0 is reserved. Do not use this combination.)
REFIN
1
I
Reference input. Add 0.1-µF decoupling capacitor between REFIN and REFM.
REFOUT
2
O
Reference output. Add 1-µF capacitor between the REFOUT pin and REFM pin when internal reference is used.
47, 48
I
Reference ground
38
I
Low true signal. A low pulse applied to this pin resets the ADC; the ongoing conversion is aborted. A low pulse shorter
than 0.5 µs only resets, and one longer than 1.5 µs resets and also powers down the ADC. Note that analog outputs
REFOUT and COMMOUT can be powered down by PD2, if necessary.
REFM
RESET/PD1
RD
41
I
Synchronization pulse for the parallel output.
+VA
4, 46
–
Analog power supplies, 4.75 V to 5.25 VDC
10
–
Regulator supply, 2.85 V to 5.25 VDC
24, 34
–
Digital power supply for bus
+VAREG
+VBD
TYPICAL CHARACTERISTICS
250000
COUNTS
COUNTS
250000
234937
+VA = 5 V,
+VAREG = 3 V,
200000 +VBD = 3 V,
Int REFIN = 4.096 V,
262144 Points,
Sigma = 0.325,
150000
100000
50000
68
14024
13025
FFFD
FFFE
FFFF
0000
Code - Hex
Figure 1.
78
93
0
8
4.098
235679
+VA = 5 V,
+VAREG = 3 V,
200000 +VBD = 3 V,
Ext REFIN = 4.096 V,
262144 Points,
Sigma = 0.319,
150000
100000
50000
0001
INTERNAL REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
(Three Devices Shown)
HISTOGRAM OF 262144
CONVERSIONS OF DC INPUT AT
CENTER CODE (External Reference)
13793
12575
FFFE
FFFF
0000
Code - Hex
19
0
FFFD
Figure 2.
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0001
REFOUT - Internal Reference Voltage - V
HISTOGRAM OF 262144
CONVERSIONS OF DC INPUT AT
CENTER CODE (Internal Reference)
+VA = 5 V,
+VAREG = 3 V,
+VBD = 3 V
D3
D2
4.097
D1
4.096
4.095
4.094
-40
-25
-10
5
20
35
50
65
TA - Free-Air Temperature - ºC
Figure 3.
80
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SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
GAIN ERROR
vs
FREE-AIR TEMPERATURE
0.040
+VA = 5 V, +VAREG = 3 V,
+VBD = 3 V, REFIN = 4.096 V
0.030
Gain Error - %FS
0.100
0.010
0.050
-25 -10
5
20 35 50
65
TA - Free-Air Temperature - ºC
0
-40 -25
80
90
88
86
+VA = 5 V, +VAREG = 3 V,
+VBD = 3 V, REFIN = 4.096 V
84
-10
5
20 35 50 65
TA - Free-Air Temperature - ºC
80
1
10
100
Figure 6.
SIGNAL-TO-NOISE + DISTORTION
vs
INPUT FREQUENCY
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
16
90
88
86
+VA = 5 V, +VAREG = 3 V,
+VBD = 3 V, REFIN = 4.096 V
84
94
SNR - Signal-to-Noise Ratio - dB
92
15.5
15
14.5
14
10
100
fi - Input Frequency - kHz
+VA = 5 V, +VAREG = 3 V, +VBD = 3 V,
REFIN = 4.096 V, fi = 18 kHz
93
92
91
+VA = 5 V, +VAREG = 3 V,
+VBD = 3 V, REFIN = 4.096 V
13.5
1
1000
fi - Input Frequency - kHz
Figure 5.
Effective Number of Bits - ENOB
SINAD - Signal-to-Noise + Distortion - dB
92
Figure 4.
94
1000
1
100
10
fi - Input Frequency - kHz
90
-40
1000
-25
5
20 35 50 65 80
-10
TA - Free-Air Temperature - ºC
Figure 7.
Figure 8.
Figure 9.
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs
FREE-AIR TEMPERATURE
SFDR - Spurious Free Dynamic Range - dB
-85
THD - Total Harmonic Distortion - dB
0.020
+VA = 5 V, +VAREG = 3 V,
+VBD = 3 V, REFIN = 4.096 V
-90
-95
-100
-105
-110
-115
-120
-125
1
10
100
fi - Input Frequency - kHz
Figure 10.
1000
-100
125
+VA = 5 V, +VAREG = 3 V,
+VBD = 3 V, REFIN = 4.096 V
120
THD - Total Harmonic Distortion - dB
Offset Voltage - mV
0.150
94
+VA = 5 V,
+VAREG = 3 V,
+VBD = 3 V,
REFIN = 4.096 V
SNR - Signal-to-Noise Ratio - dB
0.200
0
-40
SIGNAL-TO-NOISE RATIO
vs
INPUT FREQUENCY
115
110
105
100
95
90
85
1
100
10
fi - Input Frequency - kHz
Figure 11.
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1000
+VA = 5 V, +VAREG = 3 V,
+VBD = 3 V, REFIN = 4.096 V,
fi = 18 kHz
-105
-110
-115
-120
-40
-25
-10 5
20 35 50 65 80
TA - Free-Air Temperature - ºC
Figure 12.
9
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TYPICAL CHARACTERISTICS (continued)
POWER DISSIPATION
vs
THROUGHPUT
+VAREG CURRENT
vs
THROUGHPUT
25
12
180
+VA = 5 V, +VAREG = 3 V,
+VBD = 3 V, REFIN = 4.096 V,
Device not powered down
between conversions
150
140
24
11
10.5
10
130
9.5
120
9
1000
0
2000
3000
Throughput - KSPS
+VA Current - mA
160
+VA = 5 V, +VAREG = 3 V,
+VBD = 3 V, REFIN = 4.096 V,
Device not powered down between
conversions
0
4000
1000
2000
3000
Throughput - KSPS
23.5
23
22.5
21.5
21
0
4000
1000
2000
3000
Throughput - KSPS
Figure 14.
Figure 15.
DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
2
+VA = 5 V, +VAREG = 3 V,
+VBD = 3 V, REFIN = 4.096 V
+VA = 5 V, +VAREG = 3 V,
+VBD = 3 V, REFIN = 4.096 V
1
Max
1
Max
INL - LSBs
0.50
0
0
Min
-1
-40
-1
Min
-0.50
-25 -10
5
20 35 50 65
TA - Free-Air Temperature - ºC
-2
-40
80
Figure 16.
-25
-10
5
20 35 50 65
TA - Free-Air Temperature - ºC
80
85
80
75
70
65
60
+VA = 5 V, +VAREG = 3 V,
+VBD = 3 V, REFIN = 4.096 V
55
50
1
Figure 17.
10
100
1000
f - Frequency - kHz
Figure 18.
DNL
1.5
+VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V
DNL - LSBs
1
0.5
0
-0.5
-1
0
10
4000
Figure 13.
1.50
DNL - LSBs
+VA = 5 V, +VAREG = 3 V,
+VBD = 3 V, REFIN = 4.096 V,
Device not powered down between
conversions
22
CMRR - Common-Mode Rejection Ratio - dB
170
24.5
11.5
+VAREG Current - mA
PD - Power Dissipation - mW
+VA CURRENT
vs
THROUGHPUT
16384
32768
Code
Figure 19.
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65536
10000
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SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
INL
2
+VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V
1.5
INL - LSBs
1
0.5
0
-0.5
-1
-1.5
-2
0
32768
16384
49152
65536
Code
Figure 20.
FFT (10 kHz)
Amplitude - dB of Full-Scale
0
+VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V,
fi = 10 kHz, SNR = 93 dB, THD = 114 dB
-40
-80
-120
-160
-200
0
200
400
600
800
1000
1200
f - Frequency - kHz
Figure 21.
1400
1600
1800
2000
1400
1600
1800
2000
Amplitude - dB of Full-Scale
FFT (100 kHz)
0
+VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V,
fi = 100 kHz, SNR = 92 dB, THD = 102 dB
-40
-80
-120
-160
-200
0
200
400
600
800
1000
1200
f - Frequency - kHz
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
FFT (500 kHz)
Amplitude - dB of Full-Scale
0
+VA = 5 V, +VAREG = 3 V, +VBD = 3 V, REFIN = 4.096 V,
fi = 500 kHz, SNR = 90 dB, THD = 100 dB
-40
-80
-120
-160
-200
0
200
400
600
800
1000
1200
1400
1600
1800
2000
f - Frequency - kHz
Figure 23.
TIMING DIAGRAMS
tw1
tw2
tq1
tp1
tq2
CONVST
t(acq)
td1
ACQUISITION
Sample(N)
Sample(N+1)
t(CONV)
CONVERT
Conversion(N)
td2
DB (Internal)
DB(N-1)
DB(N)
td3
BUSY
Note: The DB shown here is internal to the device and output on the pins only if and when CS and RD are both low
(after td4 ns). This is shown in Figure 25.
Figure 24. Conversion Control Timing
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CS
RD
BYTE
td4
td6
td4
Hi-Z
Hi-Z
Valid
Data
DB
Valid
Data
td6
Valid
Data
Hi-Z
td5
Note: Data is output on the pins only if CS and RD are both low, td4 ns after this condition is satisfied.
Figure 25. Data Read Timing
td8
tw2
CONVST
tw3 > 1500 ns
PD1
td7
BUSY
Conversion(1)
Conversion(2)
td2
DB
Hi-Z
Undefined
Data
DB(1)
DB(2)
td9
ICC
Note: Data is valid from the first conversion initiated 5 µs after PD1 is pulled high.
Figure 26. ADC Power-Down Timing
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PD1 = 0
tw3 > 1500 ns
PD2
td8
COMMOUT
Valid
Analog
Outputs
REFOUT
Note: Analog outputs are valid 25 ms after PD2 is pulled high.
Figure 27. Analog Output Power-Down Timing
RESET TIMING
tw2
CONVST
tw3 < 500 ns
PD1
td7
BUSY
Conversion(1)
Conversion(2)
td2
DB
Undefined
Data
Note: Data valid from first conversion initiated 100 ns after PD1 is pulled high.
Figure 28. ADC Reset
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DB(2)
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PRINCIPLES OF OPERATION
The ADS8422 is a member of a family of high-speed multi-bit successive approximation register (SAR)
analog-to-digital converters (ADC). The architecture is based on charge redistribution, which inherently includes
a sample/hold function. See Figure 34 for the application circuit for the ADS8422.
The conversion clock is generated internally. The conversion time is a maximum of 180 ns that is capable of
sustaining a 4-MHz throughput.
The analog input is provided to two input pins: +IN and -IN. When a conversion is initiated, the differential input
on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are
disconnected from any internal function.
REFERENCE
The ADS8422 has a built-in 4.096-V reference but can operate with an external 4.096-V reference. When
internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with a 0.1-µF decoupling
capacitor and a 1-µF storage capacitor between pin 2 (REFOUT) and pins 47 and 48 (REFM). The internal
reference of the converter is double buffered. If an external reference is used, the second buffer provides
isolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitors
of the CDAC during conversion. Pin 2 (REFOUT) can be left unconnected (floating) if an external reference is
used.
ANALOG INPUT
The ADS8422 has a pseudo-bipolar, fully differential input. When the input is differential, the amplitude of the
input equals the difference between +IN and –IN. The peak-to-peak amplitude of each input is VREF. However
since the two inputs are 180° out of phase, the peak-to-peak amplitude of the difference voltage [+IN – (–IN)] is
equal to 2VREF. The common-mode input range is from VREF/2 – 0.2 V to VREF/2 + 0.2 V.
In order to avoid additional external circuitry on the board, the ADS8422 outputs reference input on REFIN
divided by 2 on pin 3 (COMMOUT). This voltage can be used to set the common-mode of the output from the
input driver.
Figure 29, Figure 30, Figure 31, Figure 32, and Figure 33 show the recommended circuits to interface an analog
input signal to the ADS8422.
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PRINCIPLES OF OPERATION (continued)
390 W
+VIN= Vincm + 4Vpp
+VCC
390 W
0.1 mF
THS4131
12 W
6
3
+VIN
8
4Vpp
Vincm
5
4Vpp
-VIN
2 Vocm
220 pF
C0G
1 mF
1
6
time
4
0.1 mF
-VIN= Vincm + 4Vpp
+IN
ADS8422
12 W
7
-IN
COMMOUT
3
390 W
-VCC
390 W
A.
Input common-mode voltage (Vincm) range is restricted by the amplifier. Refer to the amplifier data sheet for more
information. Output common mode of the THS4131 is set by the voltage at pin 2. The COMMOUT pin of the
ADS8422 is designed to source pin 2 of the THS4131. However to use this feature both the positive supply and
negative supply rails must equal (|-VCC| = |+VCC|), absolutely.
Figure 29. Fully Differential Input Driver Circuit for Unipolar or Bipolar Signals
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PRINCIPLES OF OPERATION (continued)
390 W
+Vin=Vincm +8Vpp
390 W
+VCC
0.1 mF
12 W
THS4131
+VIN
Vincm -VIN
6
3
8
8Vpp
2 Vocm
1 mF
220 pF
4
0.1 mF
390 W
+IN
ADS8422
C0G
1
6
time
-Vin=Vincm
5
12 W
7
-IN
COMMOUT
3
-VCC
390 W
A.
Input common-mode voltage (Vincm) range is restricted by the amplifier. Refer to the amplifier data sheet for more
information. Output common mode of the THS4131 is set by the voltage at pin 2. The COMMOUT pin of the
ADS8422 is designed to source pin 2 of the THS4131. However to use this feature both the positive supply and
negative supply rails must equal (|-VCC| = |+VCC|), absolutely.
Figure 30. Single-Ended Input Driving Circuit for When Input is Unipolar or Bipolar
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PRINCIPLES OF OPERATION (continued)
50 W
-VCC
0.1 mF
4
Vin = 0 to +4V
with
Vincm=2.048V
2
6
THS4031
3
0.1 mF
7
50 W
12 W
6
VIN
+IN
4Vpp
2.048
+VCC
1000 W
220 pF
C0G
ADS8422
time
1000 W
12 W
7
-VCC
-IN
COMMOUT
3
0.1 mF
4
2
6
THS4031
3
1 mF
0.1 mF
7
+VCC
Figure 31. Single-Ended Driving Circuit for When Input is Single-Ended Unipolar and has Common-Mode
of 2.048 V
50 W
-VCC
4
0.1 mF
2
50 W
3
+Vin
0V to +4V
with
Vcm=2.048V
4 Vpp
+IN
0.1 mF
220 pF
C0G
+VCC
-VIN
6
THS4032
7
+VIN
2.048V
12 W
6
OpAmp A
50 W
ADS8422
4Vpp
-VCC
time
0.1 mF
4
2
50 W
- Vin
0V to +4V
with
Vcm=2.048V
OpAmp B
6
3
12 W
7
-IN
THS4032
7
0.1 mF
+VCC
A.
This circuit is used to specify ADS8422 performance parameters listed in the data sheet.
Figure 32. Driver Circuit for When Input is Fully Differential Riding on Common-Mode of 2.048 V
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PRINCIPLES OF OPERATION (continued)
49.9 W
-VCC
0.1 mF
1000 W
4
+4.096V
2
1000 W
+VIN = 8Vpp
with
Vincm=0V
+4 V
3
12 W
6
THS4031
7
+VIN
+VCC
49.9 W
8Vpp
0V
+IN
6
0.1 mF
220 pF
ADS8422
8Vpp
C0G
-VIN
-VCC
-4V
0.1 mF
time
4
1000 W
+4.096V
2
3
THS4031
6
12 W
7
-IN
0.1 mF
7
-VIN = 8Vpp
with
Vincm=0V
1000 W
+VCC
Figure 33. Driver Circuit for Bipolar Fully Differential Input Signals with 0-V Common-Mode
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and
source impedance. Essentially, the current into the ADS8422 charges the internal capacitor array during the
sample period. After this capacitance has been fully charged, there is no further input current. The source of the
analog input voltage must be able to charge the input capacitance (30 pF) to a 16-bit settling level within the 70
ns acquisition time of the device. When the converter goes into hold mode, the input impedance is greater than
1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, both
-IN and +IN inputs should be within the limits specified. Outside of these ranges, the converter linearity may not
meet specifications. To minimize noise, low bandwidth input signals with low pass filters should be used.
Care should be taken to ensure that the output impedances of the sources driving the +IN and –IN inputs are
matched. If this is not observed, the two inputs could have different settling times. This may result in offset error,
gain error, and linearity error which change with temperature and input voltage.
When the converter enters hold mode, the voltage difference between the +IN and -IN inputs is captured on the
internal capacitor array.
DIGITAL INTERFACE
Timing and Control
See the timing diagrams for detailed information on timing signals and their requirements.
The ADS8422 uses an internal oscillator generated clock which controls the conversion rate and in turn the
throughput of the converter. No external clock input is required.
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PRINCIPLES OF OPERATION (continued)
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum
requirement has been met, the CONVST pin can be brought high). The converter switches from sample to hold
mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal is important
to the performance of the converter. The BUSY pin is brought high immediately following CONVST going low.
BUSY stays high through the conversion process and returns low when the conversion has ended and data is
available on the DB pins. Once the conversion is started, it cannot be stopped except with an asynchronous
RESET (or a logical PD1).
If CONVST is detected high at the end of conversion, the device immediately enters sampling mode and the
analog input is connected to the CDAC. Otherwise, the CDAC is connected to the analog input only when
CONVST goes high. The high duration of CONVST should be at least 100 ns. There is no maximum high pulse
duration specification for CONVST.
Reading Data
The ADS8422 outputs full parallel data in 2’s complement format as shown in Table 1. The parallel output is
active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of
CONVST. This is 30 ns prior to the falling edge of CONVST and 10 ns after the falling edge. No data read
should be attempted within this zone. Any other combination of CS and RD three-states the parallel output.
BYTE is used for multi-word read operation. BYTE is used whenever lower bits on the bus are output on the
higher byte of the bus. Refer to Table 1 for ideal output codes.
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION
ANALOG VALUE
Full scale range
2Vref
Least significant bit (LSB)
DIGITAL OUTPUT 2'S COMPLIMENT
2Vref)/65536
BINARY CODE
HEX CODE
(+Vref) –
0111 1111 1111 1111
7FFF
0V
0000 0000 0000 0000
0000
Midscale – 1 LSB
0V–
1111 1111 1111 1111
FFFF
-Full scale
–Vref+
1000 0000 0000 0000
8000
+Full scale
Midscale
The output data can be read as a full 16-bit word on pins DB15 – DB0 (MSB-LSB) if BYTE is low.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15-DB8. In this
case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on
pins DB15-DB8, then bringing BYTE high. When BYTE is high, the low bits (D7-D0) appear on pins DB15-DB8.
These multi-word read operations can be performed with a multiple active (toggling) RD signal or with the RD
signal tied low for simplicity.
Table 2. Conversion Data Read Out
DATA READ OUT
BYTE
PINS
DB15–DB8
PINS
DB7–DB0
High
D7 - D0
All One's
Low
D15 - D8
D7 - D0
RESET
RESET/PD1 is an asynchronous active low input signal. Maximum RESET/PD1 low time is 0.5 µs to avoid ADC
powerdown. Current conversion is aborted no later than 20 ns after the converter is in reset mode. The
converter returns to normal operation mode no later than 20 ns after the RESET/PD1 input is brought high (see
Figure 28).
The converter provides two power saving options: ADC powerdown (using pin 38, PD1) and analog output
powerdown (PD2).
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ADC powerdown is activated by asserting PD1 to 0 for longer than 1.5 µs. If the signal PD1 is asserted 0 for
less than 0.5 µs, the ADC is only reset and any ongoing conversion aborted. See Figure 26. ADC operation can
be resumed from ADC powerdown by de-asserting the PD1 pin. In ADC power-down mode, the analog outputs
from the ADC(COMMOUT, REFOUT) are not powered down thereby reducing the power-on time.
Full chip power-down is activated by turning off the power supply or by asserting both, PD1 = 0 and PD2 = 0 for
longer than 1.5 µs (see Figure 27). In this mode, even the analog outputs of the ADC (COMMOUT, REFOUT)
are powered down thereby giving maximum power saving. Device operation can be resumed from full chip
power-down by turning on the power supply or by deasserting both, PD1 = 1 and PD2 = 1.
Table 3. Effects of RESET, PD1, and PD2
COMMAND
APPLICATION TIME
POWER WHEN APPLIED
RESUME TIME
RESET/PD1 = 0
20 ns
No change
20 ns
PD1 = 0, PD2 = 1
1.5 µs
17mW
5 µs
PD1 = PD2 = 0
1.5 µs
40 µW
25 ms
PD1 = 1, PD2 = 0
Reserved – Do not use this combination
LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS8422 circuitry.
As the ADS8422 offers single-supply operation, it is often used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and
the higher the switching speed, the more difficult it is to achieve good performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving
any single conversion for an n-clock SAR converter, there are n windows in which large external transient
voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby
digital logic, or high power devices. The 50 ns period before BUSY falls should be kept free of supply glitches.
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the
external event.
On average, the ADS8422 draws very little current from an external reference as the reference voltage is
internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive
the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor is recommended from pin 1
directly to REFM (pin 48). REFM and AGND should be shorted on the same ground plane underneath the
device.
The AGND, BDGND, and AGND pins should be connected to a clean ground point. In all cases, this should be
the analog ground. Avoid connections which are too close to the grounding point of a microcontroller or digital
signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The
ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
As with the AGND connections, +VA and +VAREG should be connected to their respective power supply planes
or traces that are separate from the connection for digital logic, until they are connected at the power entry point.
Power to the ADS8422 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed
as close to the device as possible. See Table 4 for capacitor placement. In addition, a 1-µF to 10-µF capacitor is
recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor
or even a Pi filter made up of inductors and capacitors — all designed to essentially low-pass filter the +5-V
supply, thus removing the high frequency noise.
Table 4. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE
CONVERTER ANALOG SIDE
SUPPLY PINS
Pin pairs that require shortest path to decoupling capacitors
(4,5), (9,8), (10,12), (13,15), (43,44), (46,45)
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DIGITAL SIDE
(24,25), (34,35)
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APPLICATION INFORMATION
ADS8422 TO A HIGH PERFORMANCE DSP INTERFACE
Figure 34 shows a parallel interface between the ADS8422 and a Texas instruments high performance DSP
such as the TMS320C6713 using the full 16-bit bus. The ADS8422 is mapped onto the CE2 memory space of
the TMS320C6713 DSP. The read and reset signals are generated by using a 3-to-8 decoder. A read operation
from the address 0xA000C000 generates a pulse on the RD pin of the data converter, wheras a read operation
form word address 0xA0014000 generates a pulse on the RESET/PD1 pin. The CE2 signal of the DSP acts as
CS (chip select) for the converter. As the TMS320C6713 features a 32-bit external memory interface, the BYTE
input of the converter can be tied permanently low, disabling the foldback of the data bus. The BUSY signal of
the ADS8422 is appiled to the EXT_INT6 interrupt input of the DSP, enabling the EDMA controller to react on
the falling edge of this signal and to collect the conversion result. The TOUT1 (timer out 1) pin of the
TMS320C6713 is used to source the CONVST signal of the converter.
+VA = 5 V
+VAREG = 3 V
0W
0.1 mF
See Note A
AGND
0.1 mF
10 mF
AGND
CS
TMS320C6713
DSP
I/O Supply
+VBD +2.7 V
PD1/RESET
PD2
ADS8422
RD
Address
Decoder
EA[16:14]
−IN
+VAREG
+VA
REFIN
REFM
AGND
CE2
+IN
1 mF
10 mF
+VBD
0.1 mF
ARE
TOUT1
EXT_INTG
ED[15:0]
A.
Ext Ref
Input
Analog
Input
BDGND
BYTE
CONVST
BUSY
DB[15:0]
I/O Digital Ground
BDGND
This resistor (0 Ω) can be installed to use the same 5-V supply.
Figure 34. ADS8422 Application Circuitry
+VA = 5 V
+VAREG = 3 V
0W
AGND
0.1 mF
See Note A
10 mF
0.1 mF
AGND
0.1 mF
10 mF
A.
ADS8422
AGND
AGND
REFM
REFIN
REFOUT
+VA
+VAREG
1 mF
This resistor (0 Ω) can be installed to use the same 5-V supply.
Figure 35. ADS8422 Using Internal Reference
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS8422IBPFBR
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
8422I
B
ADS8422IBPFBT
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
8422I
B
ADS8422IBPFBTG4
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
8422I
B
ADS8422IPFBR
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
8422I
ADS8422IPFBRG4
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
8422I
ADS8422IPFBT
LIFEBUY
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ADS
8422I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Feb-2019
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
ADS8422IBPFBR
TQFP
PFB
48
ADS8422IBPFBT
TQFP
PFB
ADS8422IPFBR
TQFP
PFB
ADS8422IPFBT
TQFP
PFB
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
48
250
180.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
48
250
180.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS8422IBPFBR
TQFP
PFB
48
1000
350.0
350.0
43.0
ADS8422IBPFBT
TQFP
PFB
48
250
213.0
191.0
55.0
ADS8422IPFBR
TQFP
PFB
48
1000
350.0
350.0
43.0
ADS8422IPFBT
TQFP
PFB
48
250
213.0
191.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°– 7°
1,05
0,95
Seating Plane
0,75
0,45
0,08
1,20 MAX
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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