Texas Instruments | 250kSPS, 16-Bit, 6-Channel Simultaneous Sampling A/D Converters (Rev. C) | Datasheet | Texas Instruments 250kSPS, 16-Bit, 6-Channel Simultaneous Sampling A/D Converters (Rev. C) Datasheet

Texas Instruments 250kSPS, 16-Bit, 6-Channel Simultaneous Sampling A/D Converters (Rev. C) Datasheet
ADS8364
ADS
836
®
4
SBAS219C – JUNE 2002 – REVISED AUGUST 2006
250kSPS, 16-Bit, 6-Channel
Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTERS
FEATURES
DESCRIPTION
●
●
●
●
●
●
●
●
The ADS8364 includes six, 16-bit, 250kSPS ADCs (Analogto- Digital converters) with 6 fully differential input channels
grouped into two pairs for high-speed simultaneous signal
acquisition. Inputs to the sample-and-hold amplifiers are fully
differential and are maintained differential to the input of the
ADC. This provides excellent common-mode rejection of
80dB at 50KHz that is important in high-noise environments.
6 INPUT CHANNELS
FULLY DIFFERENTIAL INPUTS
6 INDEPENDENT 16-BIT ADC
4µs TOTAL THROUGHPUT PER CHANNEL
TESTED NO MISSING CODES TO 14 BITS
BUFFERED REFERENCE INPUTS
LOW POWER: 450mW
TQFP-64 PACKAGE
The ADS8364 offers a flexible high-speed parallel interface
with a direct address mode, a cycle, and a FIFO mode. The
output data for each channel is available as a 16-bit word.
APPLICATIONS
● MOTOR CONTROL
● MULTI-AXIS POSITIONING SYSTEMS
● 3-PHASE POWER CONTROL
CH A0+
CH A0–
CDAC
S/H
Amp
Comp
SAR
HOLDA
CH A1+
Interface
CDAC
A0
CH A1–
S/H
Amp
A1
Comp
A2
Conversion
and
Control
CH B0+
CH B0–
ADD
RD
CDAC
WR
S/H
Amp
CS
Comp
FD
EOC
CLK
SAR
CH B1+
CDAC
S/H
Amp
Comp
CH C0+
BYTE
16
CH B1–
CH C0–
RESET
FIFO
Register
6x
HOLDB
Data
Input/Output
CDAC
S/H
Amp
Comp
SAR
HOLDC
CH C1+
CDAC
CH C1–
S/H
Amp
Comp
REFIN
REFOUT
Internal
2.5V
Reference
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2002-2006, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Absolute Maximum Ratings over operating free-air temperature (unless
otherwise noted)(1)
Supply Voltage, AGND to AVDD ............................................................... –0.3V to 6V
Supply Voltage, BGND to BVDD ............................................................... –0.3V to 6V
Supply Voltage, DGND to DVDD .............................................................. –0.3V to 6V
Analog Input Voltage Range ..................... AGND – 0.3V to AVDD + 0.3V
Reference Input Voltage ........................... AGND – 0.3V to AVDD + 0.3V
Digital Input Voltage Range ...................... BGND – 0.3V to BVDD + 0.3V
Ground Voltage Differences, AGND to BGND/DGND ..................... ±0.3V
Voltage Differences, BVDD, DVDD to AGND .......................... –0.3V to 6V
Input Current ot Any Pin Except Supply ......................... –20mA to 20mA
Power Dissipation ....................................... See Dissipation Rating Table
Operating Virtual Junction Temperature Range, TJ ........ –40°C to 150°C
Operating Free-Air Temperature Range, TA ...................... –40°C to 85°C
Storage Temperature Range, TSTG .................................. –65°C to 150°C
Lead Temperature 1.6mm (1/16 inch) from Case for 10sec ..................... 260°C
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those
indicated under Recommended Operating Conditions is not implied. Exposure
to absolute-maximum-rated conditions of extended periods may affect device
reliability.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
MAXIMUM
INTEGRAL
LINEARITY
ERROR (LSB)
NO MISSING
CODES
ERROR (LSB)
ADS8364Y
±8
"
"
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
14
TQFP-64
PAG
–40°C to +85°C
"
"
"
"
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS8364Y/250 Tape and Reel, 250
ADS8364Y/2K Tape and Reel, 2000
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at www.ti.com.
PACKAGE DISSIPATION RATING TABLE
BOARD
PACKAGE
RθJC
RθJA
DERATING
FACTOR
ABOVE
TA = +25°C
Low-K(1)
PAG
PAG
8.6°C/W
8.6°C/W
68.5°C/W
42.8°C/W
14.598mW/°C
23.364mw/°C
High-K(2)
TA ≤ +25°C
POWER
RATING
TA = +70°C
POWER
RATING
TA = +85°C
POWER
RATING
1824mW
2920mW
1168mW
1869mW
949mW
1519mW
NOTES: (1) The JEDEC Low K (1s) board design used to derive this data was a 3-inch x 3-inch, two-layer board with 2-ounce copper traces on top of the board.
(2) The JEDEC High K (2s2p) board design used to derive this data was a 3-inch x 3-inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce
copper traces on the top and bottom of the board.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
Supply Voltage, AGND to AVDD
Supply Voltage, BGND to BVDD
4.75
2.7
4.5
4.75
–0.3
1.5
2.2
0
–40
5
5.25
3.6
5.5
5.25
0.3
2.6
2.8
±VREF
125
V
V
V
V
V
V
V
V
°C
Low-Voltage Levels
5V Logic Levels
Supply Voltage, DGND to DVDD
Difference AVDD to DVDD
Reference Input Voltage
Operating Common-Mode Signal
Analog Inputs
Operating Junction Temperature Range, TJ
–IN
+IN – (–IN)
5
5
0
2.5
2.5
EQUIVALENT INPUT CIRCUIT
AVDD
BVDD
RON = 20Ω
C(SAMPLE) = 20pF
AIN
DIN
AGND
Equivalent Analog Input Circuit
2
Diode Turn-on Voltage: 0.35V
BGND
Equivalent Digital Input Circuit
ADS8364
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SBAS219C
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at –40°C to +85°C, AVDD = DVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 5MHz, fSAMPLE = 250kSPS,
unless otherwise noted.
ADS8364Y
PARAMETER
CONDITIONS
ANALOG INPUT
Full-Scale Range
Operating Common-Mode Signal
Input Resistance
Input Capacitance
Input Leakage Current
Differential Input Resistance
Differential Input Capacitance
Common-Mode Rejection Ratio
(FSR)
TYP(1)
MAX
UNITS
±VREF
2.8
20
25
±1
40
50
84
80
300
V
V
Ω
pF
nA
Ω
pF
dB
dB
MHz
±3
1.5
±1.5
±0.05
0.2
0.8
±0.05
0.005
2
120
–87
Bits
Bits
LSB
LSB
LSB
mV
mV
ppm/°C
%FSR
%FSR
ppm/°C
µVRMS
dB
+IN – (–IN)
2.2
(CMRR)
Bandwith
(BW)
DC ACCURACY
Resolution
No Missing Codes
Integral Linearity Error
Integral Linearity Match
Differential Nonlinearity
Bipolar Offset Error
Bipolar Offset Error Match
Bipolar Offset Error Drift
Gain Error
Gain Error Match
Gain Error Drift
Noise
Power-Supply Rejection Ratio
–IN = VREF
–IN = VREF
–IN = VREF
–IN = VREF
–IN = VREF
At DC
VIN = ±1.25VPP at 50kHz
FS Sinewave, –3dB
16
14
(NMC)
(INL)
(DNL)
(VOS)
Only pair wise matching
Specified only for 14-Bit
Only pair wise matching
(TCVOS)
(GERR)
Referenced to VREF
Only pair wise matching
(TCGERR)
SAMPLING DYNAMICS
Conversion Time per ADC
Acquisition Time
Throughput Rate
Aperture Delay
Aperture Delay Matching
Aperture Jitter
Clock Frequncy
(PSRR)
4.75V < AVDD < 5.25V
(tCONV)
(tAQ)
50kHz ≤ fCLK ≤ 5MHz
fCLK = 5MHz
3.2
800
±8
±2
1
±0.25
0.05
320
250
5
100
50
0.05
AC ACCURACY
Total Harmonic Distortion
Spurous-Free Dynamic Range
Signal-to-Noise Ratio
Signal-to-Noise Ratio + Distortion
Channel-to-Channel Isolation
Effective Number of Bits
VOLTAGE REFERENCE OUTPUT
Reference Voltage Output
Initial Accuracy
Output Voltage Temperature Drift
Output Voltage Noise
MIN
(THD)
(SFDR)
(SNR)
(SINAD)
VIN = ±2.5VPP at 100kHz
VIN = ±2.5VPP at 100kHz
VIN = ±2.5VPP at 100kHz
VIN = ±2.5VPP at 100kHz
VIN = ±2.5VPP at 50kHz
–92
93.5
83.2
82.5
95
13.3
(ENOB)
(VOUT)
2.475
VOLTAGE REFERENCE INPUT
Reference Voltage Input
Reference Input Resistance
Reference Input Capacitance
Reference Input Current
f = 0.1Hz to 10Hz, CL = 10µF
f = 10Hz to 10kHz, CL = 10µF
(PSRR)
(IOUT)
(ISC)
to 0.1% at CL = 0
(VIN)
2.5
±20
40
8
60
10
0.5
100
(dVOUT/dT)
Power-Supply Refection Ratio
Output Current
Short-Circuit Current
Turn-On Settling Time
5
1.5
100
2.5
µs
ns
kSPS
ns
ps
ps
MHz
dB
dB
dB
dB
dB
Bits
2.525
±1
V
%
ppm/°C
µVPP
µVRMS
dB
µA
mA
µs
2.6
V
MΩ
pF
µA
5
1
NOTE: (1) All values are at TA = +25°C.
ADS8364
SBAS219C
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3
ELECTRICAL CHARACTERISTICS (Cont.)
Over recommended operating free-air temperature range at –40°C to +85°C, AVDD = DVDD = 5V, VREF = internal +2.5V, fCLK = 5MHz, fSAMPLE = 250kSPS, unless
otherwise noted.
ADS8364Y
PARAMETER
CONDITIONS
MIN
TYP(1)
MAX
UNITS
BVDD + 0.3
0.3 • BVDD
±50
V
V
nA
pF
INPUTS(2)
DIGITAL
Logic Family
High-Level Input Voltage
Low-Level Input Voltage
Input Current
Input Capacitance
DIGITAL OUTPUTS(2)
Logic Family
High-Level Output Voltage
Low-Level Output Voltage
High-Impedance-State Output Current
Output Capacitance
Load Capacitance
Data Format
DIGITAL INPUTS(3)
Logic Family
High-Level Input Voltage
Low-Level Input Voltage
Input Current
Input Capacitance
DIGITAL OUTPUTS(3)
Logic Family
High-Level Output Voltage
Low-Level Output Voltage
High-Impedance-State Output Current
Output Capacitance
Load Capacitance
Data Format
CMOS
(VIH)
(VIL)
(IIN)
(CI)
VI = BVDD or GND
5
CMOS
(VOH)
(VOL)
(IOZ)
(CO)
(CL)
BVDD = 4.5V, IOH = –100µA
BVDD = 4.5V, IOL = 100µA
CS = BVDD, VI = BVDD or GND
4.44
0.5
±50
5
30
V
V
nA
pF
pF
Binary Two's Complement
LVCMOS
(VIH)
(VIL)
(IIN)
(CI)
BVDD = 3.6V
BVDD = 2.7V
VI = BVDD or GND
(VOH)
(VOL)
(IOZ)
(CO)
(CL)
BVDD = 2.7V, IOH = –100µA
BVDD = 2.7V, IOL = 100µA
CS = BVDD, VI = BVDD or GND
2
–0.3
BVDD + 0.3
0.8
±50
5
V
V
nA
pF
LVCMOS
BVDD – 0.2
30
V
V
nA
pF
pF
5.25
3.6
5.5
5.25
90
300
300
4
470.9
471.5
V
V
V
V
mA
µA
µA
mA
mW
mW
0.2
±50
5
Binary Two's Complement
POWER SUPPLY
Analog Supply Voltage
Buffer I/O Supply Voltage
(AVDD)
(BVDD)
Digital Supply Voltage
Analog Operating Supply Current
Buffer I/O Operating Supply Current
(DVDD)
(AIDD)
(BIDD)
Digital Operating Supply Current
Power Dissipation
0.7 • BVDD
–0.3
Low-Voltage Levels
5V Logic Levels
4.75
2.7
4.5
4.75
80
BVDD = 3V
BVDD = 5V
(DIDD)
BVDD = 3V
BVDD = 5V
200
2.5
413.1
413.5
NOTES: (1) All values are at TA = +25°C.
(2) Applies for 5.0V nominal Supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V.
(3) Applies for 3.0V nominal Supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V.
4
ADS8364
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SBAS219C
A2
ADD
RESET
57
56
55
54
53
52
51
50
BGND
A1
58
BVDD
A0
AVDD
59
HOLD A
60
HOLD B
61
HOLD C
62
AGND
63
REFOUT
CH A0+
64
REFIN
CH A0–
PIN CONFIGURATION
49
CH A1–
1
48 D0
CH A1+
2
47 D1
AVDD
3
46 D2
AGND
4
45 D3
SGND
5
44 D4
CH B0+
6
43 D5
CH B0–
7
42 D6
AVDD
8
AGND
9
41 D7
ADS8364
40 D8
SGND 10
39 D9
CH B1– 11
38 D10
CH B1+ 12
37 D11
27
28
29
30
31
32
BGND
BGND
26
CS
25
WR
24
RD
23
CLK
22
EOC
21
FD
20
BVDD
19
BYTE
18
DVDD
17
NC
33 D15
DGND
34 D14
CH C0+ 16
CH C1+
35 D13
SGND 15
CH C1–
36 D12
CH C0–
AVDD 13
AGND 14
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
NAME
I/O
DESCRIPTION
CH A1– AI Inverting Input Channel A1
CH A1+ AI Noninverting Input channel A1
AVDD
P Analog Power Supply
AGND
P Analog Ground
SGND
P Signal Ground
CH B0+ AI Noninverting Input Channel B0
CH B0– AI Inverting Input Channel B0
AVDD
P Analog Power Supply
AGND
P Analog Ground
SGND
P Signal Ground
CH B1– AI Inverting Input Channel B1
CH B1+ AI Noninverting Input Channel B1
AVDD
P Analog Power Supply
AGND
P Analog Ground
SGND
P Signal Ground
CH C0+ AI Noninverting Input Channel C0
CH C0– AI Inverting Input Channel C0
CH C1– AI Inverting Input Channel C1
CH C1+ AI Noninverting Input Channel C1
NC
– No Connection
DGND
P Digital ground connected to AGND.
DVDD
P +5V Power Supply for Digital Logic Connected to AVDD.
BYTE
DI 2 x 8 Output Capability. Active HIGH.
BVDD
P Power supply for digital interface from 3V to 5V.
BGND
P Buffer Digital Ground
FD
DO First Data, A0 Data
EOC
DO End of Conversion, Active LOW
CLK
DI An external CMOS compatible clock can be applied to
the CLK input to synchronize the conversion process to
an external source.
RD
DI Read, Active LOW
WR
DI Write, Active LOW
CS
DI Chip Select, Active LOW
PIN
NAME
I/O
DESCRIPTION
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
BGND
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
BGND
BVDD
RESET
ADD
A2
A1
A0
HOLDA
HOLDB
HOLDC
AVDD
AGND
REFOUT
REFIN
CH A0+
CH A0–
P
DO
DO
DO
DO
DO
DO
DO
DO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
P
P
DI
DI
DI
DI
DI
DI
DI
DI
P
P
AO
AI
AI
AI
Buffer Digital Ground
Data Bit 15-MSB
Data Bit 14
Data Bit 13
Data Bit 12
Data Bit 11
Data Bit 10
Data Bit 9
Data Bit 8
Data Bit 7, Software Input 7
Data Bit 6, Software Input 6
Data Bit 5, Software Input 5
Data Bit 4, Software Input 4
Data Bit 3, Software Input 3
Data Bit 2, Software Input 2
Data Bit 1, Software Input 1
Data Bit 0, Software Input 0
Buffer Digital Ground
Power Supply for Digital Interface from 3V to 5V
Global Reset, Active LOW
Address Mode Select
Address Line 3
Address Line 2
Address Line 1
Hold Command A
Hold Command B
Hold Command C
Analog Power Supply
Analog Ground
Reference Output, attach 0.1µF and 10µF capacitors.
Reference Input
Noninverting Input Channel A0
Inverting Input Channel A0
NOTE: AI is Analog Input, AO is Analog Output, DI is Digital Input, DO is Digital Output, DIO is Digital Input/Output, P is Power Supply Connection.
ADS8364
SBAS219C
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5
TIMING CHARACTERISTICS
tC1
CLK
1
tW1
2
16
17
18
tD1
19
20
1
2
ACQUISITION
tACQ
CONVERSION
tCONV
HOLDX
tW3
tW2
EOC
CS
tD4
tD5
tW6
RD
tW5
tD6
tD7
D15-D8
Bits 15-8
Bits 15-8
D7-D0
Bits 7-0
Bits 7-0
BYTE
TIMING CHARACTERISTICS TABLE
Timing Characteristics over recommended operating free-air temperature range TMIN to TMAX, AVDD = DVDD = 5V, REFIN = REFOUT internal reference +2.5V,
fCLK = 5MHz, fSAMPLE = 250kSPS, BVDD = 2.7 ÷ 5V (unless otherwise noted).
SPEC
DESCRIPTION
MIN
tCONV
tACQ
tC1
tW1
tD1(5)
tW2
Conversion Time
Acquistion Time
Cycle Time of CLK
Pulse Width CLK HIGH Time or LOW Time.
Delay Time of Rising Edge of Clock After Falling Edge of HOLD (A,B,C)
Pulse Width of HOLDX HIGH Time to be Recognized again
tW3
Pulse Width of HOLDX LOW Time
tW4
Pulse Width of RESET
tW5
Pulse Width of RD HIGH Time
tD2
Delay Time of First Hold After RESET
tD4
tD5
tW6
Delay Time of Falling Edge of RD After Falling Edge of CS
Delay Time of Rising Edge of CS After Rising Edge of RD
Pulse Width of RD and CS Both LOW Time
tW7
Pulse Width of RD HIGH Time
tD6
Delay Time of Data Valid After Falling Edge RD
tD7
Delay Time of Data Hold From Rising Edge of RD
tD8
Delay Time of RD HIGH After CS LOW
tD9
Delay Time of RD Low After Address Setup
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
=
=
=
=
=
=
=
=
=
=
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
BVDD
=
=
=
=
=
=
=
=
=
=
=
=
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
200
60
10
15
30
20
30
20
40
30
40
20
40
0
0
50
70
20
40
40
60
5
10
50
60
10
20
TYP(1)
MAX
UNITS
3.2
0.8
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES: (1) Assured by design. (2) All input signals are specified with tr = tf = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2.
(3) See timing diagram above. (4) BYTE is asynchronous; when BYTE is 0, bits 15 through 0 appear at DB15-DB0. When BYTE is 1, bits 15 through 8
appear on DB7-DB0. RD may remain LOW between changes in BYTE. (5) Only important when synchronization to clock is important.
6
ADS8364
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SBAS219C
TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = DVDD = +5V, BVDD = 3V VREF = internal +2.5V and fCLK = 5MHz, fSAMPLE = 250kSPS, unless otherwise noted.
INTEGRAL LINEARITY ERROR vs CODE
5
4
Typical curve for all six channels.
2
3
2
1
DNL (LSB)
INL (LSB)
DIFFERENTIAL LINEARITY ERROR vs CODE
3
Typical curve for all six channels
1
0
–1
0
–1
–2
–3
–2
–4
–5
0000H
8000H
C000H
–3
0000H
FFFFH
4000H
8000H
C000H
FFFFH
Output Code
Output Code
MINIMUM AND MAXIMUM INL OF ALL CHANNELS
vs TEMPERATURE
MINIMUM AND MAXIMUM DNL OF ALL CHANNELS
vs TEMPERATURE
3
Minimum and Maximum DNL (LSB)
Minimum and Maximum INL (LSB)
4
4000H
3
2
1
0
–1
–2
2
1
0
–1
–2
–3
–3
–50
3.0
–25
0
25
50
75
100
–50
–25
0
25
50
75
Temperature (°C)
Temperature (°C)
INTEGRAL LINEARITY MATCH OF
CHANNELS A0 AND A1 vs CODE
FREQUENCY SPECTRUM
(4096 point FFT, FIN = 100kHz, –0.2dB)
100
0
–20
2.0
Amplitude (dB)
INL Match (LSB)
–40
1.0
0.0
–1.0
–60
–80
–100
–120
–2.0
–3.0
0000H
–140
–160
4000H
8000H
C000H
FFFFH
ADS8364
SBAS219C
0
31
62
93
125
Frequency (kHz)
Output Code
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7
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, AVDD = DVDD = +5V, BVDD = 3V VREF = internal +2.5V and fCLK = 5MHz, fSAMPLE = 250kSPS, unless otherwise noted.
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-NOISE + DISTORTION vs
INPUT FREQUENCY
100
1.0
0.8
90
SNR and SINAD (dB)
95
SNR and SINAD (dB)
DELTA OF SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-NOISE + DISTORTION
vs TEMPERATURE (ALL CH)
SNR
85
80
SINAD
75
0.6
SNR
0.4
0.2
0.0
–0.2
–0.4
SINAD
–0.6
70
–0.8
65
–1.0
100 125
10
–50
–25
Frequency (kHz)
25
50
75
100
Temperature (°C)
SPURIOUS-FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY (All CH)
110
0
DELTA OF SPURIOUS-FREE DYNAMIC RANGE
AND TOTAL HARMOINC DISTORTION
vs TEMPERATURE (ALL CH)
–110
3
3
2
2
–100
THD
90
–90
THD
SFDR (dB)
SFR
THD (dB)
SFDR (dB)
100
1
1
0
0
–1
80
–1
–80
SFR
–2
70
1
–70
100 125
10
–2
–3
–50
–25
Frequency (kHz)
0
50
–3
100
75
OFFSET MATCHING BETWEEN CHANNELS
vs TEMPERATURE
0.40
0.35
Channel A
Offset Matching (mV)
0.30
Offset (mV)
25
Temperature (°C)
OFFSET OF ALL CHANNELS vs TEMPERATURE
0.40
THD (dB)
1
0.25
0.20
0.15
0.10
0.30
0.20
Channel B
Channel C
0.10
0.05
0.00
0.00
–50
–25
0
25
50
75
–50
100
8
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
ADS8364
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SBAS219C
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, AVDD = DVDD = +5V, BVDD = 3V VREF = internal +2.5V and fCLK = 5MHz, fSAMPLE = 250kSPS, unless otherwise noted.
POSITIVE GAIN MATCH OF ALL CHANNELS
vs TEMPERATURE
0.0025
Channel B
0.0020
Channel A
0.0015
Channel C
0.0010
–50
–25
0
25
50
75
NEGATIVE GAIN MATCH OF ALL CHANNELS
vs TEMPERATURE
0.0025
Negative Gain Match (%FSR)
Positive Gain Match (%FSR)
0.0030
Channel C
0.0020
Channel A
0.0015
Channel B
0.0010
0.0005
0.0000
–50
100
–25
50
75
100
75
100
75
100
2.49600
Channel A
Channel B
Channel C
2.49400
Reference Voltages (V)
0.060
Gain Error (%FSR)
25
REFOUT vs TEMPERATURE
GAIN ERROR OF CHANNELS vs TEMPERATURE
0.065
0
Temperature (°C)
Temperature (°C)
0.055
0.050
0.045
0.040
2.49200
2.49000
2.48800
2.48600
0.035
2.48400
0.030
2.48200
–50
–25
0
25
50
Temperature (°C)
75
100
–50
0
25
50
Temperature (°C)
CHANNEL-TO-CHANNEL ISOLATION
–80
–25
IQ vs TEMPERATURE
83.0
82.0
81.0
80.0
–95
IQ (mV)
Signal on Ch B1 (dB)
–90
–100
79.0
78.0
77.0
76.0
–105
75.0
–110
74.0
0
10
20
30
40
50
AC Frequency on Ch B0 (kHz)
–25
0
25
50
Temperature (°C)
ADS8364
SBAS219C
–50
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9
INTRODUCTION
The ADS8364 is a high-speed, low-power, 6-channel simultaneous sampling and converting, 16-bit ADC that operates
from a single +5V supply. The input channels are fully
differential with a typical common-mode rejection of 80dB.
The part contains six 4µs successive approximation ADCs,
six differential sample-and-hold amplifiers, an internal +2.5V
reference with REFIN and REFOUT pins and a high-speed
parallel interface. There are six analog inputs that are grouped
into three channel pairs (A, B, and C). There are six ADCs,
one for each input that can be sampled and converted
simultaneously, thus preserving the relative phase information of the signals on both analog inputs. Each pair of
channels has a hold signal (HOLDA, HOLDB, and HOLDC)
to allow simultaneous sampling on each channel pair, on
four or on all six channels. The part accepts a differential
analog input voltage in the range of –VREF to +VREF, centered
on the common-mode voltage (see the Analog Input Section).
The part will also accept bipolar input ranges when a level shift
circuit is used at the front end (see Figure 6).
A conversion is initiated on the ADS8364 by bringing the
HOLDX pin LOW for a minimum of 20ns. HOLDX LOW
places the sample-and-hold amplifiers of the X channels in
the hold state simultaneously and the conversion process is
started on each channel. The EOC output will go LOW for
half a clock cycle when the conversion is latched into the
output register. The data can be read from the parallel output
bus following the conversion by bringing both RD and CS
LOW.
Conversion time for the ADS8364 is 3.2µs when a 5MHz
external clock is used. The corresponding acquisition time is
0.8µs. To achieve the maximum output data rate (250kSPS),
the read function can be performed during the next conversion. Note: This mode of operation is described in more
detail in the Timing and Control section of this data sheet.
50ps (also known as aperture jitter). These specifications
reflect the ability of the ADS8364 to capture AC input signals
accurately at the exact same moment in time.
REFERENCE
Under normal operation, the REFOUT (pin 61) can directly be
connected to the REFIN pin (pin 62) to provide an internal
+2.5V reference to the ADS8364. The ADS8364 can
operate, however, with an external reference in the range of
1.5V to 2.6V, for a corresponding full-scale range of 3.0V to
5.2V, as long as the input does not exceed the AVDD + 0.3V
value.
The reference of the ADS8364 is double-buffered. If the
internal reference is used to drive an external load, a buffer
is provided between the reference and the load applied to pin
61 (the internal reference can typically source 10µA of
current—load capacitance should be 0.1µF and 10µF to
minimize noise). If an external reference is used, the threesecond buffers provide isolation between the external reference and the CDACs. These buffers are also used to
recharge all of the capacitors of all CDACs during conversion.
ANALOG INPUT
The analog input is bipolar and fully differential. There are two
general methods of driving the analog input of the ADS8364:
single-ended or differential, as shown in Figure 1 and
Figure 2. When the input is single-ended, the –IN input is held
at the common-mode voltage. The +IN input swings around
the same common voltage and the peak-to-peak amplitude is
the (common-mode + VREF) and the (common-mode – VREF).
The value of VREF determines the range over which the
common-mode voltage may vary (see Figure 3).
–VREF to +VREF
peak-to-peak
SAMPLE-AND-HOLD SECTION
The sample-and-hold amplifiers on the ADS8364 allow the
ADCs to accurately convert an input sine wave of full-scale
amplitude to 16-bit resolution. The input bandwidth of the
sample-and-hold is greater than the Nyquist rate (Nyquist
equals one-half of the sampling rate) of the ADC even when
the ADC is operated at its maximum throughput rate of
250kSPS. The typical small-signal bandwidth of the sampleand-hold amplifiers is 300MHz.
Typical aperture delay time or the time it takes for the
ADS8364 to switch from the sample to the hold mode
following the negative edge of HOLDX signal is 5ns. The
average delta of repeated aperture delay values is typically
10
ADS8364
Common
Voltage
Single-Ended Input
VREF
peak-to-peak
Common
Voltage
ADS8364
VREF
peak-to-peak
Differential Input
FIGURE 1. Methods of Driving the ADS8364 Single-Ended or
Differential.
ADS8364
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SBAS219C
+IN
CM + VREF
+VREF
CM Voltage
–IN = CM Voltage
–VREF
t
CM – VREF
Single-Ended Inputs
+IN
CM + 1/2VREF
+VREF
CM Voltage
–VREF
–IN
CM – 1/2VREF
t
Differential Inputs
NOTES: Common-Mode Voltage (Differential Mode) =
(+IN) + (–IN)
, Common-Mode Voltage (Single-Ended Mode) = IN–.
2
The maximum differential voltage between +IN and –IN of the ADS8364 is VREF. See Figures 3 and 4 for a further
explanation of the common voltage range for single-ended and differential inputs.
FIGURE 2. Using the ADS8364 in the Single-Ended and Differential Input Modes.
5
5
AVDD = 5V
4.55
AVDD = 5V
3
2.7
Single-Ended Input
2.3
2
1
1.2
3
Differential Input
2
1.0
1
0.45
0
0
–1
–1
1.0
4.0
4
3.8
Common Voltage Range (V)
Common Voltage Range (V)
4
1.5
2.0
2.5
2.6
1.0
3.0
1.5
2.0
2.5
2.6
3.0
VREF (V)
VREF (V)
FIGURE 3. Single-Ended Input: Common-Mode Voltage
Range vs VREF.
FIGURE 4. Differential Input: Common-Mode Voltage
Range vs VREF.
When the input is differential, the amplitude of the input is the
difference between the +IN and –IN input, or: (+IN) – (–IN).
The peak-to-peak amplitude of each input is ±1/2VREF around
this common voltage. However, since the inputs are 180°
out-of-phase, the peak-to-peak amplitude of the differential
voltage is +VREF to –VREF. The value of VREF also determines
the range of the voltage that may be common to both inputs,
as shown in Figure 4.
In each case, care should be taken to ensure that the output
impedance of the sources driving the +IN and –IN inputs are
matched. Often, a small capacitor (20pF) between the positive and negative input helps to match their impedance.
Otherwise, this may result in offset error, which will change
with both temperature and input voltage.
The input current on the analog inputs depends on a number
of factors as sample rate or input voltage. Essentially, the
ADS8364
SBAS219C
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11
current into the ADS8364 charges the internal capacitor
array during the sampling period. After this capacitance has
been fully charged, there is no further input current. The
source of the analog input voltage must be able to charge the
input capacitance (25pF) to a 16-bit settling level within 3
clock cycles if the minimum acquisition time is used. When
the converter goes into the hold mode, the input impedance
is greater than 1GΩ.
R1
4kΩ
1.2kΩ
20kΩ
–IN
1183
930
906
813
720
0
680
167
32803 32804 32805 32806
32807 32808 32809 32810 32811
67
0
32812
32813
ADS8364
R2
OPA227
TRANSITION NOISE
2726
1.2kΩ
Bipolar Input
Care must be taken regarding the absolute analog input
voltage. The +IN and –IN inputs should always remain within
the range of AGND – 0.3V to AVDD + 0.3V.
The transition noise of the ADS8364 itself is low,
as shown in Figure 5. These histograms were generated by
applying a low-noise DC input and initiating 8000 conversions.
The digital output of the ADC will vary in output code due to
the internal noise of the ADS8364. This is true for all 16-bit,
SAR-type ADCs. Using a histogram to plot the output codes,
the distribution should appear bell-shaped with the peak of the
bell curve representing the nominal code for the input value.
The ±1σ, ±2σ, and ±3σ distributions will represent the 68.3%,
95.5%, and 99.7%, respectively, of all codes. The transition
noise can be calculated by dividing the number of codes
measured by 6 and this will yield the ±3σ distribution, or
99.7%, of all codes. Statistically, up to three codes could fall
outside the distribution when executing 1000 conversions.
Remember, to achieve this low-noise performance, the peakto-peak noise of the input signal and reference must be
< 50µV.
+IN
OPA227
BIPOLAR INPUT
R1
R2
±10V
±5V
±2.5V
1kΩ
2kΩ
4kΩ
5kΩ
10kΩ
20kΩ
REFOUT (pin 61)
2.5V
FIGURE 6. Level Shift Circuit for Bipolar Input Ranges.
TIMING AND CONTROL
The ADS8364 uses an external clock (CLK, pin 28) which
controls the conversion rate of the CDAC. With a 5MHz
external clock, the ADC sampling rate is 250kSPS which
corresponds to a 4µs maximum throughput time. Acquistion
and conversion takes a total of 20 clock cycles.
THEORY OF OPERATION
The ADS8364 contains six 16-bit ADCs that can operate
simultaneously in pairs. The three hold signals (HOLDA,
HOLDB, and HOLDC) initiate the conversion on the specific
channels. A simultaneous hold on all six channels can occur
with all three hold signals strobe together. The converted
values are saved in six registers. For each read operation,
the ADS8364 outputs 16 bits of information (16 Data or 3
Channel Address, Data Valid, and some synchronization
information). The Address/Mode signals (A0, A1, and A2)
select how the data is read from the ADS8364. These
Address/Mode signals can define a selection of a single
channel, a cycle mode that cycles through all channels, or a
FIFO mode that sequences the data determined by the order
of the hold signals. The FIFO mode will allow the six registers
to be used by a single-channel pair and, therefore, three
locations for CH X0 and three locations for CH X1 can be
updated before they are read from the part.
Code
EXPLANATION OF CLOCK, RESET , FD, AND EOC PINS
FIGURE 5. 8000 Conversion Histogram of a DC Input.
BIPOLAR INPUTS
The differential inputs of the ADS8364 were designed to accept
bipolar inputs (–VREF and +VREF) around the common-mode
voltage (2.5V), which corresponds to a 0V to 5V input range with
a 2.5V reference. By using a simple op amp circuit featuring
four, high-precision external resistors, the ADS8364 can be
configured to accept bipolar inputs. The conventional ±2.5V,
±5V, and ±10V input ranges could be interfaced to the ADS8364
using the resistor values shown in Figure 6.
12
Clock—An external clock has to be provided for the ADS8364.
The maximum clock frequency is 5MHz. The minimum clock
cycle is 200ns (Timing Diagram, tC1), and the clock has to remain
HIGH (Timing Diagram, tW1) or LOW for at least 60ns.
RESET —Bringing reset signal LOW will reset the ADS8364.
It will clear all the output registers, stop any actual conversions, and will close the sampling switches. The reset signal
has to stay LOW for at least 20ns (see Figure 7, tW4). The
reset signal should be back HIGH for at least 20ns (see
Figure 7, tD2), before starting the next conversion (negative
hold edge).
ADS8364
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SBAS219C
EOC—End of conversion goes low when new data of the
internal ADC is latched into the output registers, which
usually happens 16.5 clock cycles after hold initiated the
conversion. It remains low for half a clock cycle. If more than
one channel pair is converted simultaneously, the
A-channels get stored to the registers first (16.5 clock cycles
after hold), followed by the B-channels one clock cycle later,
and finally the C-channels at another clock cycle later. If a
reading (RD and CS are LOW) is in process, then the latch
process is delayed until the read operation is finished.
FD—First data or A0 data is HIGH if channel A0 is chosen to be
read next. In the FIFO mode whatever channel X0 is written to
the FIFO first is latched into the A0 register. So, for example,
when the FIFO is empty, FD is 0. Then the first result is latched
into the FIFO register A0 is, therefore, chosen to be read next,
and FD rises. After the first channel is read (1-3 read cycles
depending on BYTE and ADD) FD goes LOW again.
The ADS8364 can also convert one channel continuously
(see Figure 8). Therefore, HOLDA and HOLDC are kept
HIGH all the time. To gain acquisition time, the falling edge
of HOLDB takes place just before the rising edge of clock.
One conversion requires 20 clock cycles. Here, data is read
after the next conversion is initiated by HOLDB. To read data
from channel B, A1 is set HIGH and A2 is LOW. As A0 is
LOW during the first reading (A2 A1 A0 = 010) data B0 is put
to the output. Before the second RD, A0 switches HIGH (A2
A1 A0 = 011) so data from channel B1 is read, as shown in
Table II. However, reading data during the conversion or on a
falling hold edge might cause a loss in performance.
A2
A1
A0
0
0
0
CHA0
0
0
1
CHA1
0
1
0
CHB0
0
1
1
CHB1
1
0
0
CHC0
1
0
1
CHC1
1
1
0
Cycle mode reads registers
START OF A CONVERSION AND READING DATA
By bringing one, two, or all of the HOLDX signals LOW, the
input data of the corresponding channel X is immediately
placed in the hold mode (5ns). The conversion of this channel
X follows with the next rising edge of clock. If it is important to
detect a hold command during a certain clock-cycle, then the
falling edge of the hold signal has to occur at least 10ns before
the rising edge of clock, as shown in Figure 7, tD1. The hold
signal can remain LOW without initiating a new conversion.
The hold signal has to be HIGH for at least 15ns (as shown
in Figure 7, tW2) before it is brought LOW again and hold has
to stay LOW for at least 20ns (Figure 7, tW3).
Once a particular hold signal goes low, further impulses of
this hold signal are ignored until the conversion is finished or
the part is reset. When the conversion is finished (after 16
clock cycles) the sampling switches will close and sample the
selected channel. The start of the next conversion must be
delayed to allow the input capacitor of the ADS8364 to be
fully charged. This delay time depends on the driving amplifier, but should be at least 800ns.
CHANNEL TO BE READ
CHA0 through CHC1 on
successive transitions of the
read line.
1
1
1
FIFO Mode
TABLE II. Address Control for RD Functions.
Reading data (RD , CS )—In general, the channel/data
outputs are in tri-state. Both CS and RD have to be LOW to
enable these outputs. RD and CS have to stay LOW together for at least 40ns (see Timing Characteristics, tD6)
before the output data is valid. RD has to remain HIGH for
at least 30ns (see Timing Diagram, tW5) before bringing it
back LOW for a subsequent read command.
16.5 clock-cycles after the start of a conversion (next rising
edge of clock after the falling edge of HOLDX ), the new data
is latched into its output register. Even if the ADS8364 is
forced to wait until the read process is finished (RD signal
going HIGH) before the new data gets latched into its output
tC1
CLK
tD1
tW1
HOLD A
tW3
HOLD B
tD2
tW2
HOLD C
tW4
RESET
FIGURE 7. Start of the Conversion.
ADS8364
SBAS219C
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13
CONVERSION
CLK
1
2
ACQUISITION
16
17
18
19
20
1
2
HOLD B
EOC
CS
RD
A0
FIGURE 8. Timing of one Conversion Cycle.
CLK
16
17
18
19
20
1
2
tD1
HOLD X
tACQ
EOC
CS
tD8
tW7
RD
tD9
A0
FIGURE 9. Timing for Reading Data.
register, the possibility still exists that the new data was
latched to the output register just before the falling edge of
RD. If a read process is initiated around 16.5 clock cycles
after the conversion started, RD and CS should stay LOW
for at least 50ns (see Timing Diagram, tW6) to get the new
data stored to its register and switched to the output.
CS being LOW tells the ADS8364 that the bus on the board
is assigned to the ADS8364. If an ADC shares a bus with
digital gates, there is a possibility that digital (high-frequency)
noise will be coupled into the ADC. If the bus is just used by
the ADS8364, CS can be hardwired to ground. Reading data
at the falling edge of one of the HOLDX signals might cause
noise.
BYTE—If there is only an 8-bit bus available on a board,
then BYTE can be set HIGH. (see Figure 11) In this case, the
lower 8 bits can be read at the output pins D15 to D8 or D7
to D0 at the first RD signal and the higher bits after the
second RD signal. If the ADS8364 is used in the cycle or the
FIFO mode, then the address and a data valid information is
added to the data if ADD is HIGH. In this case, the address will
be read first, then the lower 8 bits, and finally the higher 8 bits.
14
If BYTE is LOW, then the ADS8364 operates in the 16-bit
output mode. Here, data is read between the pins DB15 and
DB0. As long as ADD is LOW, with every RD-impulse, data
from a new channel is brought to the output. If ADD is HIGH,
and the cycle or the FIFO mode is chosen; the first output
word will contain the address, while the second output word
contains the 16-bit data.
ADD-Signal–In the cycle and the FIFO mode, it might be
desirable to have address information with the 16-bit output
data. Therefore, ADD can be set HIGH. In this case, two (or
three readings if the part is operated with byte being HIGH)
RD-signals are necessary to read data of one channel, while
the ADS8364 provides channel information on the first RD
signal (see Table III and Table IV).
The signals ADD, A0, A1, A2, RESET, HOLDA, HOLDB,
and HOLDC are accessible through the data bus and control
word. All these pins are in OR configuration with hardware
pins. When software configuration is used, the corresponding pins must be connected to ground or the power supply.
When the MSB is HIGH, the device is in the configuration
mode. MSB LOW will start conversion or reset the part.
ADS8364
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SBAS219C
0111111111111111
65535
0111111111111110
65534
0111111111111101
65533
0000000000000001
32769
0000000000000000
32768
1111111111111111
32767
1000000000000010
Step
Digital Output Code
Binary Two's Complement
BTC
2
1000000000000001
1
1000000000000000
0
2.499962V
VNFS = VCM – VREF = 0V
0.000038V
2.500038V
VPFS = VCM + VREF = 5V
VPFS – 1LSB = 4.999924V
VBPZ = 2.5V
0.000076V
4.999848V
Unipolar Analog Input Voltage
1LSB = 76µV
0.000152V
VCM = 2.5V
16-BIT
VREF = 2.5V
Bipolar Input, Binary Two’s Complement Output: (BTC)
Negative Full-Scale Code = VNFS = 8000H, Vcode = VCM – VREF
Bipolar Zero Code
= VBPZ = 0000H, Vcode = VCM
Positive Full-Scale Code = VPFS = 7FFFH, Vcode = (VCM + VREF) – 1LSB
FIGURE 10. Ideal Conversion Characteristics (Condition: Single-Ended, VCM = chXX– = 2.5V, VREF = 2.5V)
CS
RD
BYTE
D7 – D0
A0
A0
A1
A1
B0
B0
LOW
HIGH
LOW
HIGH
LOW
HIGH
B1
C0
C1
A0
FIGURE 11. Reading Data in Cycling Mode.
ADS8364
SBAS219C
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15
ADD = 0
BYTE = 0
BYTE = 1
A2 A1 A0
1st RD
2nd RD
1st RD
2nd RD
3rd RD
000
001
010
011
100
101
110
111
db15...db0
db15...db0
db15...db0
db15...db0
db15...db0
db15...db0
db15...db0
db15...db0
no 2nd RD
no 2nd RD
no 2nd RD
no 2nd RD
no 2nd RD
no 2nd RD
no 2nd RD
no 2nd RD
db7...db0
db7...db0
db7...db0
db7...db0
db7...db0
db7...db0
db7...db0
db7...db0
db15...db8
db15...db8
db15...db8
db15...db8
db15...db8
db15...db8
db15...db8
db15...db8
no 3rd RD
no 3rd RD
no 3rd RD
no 3rd RD
no 3rd RD
no 3rd RD
no 3rd RD
no 3rd RD
TABLE III. Overview of the Output Formats Depending
on the Mode (Case ADD = 0).
The HOLD signals will start conversion automatically on the
next clock cycle. The format of the two words that can be
writing to ADS8364 are shown in Table V.
New data is always written into the next available register. At t0
(see Figure 12), the reset deletes all the existing data. At t1, the
new data of the channels A0 and A1 are put into registers 0 and
1. At t2, the read process of channel A0 data is finished.
Therefore, this data is dumped and A1 data is shifted to register
0. At t3, new data is available, this time from channels B0, B1,
C0 and C1. This data is written into the next available registers
(registers 1, 2, 3, and 4).
On t4, the new read process of channel A1 data is finished.
The new data of channel C0 and C1 at t5 is put on top
(registers 4 and 5).
GETTING DATA
Flexible output modes: (A0, A1, A2)
The ADS8364 has three different output modes that are selected with A2, A1, and A0.
With (A2 A1 A0) = 000 to 101, a particular channel can directly
be addressed (see Table II and Figure 9). The channel address
should be set at least 10ns (see Figure 9, tD9) before the falling
edge of RD and should not change as long as RD is LOW. In
this standard address mode, ADD will be ignored, but should be
connected to either ground or supply.
With (A2 A1 A0) = 110, the interface is running in a cycle mode
(see Figure 11). Here, data 7 down to 0 of channel A0 is read
on the first RD-signal and 15 down to 8 on the second as BYTE
is HIGH. Then A1 on the second, followed by B0, B1, C0, and
finally, C1 before reading A0 again. Data from channel A0 is
brought to the output first after a reset-signal or after powering
the part up. The third mode is a FIFO mode that is addressed
with (A2 A1 A0 = 111). Data of the channel that is converted first
will be read first. So, if a particular channel pair is most
interesting and is converted more frequently (e.g., to get a
history of a particular channel pair) then there are three output
registers per channel available to store data.
ADD = 1
If all the output registers are filled up with unread data and new
data from an additional conversion has to get latched in, then
the oldest data gets thrown away. If a read process is going on
(RD-signal LOW) and new data has to be stored, then the
ADS8364 will wait until the read process is finished (RD-signal
going HIGH) before the new data gets latched into its output
register. Again, with the ADD signal, it can be chosen if the
address should be added to the output data.
In Cycle mode and in FIFO mode, the ADS8364 offers the
ability to add the address of the channel to the output data.
As there is just a 16-bit bus available (or 8-bit bus in the case
byte is HIGH), an additional (RD-signal is necessary to get
the information (see Table III and Table IV).
The Output Code (DB15…DB0)–In the standard address
mode (A2 A1 A0 = 000…101), the ADS8364 has a 16-bit output
word on pins DB15…DB0 if BYTE = 0. If BYTE = 1 then two
RD-impulses are necessary to first read the lower bits then the
higher bits on either DB7…DB0 or DB15...DB8.
The address of the channel (a2a1a0) and a data valid (dv) bit
is added to the data if the ADS8364 is operated in the cycle
or in the FIFO-mode and ADD is set HIGH. If BYTE = 0, then
the data valid and the address of the channel is active during
the first (RD-impulse (1000 0000 0000 dv a2 a1 a0). During
the second (RD, the 16-bit data word can be read (db15…db0).
If BYTE = 1, then three (RD-impulses are needed. On the first
one, data valid, the three address bits and the data bits
db3…db0 (dv, a2, a1, a0, db3, db2, db1, db0) are read,
followed by the eight lower bits of the 16-bit data word
BYTE = 0
BYTE = 1
A2A1A0
1st RD
2nd RD
1st RD
2nd RD
3rd RD
000
001
010
011
100
101
110
111
db15...db0
db15...db0
db15...db0
db15...db0
db15...db0
db15...db0
1000 0000 0000 dv a2 a1 a0
1000 0000 0000 dv a2 a1 a0
no 2nd RD
no 2nd RD
no 2nd RD
no 2nd RD
no 2nd RD
no 2nd RD
db15...db0
db15...db0
db7...db0
db7...db0
db7...db0
db7...db0
db7...db0
db7...db0
dv a2 a1 a0 db3 db2 db0
dv a2 a1 a0 db3 db2 db0
db15...db8
db15...db8
db15...db8
db15...db8
db15...db8
db15...db8
db7...db0
db7...db0
no 3rd RD
no 3rd RD
no 3rd RD
no 3rd RD
no 3rd RD
no 3rd RD
db15...db8
db15...db8
TABLE IV. Overview Over the Output formats Depending on the Mode in Case ADD = 1
DB7 (MSB)
DB6
DB5
DB4
DB3
DB2
DB1
1
X
X
X
ADD
A2
A1
DB0 (LSB)
A0
0
X
X
X
RESET
HOLDA
HOLDB
HOLDC
TABLE V. Data Register Bits.
16
ADS8364
www.ti.com
SBAS219C
RESET
EOC
Conversion
Channel A
Conversion
Channels B and C
Conversion
Channel C
RD
reg. 5
empty
empty
empty
empty
empty
ch C1
reg. 4
empty
empty
empty
ch C1
empty
ch C0
reg. 3
empty
empty
empty
ch C0
ch C1
ch C1
reg. 2
empty
empty
empty
ch B1
ch C0
ch C0
reg. 1
empty
ch A1
empty
ch B0
ch B1
ch B1
reg. 0
empty
ch A0
ch A1
ch A1
ch B0
ch B0
t1
t0
t2
t3
t4
t5
FIGURE 12. Functionality Diagram of FIFO Registers.
(db7…db0) and finally the higher eight data bits (db15…db8).
1000 0000 0000 is added before the address in case BYTE =
0 and db3…db0 after the address if BYTE = 1. This provides
the possibility to check if the counting of the RD signals
inside the ADS8364 are still tracking with the external interface (see Table III and Table IV).
The data valid bit is useful for the FIFO mode. Valid data can
simply get read until dv turns 0. The three address bits are
listed in Table VI. If the FIFO is empty, 16 zeroes are put to
the output.
a2
a1
a0
Data From Channel A0
0
0
0
Data From Channel A1
0
0
1
Data From Channel B0
0
1
0
Data From Channel B1
0
1
1
Data From Channel C0
1
0
0
Data From Channel C1
1
0
1
ing power supplies, nearby digital logic, or high-power devices. The degree of error in the digital output depends on
the reference voltage, layout, and the exact timing of the
external event. Their error can change if the external event
changes in time with respect to the CLK input.
With this in mind, power to the ADS8364 should be clean and
well-bypassed. A 0.1µF ceramic bypass capacitor should be
placed as close to the device as possible. In addition, a 1µF
to 10µF capacitor is recommended. If needed, an even larger
capacitor and a 5Ω or 10Ω series resistor may be used to lowpass filter a noisy supply. On average, the ADS8364 draws
very little current from an external reference as the reference
voltage is internally buffered. A bypass capacitor of 0.1µF and
10µF are suggested when using the internal reference (tie pin
61 directly to pin 62).
GROUNDING
TABLE VI. Address Bit in the Output Data.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8364 circuitry. This is particularly
true if the CLK input is approaching the maximum throughput
rate.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, driving any single
conversion for an n-bit SAR converter, there are n windows
in which large external transient voltages can affect the
conversion result. Such glitches might originate from switch-
The AGND and DGND pins should be connected to a clean
ground point. In all cases, this should be the analog ground.
Avoid connections that are too close to the grounding point
of a microcontroller or digital signal processor. If required,
run a ground trace directly from the converter to the powersupply entry point. The ideal layout will include an analog
ground plane dedicated to the converter and associated
analog circuitry. Three signal ground pins, SGND, are the
input signal grounds which are on the same potential as
analog ground.
APPLICATION INFORMATION
In Figures 13 through 18, different connection diagrams to
DSPs or micro-controllers are shown.
ADS8364
SBAS219C
www.ti.com
17
3.3V
ADS8364
DVDD
BVDD
BVDD
HOLDA
HOLDB
26
30
23
55
HOLDC
FD
WR
A0
ADD
A1
BYTE
A2
CS
56
PWM1
57
PWM2
58
PWM3
54
EA0
53
EA1
52
EA2
EA3
31
8:1
OE
RD
EOC
CLK
RESET
C28xx
IS
29
RE
27
EXT_INT1
28
MCLKX
51
ADC_RST (MFSX)
DATA [0]
...
DATA [15]
D0
...
D15
48
...
33
VSS
BGND
FIGURE 13. Typical C28xx Connection (Hardware Control).
BVDD
3.3V
ADS8364
56
57
58
26
23
55
54
HOLDA
BVDD
C28xx
DVDD
HOLDB
A2
HOLDC
A1
FD
8:1
ADD
BYTE
CS
A0
RD
31
OE
29
RE
30
53
A1
WR
52
A2
EOC
CLK
A0
IS
WE
27
EXT_INT1
28
MCLKX
DATA [0]
...
DATA [15]
48
...
33
D0
...
D15
VSS
BGND
FIGURE 14. Typical C28xx Connection (Software Control).
18
ADS8364
www.ti.com
SBAS219C
3.3V
ADS8364
DVDD
BVDD
BVDD
HOLDA
HOLDB
26
54
53
52
30
23
55
FD
HOLDC
56
TOUT0
57
A2
58
A1
8:1
A0
CS
A1
C54xx
31
A0
OE
IS
29
A2
RD
WR
30
27
ADD
EOC
BYTE
CLK
<1
I/OSTRB
(1G32)
28
INT0
51
BCLKX1
RESET
XF
DATA [0]
...
DATA [15]
D0
...
D15
48
...
33
VSS
BGND
FIGURE 15. Typical C54xx Connection (FIFO with Hardware Control).
3.3V
ADS8364
BVDD
BVDD
HOLDA
30
53
52
23
54
WR
HOLDB
A1
HOLDC
DVDD
56
TOUT1
57
A2
58
A1
8:1
A2
ADD
A0
CS
BYTE
31
OE
55
RE
RD
CLK
RESET
DATA [0]
...
DATA [15]
A0
IS
BE0
29
EOC
C67xx
27
INT0
28
TOUT0
51
DB_CNTL0 (ED27)
48
...
33
D0
...
D15
VSS
BGND
FIGURE 16. Typical C67xx Connection (Cycle Mode – Hardware Control).
ADS8364
SBAS219C
www.ti.com
19
BVDD
3.3V
ADS8364
56
57
58
26
23
55
54
HOLDA
C67xx
DVDD
BVDD
HOLDB
HOLDC
A2
A1
FD
8:1
ADD
BYTE
CS
A0
RD
31
A0
IS
OE
29
RE
30
53
A1
WR
52
A2
EOC
CLK
WE
27
INT0
28
TOUT0
DATA [0]
...
DATA [15]
D0
...
D15
48
...
33
VSS
BGND
FIGURE 17. Typical C67xx Connection (Software Control).
3.3V
ADS8364
BVDD
DVDD
BVDD
HOLDA
30
52
54
53
23
55
29
WR
HOLDB
ADD
HOLDC
A1
A2
CS
RESET
BYTE
EOC
A0
CLK
RD
DATA [0]
...
DATA [7]
MSP430x1xx
56
TACLK (P1.0)
57
58
31
P1.1
51
P1.2
27
P1.3 (ADC_INT)
28
SMCLK (P1.4)
48
...
41
P2.0
...
P2.7
VSS
BGND
FIGURE 18. Typical MSP430x1xx Connection (Cycle Mode – Hardware Control).
20
ADS8364
www.ti.com
SBAS219C
Revision History
DATE REVISION PAGE
8/06
SECTION
1
—
2
Dissipation Ratings Table
DESCRIPTION
Changed Throughput Rate from 250kHz to 250kSPS throughout document.
C
Changed package from DGK to PAG.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
ADS8364
SBAS219C
www.ti.com
21
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS8364Y/250
ACTIVE
TQFP
PAG
64
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS8364Y
ADS8364Y/2K
ACTIVE
TQFP
PAG
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
ADS8364Y
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS8364Y/250
TQFP
PAG
64
250
180.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
ADS8364Y/2K
TQFP
PAG
64
2000
330.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS8364Y/250
TQFP
PAG
ADS8364Y/2K
TQFP
PAG
64
250
213.0
191.0
55.0
64
2000
350.0
350.0
43.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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