Texas Instruments | ADS5440-EP | Datasheet | Texas Instruments ADS5440-EP Datasheet

Texas Instruments ADS5440-EP Datasheet
ADS5440-EP
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SGLS359 – AUGUST 2006
13-BIT 210-MSPS ANALOG-TO-DIGITAL CONVERTER
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controlled Baseline
– One Assembly
– One Test Site
– One Fabrication Site
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree(1)
13-Bit Resolution
210-MSPS Sample Rate
SNR = 69 dBc at 100-MHz IF and 210 MSPS
SFDR = 76 dBc at 100-MHz IF and 210 MSPS
SNR = 68.1 dBc at 230-MHz IF and 210 MSPS
SFDR = 74 dBc at 230-MHz IF and 210 MSPS
2.2-VPP Differential Input Voltage
Fully Buffered Analog Inputs
5-V Analog Supply Voltage
LVDS Compatible Outputs
Total Power Dissipation: 2 W
Offset Binary Output Format
•
•
•
TQFP-80 PowerPAD™ Package
Pin Compatible With the ADS5444
Military Temperature Range = –55°C to 125°C
(1)
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
APPLICATIONS
•
•
•
•
•
Test and Measurement
Software-Defined Radio
Multichannel Base Station Receivers
Base Station Tx Digital Predistortion
Communications Instrumentation
RELATED PRODUCTS
•
•
•
ADS5424 - 14-Bit, 105-MSPS ADC
ADS5423 - 14-Bit, 80-MSPS ADC
ADS5444 - 13-Bit, 250-MSPS ADC
DESCRIPTION
The ADS5440 is a 13-bit 210-MSPS analog-to-digital converter (ADC) that operates from a 5-V supply, while
providing LVDS-compatible digital outputs from a 3.3-V supply. The ADS5440 input buffer isolates the internal
switching of the onboard track and hold (T&H) from disturbing the signal source. An internal reference generator
is also provided to further simplify the system design. The ADS5440 has outstanding low noise and linearity over
input frequency.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
ADS5440-EP
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SGLS359 – AUGUST 2006
AVDD
AIN
AIN
A1
TH1
+
TH2
Σ
A2
+
TH3
ADC1
Reference
A3
ADC3
−
−
VREF
Σ
DVDD
DAC1
ADC2
5
DAC2
5
5
Digital Error Correction
CLK
CLK
Timing
OVR
OVR
DRY
DRY
D[12:0]
GND
B0061-01
The ADS5440 is available in an 80-pin TQFP PowerPAD™ package. The ADS5440 is built on a state-of-the-art
Texas Instruments complementary bipolar process (BiCom3X) and is specified over the full military temperature
range (–55°C to 125°C).
2
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGING/ORDERING INFORMATION (1)
Product
Package
Lead
HTQFP-80 (2)
PowerPAD
ADS5440
(1)
(2)
Package
Designator
Specified
Temperature
Range
Package
Marking
–55°C to 125°C
ADS5440M-EP
(1)
PFP
Ordering
Number
Transport
Media,
Quantity
ADS5440MPFPEP
Tray, 96
For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet.
Thermal pad size: 7,5 mm x 7,5 mm (typ)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE/UNIT
AVDD to GND
Supply voltage
6V
DRVDD to GND
5V
Analog input to GND
–0.3 V to AVDD + 0.3 V
Clock input to GND
–0.3 V to AVDD + 0.3 V
±2.5 V
CLK to CLK
Digital data output to GND
–0.3 V to DRVDD + 0.3 V
Operating temperature range
–55°C to 125°C
Maximum junction temperature
150°C
Storage temperature range
–65°C to 150°C
ESD Human Body Model (HBM)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond
those specified is not implied.
1000
Years Estimated Life
(1)
2.5 kV
100
Wirebond Voiding Fail Mode
10
Electromigration Fail Mode
1
0.1
120
130
140
150
160
170
180
Continuous TJ − 5C
Figure 1. ADS5440MPFPEP Operating Life Derating Chart
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THERMAL CHARACTERISTICS (1)
PARAMETER
θJA
TYP
Soldered slug, no airflow
21.7
Soldered slug, 250-LFPM airflow
15.4
Unsoldered slug, no airflow
θJC
(1)
TEST CONDITIONS
UNIT
°C/W
50
Unsoldered slug, 250-LFPM airflow
43.4
Bottom of package (heatslug)
2.99
°C/W
Using 36 thermal vias (6 x 6 array). See the Section 2.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
3
3.3
3.6
V
SUPPLIES
AVDD
Analog supply voltage
DRVDD
Output driver supply voltage
ANALOG INPUT
VCM
Differential input range
2.2
VPP
Input common mode
2.4
V
CLOCK INPUT
1/tC
ADCLK input sample rate (sine wave)
10
210
Clock amplitude, differential sine wave
Clock duty cycle
TA
MSPS
3
VPP
50%
Open free air-temperature
–55
°C
125
ELECTRICAL CHARACTERISTICS
Min, Typ, and Max values at TA = 25°C, full temperature range is TMIN = –55°C to TMAX = 125°C, sampling rate = 210 MSPS,
50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1-dBFS differential input, and 3-VPP differential clock (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
UNIT
13
Bits
2.2
Vpp
1
kΩ
ANALOG INPUTS
Differential input range
Differential input resistance (DC)
Differential input capacitance
1.5
pF
Analog input bandwidth
800
MHz
2.4
V
INTERNAL REFERENCE VOLTAGE
VREF
Reference voltage
DYNAMIC ACCURACY
No missing codes
DNL
INL
Differential linearity error
Integral linearity error
Assured
–1
±0.4
1
TA = 25°C
–2.2
± 0.9
2.2
Full temp range
–3.2
±0.9
3.2
fIN = 10 MHz
fIN = 10 MHz
Offset error
–11
Offset temperature coefficient
Gain error
–5
Gain temperature coefficient
PSRR
4
11
0.0005
fIN = 100 MHz
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LSB
LSB
mV
mV/°C
5
%FS
–0.02
∆%/°C
1
mV/V
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ELECTRICAL CHARACTERISTICS (continued)
Min, Typ, and Max values at TA = 25°C, full temperature range is TMIN = –55°C to TMAX = 125°C, sampling rate = 210 MSPS,
50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1-dBFS differential input, and 3-VPP differential clock (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
340
410
mA
80
100
mA
2
2.35
W
POWER SUPPLY
IAVDD
Analog supply current
IDRVDD
Output buffer supply current
VIN = full scale, fIN = 100 MHz, FS = 210 MSPS
Power dissipation
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz
69.8
fIN = 70 MHz
fIN = 100 MHz
SNR
Signal-to-noise ratio
69.2
TA = 25°C
Full temp range
67.5
66
fIN = 170 MHz
fIN = 230 MHz
68
fIN = 300 MHz
66.9
fIN = 400 MHz
65
fIN = 10 MHz
84
fIN = 100 MHz
HD2
HD3
Spurious free dynamic range
Second harmonic
Third harmonic
Worst other harmonic/spur (other
than HD2 and HD3)
69
68.3
fIN = 70 MHz
SFDR
69
dBc
77
TA = 25°C
Full temp range
70
76
64.5
76
fIN = 170 MHz
74
fIN = 230 MHz
74
fIN = 300 MHz
69
fIN = 400 MHz
64
fIN = 10 MHz
96
fIN = 70 MHz
83
fIN = 100 MHz
87
fIN = 170 MHz
76
fIN = 230 MHz
76
fIN = 300 MHz
69
fIN = 400 MHz
64
fIN = 10 MHz
84
fIN = 70 MHz
77
fIN = 100 MHz
76
fIN = 170 MHz
74
fIN = 230 MHz
74
fIN = 300 MHz
73
fIN = 400 MHz
70
fIN = 10 MHz
92
fIN = 70 MHz
92
fIN = 100 MHz
87
fIN = 170 MHz
87
fIN = 230 MHz
83
fIN = 300 MHz
83
fIN = 400 MHz
80
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dBc
dBc
dBc
dBc
5
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ELECTRICAL CHARACTERISTICS (continued)
Min, Typ, and Max values at TA = 25°C, full temperature range is TMIN = –55°C to TMAX = 125°C, sampling rate = 210 MSPS,
50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1-dBFS differential input, and 3-VPP differential clock (unless otherwise
noted)
PARAMETER
SINAD
TEST CONDITIONS
MIN
fIN = 10 MHz
69.6
fIN = 70 MHz
68.8
fIN = 100 MHz
68
fIN = 170 MHz
66.8
fIN = 230 MHz
66
fIN = 300 MHz
64
fIN = 400 MHz
ENOB
TYP
Effective number of bits
fIN = 10 MHz
RMS idle channel noise
Inputs tied to common-mode
MAX
UNIT
dBc
60
11.4
Bits
0.4
LSB
DIGITAL CHARACTERISTICS – LVDS DIGITAL OUTPUTS
6
Differential output voltage
0.247
Output offset voltage
1.125
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1.25
0.452
V
1.375
V
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TIMING CHARACTERISTICS
tA
N+3
N
AIN
N+1
N+2
tCLK
CLK, CLK
tCLKH
N+1
N
N+4
tCLKL
N+2
N+3
N+4
tC_DR
D[12:0],
OVR, OVR
N−3
tr
N−2
tf
tsu_c
N−1
th_c
N
th_DR
tsu_DR
DRY, DRY
tDR
T0073-01
Figure 2. Timing Diagram
TIMING CHARACTERISTICS
Min, Typ, Max over full temperature range, 50% clock duty cycle, sampling rate = 210 MSPS, AVDD = 5 V, DRVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tA
Aperture delay
500
ps
tJ
Clock slope independent aperture uncertainty (jitter)
150
fs RMS
4
cycles
Latency
Clock Input
tCLK
Clock period
4.76
ns
tCLKH
Clock pulse width high
2.38
ns
tCLKL
Clock pulse width low
2.38
ns
Clock to DataReady (DRY)
tDR
Clock rising to DataReady falling
tC_DR
Clock rising to DataReady rising
1.1
Clock duty cycle = 50%
(1)
3.1
3.5
ns
3.9
ns
Clock to DATA, OVR (2)
tr
Data rise time (20% to 80%)
0.6
ns
tf
Data fall time(80% to 20%)
0.6
ns
tsu_c
Data valid to clock (setup time)
3.5
ns
th_c
Clock to invalid Data (hold time)
0.2
ns
DataReady (DRY)/DATA, OVR (2)
tsu(DR)
Data valid to DRY
2.1
2.4
ns
th(DR)
DRY to invalid Data
0.9
1.3
ns
(1)
(2)
tC_DR = tDR + tCLKH for clock duty cycles other than 50%
Data is updated with clock falling edge or DRY rising edge.
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D5
D5
D6
D6
GND
DVDD
D7
D7
D8
D8
D9
D9
D10
D10
D11
D11
D12
D12
DRY
DRY
GND
21
7 8 9 10 11 12 13 14 15 16 17 18 19 20
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
6
39
4 5
61
1 2 3
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
GND
AVDD
GND
AVDD
GND
AVDD
GND
NC
GND
AVDD
GND
NC
GND
AVDD
GND
AVDD
GND
AVDD
GND
AVDD
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D4
D4
D3
D3
D2
D2
D1
D1
GND
DVDD
D0
D0
NC
NC
NC
NC
NC
NC
OVR
OVR
DVDD
GND
AVDD
NC
NC
VREF
GND
AVDD
GND
CLK
CLK
GND
AVDD
AVDD
GND
AIN
AIN
GND
AVDD
GND
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DEVICE INFORMATION
PFP PACKAGE
(TOP VIEW)
P0027-01
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DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS
TERMINAL
NAME
DESCRIPTION
NO.
3, 8, 13, 14, 19, 21,
23, 25, 27, 31, 35, 37, Analog power supply
39
AVDD
DVDD
1, 51, 66
Output driver power supply
2, 7, 9, 12, 15, 18, 20,
22, 24, 26, 28, 30, 32, Ground
34, 36, 38, 40, 52, 65
GND
VREF
6
Reference voltage
CLK
10
Differential input clock (positive). Conversion initiated on rising edge.
CLK
11
Differential input clock (negative)
AIN
16
Differential input signal (positive)
AIN
17
Differential input signal (negative)
OVR, OVR
42, 41
Over range indicator LVDS output. A logic high signals an analog input in excess of the
full-scale range.
D0, D0
50, 49
LVDS digital output pair, least-significant bit (LSB)
D1–D6, D1–D6
53–64
LVDS digital output pairs
D7–D11, D7–D11
67–76
LVDS digital output pairs
D12, D12
78, 77
LVDS digital output pair, most-significant bit (MSB)
DRY, DRY
80, 79
Data ready LVDS output pair
NC
4, 5, 29, 33, 43–48
No connect
DEFINITION OF SPECIFICATIONS
Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the
low frequency value.
Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the
sampling occurs.
Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic
high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A
perfect differential sine wave clock results in a 50% duty cycle.
Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric testing is
performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart.
The DNL is the deviation of any single step from this ideal value, measured in units of LSB.
Integral Nonlinearity (INL) The INL is the deviation of the ADCs transfer function from a best fit line determined by a least
squares curve fit of that transfer function. The INL at each analog input value is the difference between the
actual transfer function and this best fit line, measured in units of LSB.
Gain Error
The gain error is the deviation of the ADCs actual input full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
Offset Error
Offset error is the deviation of output code from mid-code when both inputs are tied to common-mode.
Temperature Drift Temperature drift (with respect to gain error and offset error) specifies the change from the value at the
nominal temperature to the value at TMIN or TMAX. It is computed as the maximum variation the parameters
over the whole temperature range divided by TMIN – TMAX.
Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding
the power at dc and the first five harmonics.
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DEFINITION OF SPECIFICATIONS (continued)
SNR + 10log
P
S
10 P
N
(1)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the
other spectral components including noise (PN) and distortion (PD), but excluding dc.
P
SINAD + 10log
S
10 P ) P
N
D
(2)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as
the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Effective Resolution Bandwidth The highest input frequency where the SNR (dB) is dropped by 3 dB for a full-scale input
amplitude.
Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first five
harmonics (PD).
P
THD + 10log
10 P
S
D
(3)
THD is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion IMD3 is the ratio of the power of the fundamental (at frequencies f1, f2) to the power
of the worst spectral component at either frequency 2f1– f2 or 2f2– f1). IMD3 is either given in units of dBc (dB
to carrier) when the absolute power of the fundamental is used as the reference or dBFS (dB to full scale)
when the power of the fundamental is extrapolated to the converter’s full-scale range.
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TYPICAL CHARACTERISTICS
Spectral Performance
(FFT For 10-MHz Input Signal)
Spectral Performance
(FFT For 100-MHz Input Signal)
0
0
SFDR = 83 dBc
SNR = 69.9 dBc
THD = 81.4 dBc
SINAD = 69.6 dBc
−20
−40
Amplitude − dB
Amplitude − dB
−20
SFDR = 76 dBc
SNR = 69 dBc
THD = 74.8 dBc
SINAD = 67.9 dBc
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
10
20
30
40
50
60
70
80
90 100
0
10
20
f − Frequency − MHz
30
40
50
60
70
80
90 100
f − Frequency − MHz
G001
G002
Figure 3.
Figure 4.
Spectral Performance
(FFT For 170-MHz Input Signal)
Spectral Performance
(FFT For 230-MHz Input Signal)
0
0
SFDR = 74 dBc
SNR = 68.3 dBc
THD = 71.5 dBc
SINAD = 66.8 dBc
−20
−40
Amplitude − dB
Amplitude − dB
−20
SFDR = 74 dBc
SNR = 67.9 dBc
THD = 70.3 dBc
SINAD = 65.9 dBc
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
10
20
30
40
50
60
70
80
90 100
0
10
f − Frequency − MHz
20
30
40
50
60
70
80
90 100
f − Frequency − MHz
G003
Figure 5.
G004
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
Spectral Performance
(FFT For 300-MHz Input Signal)
Spectral Performance
(FFT For 400-MHz Input Signal)
0
0
SFDR = 69 dBc
SNR = 66.9 dBc
THD = 67.1 dBc
SINAD = 63.9 dBc
−20
−40
Amplitude − dB
Amplitude − dB
−20
SFDR = 63.3 dBc
SNR = 64.9 dBc
THD = 62.1 dBc
SINAD = 60.1 dBc
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
10
20
30
40
50
60
70
80
90 100
0
10
20
f − Frequency − MHz
30
40
50
60
70
80
90 100
f − Frequency − MHz
G005
G006
Figure 7.
Figure 8.
Two-Tone Intermodulation Distortion
(FFT For 51.5-MHz and 52.5 MHz Input Signals)
Two-Tone Intermodulation Distortion
(FFT For 51.5-MHz and 52.5 MHz Input Signals)
0
0
FIN1 = 51.5 MHz, −7 dBFS
FIN2 = 52.5 MHz, −7 dBFS
IMD3 = 89.3 dBFS
−20
−40
Amplitude − dB
Amplitude − dB
−20
FIN1 = 51.5 MHz, −16 dBFS
FIN2 = 52.5 MHz, −16 dBFS
IMD3 = 97.4 dBFS
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
10
20
30
40
50
60
70
80
90 100
0
10
f − Frequency − MHz
20
30
40
50
60
G007
Figure 9.
12
70
80
90 100
f − Frequency − MHz
G008
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
Two-Tone Intermodulation Distortion
(FFT For 151-MHz and 152 MHz Input Signals)
Two-Tone Intermodulation Distortion
(FFT For 151-MHz and 152 MHz Input Signals)
0
0
FIN1 = 151 MHz, −7 dBFS
FIN2 = 152 MHz, −7 dBFS
IMD3 = 87.9 dBFS
−20
−40
Amplitude − dB
Amplitude − dB
−20
FIN1 = 151 MHz, −16 dBFS
FIN2 = 152 MHz, −16 dBFS
IMD3 = 99.4 dBFS
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
10
20
30
40
50
60
70
80
90 100
0
10
20
f − Frequency − MHz
30
40
50
60
70
80
90 100
f − Frequency − MHz
G009
G010
Figure 11.
Figure 12.
Two-Tone Intermodulation Distortion
(FFT For 254-MHz and 255 MHz Input Signals)
Two-Tone Intermodulation Distortion
(FFT For 254-MHz and 255 MHz Input Signals)
0
0
FIN1 = 254 MHz, −7 dBFS
FIN2 = 255 MHz, −7 dBFS
IMD3 = 80.5 dBFS
−20
−40
Amplitude − dB
Amplitude − dB
−20
FIN1 = 254 MHz, −16 dBFS
FIN2 = 255 MHz, −16 dBFS
IMD3 = 93.9 dBFS
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
10
20
30
40
50
60
70
80
90 100
0
10
f − Frequency − MHz
20
30
40
50
60
70
80
90 100
f − Frequency − MHz
G011
Figure 13.
G012
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
Two-Tone Intermodulation Distortion
(FFT For 355-MHz and 356 MHz Input Signals)
Two-Tone Intermodulation Distortion
(FFT For 355-MHz and 356 MHz Input Signals)
0
0
FIN1 = 355 MHz, −7 dBFS
FIN2 = 356 MHz, −7 dBFS
IMD3 = 79.7 dBFS
−20
−40
Amplitude − dB
Amplitude − dB
−20
FIN1 = 355 MHz, −16 dBFS
FIN2 = 356 MHz, −16 dBFS
IMD3 = 96.8 dBFS
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
10
20
30
40
50
60
70
80
90 100
0
10
20
f − Frequency − MHz
30
40
50
60
70
80
90 100
f − Frequency − MHz
G013
G014
Figure 15.
Figure 16.
WCDMA Carrier
(fIN = 70 MHz)
WCDMA Carrier
(fIN = 140 MHz)
0
0
fS = 184.32 MSPS
fIN = 70 MHz
ACPR Adj Top = 73 dB
ACPR Adj Low = 72.7 dB
−20
−20
−40
Amplitude − dB
−40
Amplitude − dB
fS = 184.32 MSPS
fIN = 140 MHz
ACPR Adj Top = 72.1 dB
ACPR Adj Low = 72.1 dB
−60
−80
−60
−80
−100
−100
−120
−120
−140
−140
0
10
20
30
40
50
60
70
80
90
0
f − Frequency − MHz
10
20
30
40
50
G015
Figure 17.
14
60
70
80
90
f − Frequency − MHz
G016
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
Input Bandwidth
Differential Nonlinearity
0.4
0
−1
Differential Nonlinearity − LSB
−2
Input Amplitude − dB
fS = 210 MSPS
fIN = 10 MHz
0.3
−3
−4
−5
−6
−7
−8
−9
1
0.1
0.0
−0.1
−0.2
−0.3
fS = 210 MSPS
AIN = −1 dBFS
−10
0.2
−0.4
10
100
fIN − Input Frequency − MHz
0
1k
1024 2048 3072 4096 5120 6144 7168 8192
Code
G017
G018
Figure 19.
Figure 20.
Noise Histogram With Inputs Shorted
45
0.8
40
0.6
35
0.4
Percentage − %
INL − Integral Nonlinearity − LSB
Integral Nonlinearity
1.0
0.2
0.0
−0.2
−0.4
30
25
20
15
10
−0.6
−0.8
5
fS = 210 MSPS
fIN = 10 MHz
−1.0
0
0
1024 2048 3072 4096 5120 6144 7168 8192
4101
Code
G019
Figure 21.
4102
4103
4104
4105
4106
Code Number
G020
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
AC Performance
vs
Input Amplitude
AC Performance
vs
Input Amplitude
100
100
SFDR (dBFS)
80
SNR (dBFS)
60
40
Performance − dB
Performance − dB
80
SFDR (dBFS)
SFDR (dBc)
20
SNR (dBFS)
60
SFDR (dBc)
40
20
SNR (dBc)
SNR (dBc)
0
0
fS = 210 MSPS
fIN = 100 MHz
−20
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
fS = 210 MSPS
fIN = 230 MHz
−20
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
Input Amplitude − dBFS
G021
G022
Figure 23.
Figure 24.
Two-Tone Spurious Free Dynamic Range
vs
Input Amplitude
Spurious Free Dynamic Range
vs
Clock Duty Cycle
80.0
SFDR − Spurious-Free Dynamic Range − dBc
SFDR − Spurious-Free Dynamic Range − dB
120
SFDR (dBFS)
100
80
60
SFDR (dBc)
40
20
90 dBFS Line
fS = 210 MSPS
f1 = 151 MHz
f2 = 152 MHz
0
−20
−110−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
fS = 210 MSPS Square Wave
77.5
75.0
fIN = 100.33 MHz
72.5
fIN = 230.13 MHz
70.0
67.5
65.0
62.5
60.0
40
0
Input Amplitude − dBFS
45
50
55
60
Duty Cycle − %
G023
Figure 25.
16
0
Input Amplitude − dBFS
G024
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
Spurious Free Dynamic Range
vs
Clock Level
Signal-to-Noise Ratio
vs
Clock Level
70
fS = 210 MSPS
fIN = 100.33 MHz
76
69
SNR − Signal-to-Noise Ratio − dBc
SFDR − Spurious-Free Dynamic Range − dBc
78
74
72
fIN = 230.13 MHz
70
68
66
64
62
68
67
fIN = 230.13 MHz
66
65
64
63
62
61
60
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
60
0.0
4.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Clock Amplitude − VP−P
Clock Amplitude − VP−P
Figure 27.
Figure 28.
Performance
vs
Clock Common Mode Level
Spurious Free Dynamic Range
vs
AVDD Across Temperature
4.0
G026
G025
84
SFDR − Spurious-Free Dynamic Range − dBc
80
SFDR
70
SNR
60
Performance − dBc
fIN = 100.33 MHz
fS = 210 MSPS
50
40
30
fs = 210 MSPS
fin = 100 MHz
20
10
0
1
2
3
4
82
fS = 210 MSPS
fIN = 100 MHz
80
78
76
TA = 25°C
TA = 0°C
74
TA = 85°C
72
TA = −40°C
70
4.65
5
TA = 65°C
Clock Common-Mode Voltage − V
G027
Figure 29.
4.75
4.85
4.95
5.05
5.15
AVDD − Supply Voltage − V
5.25
5.35
G028
Figure 30.
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TYPICAL CHARACTERISTICS (continued)
Signal-to-Noise Ratio
vs
AVDD Across Temperature
Spurious Free Dynamic Range
vs
DRVDD Across Temperature
70
80
69
68
SFDR − Spurious-Free Dynamic Range − dBc
SNR − Signal-to-Noise Ratio − dBc
TA = 0°C
TA = 65°C
TA = −40°C
TA = 85°C
TA = 25°C
67
66
fS = 210 MSPS
fIN = 100 MHz
65
4.70
4.80
4.90
5.00
5.10
5.20
TA = 65°C
78
TA = 25°C
77
76
TA = 0°C
75
74
TA = 85°C
73
TA = −40°C
72
71
70
2.9
5.30
AVDD − Supply Voltage − V
fS = 210 MSPS
fIN = 100 MHz
79
3.1
3.3
G029
Figure 31.
Figure 32.
Signal-to-Noise Ratio
vs
DRVDD Across Temperature
70
SNR − Signal-to-Noise Ratio − dBc
TA = 0°C
69
TA = 65°C
TA = 85°C
68
TA = −40°C
TA = 25°C
67
66
fS = 210 MSPS
fIN = 100 MHz
65
3.0
3.1
3.2
3.3
3.4
3.5
DRVDD − Supply Voltage − V
Figure 33.
18
3.5
DRVDD − Supply Voltage − V
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3.7
G031
3.7
G030
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TYPICAL CHARACTERISTICS (continued)
SNR
vs
Input Frequency and Sampling Frequency
240
69
220
68
fS − Sampling Frequency − MHz
200
65
66
180
160
67
140
68
69
69
65
120
66
67
100
80
66
60
67
40
68
20
10
10
65
68
69
67
66
50
65
66
65
63
100
62
150
64
62
61
60
63
64
200
64
63
62
250
60
59
58
300
61
58
350
59
57 56
400
fIN − Input Frequency − MHz
54
56
58
60
62
64
SNR − dBc
66
68
70
M0048−01
Figure 34.
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TYPICAL CHARACTERISTICS (continued)
SFDR
vs
Input Frequency and Sampling Frequency
240
72
220
76
fS − Sampling Frequency − MHz
200
72
74
70
78
180
66
68
78
80
74
76
66
160
82
140
120
60
72
84
100
80
80
82
68
70
62
74
84
86
80
84
76
82
84
78
82
84
40
20
10
10
64
84
82
80
82
82
50
66
100
150
78
76
72
74
200
250
70
68
300
64
62
350
60
58
400
fIN − Input Frequency − MHz
55
60
65
70
SFDR − dBc
Figure 35.
20
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75
80
85
M0048−02
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APPLICATION INFORMATION
Theory of Operation
The ADS5440 is a 13-bit, 210-MSPS, monolithic pipeline analog-to-digital converter (ADC). Its bipolar analog
core operates from a 5-V supply, while the output uses a 3.3 V supply to provide LVDS compatible outputs. The
conversion process is initiated by the rising edge of the external input clock. At that instant, the differential input
signal is captured by the input track and hold (T&H) and the input sample is sequentially converted by a series
of small resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the
falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process
results in a data latency of four clock cycles, after which the output data is available as a 13-bit parallel word,
coded in offset binary format.
Input Configuration
The analog input for the ADS5440 consists of an analog differential buffer followed by a bipolar T&H. The
analog buffer isolates the source driving the input of the ADC from any internal switching. The input common
mode is set internally through a 500-Ω resistor connected from 2.4 V to each of the inputs. This results in a
differential input impedance of 1 kΩ.
For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swings
symmetrically between 2.4 + 0.55 V and 2.4 – 0.55 V. This means that each input has a maximum signal swing
of 1.1 VPP for a total differential input signal swing of 2.2 VPP. The maximum swing is determined by the internal
reference voltage generator eliminating the need for any external circuitry for this purpose.
The ADS5440 obtains optimum performance when the analog inputs are driven differentially. The circuit in
Figure 36 shows one possible configuration using an RF transformer with termination either on the primary or on
the secondary of the transformer. If voltage gain is required, a step up transformer can be used. For voltage
gains that would require an impractical transformer turn ratio, a single-ended amplifier driving the transformer is
shown in Figure 37.
R0
50 W
Z0
50 W
AIN
1:1
R
50 W
AC S ignal
Source
ADS5440
AIN
AD T 1−1W T
Figure 36. Converting a Single-Ended Input to a Differential Signal Using RF Transformers
5V
VIN
−5 V
RS
100 Ω
+
OPA695
−
0.1 µF
1000 µF
RIN
1:1
RT
100 Ω
RIN
AIN
CIN
ADS5440
AIN
R1
400 Ω
R2
57.5 Ω
AV = 8V/V
(18 dB)
Figure 37. Using the OPA695 With the ADS5440
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Application Information (continued)
From VIN
50 Ω
Source
100 Ω
348 Ω
13-Bit
210 MSPS
+5V
78.9 Ω
49.9 Ω
0.22 µF
18 pF
100 Ω
49.9 Ω
THS4509
AIN
ADS5440
AIN
VREF
CM
49.9 Ω
0.22 µF
78.9 Ω
49.9 Ω
0.22 µF
0.1 µF
0.1 µF
348 Ω
Figure 38. Using the THS4509 With the ADS5440
Besides the OPA695, TI offers a wide selection of single-ended operational amplifiers that can be selected
depending on the application. An RF gain block amplifier, such as the TI THS9001, can also be used with an RF
transformer for high input frequency applications. For applications requiring dc-coupling with the signal source, a
differential input/differential output amplifier like the THS4509 (see Figure 38) is a good solution, as it minimizes
board space and reduces the number of components.
In this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to
differential, and sets the proper input common-mode voltage to the ADS5440.
The 50-Ω resistors and 18-pF capacitor between the THS4509 outputs and ADS5440 inputs (along with the
input capacitance of the ADC) limit the bandwidth of the signal to about 70 MHz (–3 dB).
Input termination is accomplished via the 78.9-Ω resistor and 0.22-µF capacitor to ground in conjunction with the
input impedance of the amplifier circuit. A 0.22-µF capacitor and 49.9-Ω resistor is inserted to ground across the
78.9-Ω resistor and 0.22-µF capacitor on the alternate input to balance the circuit.
Gain is a function of the source impedance, termination, and 348-Ω feedback resistor. See the THS4509 data
sheet (SLOS454) for further component values to set proper 50-Ω termination for other common gains.
Since the ADS5440 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a single
power supply input with VS+ = 5 V and VS– = 0 V (ground). This maintains maximum headroom on the internal
transistors of the THS4509.
Clock Inputs
The ADS5440 clock input can be driven with either a differential clock signal or a single-ended clock input, with
little or no difference in performance between both configurations. In low input frequency applications, where
jitter may not be a big concern, the use of single-ended clock (see Figure 39) could save some cost and board
space without any trade-off in performance. When driven on this configuration, it is best to connect CLK to
ground with a 0.01-µF capacitor, while CLK is ac-coupled with a 0.01 µF capacitor to the clock source, as shown
in Figure 39.
Square Wave or
Sine Wave
CLK
0.01 µF
ADS5440
CLK
0.01 µF
Figure 39. Single-Ended Clock
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Application Information (continued)
0.1 µF
Clock
Source
1:4
CLK
MA3X71600LCT−ND
ADS5440
CLK
Figure 40. Differential Clock
For jitter-sensitive applications, the use of a differential clock has some advantages (as with any other ADC) at
the system level. The first advantage is that it allows for common-mode noise rejection at the PCB level.
A differential clock also allows for the use of bigger clock amplitudes without exceeding the absolute maximum
ratings. In the case of a sinusoidal clock, this results in higher slew rates and reduces the impact of clock noise
on jitter. See Clocking High Speed Data Converters (SLYT075) for more detail.
Figure 40 shows this approach. The back-to-back Schottky diodes can be added to limit the clock amplitude in
cases where this would exceed the absolute maximum ratings, even when using a differential clock.
100 nF
MC100EP16DT
100 nF
D
D
CLK
Q
VBB Q
499 W
100 nF
100 nF
ADS5440
CLK
499 W
50 Ω
50 Ω
100 nF
113 Ω
Figure 41. Differential Clock Using PECL Logic
Another possibility is the use of a logic based clock, such as PECL. In this case, the slew rate of the edges will
most likely be much higher than the one obtained for the same clock amplitude based on a sinusoidal clock.
This solution would minimize the effect of the slope dependent ADC jitter. Using logic gates to square a
sinusoidal clock may not produce the best results as logic gates may not have been optimized to act as
comparators, adding too much jitter while squaring the inputs.
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩ resistors. It is
recommended to use ac coupling, but if this scheme is not possible due to, for instance, asynchronous clocking,
the ADS5440 features good tolerance to clock common-mode variation.
Additionally, the internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50% duty
cycle clock signal should be provided.
Digital Outputs
The ADC provides 13 data outputs (D12 to D0, with D12 being the MSB and D0 the LSB), a data-ready signal
(DRY), and an over-range indicator (OVR) that equals a logic high when the output reaches the full-scale limits.
The output format is offset binary. It is recommended to use the DRY signal to capture the output data of the
ADS5440.
The ADS5440 digital outputs are LVDS compatible.
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Application Information (continued)
Power Supplies
The use of low noise power supplies with adequate decoupling is recommended. Linear supplies are the
preferred choice versus switched ones, which tend to generate more noise components that can be coupled to
the ADS5440.
The ADS5440 uses two power supplies. For the analog portion of the design, a 5-V AVDD is used, while for the
digital outputs supply (DRVDD) we recommend the use of 3.3 V. All the ground pins are marked as GND,
although AGND pins and DRGND pins are not tied together inside the package.
Layout Information
The evaluation board represents a good guideline of how to layout the board to obtain the maximum
performance out of the ADS5440. General design rules as the use of multilayer boards, single ground plane for
ADC ground connections and local decoupling ceramic chip capacitors should be applied. The input traces
should be isolated from any external source of interference or noise including the digital outputs, as well as the
clock traces. The clock signal traces should also be isolated from other signals, especially in applications where
low jitter is required as high IF sampling.
Besides performance oriented rules, care has to be taken when considering the heat dissipation out of the
device. The thermal heatsink should be soldered to the board as described in the PowerPad Package section.
PowerPAD™ Package
The PowerPAD package is a thermally-enhanced standard size IC package designed to eliminate the use of
bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using
standard printed circuit board (PCB) assembly techniques, and can be removed and replaced using standard
repair procedures.
The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of
the IC. This provides an extremely low thermal resistance path between the die and the exterior of the package.
The thermal pad on the bottom of the IC can then be soldered directly to the PCB using the PCB as a heatsink.
Assembly Process
1. Prepare the PCB top-side etch pattern including etch for the leads, as well as the thermal pad as illustrated
in the Mechanical Data section.
2. Place a 6-by-6 array of thermal vias in the thermal pad area. These holes should be 13 mils in diameter.
The small size prevents wicking of the solder through the holes.
3. It is recommended to place a small number of 25-mil diameter holes under the package, but outside the
thermal pad area to provide an additional heat path.
4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as
a ground plane).
5. Do not use the typical web or spoke via connection pattern when connecting the thermal vias to the ground
plane. The spoke pattern increases the thermal resistance to the ground plane.
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.
7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.
8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
For more detailed information regarding the PowerPAD package and its thermal properties, see either the
SLMA004 application brief, PowerPAD Made Easy, or the technical brief, PowerPAD Thermally Enhanced
Package SLMA002.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS5440MPFPEP
ACTIVE
HTQFP
PFP
80
96
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
ADS5440M-EP
V62/06669-01XE
ACTIVE
HTQFP
PFP
80
96
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-55 to 125
ADS5440M-EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS5440-EP :
• Catalog: ADS5440
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
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TI is not responsible or liable for any such statements.
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anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
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requirements. Nonetheless, such components are subject to these terms.
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Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated
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